Skip to content

Instantly share code, notes, and snippets.

@mcclure

mcclure/misbehaving.v Secret

Created August 11, 2023 03:12
Show Gist options
  • Save mcclure/b4b94fb92d421c5420722c1dd8ec9ccf to your computer and use it in GitHub Desktop.
Save mcclure/b4b94fb92d421c5420722c1dd8ec9ccf to your computer and use it in GitHub Desktop.
Download ZIP
Raw
misbehaving.v
/* Automatically generated by Amaranth 0.4.dev149+g7a9dbc8. Do not edit. */
/* Generated by Amaranth Yosys 0.25 (PyPI ver 0.25.0.0.post74, git sha1 e02b7f64b) */
(* \amaranth.hierarchy = "top.button_ffwd_watcher" *)
(* generator = "Amaranth" *)
module button_ffwd_watcher(rst, clk, overflow);
reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:35" *)
wire [8:0] \$1 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:35" *)
wire [8:0] \$2 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:39" *)
wire \$4 ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:415" *)
input clk;
wire clk;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:8" *)
reg [7:0] count = 8'h00;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:8" *)
reg [7:0] \count$next ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:13" *)
output overflow;
wire overflow;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:415" *)
input rst;
wire rst;
assign \$2 = count + (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:35" *) 1'h1;
assign \$4 = ! (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:39" *) count;
always @(posedge clk)
count <= \count$next ;
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\count$next = count;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/hdl/xfrm.py:504" *)
casez (rst)
1'h1:
\count$next = 8'h00;
endcase
end
assign \$1 = \$2 ;
assign overflow = \$4 ;
endmodule
(* \amaranth.hierarchy = "top.button_step_watcher" *)
(* generator = "Amaranth" *)
module button_step_watcher(rst, clk, overflow);
reg \$auto$verilog_backend.cc:2083:dump_module$2 = 0;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:35" *)
wire [8:0] \$1 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:35" *)
wire [8:0] \$2 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:39" *)
wire \$4 ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:415" *)
input clk;
wire clk;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:8" *)
reg [7:0] count = 8'h00;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:8" *)
reg [7:0] \count$next ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:13" *)
output overflow;
wire overflow;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:415" *)
input rst;
wire rst;
assign \$2 = count + (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:35" *) 1'h1;
assign \$4 = ! (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:39" *) count;
always @(posedge clk)
count <= \count$next ;
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
\count$next = count;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/hdl/xfrm.py:504" *)
casez (rst)
1'h1:
\count$next = 8'h00;
endcase
end
assign \$1 = \$2 ;
assign overflow = \$4 ;
endmodule
(* \amaranth.hierarchy = "top.cd_sync" *)
(* generator = "Amaranth" *)
module cd_sync(clk, rst);
reg \$auto$verilog_backend.cc:2083:dump_module$3 = 0;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:409" *)
wire \$1 ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:409" *)
wire \$3 ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:412" *)
wire [13:0] \$5 ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:412" *)
wire [13:0] \$6 ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:420" *)
wire \$8 ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:415" *)
output clk;
wire clk;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:379" *)
wire clk_i;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:405" *)
wire por_clk;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:407" *)
reg ready = 1'h0;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:407" *)
reg \ready$next ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:415" *)
output rst;
wire rst;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:406" *)
reg [12:0] timer = 13'h0000;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:406" *)
reg [12:0] \timer$next ;
always @(posedge por_clk)
ready <= \ready$next ;
always @(posedge por_clk)
timer <= \timer$next ;
assign \$1 = timer == (* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:409" *) 13'h12c0;
assign \$3 = timer == (* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:409" *) 13'h12c0;
assign \$6 = timer + (* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:412" *) 1'h1;
assign \$8 = ~ (* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:420" *) ready;
SB_HFOSC #(
.CLKHF_DIV("0b00")
) \U$$0 (
.CLKHF(clk_i),
.CLKHFEN(1'h1),
.CLKHFPU(1'h1)
);
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
\ready$next = ready;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:409" *)
casez (\$1 )
/* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:409" */
1'h1:
\ready$next = 1'h1;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$3 ) begin end
\timer$next = timer;
(* full_case = 32'd1 *)
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:409" *)
casez (\$3 )
/* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:409" */
1'h1:
/* empty */;
/* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:411" */
default:
\timer$next = \$6 [12:0];
endcase
end
assign \$5 = \$6 ;
assign rst = \$8 ;
assign clk = clk_i;
assign por_clk = clk_i;
endmodule
(* \amaranth.hierarchy = "top.current_led" *)
(* generator = "Amaranth" *)
module current_led(rst, clk, count);
reg \$auto$verilog_backend.cc:2083:dump_module$4 = 0;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:35" *)
wire [6:0] \$1 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:35" *)
wire [6:0] \$2 ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:415" *)
input clk;
wire clk;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:8" *)
output [5:0] count;
reg [5:0] count = 6'h00;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:8" *)
reg [5:0] \count$next ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:415" *)
input rst;
wire rst;
assign \$2 = count + (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:35" *) 1'h1;
always @(posedge clk)
count <= \count$next ;
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$4 ) begin end
\count$next = count;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/hdl/xfrm.py:504" *)
casez (rst)
1'h1:
\count$next = 6'h00;
endcase
end
assign \$1 = \$2 ;
endmodule
(* \amaranth.hierarchy = "top.pin_aled_0" *)
(* generator = "Amaranth" *)
module pin_aled_0(aled_0__io, aled_0__o);
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout [3:0] aled_0__io;
wire [3:0] aled_0__io;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
input [3:0] aled_0__o;
wire [3:0] aled_0__o;
SB_IO #(
.IO_STANDARD("SB_LVCMOS"),
.PIN_TYPE(6'h19)
) aled_0_0 (
.D_OUT_0(aled_0__o[0]),
.PACKAGE_PIN(aled_0__io[0])
);
SB_IO #(
.IO_STANDARD("SB_LVCMOS"),
.PIN_TYPE(6'h19)
) aled_0_1 (
.D_OUT_0(aled_0__o[1]),
.PACKAGE_PIN(aled_0__io[1])
);
SB_IO #(
.IO_STANDARD("SB_LVCMOS"),
.PIN_TYPE(6'h19)
) aled_0_2 (
.D_OUT_0(aled_0__o[2]),
.PACKAGE_PIN(aled_0__io[2])
);
SB_IO #(
.IO_STANDARD("SB_LVCMOS"),
.PIN_TYPE(6'h19)
) aled_0_3 (
.D_OUT_0(aled_0__o[3]),
.PACKAGE_PIN(aled_0__io[3])
);
endmodule
(* \amaranth.hierarchy = "top.pin_button_0" *)
(* generator = "Amaranth" *)
module pin_button_0(button_0__io);
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire button_0__i;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout button_0__io;
wire button_0__io;
SB_IO #(
.IO_STANDARD("SB_LVCMOS"),
.PIN_TYPE(6'h01)
) button_0_0 (
.D_IN_0(button_0__i),
.PACKAGE_PIN(button_0__io)
);
endmodule
(* \amaranth.hierarchy = "top.pin_button_1" *)
(* generator = "Amaranth" *)
module pin_button_1(button_1__io);
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire button_1__i;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout button_1__io;
wire button_1__io;
SB_IO #(
.IO_STANDARD("SB_LVCMOS"),
.PIN_TYPE(6'h01)
) button_1_0 (
.D_IN_0(button_1__i),
.PACKAGE_PIN(button_1__io)
);
endmodule
(* \amaranth.hierarchy = "top.pin_kled_0" *)
(* generator = "Amaranth" *)
module pin_kled_0(kled_0__oe, kled_0__io, kled_0__o);
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout kled_0__io;
wire kled_0__io;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
input kled_0__o;
wire kled_0__o;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
input kled_0__oe;
wire kled_0__oe;
SB_IO #(
.IO_STANDARD("SB_LVCMOS"),
.PIN_TYPE(6'h29)
) kled_0_0 (
.D_OUT_0(kled_0__o),
.OUTPUT_ENABLE(kled_0__oe),
.PACKAGE_PIN(kled_0__io)
);
endmodule
(* \amaranth.hierarchy = "top.pin_kled_1" *)
(* generator = "Amaranth" *)
module pin_kled_1(kled_1__oe, kled_1__io, kled_1__o);
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout kled_1__io;
wire kled_1__io;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
input kled_1__o;
wire kled_1__o;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
input kled_1__oe;
wire kled_1__oe;
SB_IO #(
.IO_STANDARD("SB_LVCMOS"),
.PIN_TYPE(6'h29)
) kled_1_0 (
.D_OUT_0(kled_1__o),
.OUTPUT_ENABLE(kled_1__oe),
.PACKAGE_PIN(kled_1__io)
);
endmodule
(* \amaranth.hierarchy = "top.pin_kled_2" *)
(* generator = "Amaranth" *)
module pin_kled_2(kled_2__oe, kled_2__io, kled_2__o);
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout kled_2__io;
wire kled_2__io;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
input kled_2__o;
wire kled_2__o;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
input kled_2__oe;
wire kled_2__oe;
SB_IO #(
.IO_STANDARD("SB_LVCMOS"),
.PIN_TYPE(6'h29)
) kled_2_0 (
.D_OUT_0(kled_2__o),
.OUTPUT_ENABLE(kled_2__oe),
.PACKAGE_PIN(kled_2__io)
);
endmodule
(* \amaranth.hierarchy = "top.pin_kled_3" *)
(* generator = "Amaranth" *)
module pin_kled_3(kled_3__oe, kled_3__io, kled_3__o);
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout kled_3__io;
wire kled_3__io;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
input kled_3__o;
wire kled_3__o;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
input kled_3__oe;
wire kled_3__oe;
SB_IO #(
.IO_STANDARD("SB_LVCMOS"),
.PIN_TYPE(6'h29)
) kled_3_0 (
.D_OUT_0(kled_3__o),
.OUTPUT_ENABLE(kled_3__oe),
.PACKAGE_PIN(kled_3__io)
);
endmodule
(* \amaranth.hierarchy = "top" *)
(* top = 1 *)
(* generator = "Amaranth" *)
module top(button_1__io, kled_0__io, kled_1__io, kled_2__io, kled_3__io, aled_0__io, button_0__io);
reg \$auto$verilog_backend.cc:2083:dump_module$5 = 0;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:99" *)
wire \$1 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:115" *)
wire \$10 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *)
wire \$12 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *)
wire \$14 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:121" *)
wire \$16 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:124" *)
wire \$19 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:115" *)
wire \$20 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:115" *)
wire \$22 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *)
wire \$24 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *)
wire \$26 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:121" *)
wire \$28 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:99" *)
wire \$3 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:124" *)
wire \$31 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:115" *)
wire \$32 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:115" *)
wire \$34 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *)
wire \$36 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *)
wire \$38 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:121" *)
wire \$40 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:124" *)
wire \$43 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *)
wire \$44 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *)
wire \$46 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:121" *)
wire \$48 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:99" *)
wire \$5 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *)
wire \$51 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *)
wire \$53 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:137" *)
wire \$55 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *)
wire \$57 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *)
wire \$59 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:137" *)
wire \$61 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *)
wire \$63 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *)
wire \$65 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:137" *)
wire \$67 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *)
wire \$69 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:124" *)
wire \$7 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *)
wire \$71 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:137" *)
wire \$73 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:142" *)
wire \$75 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:144" *)
wire [4:0] \$77 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:144" *)
wire [4:0] \$78 ;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:115" *)
wire \$8 ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout [3:0] aled_0__io;
wire [3:0] aled_0__io;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout button_0__io;
wire button_0__io;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout button_1__io;
wire button_1__io;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:13" *)
wire button_ffwd_watcher_overflow;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:13" *)
wire button_step_watcher_overflow;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:415" *)
wire clk;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:8" *)
wire [5:0] current_led_count;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:66" *)
reg [15:0] grid = 16'h0000;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:66" *)
reg [15:0] \grid$next ;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout kled_0__io;
wire kled_0__io;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout kled_1__io;
wire kled_1__io;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout kled_2__io;
wire kled_2__io;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:129" *)
inout kled_3__io;
wire kled_3__io;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:69" *)
wire may_light;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:70" *)
wire may_scroll;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire [3:0] pin_aled_0_aled_0__o;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire pin_kled_0_kled_0__o;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire pin_kled_0_kled_0__oe;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire pin_kled_1_kled_1__o;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire pin_kled_1_kled_1__oe;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire pin_kled_2_kled_2__o;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire pin_kled_2_kled_2__oe;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire pin_kled_3_kled_3__o;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/build/res.py:143" *)
wire pin_kled_3_kled_3__oe;
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/vendor/lattice_ice40.py:415" *)
wire rst;
assign \$12 = ! (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *) current_led_count[1:0];
assign \$14 = \$10 & (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *) \$12 ;
assign \$7 = ~ (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:124" *) \$16 ;
assign \$1 = ~ (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:99" *) button_ffwd_watcher_overflow;
assign \$20 = ! (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:115" *) current_led_count[5:4];
assign \$24 = current_led_count[1:0] == (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *) 1'h1;
assign \$26 = \$22 & (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *) \$24 ;
assign \$19 = ~ (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:124" *) \$28 ;
assign \$32 = ! (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:115" *) current_led_count[5:4];
assign \$36 = current_led_count[1:0] == (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *) 2'h2;
assign \$38 = \$34 & (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *) \$36 ;
assign \$3 = ~ (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:99" *) button_step_watcher_overflow;
assign \$31 = ~ (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:124" *) \$40 ;
assign \$44 = current_led_count[1:0] == (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:116" *) 2'h3;
assign \$43 = ~ (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:124" *) \$48 ;
assign \$51 = ! (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *) current_led_count[3:2];
assign \$57 = current_led_count[3:2] == (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *) 1'h1;
assign \$5 = \$1 | (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:99" *) \$3 ;
assign \$63 = current_led_count[3:2] == (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *) 2'h2;
assign \$69 = current_led_count[3:2] == (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:132" *) 2'h3;
assign \$75 = ~ (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:142" *) button_ffwd_watcher_overflow;
assign \$78 = grid[15:12] + (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:144" *) 1'h1;
always @(posedge clk)
grid <= \grid$next ;
assign \$8 = ! (* src = "/Users/mcc/work/f/template-fpga/src/counter.py:115" *) current_led_count[5:4];
button_ffwd_watcher button_ffwd_watcher (
.clk(clk),
.overflow(button_ffwd_watcher_overflow),
.rst(rst)
);
button_step_watcher button_step_watcher (
.clk(clk),
.overflow(button_step_watcher_overflow),
.rst(rst)
);
cd_sync cd_sync (
.clk(clk),
.rst(rst)
);
current_led current_led (
.clk(clk),
.count(current_led_count),
.rst(rst)
);
pin_aled_0 pin_aled_0 (
.aled_0__io(aled_0__io),
.aled_0__o(pin_aled_0_aled_0__o)
);
pin_button_0 pin_button_0 (
.button_0__io(button_0__io)
);
pin_button_1 pin_button_1 (
.button_1__io(button_1__io)
);
pin_kled_0 pin_kled_0 (
.kled_0__io(kled_0__io),
.kled_0__o(1'h1),
.kled_0__oe(pin_kled_0_kled_0__oe)
);
pin_kled_1 pin_kled_1 (
.kled_1__io(kled_1__io),
.kled_1__o(1'h1),
.kled_1__oe(pin_kled_1_kled_1__oe)
);
pin_kled_2 pin_kled_2 (
.kled_2__io(kled_2__io),
.kled_2__o(1'h1),
.kled_2__oe(pin_kled_2_kled_2__oe)
);
pin_kled_3 pin_kled_3 (
.kled_3__io(kled_3__io),
.kled_3__o(1'h1),
.kled_3__oe(pin_kled_3_kled_3__oe)
);
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$5 ) begin end
\grid$next = grid;
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:142" *)
casez (\$75 )
/* src = "/Users/mcc/work/f/template-fpga/src/counter.py:142" */
1'h1:
\grid$next [15:12] = \$78 [3:0];
endcase
(* src = "/Users/mcc/work/f/template-fpga/src/counter.py:146" *)
casez (may_scroll)
/* src = "/Users/mcc/work/f/template-fpga/src/counter.py:146" */
1'h1:
\grid$next [11:0] = grid[15:4];
endcase
(* src = "/Users/mcc/work/f/template-fpga/.venv/lib/pypy3.10/site-packages/amaranth/hdl/xfrm.py:504" *)
casez (rst)
1'h1:
\grid$next = 16'h0000;
endcase
end
assign \$77 = \$78 ;
assign pin_kled_3_kled_3__oe = \$73 ;
assign pin_kled_2_kled_2__oe = \$67 ;
assign pin_kled_1_kled_1__oe = \$61 ;
assign pin_kled_0_kled_0__oe = \$55 ;
assign pin_kled_3_kled_3__o = 1'h1;
assign pin_kled_2_kled_2__o = 1'h1;
assign pin_kled_1_kled_1__o = 1'h1;
assign pin_kled_0_kled_0__o = 1'h1;
assign pin_aled_0_aled_0__o[3] = \$43 ;
assign pin_aled_0_aled_0__o[2] = \$31 ;
assign pin_aled_0_aled_0__o[1] = \$19 ;
assign pin_aled_0_aled_0__o[0] = \$7 ;
assign may_scroll = \$5 ;
assign may_light = 1'h1;
assign \$10 = \$8 ;
assign \$16 = \$14 ;
assign \$22 = \$20 ;
assign \$28 = \$26 ;
assign \$34 = \$32 ;
assign \$40 = \$38 ;
assign \$46 = \$44 ;
assign \$48 = \$44 ;
assign \$53 = \$51 ;
assign \$55 = \$51 ;
assign \$59 = \$57 ;
assign \$61 = \$57 ;
assign \$65 = \$63 ;
assign \$67 = \$63 ;
assign \$71 = \$69 ;
assign \$73 = \$69 ;
endmodule
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment