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Gist for sharing examples with VTR devs
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README.md

Gist for sharing examples with VTR devs

Raw
arch.xml
<?xml version="1.0"?>
<!-- set: ai sw=1 ts=1 sta et -->
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
<!-- ODIN-II model description for non-standard block type -->
<models>
<model name="SB_LUT4">
<input_ports>
<port combinational_sink_ports="O" name="I0"/>
<port combinational_sink_ports="O" name="I1"/>
<port combinational_sink_ports="O" name="I2"/>
<port combinational_sink_ports="O" name="I3"/>
</input_ports>
<output_ports>
<port name="O"/>
</output_ports>
</model>
<model name="SB_DFF">
<input_ports>
<port is_clock="1" name="C"/>
<port clock="C" name="D"/>
</input_ports>
<output_ports>
<port clock="C" name="Q"/>
</output_ports>
</model>
<model name="SB_DFFE">
<input_ports>
<port is_clock="1" name="C"/>
<port clock="C" name="E"/>
<port clock="C" name="D"/>
</input_ports>
<output_ports>
<port clock="C" name="Q"/>
</output_ports>
</model>
<model name="SB_DFFSR">
<input_ports>
<port is_clock="1" name="C"/>
<port clock="C" name="R"/>
<port clock="C" name="D"/>
</input_ports>
<output_ports>
<port clock="C" name="Q"/>
</output_ports>
</model>
<model name="SB_DFFR">
<input_ports>
<port is_clock="1" name="C"/>
<port clock="C" name="R"/>
<port clock="C" name="D"/>
</input_ports>
<output_ports>
<port clock="C" name="Q"/>
</output_ports>
</model>
<model name="SB_DFFSS">
<input_ports>
<port is_clock="1" name="C"/>
<port clock="C" name="S"/>
<port clock="C" name="D"/>
</input_ports>
<output_ports>
<port clock="C" name="Q"/>
</output_ports>
</model>
<model name="SB_DFFS">
<input_ports>
<port is_clock="1" name="C"/>
<port clock="C" name="S"/>
<port clock="C" name="D"/>
</input_ports>
<output_ports>
<port clock="C" name="Q"/>
</output_ports>
</model>
<model name="SB_DFFESR">
<input_ports>
<port is_clock="1" name="C"/>
<port clock="C" name="E"/>
<port clock="C" name="R"/>
<port clock="C" name="D"/>
</input_ports>
<output_ports>
<port clock="C" name="Q"/>
</output_ports>
</model>
<model name="SB_DFFER">
<input_ports>
<port is_clock="1" name="C"/>
<port clock="C" name="E"/>
<port clock="C" name="R"/>
<port clock="C" name="D"/>
</input_ports>
<output_ports>
<port clock="C" name="Q"/>
</output_ports>
</model>
<model name="SB_DFFESS">
<input_ports>
<port is_clock="1" name="C"/>
<port clock="C" name="E"/>
<port clock="C" name="S"/>
<port clock="C" name="D"/>
</input_ports>
<output_ports>
<port clock="C" name="Q"/>
</output_ports>
</model>
<model name="SB_DFFES">
<input_ports>
<port is_clock="1" name="C"/>
<port clock="C" name="E"/>
<port clock="C" name="R"/>
<port clock="C" name="D"/>
</input_ports>
<output_ports>
<port clock="C" name="Q"/>
</output_ports>
</model>
<model name="SB_CARRY">
<input_ports>
<port combinational_sink_ports="CO" name="I0"/>
<!-- I1 -->
<port combinational_sink_ports="CO" name="I1"/>
<!-- I2 -->
<port combinational_sink_ports="CO" name="CI"/>
<!-- FCIN -->
</input_ports>
<output_ports>
<port name="CO"/>
<!-- FCOUT -->
</output_ports>
</model>
<model name="SB_RAM40_4K">
<input_ports>
<!-- Read port -->
<port is_clock="1" name="RCLK"/>
<port clock="RCLK" combinational_sink_ports="RDATA" name="RCLKE"/>
<port clock="RCLK" combinational_sink_ports="RDATA" name="RE"/>
<port clock="RCLK" combinational_sink_ports="RDATA" name="RADDR"/>
<!-- Write port -->
<port is_clock="1" name="WCLK"/>
<port clock="WCLK" combinational_sink_ports="RDATA" name="WCLKE"/>
<port clock="WCLK" combinational_sink_ports="RDATA" name="WE"/>
<port clock="WCLK" combinational_sink_ports="RDATA" name="WADDR"/>
<port clock="WCLK" combinational_sink_ports="RDATA" name="MASK"/>
<port clock="WCLK" combinational_sink_ports="RDATA" name="WDATA"/>
</input_ports>
<output_ports>
<port clock="RCLK" name="RDATA"/>
</output_ports>
</model>
</models>
<!-- Description of the block tiles available in the iCE40 -->
<complexblocklist>
<!-- set: ai sw=1 ts=1 sta et -->
<!-- A diagram for the iCE40 PLB "Logic Cell" is shown in;
http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf
Architecture iCE40 LP/HX Family Data Sheet
* Figure 2-2. PLB Block Diagram
It is 8 x (SB_CARRY + SB_LUT4 + FF)
-->
<pb_type name="BLK_TL-PLB">
<!-- SB_LUT4 inputs -->
<input equivalent="false" name="I0" num_pins="4"/>
<input equivalent="false" name="I1" num_pins="4"/>
<input equivalent="false" name="I2" num_pins="4"/>
<input equivalent="false" name="I3" num_pins="4"/>
<input equivalent="false" name="I4" num_pins="4"/>
<input equivalent="false" name="I5" num_pins="4"/>
<input equivalent="false" name="I6" num_pins="4"/>
<input equivalent="false" name="I7" num_pins="4"/>
<!-- D flip-flop outputs -->
<output equivalent="false" name="O0" num_pins="1"/>
<output equivalent="false" name="O1" num_pins="1"/>
<output equivalent="false" name="O2" num_pins="1"/>
<output equivalent="false" name="O3" num_pins="1"/>
<output equivalent="false" name="O4" num_pins="1"/>
<output equivalent="false" name="O5" num_pins="1"/>
<output equivalent="false" name="O6" num_pins="1"/>
<output equivalent="false" name="O7" num_pins="1"/>
<output equivalent="false" name="FCOUT0" num_pins="1"/>
<output equivalent="false" name="FCOUT1" num_pins="1"/>
<output equivalent="false" name="FCOUT2" num_pins="1"/>
<output equivalent="false" name="FCOUT3" num_pins="1"/>
<output equivalent="false" name="FCOUT4" num_pins="1"/>
<output equivalent="false" name="FCOUT5" num_pins="1"/>
<output equivalent="false" name="FCOUT6" num_pins="1"/>
<output equivalent="false" name="FCOUT7" num_pins="1"/>
<!-- D flip-flop controls -->
<clock equivalent="false" name="CLK" num_pins="1"/>
<input equivalent="false" name="EN" num_pins="1"/>
<input equivalent="false" name="SR" num_pins="1"/>
<!-- Carry chain -->
<input equivalent="false" name="FCIN" num_pins="1"/>
<output equivalent="false" name="FCOUT" num_pins="1"/>
<!-- A BLK_IG-PLB_LOCAL contains the same 'cell' repeated 8 times. -->
<!-- set: ai sw=1 ts=1 sta et -->
<!-- A diagram for the iCE40 PLB "Logic Cell" is shown in;
http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf
Architecture iCE40 LP/HX Family Data Sheet
* Figure 2-2. PLB Block Diagram
It is 8 x (SB_CARRY + SB_LUT4 + FF)
-->
<pb_type name="BLK_IG-PLB_LOCAL" num_pb="1">
<!-- SB_LUT4 inputs -->
<input equivalent="false" name="I0" num_pins="4"/>
<input equivalent="false" name="I1" num_pins="4"/>
<input equivalent="false" name="I2" num_pins="4"/>
<input equivalent="false" name="I3" num_pins="4"/>
<input equivalent="false" name="I4" num_pins="4"/>
<input equivalent="false" name="I5" num_pins="4"/>
<input equivalent="false" name="I6" num_pins="4"/>
<input equivalent="false" name="I7" num_pins="4"/>
<!-- D flip-flop outputs -->
<output equivalent="false" name="O0" num_pins="1"/>
<output equivalent="false" name="O1" num_pins="1"/>
<output equivalent="false" name="O2" num_pins="1"/>
<output equivalent="false" name="O3" num_pins="1"/>
<output equivalent="false" name="O4" num_pins="1"/>
<output equivalent="false" name="O5" num_pins="1"/>
<output equivalent="false" name="O6" num_pins="1"/>
<output equivalent="false" name="O7" num_pins="1"/>
<output equivalent="false" name="FCOUT0" num_pins="1"/>
<output equivalent="false" name="FCOUT1" num_pins="1"/>
<output equivalent="false" name="FCOUT2" num_pins="1"/>
<output equivalent="false" name="FCOUT3" num_pins="1"/>
<output equivalent="false" name="FCOUT4" num_pins="1"/>
<output equivalent="false" name="FCOUT5" num_pins="1"/>
<output equivalent="false" name="FCOUT6" num_pins="1"/>
<output equivalent="false" name="FCOUT7" num_pins="1"/>
<!-- D flip-flop controls -->
<clock equivalent="false" name="CLK" num_pins="1"/>
<input equivalent="false" name="EN" num_pins="1"/>
<input equivalent="false" name="SR" num_pins="1"/>
<!-- Carry chain -->
<input equivalent="false" name="FCIN" num_pins="1"/>
<output equivalent="false" name="FCOUT" num_pins="1"/>
<pb_type name="BLK_IG-LUT_CARRY" num_pb="8">
<input equivalent="false" name="I" num_pins="4"/>
<output equivalent="false" name="O" num_pins="1"/>
<input equivalent="false" name="FCIN" num_pins="1"/>
<output equivalent="false" name="FCOUT" num_pins="1"/>
<!-- set: ai sw=1 ts=1 sta et -->
<!-- 4 input LUT found in the ICE40 -->
<pb_type name="LUT" num_pb="1">
<input name="I" num_pins="4"/>
<output name="O" num_pins="1"/>
<!--
FIXME: The VPR LUT mode must be first, otherwise VPR can't route
through the LUT.
-->
<mode name="VPR_LUT4">
<pb_type blif_model=".names" class="lut" name="LUT4" num_pb="1">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<delay_matrix in_port="LUT4.in" out_port="LUT4.out" type="max">
10e-12
10e-12
10e-12
10e-12
</delay_matrix>
</pb_type>
<interconnect>
<direct input="LUT.I" name="I" output="LUT4.in"/>
<direct input="LUT4.out" name="O" output="LUT.O"/>
</interconnect>
</mode>
<mode name="SB_LUT4">
<pb_type blif_model=".subckt SB_LUT4" name="SB_LUT4" num_pb="1">
<input name="I0" num_pins="1"/>
<input name="I1" num_pins="1"/>
<input name="I2" num_pins="1"/>
<input name="I3" num_pins="1"/>
<output name="O" num_pins="1"/>
<delay_constant in_port="SB_LUT4.I0" max="10e-12" out_port="SB_LUT4.O"/>
<delay_constant in_port="SB_LUT4.I1" max="10e-12" out_port="SB_LUT4.O"/>
<delay_constant in_port="SB_LUT4.I2" max="10e-12" out_port="SB_LUT4.O"/>
<delay_constant in_port="SB_LUT4.I3" max="10e-12" out_port="SB_LUT4.O"/>
</pb_type>
<interconnect>
<direct input="LUT.I[0:0]" name="I0" output="SB_LUT4.I0"/>
<direct input="LUT.I[1:1]" name="I1" output="SB_LUT4.I1"/>
<direct input="LUT.I[2:2]" name="I2" output="SB_LUT4.I2"/>
<direct input="LUT.I[3:3]" name="I3" output="SB_LUT4.I3"/>
<direct input="SB_LUT4.O" name="O" output="LUT.O"/>
</interconnect>
</mode>
</pb_type>
<!-- set: ai sw=1 ts=1 sta et -->
<!-- Carry logic found in the ICE40 -->
<pb_type blif_model=".subckt SB_CARRY" name="SB_CARRY" num_pb="1">
<input name="I1" num_pins="1"/>
<input name="CI" num_pins="1"/>
<input name="I0" num_pins="1"/>
<output name="CO" num_pins="1"/>
<delay_constant in_port="SB_CARRY.CI" max="10e-12" out_port="SB_CARRY.CO"/>
<delay_constant in_port="SB_CARRY.I1" max="10e-12" out_port="SB_CARRY.CO"/>
<delay_constant in_port="SB_CARRY.I0" max="10e-12" out_port="SB_CARRY.CO"/>
</pb_type>
<interconnect>
<direct input="BLK_IG-LUT_CARRY.I[0]" name="LUT.I[0]" output="LUT.I[0]"/>
<direct input="BLK_IG-LUT_CARRY.I[1]" name="LUT.I[1]" output="LUT.I[1]"/>
<direct input="BLK_IG-LUT_CARRY.I[2]" name="LUT.I[2]" output="LUT.I[2]"/>
<!-- Disable FCIN->I3 mux until https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/325 is fixed.
<mux name="LUT.I[3]" input="BLK_IG-LUT_CARRY.I[3] BLK_IG-LUT_CARRY.FCIN" output="LUT.I[3]" /> -->
<direct input="BLK_IG-LUT_CARRY.I[3]" name="LUT.I[3]" output="LUT.I[3]"/>
<direct input="LUT.O" name="LUT.O" output="BLK_IG-LUT_CARRY.O"/>
<direct input="BLK_IG-LUT_CARRY.I[1]" name="SB_CARRY.I0" output="SB_CARRY.I0"/>
<direct input="BLK_IG-LUT_CARRY.I[2]" name="SB_CARRY.I1" output="SB_CARRY.I1"/>
<direct input="BLK_IG-LUT_CARRY.FCIN" name="BLK_IG-LUT_CARRY.FCIN" output="SB_CARRY.CI">
<pack_pattern in_port="BLK_IG-LUT_CARRY.FCIN" name="CARRYCHAIN" out_port="SB_CARRY.CI"/>
</direct>
<direct input="SB_CARRY.CO" name="BLK_IG-LUT_CARRY.FCOUT" output="BLK_IG-LUT_CARRY.FCOUT">
<pack_pattern in_port="SB_CARRY.CO" name="CARRYCHAIN" out_port="BLK_IG-LUT_CARRY.FCOUT"/>
</direct>
</interconnect>
</pb_type>
<pb_type name="BLK_IG-FF_ARRAY" num_pb="1">
<input equivalent="false" name="D" num_pins="8"/>
<output equivalent="false" name="Q" num_pins="8"/>
<clock equivalent="false" name="CLK" num_pins="1"/>
<input equivalent="false" name="EN" num_pins="1"/>
<input equivalent="false" name="SR" num_pins="1"/>
<mode name="dff">
<pb_type name="BLK_IG-FF" num_pb="8">
<input equivalent="false" name="D" num_pins="1"/>
<output equivalent="false" name="Q" num_pins="1"/>
<clock name="CLK" num_pins="1"/>
<input equivalent="false" name="EN" num_pins="1"/>
<input equivalent="false" name="SR" num_pins="1"/>
<!-- set: ai sw=1 ts=1 sta et -->
<!-- Flip flop found inside the iCE40 -->
<pb_type name="DFF" num_pb="1">
<clock name="C" num_pins="1"/>
<input name="E" num_pins="1"/>
<input name="S" num_pins="1"/>
<input name="D" num_pins="1"/>
<output name="Q" num_pins="1"/>
<!-- Plain VPR flip flop -->
<mode name="VPR_FF">
<pb_type blif_model=".latch" class="flipflop" name="VPR_FF" num_pb="1">
<clock name="clk" num_pins="1" port_class="clock"/>
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<T_setup clock="clk" port="VPR_FF.D" value="10e-12"/>
<T_clock_to_Q clock="clk" max="10e-12" port="VPR_FF.Q"/>
</pb_type>
<interconnect>
<direct input="DFF.C" name="C" output="VPR_FF.clk"/>
<direct input="DFF.D" name="D" output="VPR_FF.D"/>
<direct input="VPR_FF.Q" name="Q" output="DFF.Q"/>
</interconnect>
</mode>
<!-- module SB_DFF (output Q, input C, D); -->
<mode name="SB_DFF">
<pb_type blif_model=".subckt SB_DFF" name="SB_DFF" num_pb="1">
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<input name="D" num_pins="1"/>
<T_clock_to_Q clock="C" max="10e-12" port="SB_DFF.Q"/>
<T_setup clock="C" port="SB_DFF.D" value="10e-12"/>
</pb_type>
<interconnect>
<direct input="SB_DFF.Q" name="Q" output="DFF.Q"/>
<direct input="DFF.C" name="C" output="SB_DFF.C"/>
<direct input="DFF.D" name="D" output="SB_DFF.D"/>
</interconnect>
</mode>
</pb_type>
<!-- set: ai sw=1 ts=1 sta et -->
<interconnect>
<direct input="BLK_IG-FF.D" name="D" output="DFF.D"/>
<direct input="DFF.Q" name="Q" output="BLK_IG-FF.Q"/>
<direct input="BLK_IG-FF.EN" name="EN" output="DFF.E"/>
<direct input="BLK_IG-FF.CLK" name="CLK" output="DFF.C"/>
<direct input="BLK_IG-FF.SR" name="SR" output="DFF.S"/>
</interconnect>
</pb_type>
<!-- set: ai sw=1 ts=1 sta et -->
<interconnect>
<direct input="BLK_IG-FF_ARRAY.D[7:0]" name="D" output="BLK_IG-FF[7:0].D"/>
<direct input="BLK_IG-FF[7:0].Q" name="Q" output="BLK_IG-FF_ARRAY.Q[7:0]"/>
<complete input="BLK_IG-FF_ARRAY.CLK" name="CLK" output="BLK_IG-FF[7:0].CLK"/>
<complete input="BLK_IG-FF_ARRAY.SR" name="SR" output="BLK_IG-FF[7:0].SR"/>
<complete input="BLK_IG-FF_ARRAY.EN" name="EN" output="BLK_IG-FF[7:0].EN"/>
</interconnect>
</mode>
<mode name="dffe">
<pb_type name="BLK_IG-FF" num_pb="8">
<input equivalent="false" name="D" num_pins="1"/>
<output equivalent="false" name="Q" num_pins="1"/>
<clock name="CLK" num_pins="1"/>
<input equivalent="false" name="EN" num_pins="1"/>
<input equivalent="false" name="SR" num_pins="1"/>
<!-- set: ai sw=1 ts=1 sta et -->
<!-- Flip flop found inside the iCE40 -->
<pb_type name="DFF" num_pb="1">
<clock name="C" num_pins="1"/>
<input name="E" num_pins="1"/>
<input name="S" num_pins="1"/>
<input name="D" num_pins="1"/>
<output name="Q" num_pins="1"/>
<!-- module SB_DFFE (output Q, input C, E, D); -->
<mode name="SB_DFFE">
<pb_type blif_model=".subckt SB_DFFE" name="SB_DFFE" num_pb="1">
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<input name="E" num_pins="1"/>
<input name="D" num_pins="1"/>
<T_clock_to_Q clock="C" max="10e-12" port="SB_DFFE.Q"/>
<T_setup clock="C" port="SB_DFFE.E" value="10e-12"/>
<T_setup clock="C" port="SB_DFFE.D" value="10e-12"/>
</pb_type>
<interconnect>
<direct input="SB_DFFE.Q" name="Q" output="DFF.Q"/>
<direct input="DFF.C" name="C" output="SB_DFFE.C"/>
<direct input="DFF.E" name="E" output="SB_DFFE.E"/>
<direct input="DFF.D" name="D" output="SB_DFFE.D"/>
</interconnect>
</mode>
</pb_type>
<!-- set: ai sw=1 ts=1 sta et -->
<interconnect>
<direct input="BLK_IG-FF.D" name="D" output="DFF.D"/>
<direct input="DFF.Q" name="Q" output="BLK_IG-FF.Q"/>
<direct input="BLK_IG-FF.EN" name="EN" output="DFF.E"/>
<direct input="BLK_IG-FF.CLK" name="CLK" output="DFF.C"/>
<direct input="BLK_IG-FF.SR" name="SR" output="DFF.S"/>
</interconnect>
</pb_type>
<!-- set: ai sw=1 ts=1 sta et -->
<interconnect>
<direct input="BLK_IG-FF_ARRAY.D[7:0]" name="D" output="BLK_IG-FF[7:0].D"/>
<direct input="BLK_IG-FF[7:0].Q" name="Q" output="BLK_IG-FF_ARRAY.Q[7:0]"/>
<complete input="BLK_IG-FF_ARRAY.CLK" name="CLK" output="BLK_IG-FF[7:0].CLK"/>
<complete input="BLK_IG-FF_ARRAY.SR" name="SR" output="BLK_IG-FF[7:0].SR"/>
<complete input="BLK_IG-FF_ARRAY.EN" name="EN" output="BLK_IG-FF[7:0].EN"/>
</interconnect>
</mode>
<mode name="dffs">
<pb_type name="BLK_IG-FF" num_pb="8">
<input equivalent="false" name="D" num_pins="1"/>
<output equivalent="false" name="Q" num_pins="1"/>
<clock name="CLK" num_pins="1"/>
<input equivalent="false" name="EN" num_pins="1"/>
<input equivalent="false" name="SR" num_pins="1"/>
<!-- set: ai sw=1 ts=1 sta et -->
<!-- Flip flop found inside the iCE40 -->
<pb_type name="DFF" num_pb="1">
<clock name="C" num_pins="1"/>
<input name="E" num_pins="1"/>
<input name="S" num_pins="1"/>
<input name="D" num_pins="1"/>
<output name="Q" num_pins="1"/>
<!-- module SB_DFFSR (output Q, input C, R, D); -->
<mode name="SB_DFFSR">
<pb_type blif_model=".subckt SB_DFFSR" name="SB_DFFSR" num_pb="1">
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<input name="R" num_pins="1"/>
<input name="D" num_pins="1"/>
<T_clock_to_Q clock="C" max="10e-12" port="SB_DFFSR.Q"/>
<T_setup clock="C" port="SB_DFFSR.R" value="10e-12"/>
<T_setup clock="C" port="SB_DFFSR.D" value="10e-12"/>
</pb_type>
<interconnect>
<direct input="SB_DFFSR.Q" name="Q" output="DFF.Q"/>
<direct input="DFF.C" name="C" output="SB_DFFSR.C"/>
<direct input="DFF.S" name="S" output="SB_DFFSR.R"/>
<direct input="DFF.D" name="D" output="SB_DFFSR.D"/>
</interconnect>
</mode>
<!-- module SB_DFFR (output Q, input C, R, D); -->
<mode name="SB_DFFR">
<pb_type blif_model=".subckt SB_DFFR" name="SB_DFFR" num_pb="1">
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<input name="R" num_pins="1"/>
<input name="D" num_pins="1"/>
<T_clock_to_Q clock="C" max="10e-12" port="SB_DFFR.Q"/>
<T_setup clock="C" port="SB_DFFR.R" value="10e-12"/>
<T_setup clock="C" port="SB_DFFR.D" value="10e-12"/>
</pb_type>
<interconnect>
<direct input="SB_DFFR.Q" name="Q" output="DFF.Q"/>
<direct input="DFF.C" name="C" output="SB_DFFR.C"/>
<direct input="DFF.S" name="S" output="SB_DFFR.R"/>
<direct input="DFF.D" name="D" output="SB_DFFR.D"/>
</interconnect>
</mode>
<!-- module SB_DFFSS (output Q, input C, S, D); -->
<mode name="SB_DFFSS">
<pb_type blif_model=".subckt SB_DFFSS" name="SB_DFFSS" num_pb="1">
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<input name="S" num_pins="1"/>
<input name="D" num_pins="1"/>
<T_clock_to_Q clock="C" max="10e-12" port="SB_DFFSS.Q"/>
<T_setup clock="C" port="SB_DFFSS.S" value="10e-12"/>
<T_setup clock="C" port="SB_DFFSS.D" value="10e-12"/>
</pb_type>
<interconnect>
<direct input="SB_DFFSS.Q" name="Q" output="DFF.Q"/>
<direct input="DFF.C" name="C" output="SB_DFFSS.C"/>
<direct input="DFF.S" name="S" output="SB_DFFSS.S"/>
<direct input="DFF.D" name="D" output="SB_DFFSS.D"/>
</interconnect>
</mode>
<!-- module SB_DFFS (output Q, input C, S, D); -->
<mode name="SB_DFFS">
<pb_type blif_model=".subckt SB_DFFS" name="SB_DFFS" num_pb="1">
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<input name="S" num_pins="1"/>
<input name="D" num_pins="1"/>
<T_clock_to_Q clock="C" max="10e-12" port="SB_DFFS.Q"/>
<T_setup clock="C" port="SB_DFFS.S" value="10e-12"/>
<T_setup clock="C" port="SB_DFFS.D" value="10e-12"/>
</pb_type>
<interconnect>
<direct input="SB_DFFS.Q" name="Q" output="DFF.Q"/>
<direct input="DFF.C" name="C" output="SB_DFFS.C"/>
<direct input="DFF.S" name="S" output="SB_DFFS.S"/>
<direct input="DFF.D" name="D" output="SB_DFFS.D"/>
</interconnect>
</mode>
</pb_type>
<!-- set: ai sw=1 ts=1 sta et -->
<interconnect>
<direct input="BLK_IG-FF.D" name="D" output="DFF.D"/>
<direct input="DFF.Q" name="Q" output="BLK_IG-FF.Q"/>
<direct input="BLK_IG-FF.EN" name="EN" output="DFF.E"/>
<direct input="BLK_IG-FF.CLK" name="CLK" output="DFF.C"/>
<direct input="BLK_IG-FF.SR" name="SR" output="DFF.S"/>
</interconnect>
</pb_type>
<!-- set: ai sw=1 ts=1 sta et -->
<interconnect>
<direct input="BLK_IG-FF_ARRAY.D[7:0]" name="D" output="BLK_IG-FF[7:0].D"/>
<direct input="BLK_IG-FF[7:0].Q" name="Q" output="BLK_IG-FF_ARRAY.Q[7:0]"/>
<complete input="BLK_IG-FF_ARRAY.CLK" name="CLK" output="BLK_IG-FF[7:0].CLK"/>
<complete input="BLK_IG-FF_ARRAY.SR" name="SR" output="BLK_IG-FF[7:0].SR"/>
<complete input="BLK_IG-FF_ARRAY.EN" name="EN" output="BLK_IG-FF[7:0].EN"/>
</interconnect>
</mode>
<mode name="dffes">
<pb_type name="BLK_IG-FF" num_pb="8">
<input equivalent="false" name="D" num_pins="1"/>
<output equivalent="false" name="Q" num_pins="1"/>
<clock name="CLK" num_pins="1"/>
<input equivalent="false" name="EN" num_pins="1"/>
<input equivalent="false" name="SR" num_pins="1"/>
<!-- set: ai sw=1 ts=1 sta et -->
<!-- Flip flop found inside the iCE40 -->
<pb_type name="DFF" num_pb="1">
<clock name="C" num_pins="1"/>
<input name="E" num_pins="1"/>
<input name="S" num_pins="1"/>
<input name="D" num_pins="1"/>
<output name="Q" num_pins="1"/>
<!-- module SB_DFFESR (output Q, input C, E, R, D); -->
<mode name="SB_DFFESR">
<pb_type blif_model=".subckt SB_DFFESR" name="SB_DFFESR" num_pb="1">
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<input name="E" num_pins="1"/>
<input name="R" num_pins="1"/>
<input name="D" num_pins="1"/>
<T_clock_to_Q clock="C" max="10e-12" port="SB_DFFESR.Q"/>
<T_setup clock="C" port="SB_DFFESR.E" value="10e-12"/>
<T_setup clock="C" port="SB_DFFESR.R" value="10e-12"/>
<T_setup clock="C" port="SB_DFFESR.D" value="10e-12"/>
</pb_type>
<interconnect>
<direct input="SB_DFFESR.Q" name="Q" output="DFF.Q"/>
<direct input="DFF.C" name="C" output="SB_DFFESR.C"/>
<direct input="DFF.E" name="E" output="SB_DFFESR.E"/>
<direct input="DFF.S" name="S" output="SB_DFFESR.R"/>
<direct input="DFF.D" name="D" output="SB_DFFESR.D"/>
</interconnect>
</mode>
<!-- module SB_DFFER (output Q, input C, E, R, D); -->
<mode name="SB_DFFER">
<pb_type blif_model=".subckt SB_DFFER" name="SB_DFFER" num_pb="1">
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<input name="E" num_pins="1"/>
<input name="R" num_pins="1"/>
<input name="D" num_pins="1"/>
<T_clock_to_Q clock="C" max="10e-12" port="SB_DFFER.Q"/>
<T_setup clock="C" port="SB_DFFER.E" value="10e-12"/>
<T_setup clock="C" port="SB_DFFER.R" value="10e-12"/>
<T_setup clock="C" port="SB_DFFER.D" value="10e-12"/>
</pb_type>
<interconnect>
<direct input="SB_DFFER.Q" name="Q" output="DFF.Q"/>
<direct input="DFF.C" name="C" output="SB_DFFER.C"/>
<direct input="DFF.E" name="E" output="SB_DFFER.E"/>
<direct input="DFF.S" name="S" output="SB_DFFER.R"/>
<direct input="DFF.D" name="D" output="SB_DFFER.D"/>
</interconnect>
</mode>
<!-- module SB_DFFESS (output Q, input C, E, S, D); -->
<mode name="SB_DFFESS">
<pb_type blif_model=".subckt SB_DFFESS" name="SB_DFFESS" num_pb="1">
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<input name="E" num_pins="1"/>
<input name="S" num_pins="1"/>
<input name="D" num_pins="1"/>
<T_clock_to_Q clock="C" max="10e-12" port="SB_DFFESS.Q"/>
<T_setup clock="C" port="SB_DFFESS.E" value="10e-12"/>
<T_setup clock="C" port="SB_DFFESS.S" value="10e-12"/>
<T_setup clock="C" port="SB_DFFESS.D" value="10e-12"/>
</pb_type>
<interconnect>
<direct input="SB_DFFESS.Q" name="Q" output="DFF.Q"/>
<direct input="DFF.C" name="C" output="SB_DFFESS.C"/>
<direct input="DFF.E" name="E" output="SB_DFFESS.E"/>
<direct input="DFF.S" name="S" output="SB_DFFESS.S"/>
<direct input="DFF.D" name="D" output="SB_DFFESS.D"/>
</interconnect>
</mode>
<!-- module SB_DFFES (output Q, input C, E, R, D); -->
<mode name="SB_DFFES">
<pb_type blif_model=".subckt SB_DFFES" name="SB_DFFES" num_pb="1">
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<input name="E" num_pins="1"/>
<input name="R" num_pins="1"/>
<input name="D" num_pins="1"/>
<T_clock_to_Q clock="C" max="10e-12" port="SB_DFFES.Q"/>
<T_setup clock="C" port="SB_DFFES.E" value="10e-12"/>
<T_setup clock="C" port="SB_DFFES.R" value="10e-12"/>
<T_setup clock="C" port="SB_DFFES.D" value="10e-12"/>
</pb_type>
<interconnect>
<direct input="SB_DFFES.Q" name="Q" output="DFF.Q"/>
<direct input="DFF.C" name="C" output="SB_DFFES.C"/>
<direct input="DFF.E" name="E" output="SB_DFFES.E"/>
<direct input="DFF.S" name="S" output="SB_DFFES.R"/>
<direct input="DFF.D" name="D" output="SB_DFFES.D"/>
</interconnect>
</mode>
</pb_type>
<!-- set: ai sw=1 ts=1 sta et -->
<interconnect>
<direct input="BLK_IG-FF.D" name="D" output="DFF.D"/>
<direct input="DFF.Q" name="Q" output="BLK_IG-FF.Q"/>
<direct input="BLK_IG-FF.EN" name="EN" output="DFF.E"/>
<direct input="BLK_IG-FF.CLK" name="CLK" output="DFF.C"/>
<direct input="BLK_IG-FF.SR" name="SR" output="DFF.S"/>
</interconnect>
</pb_type>
<!-- set: ai sw=1 ts=1 sta et -->
<interconnect>
<direct input="BLK_IG-FF_ARRAY.D[7:0]" name="D" output="BLK_IG-FF[7:0].D"/>
<direct input="BLK_IG-FF[7:0].Q" name="Q" output="BLK_IG-FF_ARRAY.Q[7:0]"/>
<complete input="BLK_IG-FF_ARRAY.CLK" name="CLK" output="BLK_IG-FF[7:0].CLK"/>
<complete input="BLK_IG-FF_ARRAY.SR" name="SR" output="BLK_IG-FF[7:0].SR"/>
<complete input="BLK_IG-FF_ARRAY.EN" name="EN" output="BLK_IG-FF[7:0].EN"/>
</interconnect>
</mode>
</pb_type>
<interconnect>
<direct input="BLK_IG-PLB_LOCAL.I0[0]" name="I0[0]" output="BLK_IG-LUT_CARRY[0].I[0]"/>
<direct input="BLK_IG-PLB_LOCAL.I0[1]" name="I0[1]" output="BLK_IG-LUT_CARRY[0].I[1]"/>
<direct input="BLK_IG-PLB_LOCAL.I0[2]" name="I0[2]" output="BLK_IG-LUT_CARRY[0].I[2]"/>
<direct input="BLK_IG-PLB_LOCAL.I0[3]" name="I0[3]" output="BLK_IG-LUT_CARRY[0].I[3]"/>
<direct input="BLK_IG-PLB_LOCAL.I1[0]" name="I1[0]" output="BLK_IG-LUT_CARRY[1].I[0]"/>
<direct input="BLK_IG-PLB_LOCAL.I1[1]" name="I1[1]" output="BLK_IG-LUT_CARRY[1].I[1]"/>
<mux input="BLK_IG-PLB_LOCAL.I1[2] BLK_IG-LUT_CARRY[0].O" name="I1[2]" output="BLK_IG-LUT_CARRY[1].I[2]"/>
<direct input="BLK_IG-PLB_LOCAL.I1[3]" name="I1[3]" output="BLK_IG-LUT_CARRY[1].I[3]"/>
<direct input="BLK_IG-PLB_LOCAL.I2[0]" name="I2[0]" output="BLK_IG-LUT_CARRY[2].I[0]"/>
<direct input="BLK_IG-PLB_LOCAL.I2[1]" name="I2[1]" output="BLK_IG-LUT_CARRY[2].I[1]"/>
<mux input="BLK_IG-PLB_LOCAL.I2[2] BLK_IG-LUT_CARRY[1].O" name="I2[2]" output="BLK_IG-LUT_CARRY[2].I[2]"/>
<direct input="BLK_IG-PLB_LOCAL.I2[3]" name="I2[3]" output="BLK_IG-LUT_CARRY[2].I[3]"/>
<direct input="BLK_IG-PLB_LOCAL.I3[0]" name="I3[0]" output="BLK_IG-LUT_CARRY[3].I[0]"/>
<direct input="BLK_IG-PLB_LOCAL.I3[1]" name="I3[1]" output="BLK_IG-LUT_CARRY[3].I[1]"/>
<mux input="BLK_IG-PLB_LOCAL.I3[2] BLK_IG-LUT_CARRY[2].O" name="I3[2]" output="BLK_IG-LUT_CARRY[3].I[2]"/>
<direct input="BLK_IG-PLB_LOCAL.I3[3]" name="I3[3]" output="BLK_IG-LUT_CARRY[3].I[3]"/>
<direct input="BLK_IG-PLB_LOCAL.I4[0]" name="I4[0]" output="BLK_IG-LUT_CARRY[4].I[0]"/>
<direct input="BLK_IG-PLB_LOCAL.I4[1]" name="I4[1]" output="BLK_IG-LUT_CARRY[4].I[1]"/>
<mux input="BLK_IG-PLB_LOCAL.I4[2] BLK_IG-LUT_CARRY[3].O" name="I4[2]" output="BLK_IG-LUT_CARRY[4].I[2]"/>
<direct input="BLK_IG-PLB_LOCAL.I4[3]" name="I4[3]" output="BLK_IG-LUT_CARRY[4].I[3]"/>
<direct input="BLK_IG-PLB_LOCAL.I5[0]" name="I5[0]" output="BLK_IG-LUT_CARRY[5].I[0]"/>
<direct input="BLK_IG-PLB_LOCAL.I5[1]" name="I5[1]" output="BLK_IG-LUT_CARRY[5].I[1]"/>
<mux input="BLK_IG-PLB_LOCAL.I5[2] BLK_IG-LUT_CARRY[4].O" name="I5[2]" output="BLK_IG-LUT_CARRY[5].I[2]"/>
<direct input="BLK_IG-PLB_LOCAL.I5[3]" name="I5[3]" output="BLK_IG-LUT_CARRY[5].I[3]"/>
<direct input="BLK_IG-PLB_LOCAL.I6[0]" name="I6[0]" output="BLK_IG-LUT_CARRY[6].I[0]"/>
<direct input="BLK_IG-PLB_LOCAL.I6[1]" name="I6[1]" output="BLK_IG-LUT_CARRY[6].I[1]"/>
<mux input="BLK_IG-PLB_LOCAL.I6[2] BLK_IG-LUT_CARRY[5].O" name="I6[2]" output="BLK_IG-LUT_CARRY[6].I[2]"/>
<direct input="BLK_IG-PLB_LOCAL.I6[3]" name="I6[3]" output="BLK_IG-LUT_CARRY[6].I[3]"/>
<direct input="BLK_IG-PLB_LOCAL.I7[0]" name="I7[0]" output="BLK_IG-LUT_CARRY[7].I[0]"/>
<direct input="BLK_IG-PLB_LOCAL.I7[1]" name="I7[1]" output="BLK_IG-LUT_CARRY[7].I[1]"/>
<mux input="BLK_IG-PLB_LOCAL.I7[2] BLK_IG-LUT_CARRY[6].O" name="I7[2]" output="BLK_IG-LUT_CARRY[7].I[2]"/>
<direct input="BLK_IG-PLB_LOCAL.I7[3]" name="I7[3]" output="BLK_IG-LUT_CARRY[7].I[3]"/>
<direct input="BLK_IG-LUT_CARRY[7:0].O" name="LUT2FF" output="BLK_IG-FF_ARRAY.D[7:0]"/>
<mux input="BLK_IG-LUT_CARRY[0].O BLK_IG-FF_ARRAY.Q[0]" name="O0" output="BLK_IG-PLB_LOCAL.O0"/>
<mux input="BLK_IG-LUT_CARRY[1].O BLK_IG-FF_ARRAY.Q[1]" name="O1" output="BLK_IG-PLB_LOCAL.O1"/>
<mux input="BLK_IG-LUT_CARRY[2].O BLK_IG-FF_ARRAY.Q[2]" name="O2" output="BLK_IG-PLB_LOCAL.O2"/>
<mux input="BLK_IG-LUT_CARRY[3].O BLK_IG-FF_ARRAY.Q[3]" name="O3" output="BLK_IG-PLB_LOCAL.O3"/>
<mux input="BLK_IG-LUT_CARRY[4].O BLK_IG-FF_ARRAY.Q[4]" name="O4" output="BLK_IG-PLB_LOCAL.O4"/>
<mux input="BLK_IG-LUT_CARRY[5].O BLK_IG-FF_ARRAY.Q[5]" name="O5" output="BLK_IG-PLB_LOCAL.O5"/>
<mux input="BLK_IG-LUT_CARRY[6].O BLK_IG-FF_ARRAY.Q[6]" name="O6" output="BLK_IG-PLB_LOCAL.O6"/>
<mux input="BLK_IG-LUT_CARRY[7].O BLK_IG-FF_ARRAY.Q[7]" name="O7" output="BLK_IG-PLB_LOCAL.O7"/>
<complete input="BLK_IG-PLB_LOCAL.CLK" name="CLK" output="BLK_IG-FF_ARRAY.CLK"/>
<complete input="BLK_IG-PLB_LOCAL.SR" name="SR" output="BLK_IG-FF_ARRAY.SR"/>
<complete input="BLK_IG-PLB_LOCAL.EN" name="EN" output="BLK_IG-FF_ARRAY.EN"/>
<direct input="BLK_IG-LUT_CARRY[0].FCOUT" name="FCOUT0" output="BLK_IG-PLB_LOCAL.FCOUT0"/>
<direct input="BLK_IG-LUT_CARRY[1].FCOUT" name="FCOUT1" output="BLK_IG-PLB_LOCAL.FCOUT1"/>
<direct input="BLK_IG-LUT_CARRY[2].FCOUT" name="FCOUT2" output="BLK_IG-PLB_LOCAL.FCOUT2"/>
<direct input="BLK_IG-LUT_CARRY[3].FCOUT" name="FCOUT3" output="BLK_IG-PLB_LOCAL.FCOUT3"/>
<direct input="BLK_IG-LUT_CARRY[4].FCOUT" name="FCOUT4" output="BLK_IG-PLB_LOCAL.FCOUT4"/>
<direct input="BLK_IG-LUT_CARRY[5].FCOUT" name="FCOUT5" output="BLK_IG-PLB_LOCAL.FCOUT5"/>
<direct input="BLK_IG-LUT_CARRY[6].FCOUT" name="FCOUT6" output="BLK_IG-PLB_LOCAL.FCOUT6"/>
<direct input="BLK_IG-LUT_CARRY[7].FCOUT" name="FCOUT7" output="BLK_IG-PLB_LOCAL.FCOUT7"/>
<direct input="BLK_IG-PLB_LOCAL.FCIN" name="FCIN" output="BLK_IG-LUT_CARRY[0].FCIN">
<pack_pattern in_port="BLK_IG-PLB_LOCAL.FCIN" name="CARRYCHAIN" out_port="BLK_IG-LUT_CARRY[0].FCIN"/>
</direct>
<direct input="BLK_IG-LUT_CARRY[0].FCOUT" name="FCC0" output="BLK_IG-LUT_CARRY[1].FCIN">
<pack_pattern in_port="BLK_IG-LUT_CARRY[0].FCOUT" name="CARRYCHAIN" out_port="BLK_IG-LUT_CARRY[1].FCIN"/>
</direct>
<direct input="BLK_IG-LUT_CARRY[1].FCOUT" name="FCC1" output="BLK_IG-LUT_CARRY[2].FCIN">
<pack_pattern in_port="BLK_IG-LUT_CARRY[1].FCOUT" name="CARRYCHAIN" out_port="BLK_IG-LUT_CARRY[2].FCIN"/>
</direct>
<direct input="BLK_IG-LUT_CARRY[2].FCOUT" name="FCC2" output="BLK_IG-LUT_CARRY[3].FCIN">
<pack_pattern in_port="BLK_IG-LUT_CARRY[2].FCOUT" name="CARRYCHAIN" out_port="BLK_IG-LUT_CARRY[3].FCIN"/>
</direct>
<direct input="BLK_IG-LUT_CARRY[3].FCOUT" name="FCC3" output="BLK_IG-LUT_CARRY[4].FCIN">
<pack_pattern in_port="BLK_IG-LUT_CARRY[3].FCOUT" name="CARRYCHAIN" out_port="BLK_IG-LUT_CARRY[4].FCIN"/>
</direct>
<direct input="BLK_IG-LUT_CARRY[4].FCOUT" name="FCC4" output="BLK_IG-LUT_CARRY[5].FCIN">
<pack_pattern in_port="BLK_IG-LUT_CARRY[4].FCOUT" name="CARRYCHAIN" out_port="BLK_IG-LUT_CARRY[5].FCIN"/>
</direct>
<direct input="BLK_IG-LUT_CARRY[5].FCOUT" name="FCC5" output="BLK_IG-LUT_CARRY[6].FCIN">
<pack_pattern in_port="BLK_IG-LUT_CARRY[5].FCOUT" name="CARRYCHAIN" out_port="BLK_IG-LUT_CARRY[6].FCIN"/>
</direct>
<direct input="BLK_IG-LUT_CARRY[6].FCOUT" name="FCC6" output="BLK_IG-LUT_CARRY[7].FCIN">
<pack_pattern in_port="BLK_IG-LUT_CARRY[6].FCOUT" name="CARRYCHAIN" out_port="BLK_IG-LUT_CARRY[7].FCIN"/>
</direct>
<direct input="BLK_IG-LUT_CARRY[7].FCOUT" name="FCOUT" output="BLK_IG-PLB_LOCAL.FCOUT">
<pack_pattern in_port="BLK_IG-LUT_CARRY[7].FCOUT" name="CARRYCHAIN" out_port="BLK_IG-PLB_LOCAL.FCOUT"/>
</direct>
</interconnect>
</pb_type>
<interconnect>
<!-- Inputs -->
<direct input="BLK_TL-PLB.I0" name="I0" output="BLK_IG-PLB_LOCAL.I0"/>
<direct input="BLK_TL-PLB.I1" name="I1" output="BLK_IG-PLB_LOCAL.I1"/>
<direct input="BLK_TL-PLB.I2" name="I2" output="BLK_IG-PLB_LOCAL.I2"/>
<direct input="BLK_TL-PLB.I3" name="I3" output="BLK_IG-PLB_LOCAL.I3"/>
<direct input="BLK_TL-PLB.I4" name="I4" output="BLK_IG-PLB_LOCAL.I4"/>
<direct input="BLK_TL-PLB.I5" name="I5" output="BLK_IG-PLB_LOCAL.I5"/>
<direct input="BLK_TL-PLB.I6" name="I6" output="BLK_IG-PLB_LOCAL.I6"/>
<direct input="BLK_TL-PLB.I7" name="I7" output="BLK_IG-PLB_LOCAL.I7"/>
<!-- Outputs -->
<direct input="BLK_IG-PLB_LOCAL.O0" name="O0" output="BLK_TL-PLB.O0"/>
<direct input="BLK_IG-PLB_LOCAL.O1" name="O1" output="BLK_TL-PLB.O1"/>
<direct input="BLK_IG-PLB_LOCAL.O2" name="O2" output="BLK_TL-PLB.O2"/>
<direct input="BLK_IG-PLB_LOCAL.O3" name="O3" output="BLK_TL-PLB.O3"/>
<direct input="BLK_IG-PLB_LOCAL.O4" name="O4" output="BLK_TL-PLB.O4"/>
<direct input="BLK_IG-PLB_LOCAL.O5" name="O5" output="BLK_TL-PLB.O5"/>
<direct input="BLK_IG-PLB_LOCAL.O6" name="O6" output="BLK_TL-PLB.O6"/>
<direct input="BLK_IG-PLB_LOCAL.O7" name="O7" output="BLK_TL-PLB.O7"/>
<direct input="BLK_IG-PLB_LOCAL.FCOUT0" name="FCOUT0" output="BLK_TL-PLB.FCOUT0"/>
<direct input="BLK_IG-PLB_LOCAL.FCOUT1" name="FCOUT1" output="BLK_TL-PLB.FCOUT1"/>
<direct input="BLK_IG-PLB_LOCAL.FCOUT2" name="FCOUT2" output="BLK_TL-PLB.FCOUT2"/>
<direct input="BLK_IG-PLB_LOCAL.FCOUT3" name="FCOUT3" output="BLK_TL-PLB.FCOUT3"/>
<direct input="BLK_IG-PLB_LOCAL.FCOUT4" name="FCOUT4" output="BLK_TL-PLB.FCOUT4"/>
<direct input="BLK_IG-PLB_LOCAL.FCOUT5" name="FCOUT5" output="BLK_TL-PLB.FCOUT5"/>
<direct input="BLK_IG-PLB_LOCAL.FCOUT6" name="FCOUT6" output="BLK_TL-PLB.FCOUT6"/>
<direct input="BLK_IG-PLB_LOCAL.FCOUT7" name="FCOUT7" output="BLK_TL-PLB.FCOUT7"/>
<direct input="BLK_TL-PLB.CLK" name="CLK" output="BLK_IG-PLB_LOCAL.CLK"/>
<direct input="BLK_TL-PLB.SR" name="SR" output="BLK_IG-PLB_LOCAL.SR"/>
<direct input="BLK_TL-PLB.EN" name="EN" output="BLK_IG-PLB_LOCAL.EN"/>
<direct input="BLK_TL-PLB.FCIN" name="FCIN" output="BLK_IG-PLB_LOCAL.FCIN"/>
<direct input="BLK_IG-PLB_LOCAL.FCOUT" name="FCOUT" output="BLK_TL-PLB.FCOUT"/>
</interconnect>
<pinlocations pattern="custom">
<loc side="right" xoffset="0" yoffset="0">
BLK_TL-PLB.I0
BLK_TL-PLB.I1
BLK_TL-PLB.I2
BLK_TL-PLB.I3
BLK_TL-PLB.I4
BLK_TL-PLB.I5
BLK_TL-PLB.I6
BLK_TL-PLB.I7
BLK_TL-PLB.O0
BLK_TL-PLB.O1
BLK_TL-PLB.O2
BLK_TL-PLB.O3
BLK_TL-PLB.O4
BLK_TL-PLB.O5
BLK_TL-PLB.O6
BLK_TL-PLB.O7
BLK_TL-PLB.FCOUT0
BLK_TL-PLB.FCOUT1
BLK_TL-PLB.FCOUT2
BLK_TL-PLB.FCOUT3
BLK_TL-PLB.FCOUT4
BLK_TL-PLB.FCOUT5
BLK_TL-PLB.FCOUT6
BLK_TL-PLB.FCOUT7
BLK_TL-PLB.CLK
BLK_TL-PLB.EN
BLK_TL-PLB.SR
</loc>
<loc side="top" xoffset="0" yoffset="0">
BLK_TL-PLB.FCIN
</loc>
<loc side="bottom" xoffset="0" yoffset="0">
BLK_TL-PLB.FCOUT
</loc>
</pinlocations>
<switchblock_locations pattern="external_full_internal_straight"/>
<fc in_type="frac" in_val="0.5" out_type="frac" out_val="1.0">
<!-- Carry chain doesn't connect to the interconnect -->
<fc_override fc_type="frac" fc_val="0.0" port_name="FCOUT"/>
<fc_override fc_type="frac" fc_val="0.0" port_name="FCIN"/>
</fc>
</pb_type>
<!-- set: ai sw=1 ts=1 sta et -->
<!-- A diagram for the iCE40 PLB "Block RAM" is shown in;
http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf
-->
<pb_type height="1" name="BLK_TL-RAMB">
<!-- Read port -->
<output equivalent="false" name="RDATAT" num_pins="8"/>
<output equivalent="false" name="RDATAB" num_pins="8"/>
<input equivalent="false" name="RADDR" num_pins="11"/>
<input equivalent="false" name="RE" num_pins="1"/>
<input equivalent="false" name="RCLKE" num_pins="1"/>
<clock equivalent="false" name="RCLK" num_pins="1"/>
<!-- Write port -->
<input equivalent="false" name="WDATAT" num_pins="8"/>
<input equivalent="false" name="WDATAB" num_pins="8"/>
<input equivalent="false" name="MASKT" num_pins="8"/>
<input equivalent="false" name="MASKB" num_pins="8"/>
<input equivalent="false" name="WADDR" num_pins="11"/>
<input equivalent="false" name="WE" num_pins="1"/>
<input equivalent="false" name="WCLKE" num_pins="1"/>
<clock equivalent="false" name="WCLK" num_pins="1"/>
<!-- set: ai sw=1 ts=1 sta et -->
<!-- Block ram found inside the iCE40 -->
<pb_type name="SB_RAM" num_pb="1">
<!-- Read port -->
<output equivalent="false" name="RDATA" num_pins="16"/>
<clock equivalent="false" name="RCLK" num_pins="1"/>
<input equivalent="false" name="RCLKE" num_pins="1"/>
<input equivalent="false" name="RE" num_pins="1"/>
<input equivalent="false" name="RADDR" num_pins="11"/>
<!-- Write port -->
<clock equivalent="false" name="WCLK" num_pins="1"/>
<input equivalent="false" name="WCLKE" num_pins="1"/>
<input equivalent="false" name="WE" num_pins="1"/>
<input equivalent="false" name="WADDR" num_pins="11"/>
<input equivalent="false" name="MASK" num_pins="16"/>
<input equivalent="false" name="WDATA" num_pins="16"/>
<mode name="SB_RAM40_4K">
<!--
<pb_type name="SB_RAM256x16" blif_model=".subckt dual_port_ram" num_pb="1" class="memory">
<output name="RDATA" num_pins="16" equivalent="false" port_class="data_out1" />
<input name="RADDR" num_pins="8" equivalent="false" port_class="address1" />
<clock name="CLK1" num_pins="1" equivalent="false" port_class="clock1" />
<input name="DATAIN2" num_pins="16" equivalent="false" port_class="data_in2" />
<input name="WE2" num_pins="1" equivalent="false" port_class="write_en2" />
<input name="WADDR" num_pins="8" equivalent="false" port_class="address2" />
<clock name="WCLK" num_pins="1" equivalent="false" port_class="clock2" />
-->
<pb_type blif_model=".subckt SB_RAM40_4K" name="SB_RAM256x16" num_pb="1">
<!-- Read port -->
<output equivalent="false" name="RDATA" num_pins="16"/>
<clock equivalent="false" name="RCLK" num_pins="1"/>
<input equivalent="false" name="RCLKE" num_pins="1"/>
<input equivalent="false" name="RE" num_pins="1"/>
<input equivalent="false" name="RADDR" num_pins="11"/>
<!-- Write port -->
<clock equivalent="false" name="WCLK" num_pins="1"/>
<input equivalent="false" name="WCLKE" num_pins="1"/>
<input equivalent="false" name="WE" num_pins="1"/>
<input equivalent="false" name="WADDR" num_pins="11"/>
<input equivalent="false" name="MASK" num_pins="16"/>
<input equivalent="false" name="WDATA" num_pins="16"/>
<!-- Read port timing -->
<T_setup clock="RCLK" port="SB_RAM256x16.RDATA" value="50e-12"/>
<T_setup clock="RCLK" port="SB_RAM256x16.RCLKE" value="50e-12"/>
<T_setup clock="RCLK" port="SB_RAM256x16.RE" value="50e-12"/>
<T_setup clock="RCLK" port="SB_RAM256x16.RADDR" value="50e-12"/>
<T_clock_to_Q clock="RCLK" max="200e-12" port="SB_RAM256x16.RDATA"/>
<T_clock_to_Q clock="RCLK" max="200e-12" port="SB_RAM256x16.RCLKE"/>
<T_clock_to_Q clock="RCLK" max="200e-12" port="SB_RAM256x16.RE"/>
<T_clock_to_Q clock="RCLK" max="200e-12" port="SB_RAM256x16.RADDR"/>
<delay_constant in_port="SB_RAM256x16.RCLKE" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.RE" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.RADDR" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<!-- Write port timing -->
<T_setup clock="WCLK" port="SB_RAM256x16.WCLKE" value="50e-12"/>
<T_setup clock="WCLK" port="SB_RAM256x16.WE" value="50e-12"/>
<T_setup clock="WCLK" port="SB_RAM256x16.WADDR" value="50e-12"/>
<T_setup clock="WCLK" port="SB_RAM256x16.MASK" value="50e-12"/>
<T_setup clock="WCLK" port="SB_RAM256x16.WDATA" value="50e-12"/>
<T_clock_to_Q clock="WCLK" max="200e-12" port="SB_RAM256x16.WCLKE"/>
<T_clock_to_Q clock="WCLK" max="200e-12" port="SB_RAM256x16.WE"/>
<T_clock_to_Q clock="WCLK" max="200e-12" port="SB_RAM256x16.WADDR"/>
<T_clock_to_Q clock="WCLK" max="200e-12" port="SB_RAM256x16.MASK"/>
<T_clock_to_Q clock="WCLK" max="200e-12" port="SB_RAM256x16.WDATA"/>
<delay_constant in_port="SB_RAM256x16.WCLKE" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.WE" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.WADDR" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.MASK" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.WDATA" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
</pb_type>
<interconnect>
<!-- Read port -->
<direct input="SB_RAM256x16.RDATA[0]" name="RDATA00" output="SB_RAM.RDATA[0]"/>
<direct input="SB_RAM256x16.RDATA[1]" name="RDATA01" output="SB_RAM.RDATA[1]"/>
<direct input="SB_RAM256x16.RDATA[2]" name="RDATA02" output="SB_RAM.RDATA[2]"/>
<direct input="SB_RAM256x16.RDATA[3]" name="RDATA03" output="SB_RAM.RDATA[3]"/>
<direct input="SB_RAM256x16.RDATA[4]" name="RDATA04" output="SB_RAM.RDATA[4]"/>
<direct input="SB_RAM256x16.RDATA[5]" name="RDATA05" output="SB_RAM.RDATA[5]"/>
<direct input="SB_RAM256x16.RDATA[6]" name="RDATA06" output="SB_RAM.RDATA[6]"/>
<direct input="SB_RAM256x16.RDATA[7]" name="RDATA07" output="SB_RAM.RDATA[7]"/>
<direct input="SB_RAM256x16.RDATA[8]" name="RDATA08" output="SB_RAM.RDATA[8]"/>
<direct input="SB_RAM256x16.RDATA[9]" name="RDATA09" output="SB_RAM.RDATA[9]"/>
<direct input="SB_RAM256x16.RDATA[10]" name="RDATA10" output="SB_RAM.RDATA[10]"/>
<direct input="SB_RAM256x16.RDATA[11]" name="RDATA11" output="SB_RAM.RDATA[11]"/>
<direct input="SB_RAM256x16.RDATA[12]" name="RDATA12" output="SB_RAM.RDATA[12]"/>
<direct input="SB_RAM256x16.RDATA[13]" name="RDATA13" output="SB_RAM.RDATA[13]"/>
<direct input="SB_RAM256x16.RDATA[14]" name="RDATA14" output="SB_RAM.RDATA[14]"/>
<direct input="SB_RAM256x16.RDATA[15]" name="RDATA15" output="SB_RAM.RDATA[15]"/>
<direct input="SB_RAM.RCLK" name="RCLK" output="SB_RAM256x16.RCLK"/>
<direct input="SB_RAM.RCLKE" name="RCLKE" output="SB_RAM256x16.RCLKE"/>
<direct input="SB_RAM.RE" name="RE" output="SB_RAM256x16.RE"/>
<direct input="SB_RAM.RADDR[0]" name="RADDR00" output="SB_RAM256x16.RADDR[0]"/>
<direct input="SB_RAM.RADDR[1]" name="RADDR01" output="SB_RAM256x16.RADDR[1]"/>
<direct input="SB_RAM.RADDR[2]" name="RADDR02" output="SB_RAM256x16.RADDR[2]"/>
<direct input="SB_RAM.RADDR[3]" name="RADDR03" output="SB_RAM256x16.RADDR[3]"/>
<direct input="SB_RAM.RADDR[4]" name="RADDR04" output="SB_RAM256x16.RADDR[4]"/>
<direct input="SB_RAM.RADDR[5]" name="RADDR05" output="SB_RAM256x16.RADDR[5]"/>
<direct input="SB_RAM.RADDR[6]" name="RADDR06" output="SB_RAM256x16.RADDR[6]"/>
<direct input="SB_RAM.RADDR[7]" name="RADDR07" output="SB_RAM256x16.RADDR[7]"/>
<direct input="SB_RAM.RADDR[8]" name="RADDR08" output="SB_RAM256x16.RADDR[8]"/>
<direct input="SB_RAM.RADDR[9]" name="RADDR09" output="SB_RAM256x16.RADDR[9]"/>
<direct input="SB_RAM.RADDR[10]" name="RADDR10" output="SB_RAM256x16.RADDR[10]"/>
<!-- Write port -->
<direct input="SB_RAM.WCLK" name="WCLK" output="SB_RAM256x16.WCLK"/>
<direct input="SB_RAM.WCLKE" name="WCLKE" output="SB_RAM256x16.WCLKE"/>
<direct input="SB_RAM.WE" name="WE" output="SB_RAM256x16.WE"/>
<direct input="SB_RAM.WADDR[0]" name="WADDR00" output="SB_RAM256x16.WADDR[0]"/>
<direct input="SB_RAM.WADDR[1]" name="WADDR01" output="SB_RAM256x16.WADDR[1]"/>
<direct input="SB_RAM.WADDR[2]" name="WADDR02" output="SB_RAM256x16.WADDR[2]"/>
<direct input="SB_RAM.WADDR[3]" name="WADDR03" output="SB_RAM256x16.WADDR[3]"/>
<direct input="SB_RAM.WADDR[4]" name="WADDR04" output="SB_RAM256x16.WADDR[4]"/>
<direct input="SB_RAM.WADDR[5]" name="WADDR05" output="SB_RAM256x16.WADDR[5]"/>
<direct input="SB_RAM.WADDR[6]" name="WADDR06" output="SB_RAM256x16.WADDR[6]"/>
<direct input="SB_RAM.WADDR[7]" name="WADDR07" output="SB_RAM256x16.WADDR[7]"/>
<direct input="SB_RAM.WADDR[8]" name="WADDR08" output="SB_RAM256x16.WADDR[8]"/>
<direct input="SB_RAM.WADDR[9]" name="WADDR09" output="SB_RAM256x16.WADDR[9]"/>
<direct input="SB_RAM.WADDR[10]" name="WADDR10" output="SB_RAM256x16.WADDR[10]"/>
<direct input="SB_RAM.MASK[0]" name="MASK00" output="SB_RAM256x16.MASK[0]"/>
<direct input="SB_RAM.MASK[1]" name="MASK01" output="SB_RAM256x16.MASK[1]"/>
<direct input="SB_RAM.MASK[2]" name="MASK02" output="SB_RAM256x16.MASK[2]"/>
<direct input="SB_RAM.MASK[3]" name="MASK03" output="SB_RAM256x16.MASK[3]"/>
<direct input="SB_RAM.MASK[4]" name="MASK04" output="SB_RAM256x16.MASK[4]"/>
<direct input="SB_RAM.MASK[5]" name="MASK05" output="SB_RAM256x16.MASK[5]"/>
<direct input="SB_RAM.MASK[6]" name="MASK06" output="SB_RAM256x16.MASK[6]"/>
<direct input="SB_RAM.MASK[7]" name="MASK07" output="SB_RAM256x16.MASK[7]"/>
<direct input="SB_RAM.MASK[8]" name="MASK08" output="SB_RAM256x16.MASK[8]"/>
<direct input="SB_RAM.MASK[9]" name="MASK09" output="SB_RAM256x16.MASK[9]"/>
<direct input="SB_RAM.MASK[10]" name="MASK10" output="SB_RAM256x16.MASK[10]"/>
<direct input="SB_RAM.MASK[11]" name="MASK11" output="SB_RAM256x16.MASK[11]"/>
<direct input="SB_RAM.MASK[12]" name="MASK12" output="SB_RAM256x16.MASK[12]"/>
<direct input="SB_RAM.MASK[13]" name="MASK13" output="SB_RAM256x16.MASK[13]"/>
<direct input="SB_RAM.MASK[14]" name="MASK14" output="SB_RAM256x16.MASK[14]"/>
<direct input="SB_RAM.MASK[15]" name="MASK15" output="SB_RAM256x16.MASK[15]"/>
<direct input="SB_RAM.WDATA[0]" name="WDATA00" output="SB_RAM256x16.WDATA[0]"/>
<direct input="SB_RAM.WDATA[1]" name="WDATA01" output="SB_RAM256x16.WDATA[1]"/>
<direct input="SB_RAM.WDATA[2]" name="WDATA02" output="SB_RAM256x16.WDATA[2]"/>
<direct input="SB_RAM.WDATA[3]" name="WDATA03" output="SB_RAM256x16.WDATA[3]"/>
<direct input="SB_RAM.WDATA[4]" name="WDATA04" output="SB_RAM256x16.WDATA[4]"/>
<direct input="SB_RAM.WDATA[5]" name="WDATA05" output="SB_RAM256x16.WDATA[5]"/>
<direct input="SB_RAM.WDATA[6]" name="WDATA06" output="SB_RAM256x16.WDATA[6]"/>
<direct input="SB_RAM.WDATA[7]" name="WDATA07" output="SB_RAM256x16.WDATA[7]"/>
<direct input="SB_RAM.WDATA[8]" name="WDATA08" output="SB_RAM256x16.WDATA[8]"/>
<direct input="SB_RAM.WDATA[9]" name="WDATA09" output="SB_RAM256x16.WDATA[9]"/>
<direct input="SB_RAM.WDATA[10]" name="WDATA10" output="SB_RAM256x16.WDATA[10]"/>
<direct input="SB_RAM.WDATA[11]" name="WDATA11" output="SB_RAM256x16.WDATA[11]"/>
<direct input="SB_RAM.WDATA[12]" name="WDATA12" output="SB_RAM256x16.WDATA[12]"/>
<direct input="SB_RAM.WDATA[13]" name="WDATA13" output="SB_RAM256x16.WDATA[13]"/>
<direct input="SB_RAM.WDATA[14]" name="WDATA14" output="SB_RAM256x16.WDATA[14]"/>
<direct input="SB_RAM.WDATA[15]" name="WDATA15" output="SB_RAM256x16.WDATA[15]"/>
</interconnect>
</mode>
</pb_type>
<interconnect>
<direct input="SB_RAM.RDATA[0]" name="RDATA00" output="BLK_TL-RAMB.RDATAT[0]"/>
<direct input="SB_RAM.RDATA[1]" name="RDATA01" output="BLK_TL-RAMB.RDATAT[1]"/>
<direct input="SB_RAM.RDATA[2]" name="RDATA02" output="BLK_TL-RAMB.RDATAT[2]"/>
<direct input="SB_RAM.RDATA[3]" name="RDATA03" output="BLK_TL-RAMB.RDATAT[3]"/>
<direct input="SB_RAM.RDATA[4]" name="RDATA04" output="BLK_TL-RAMB.RDATAT[4]"/>
<direct input="SB_RAM.RDATA[5]" name="RDATA05" output="BLK_TL-RAMB.RDATAT[5]"/>
<direct input="SB_RAM.RDATA[6]" name="RDATA06" output="BLK_TL-RAMB.RDATAT[6]"/>
<direct input="SB_RAM.RDATA[7]" name="RDATA07" output="BLK_TL-RAMB.RDATAT[7]"/>
<direct input="SB_RAM.RDATA[8]" name="RDATA08" output="BLK_TL-RAMB.RDATAB[0]"/>
<direct input="SB_RAM.RDATA[9]" name="RDATA09" output="BLK_TL-RAMB.RDATAB[1]"/>
<direct input="SB_RAM.RDATA[10]" name="RDATA10" output="BLK_TL-RAMB.RDATAB[2]"/>
<direct input="SB_RAM.RDATA[11]" name="RDATA11" output="BLK_TL-RAMB.RDATAB[3]"/>
<direct input="SB_RAM.RDATA[12]" name="RDATA12" output="BLK_TL-RAMB.RDATAB[4]"/>
<direct input="SB_RAM.RDATA[13]" name="RDATA13" output="BLK_TL-RAMB.RDATAB[5]"/>
<direct input="SB_RAM.RDATA[14]" name="RDATA14" output="BLK_TL-RAMB.RDATAB[6]"/>
<direct input="SB_RAM.RDATA[15]" name="RDATA15" output="BLK_TL-RAMB.RDATAB[7]"/>
<direct input="BLK_TL-RAMB.RADDR[0]" name="RADDR00" output="SB_RAM.RADDR[0]"/>
<direct input="BLK_TL-RAMB.RADDR[1]" name="RADDR01" output="SB_RAM.RADDR[1]"/>
<direct input="BLK_TL-RAMB.RADDR[2]" name="RADDR02" output="SB_RAM.RADDR[2]"/>
<direct input="BLK_TL-RAMB.RADDR[3]" name="RADDR03" output="SB_RAM.RADDR[3]"/>
<direct input="BLK_TL-RAMB.RADDR[4]" name="RADDR04" output="SB_RAM.RADDR[4]"/>
<direct input="BLK_TL-RAMB.RADDR[5]" name="RADDR05" output="SB_RAM.RADDR[5]"/>
<direct input="BLK_TL-RAMB.RADDR[6]" name="RADDR06" output="SB_RAM.RADDR[6]"/>
<direct input="BLK_TL-RAMB.RADDR[7]" name="RADDR07" output="SB_RAM.RADDR[7]"/>
<direct input="BLK_TL-RAMB.RADDR[8]" name="RADDR08" output="SB_RAM.RADDR[8]"/>
<direct input="BLK_TL-RAMB.RADDR[9]" name="RADDR09" output="SB_RAM.RADDR[9]"/>
<direct input="BLK_TL-RAMB.RADDR[10]" name="RADDR10" output="SB_RAM.RADDR[10]"/>
<direct input="BLK_TL-RAMB.RE" name="RE" output="SB_RAM.RE"/>
<direct input="BLK_TL-RAMB.RCLKE" name="RCLKE" output="SB_RAM.RCLKE"/>
<direct input="BLK_TL-RAMB.RCLK" name="RCLK" output="SB_RAM.RCLK"/>
<direct input="BLK_TL-RAMB.WDATAT[0]" name="WDATA00" output="SB_RAM.WDATA[0]"/>
<direct input="BLK_TL-RAMB.WDATAT[1]" name="WDATA01" output="SB_RAM.WDATA[1]"/>
<direct input="BLK_TL-RAMB.WDATAT[2]" name="WDATA02" output="SB_RAM.WDATA[2]"/>
<direct input="BLK_TL-RAMB.WDATAT[3]" name="WDATA03" output="SB_RAM.WDATA[3]"/>
<direct input="BLK_TL-RAMB.WDATAT[4]" name="WDATA04" output="SB_RAM.WDATA[4]"/>
<direct input="BLK_TL-RAMB.WDATAT[5]" name="WDATA05" output="SB_RAM.WDATA[5]"/>
<direct input="BLK_TL-RAMB.WDATAT[6]" name="WDATA06" output="SB_RAM.WDATA[6]"/>
<direct input="BLK_TL-RAMB.WDATAT[7]" name="WDATA07" output="SB_RAM.WDATA[7]"/>
<direct input="BLK_TL-RAMB.WDATAB[0]" name="WDATA08" output="SB_RAM.WDATA[8]"/>
<direct input="BLK_TL-RAMB.WDATAB[1]" name="WDATA09" output="SB_RAM.WDATA[9]"/>
<direct input="BLK_TL-RAMB.WDATAB[2]" name="WDATA10" output="SB_RAM.WDATA[10]"/>
<direct input="BLK_TL-RAMB.WDATAB[3]" name="WDATA11" output="SB_RAM.WDATA[11]"/>
<direct input="BLK_TL-RAMB.WDATAB[4]" name="WDATA12" output="SB_RAM.WDATA[12]"/>
<direct input="BLK_TL-RAMB.WDATAB[5]" name="WDATA13" output="SB_RAM.WDATA[13]"/>
<direct input="BLK_TL-RAMB.WDATAB[6]" name="WDATA14" output="SB_RAM.WDATA[14]"/>
<direct input="BLK_TL-RAMB.WDATAB[7]" name="WDATA15" output="SB_RAM.WDATA[15]"/>
<direct input="BLK_TL-RAMB.MASKT[0]" name="MASK00" output="SB_RAM.MASK[0]"/>
<direct input="BLK_TL-RAMB.MASKT[1]" name="MASK01" output="SB_RAM.MASK[1]"/>
<direct input="BLK_TL-RAMB.MASKT[2]" name="MASK02" output="SB_RAM.MASK[2]"/>
<direct input="BLK_TL-RAMB.MASKT[3]" name="MASK03" output="SB_RAM.MASK[3]"/>
<direct input="BLK_TL-RAMB.MASKT[4]" name="MASK04" output="SB_RAM.MASK[4]"/>
<direct input="BLK_TL-RAMB.MASKT[5]" name="MASK05" output="SB_RAM.MASK[5]"/>
<direct input="BLK_TL-RAMB.MASKT[6]" name="MASK06" output="SB_RAM.MASK[6]"/>
<direct input="BLK_TL-RAMB.MASKT[7]" name="MASK07" output="SB_RAM.MASK[7]"/>
<direct input="BLK_TL-RAMB.MASKB[0]" name="MASK08" output="SB_RAM.MASK[8]"/>
<direct input="BLK_TL-RAMB.MASKB[1]" name="MASK09" output="SB_RAM.MASK[9]"/>
<direct input="BLK_TL-RAMB.MASKB[2]" name="MASK10" output="SB_RAM.MASK[10]"/>
<direct input="BLK_TL-RAMB.MASKB[3]" name="MASK11" output="SB_RAM.MASK[11]"/>
<direct input="BLK_TL-RAMB.MASKB[4]" name="MASK12" output="SB_RAM.MASK[12]"/>
<direct input="BLK_TL-RAMB.MASKB[5]" name="MASK13" output="SB_RAM.MASK[13]"/>
<direct input="BLK_TL-RAMB.MASKB[6]" name="MASK14" output="SB_RAM.MASK[14]"/>
<direct input="BLK_TL-RAMB.MASKB[7]" name="MASK15" output="SB_RAM.MASK[15]"/>
<direct input="BLK_TL-RAMB.WADDR[0]" name="WADDR00" output="SB_RAM.WADDR[0]"/>
<direct input="BLK_TL-RAMB.WADDR[1]" name="WADDR01" output="SB_RAM.WADDR[1]"/>
<direct input="BLK_TL-RAMB.WADDR[2]" name="WADDR02" output="SB_RAM.WADDR[2]"/>
<direct input="BLK_TL-RAMB.WADDR[3]" name="WADDR03" output="SB_RAM.WADDR[3]"/>
<direct input="BLK_TL-RAMB.WADDR[4]" name="WADDR04" output="SB_RAM.WADDR[4]"/>
<direct input="BLK_TL-RAMB.WADDR[5]" name="WADDR05" output="SB_RAM.WADDR[5]"/>
<direct input="BLK_TL-RAMB.WADDR[6]" name="WADDR06" output="SB_RAM.WADDR[6]"/>
<direct input="BLK_TL-RAMB.WADDR[7]" name="WADDR07" output="SB_RAM.WADDR[7]"/>
<direct input="BLK_TL-RAMB.WADDR[8]" name="WADDR08" output="SB_RAM.WADDR[8]"/>
<direct input="BLK_TL-RAMB.WADDR[9]" name="WADDR09" output="SB_RAM.WADDR[9]"/>
<direct input="BLK_TL-RAMB.WADDR[10]" name="WADDR10" output="SB_RAM.WADDR[10]"/>
<direct input="BLK_TL-RAMB.WE" name="WE" output="SB_RAM.WE"/>
<direct input="BLK_TL-RAMB.WCLKE" name="WCLKE" output="SB_RAM.WCLKE"/>
<direct input="BLK_TL-RAMB.WCLK" name="WCLK" output="SB_RAM.WCLK"/>
</interconnect>
<fc in_type="frac" in_val="0.5" out_type="frac" out_val="1.0">
<fc_override fc_type="abs" fc_val="2" port_name="RDATAT" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="RDATAB" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="RADDR" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="RE" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="RCLKE" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="RCLK" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WDATAT" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WDATAB" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="MASKT" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="MASKB" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WADDR" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WE" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WCLKE" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WCLK" segment_name="local"/>
</fc>
<pinlocations pattern="custom">
<!-- RAMB Tile -->
<loc side="right" xoffset="0" yoffset="0">
BLK_TL-RAMB.RDATAB
BLK_TL-RAMB.WADDR
BLK_TL-RAMB.MASKB
BLK_TL-RAMB.WDATAB
BLK_TL-RAMB.WCLKE
BLK_TL-RAMB.WCLK
BLK_TL-RAMB.WE
BLK_TL-RAMB.RDATAT
BLK_TL-RAMB.RADDR
BLK_TL-RAMB.MASKT
BLK_TL-RAMB.WDATAT
BLK_TL-RAMB.RCLKE
BLK_TL-RAMB.RCLK
BLK_TL-RAMB.RE
</loc>
</pinlocations>
<!--
</loc>
<loc side="right" xoffset="0" yoffset="1"> -->
<switchblock_locations pattern="external_full_internal_straight"/>
</pb_type>
<!-- End RAMB -->
<!-- set: ai sw=1 ts=1 sta et -->
<!-- A diagram for the iCE40 PLB "Block RAM" is shown in;
http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf
-->
<pb_type height="1" name="BLK_TL-RAMT">
<!-- Read port -->
<output equivalent="false" name="RDATAT" num_pins="8"/>
<output equivalent="false" name="RDATAB" num_pins="8"/>
<input equivalent="false" name="RADDR" num_pins="11"/>
<input equivalent="false" name="RE" num_pins="1"/>
<input equivalent="false" name="RCLKE" num_pins="1"/>
<clock equivalent="false" name="RCLK" num_pins="1"/>
<!-- Write port -->
<input equivalent="false" name="WDATAT" num_pins="8"/>
<input equivalent="false" name="WDATAB" num_pins="8"/>
<input equivalent="false" name="MASKT" num_pins="8"/>
<input equivalent="false" name="MASKB" num_pins="8"/>
<input equivalent="false" name="WADDR" num_pins="11"/>
<input equivalent="false" name="WE" num_pins="1"/>
<input equivalent="false" name="WCLKE" num_pins="1"/>
<clock equivalent="false" name="WCLK" num_pins="1"/>
<!-- set: ai sw=1 ts=1 sta et -->
<!-- Block ram found inside the iCE40 -->
<pb_type name="SB_RAM" num_pb="1">
<!-- Read port -->
<output equivalent="false" name="RDATA" num_pins="16"/>
<clock equivalent="false" name="RCLK" num_pins="1"/>
<input equivalent="false" name="RCLKE" num_pins="1"/>
<input equivalent="false" name="RE" num_pins="1"/>
<input equivalent="false" name="RADDR" num_pins="11"/>
<!-- Write port -->
<clock equivalent="false" name="WCLK" num_pins="1"/>
<input equivalent="false" name="WCLKE" num_pins="1"/>
<input equivalent="false" name="WE" num_pins="1"/>
<input equivalent="false" name="WADDR" num_pins="11"/>
<input equivalent="false" name="MASK" num_pins="16"/>
<input equivalent="false" name="WDATA" num_pins="16"/>
<mode name="SB_RAM40_4K">
<!--
<pb_type name="SB_RAM256x16" blif_model=".subckt dual_port_ram" num_pb="1" class="memory">
<output name="RDATA" num_pins="16" equivalent="false" port_class="data_out1" />
<input name="RADDR" num_pins="8" equivalent="false" port_class="address1" />
<clock name="CLK1" num_pins="1" equivalent="false" port_class="clock1" />
<input name="DATAIN2" num_pins="16" equivalent="false" port_class="data_in2" />
<input name="WE2" num_pins="1" equivalent="false" port_class="write_en2" />
<input name="WADDR" num_pins="8" equivalent="false" port_class="address2" />
<clock name="WCLK" num_pins="1" equivalent="false" port_class="clock2" />
-->
<pb_type blif_model=".subckt SB_RAM40_4K" name="SB_RAM256x16" num_pb="1">
<!-- Read port -->
<output equivalent="false" name="RDATA" num_pins="16"/>
<clock equivalent="false" name="RCLK" num_pins="1"/>
<input equivalent="false" name="RCLKE" num_pins="1"/>
<input equivalent="false" name="RE" num_pins="1"/>
<input equivalent="false" name="RADDR" num_pins="11"/>
<!-- Write port -->
<clock equivalent="false" name="WCLK" num_pins="1"/>
<input equivalent="false" name="WCLKE" num_pins="1"/>
<input equivalent="false" name="WE" num_pins="1"/>
<input equivalent="false" name="WADDR" num_pins="11"/>
<input equivalent="false" name="MASK" num_pins="16"/>
<input equivalent="false" name="WDATA" num_pins="16"/>
<!-- Read port timing -->
<T_setup clock="RCLK" port="SB_RAM256x16.RDATA" value="50e-12"/>
<T_setup clock="RCLK" port="SB_RAM256x16.RCLKE" value="50e-12"/>
<T_setup clock="RCLK" port="SB_RAM256x16.RE" value="50e-12"/>
<T_setup clock="RCLK" port="SB_RAM256x16.RADDR" value="50e-12"/>
<T_clock_to_Q clock="RCLK" max="200e-12" port="SB_RAM256x16.RDATA"/>
<T_clock_to_Q clock="RCLK" max="200e-12" port="SB_RAM256x16.RCLKE"/>
<T_clock_to_Q clock="RCLK" max="200e-12" port="SB_RAM256x16.RE"/>
<T_clock_to_Q clock="RCLK" max="200e-12" port="SB_RAM256x16.RADDR"/>
<delay_constant in_port="SB_RAM256x16.RCLKE" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.RE" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.RADDR" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<!-- Write port timing -->
<T_setup clock="WCLK" port="SB_RAM256x16.WCLKE" value="50e-12"/>
<T_setup clock="WCLK" port="SB_RAM256x16.WE" value="50e-12"/>
<T_setup clock="WCLK" port="SB_RAM256x16.WADDR" value="50e-12"/>
<T_setup clock="WCLK" port="SB_RAM256x16.MASK" value="50e-12"/>
<T_setup clock="WCLK" port="SB_RAM256x16.WDATA" value="50e-12"/>
<T_clock_to_Q clock="WCLK" max="200e-12" port="SB_RAM256x16.WCLKE"/>
<T_clock_to_Q clock="WCLK" max="200e-12" port="SB_RAM256x16.WE"/>
<T_clock_to_Q clock="WCLK" max="200e-12" port="SB_RAM256x16.WADDR"/>
<T_clock_to_Q clock="WCLK" max="200e-12" port="SB_RAM256x16.MASK"/>
<T_clock_to_Q clock="WCLK" max="200e-12" port="SB_RAM256x16.WDATA"/>
<delay_constant in_port="SB_RAM256x16.WCLKE" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.WE" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.WADDR" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.MASK" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
<delay_constant in_port="SB_RAM256x16.WDATA" max="740e-12" out_port="SB_RAM256x16.RDATA"/>
</pb_type>
<interconnect>
<!-- Read port -->
<direct input="SB_RAM256x16.RDATA[0]" name="RDATA00" output="SB_RAM.RDATA[0]"/>
<direct input="SB_RAM256x16.RDATA[1]" name="RDATA01" output="SB_RAM.RDATA[1]"/>
<direct input="SB_RAM256x16.RDATA[2]" name="RDATA02" output="SB_RAM.RDATA[2]"/>
<direct input="SB_RAM256x16.RDATA[3]" name="RDATA03" output="SB_RAM.RDATA[3]"/>
<direct input="SB_RAM256x16.RDATA[4]" name="RDATA04" output="SB_RAM.RDATA[4]"/>
<direct input="SB_RAM256x16.RDATA[5]" name="RDATA05" output="SB_RAM.RDATA[5]"/>
<direct input="SB_RAM256x16.RDATA[6]" name="RDATA06" output="SB_RAM.RDATA[6]"/>
<direct input="SB_RAM256x16.RDATA[7]" name="RDATA07" output="SB_RAM.RDATA[7]"/>
<direct input="SB_RAM256x16.RDATA[8]" name="RDATA08" output="SB_RAM.RDATA[8]"/>
<direct input="SB_RAM256x16.RDATA[9]" name="RDATA09" output="SB_RAM.RDATA[9]"/>
<direct input="SB_RAM256x16.RDATA[10]" name="RDATA10" output="SB_RAM.RDATA[10]"/>
<direct input="SB_RAM256x16.RDATA[11]" name="RDATA11" output="SB_RAM.RDATA[11]"/>
<direct input="SB_RAM256x16.RDATA[12]" name="RDATA12" output="SB_RAM.RDATA[12]"/>
<direct input="SB_RAM256x16.RDATA[13]" name="RDATA13" output="SB_RAM.RDATA[13]"/>
<direct input="SB_RAM256x16.RDATA[14]" name="RDATA14" output="SB_RAM.RDATA[14]"/>
<direct input="SB_RAM256x16.RDATA[15]" name="RDATA15" output="SB_RAM.RDATA[15]"/>
<direct input="SB_RAM.RCLK" name="RCLK" output="SB_RAM256x16.RCLK"/>
<direct input="SB_RAM.RCLKE" name="RCLKE" output="SB_RAM256x16.RCLKE"/>
<direct input="SB_RAM.RE" name="RE" output="SB_RAM256x16.RE"/>
<direct input="SB_RAM.RADDR[0]" name="RADDR00" output="SB_RAM256x16.RADDR[0]"/>
<direct input="SB_RAM.RADDR[1]" name="RADDR01" output="SB_RAM256x16.RADDR[1]"/>
<direct input="SB_RAM.RADDR[2]" name="RADDR02" output="SB_RAM256x16.RADDR[2]"/>
<direct input="SB_RAM.RADDR[3]" name="RADDR03" output="SB_RAM256x16.RADDR[3]"/>
<direct input="SB_RAM.RADDR[4]" name="RADDR04" output="SB_RAM256x16.RADDR[4]"/>
<direct input="SB_RAM.RADDR[5]" name="RADDR05" output="SB_RAM256x16.RADDR[5]"/>
<direct input="SB_RAM.RADDR[6]" name="RADDR06" output="SB_RAM256x16.RADDR[6]"/>
<direct input="SB_RAM.RADDR[7]" name="RADDR07" output="SB_RAM256x16.RADDR[7]"/>
<direct input="SB_RAM.RADDR[8]" name="RADDR08" output="SB_RAM256x16.RADDR[8]"/>
<direct input="SB_RAM.RADDR[9]" name="RADDR09" output="SB_RAM256x16.RADDR[9]"/>
<direct input="SB_RAM.RADDR[10]" name="RADDR10" output="SB_RAM256x16.RADDR[10]"/>
<!-- Write port -->
<direct input="SB_RAM.WCLK" name="WCLK" output="SB_RAM256x16.WCLK"/>
<direct input="SB_RAM.WCLKE" name="WCLKE" output="SB_RAM256x16.WCLKE"/>
<direct input="SB_RAM.WE" name="WE" output="SB_RAM256x16.WE"/>
<direct input="SB_RAM.WADDR[0]" name="WADDR00" output="SB_RAM256x16.WADDR[0]"/>
<direct input="SB_RAM.WADDR[1]" name="WADDR01" output="SB_RAM256x16.WADDR[1]"/>
<direct input="SB_RAM.WADDR[2]" name="WADDR02" output="SB_RAM256x16.WADDR[2]"/>
<direct input="SB_RAM.WADDR[3]" name="WADDR03" output="SB_RAM256x16.WADDR[3]"/>
<direct input="SB_RAM.WADDR[4]" name="WADDR04" output="SB_RAM256x16.WADDR[4]"/>
<direct input="SB_RAM.WADDR[5]" name="WADDR05" output="SB_RAM256x16.WADDR[5]"/>
<direct input="SB_RAM.WADDR[6]" name="WADDR06" output="SB_RAM256x16.WADDR[6]"/>
<direct input="SB_RAM.WADDR[7]" name="WADDR07" output="SB_RAM256x16.WADDR[7]"/>
<direct input="SB_RAM.WADDR[8]" name="WADDR08" output="SB_RAM256x16.WADDR[8]"/>
<direct input="SB_RAM.WADDR[9]" name="WADDR09" output="SB_RAM256x16.WADDR[9]"/>
<direct input="SB_RAM.WADDR[10]" name="WADDR10" output="SB_RAM256x16.WADDR[10]"/>
<direct input="SB_RAM.MASK[0]" name="MASK00" output="SB_RAM256x16.MASK[0]"/>
<direct input="SB_RAM.MASK[1]" name="MASK01" output="SB_RAM256x16.MASK[1]"/>
<direct input="SB_RAM.MASK[2]" name="MASK02" output="SB_RAM256x16.MASK[2]"/>
<direct input="SB_RAM.MASK[3]" name="MASK03" output="SB_RAM256x16.MASK[3]"/>
<direct input="SB_RAM.MASK[4]" name="MASK04" output="SB_RAM256x16.MASK[4]"/>
<direct input="SB_RAM.MASK[5]" name="MASK05" output="SB_RAM256x16.MASK[5]"/>
<direct input="SB_RAM.MASK[6]" name="MASK06" output="SB_RAM256x16.MASK[6]"/>
<direct input="SB_RAM.MASK[7]" name="MASK07" output="SB_RAM256x16.MASK[7]"/>
<direct input="SB_RAM.MASK[8]" name="MASK08" output="SB_RAM256x16.MASK[8]"/>
<direct input="SB_RAM.MASK[9]" name="MASK09" output="SB_RAM256x16.MASK[9]"/>
<direct input="SB_RAM.MASK[10]" name="MASK10" output="SB_RAM256x16.MASK[10]"/>
<direct input="SB_RAM.MASK[11]" name="MASK11" output="SB_RAM256x16.MASK[11]"/>
<direct input="SB_RAM.MASK[12]" name="MASK12" output="SB_RAM256x16.MASK[12]"/>
<direct input="SB_RAM.MASK[13]" name="MASK13" output="SB_RAM256x16.MASK[13]"/>
<direct input="SB_RAM.MASK[14]" name="MASK14" output="SB_RAM256x16.MASK[14]"/>
<direct input="SB_RAM.MASK[15]" name="MASK15" output="SB_RAM256x16.MASK[15]"/>
<direct input="SB_RAM.WDATA[0]" name="WDATA00" output="SB_RAM256x16.WDATA[0]"/>
<direct input="SB_RAM.WDATA[1]" name="WDATA01" output="SB_RAM256x16.WDATA[1]"/>
<direct input="SB_RAM.WDATA[2]" name="WDATA02" output="SB_RAM256x16.WDATA[2]"/>
<direct input="SB_RAM.WDATA[3]" name="WDATA03" output="SB_RAM256x16.WDATA[3]"/>
<direct input="SB_RAM.WDATA[4]" name="WDATA04" output="SB_RAM256x16.WDATA[4]"/>
<direct input="SB_RAM.WDATA[5]" name="WDATA05" output="SB_RAM256x16.WDATA[5]"/>
<direct input="SB_RAM.WDATA[6]" name="WDATA06" output="SB_RAM256x16.WDATA[6]"/>
<direct input="SB_RAM.WDATA[7]" name="WDATA07" output="SB_RAM256x16.WDATA[7]"/>
<direct input="SB_RAM.WDATA[8]" name="WDATA08" output="SB_RAM256x16.WDATA[8]"/>
<direct input="SB_RAM.WDATA[9]" name="WDATA09" output="SB_RAM256x16.WDATA[9]"/>
<direct input="SB_RAM.WDATA[10]" name="WDATA10" output="SB_RAM256x16.WDATA[10]"/>
<direct input="SB_RAM.WDATA[11]" name="WDATA11" output="SB_RAM256x16.WDATA[11]"/>
<direct input="SB_RAM.WDATA[12]" name="WDATA12" output="SB_RAM256x16.WDATA[12]"/>
<direct input="SB_RAM.WDATA[13]" name="WDATA13" output="SB_RAM256x16.WDATA[13]"/>
<direct input="SB_RAM.WDATA[14]" name="WDATA14" output="SB_RAM256x16.WDATA[14]"/>
<direct input="SB_RAM.WDATA[15]" name="WDATA15" output="SB_RAM256x16.WDATA[15]"/>
</interconnect>
</mode>
</pb_type>
<interconnect>
<direct input="SB_RAM.RDATA[0]" name="RDATA00" output="BLK_TL-RAMT.RDATAT[0]"/>
<direct input="SB_RAM.RDATA[1]" name="RDATA01" output="BLK_TL-RAMT.RDATAT[1]"/>
<direct input="SB_RAM.RDATA[2]" name="RDATA02" output="BLK_TL-RAMT.RDATAT[2]"/>
<direct input="SB_RAM.RDATA[3]" name="RDATA03" output="BLK_TL-RAMT.RDATAT[3]"/>
<direct input="SB_RAM.RDATA[4]" name="RDATA04" output="BLK_TL-RAMT.RDATAT[4]"/>
<direct input="SB_RAM.RDATA[5]" name="RDATA05" output="BLK_TL-RAMT.RDATAT[5]"/>
<direct input="SB_RAM.RDATA[6]" name="RDATA06" output="BLK_TL-RAMT.RDATAT[6]"/>
<direct input="SB_RAM.RDATA[7]" name="RDATA07" output="BLK_TL-RAMT.RDATAT[7]"/>
<direct input="SB_RAM.RDATA[8]" name="RDATA08" output="BLK_TL-RAMT.RDATAB[0]"/>
<direct input="SB_RAM.RDATA[9]" name="RDATA09" output="BLK_TL-RAMT.RDATAB[1]"/>
<direct input="SB_RAM.RDATA[10]" name="RDATA10" output="BLK_TL-RAMT.RDATAB[2]"/>
<direct input="SB_RAM.RDATA[11]" name="RDATA11" output="BLK_TL-RAMT.RDATAB[3]"/>
<direct input="SB_RAM.RDATA[12]" name="RDATA12" output="BLK_TL-RAMT.RDATAB[4]"/>
<direct input="SB_RAM.RDATA[13]" name="RDATA13" output="BLK_TL-RAMT.RDATAB[5]"/>
<direct input="SB_RAM.RDATA[14]" name="RDATA14" output="BLK_TL-RAMT.RDATAB[6]"/>
<direct input="SB_RAM.RDATA[15]" name="RDATA15" output="BLK_TL-RAMT.RDATAB[7]"/>
<direct input="BLK_TL-RAMT.RADDR[0]" name="RADDR00" output="SB_RAM.RADDR[0]"/>
<direct input="BLK_TL-RAMT.RADDR[1]" name="RADDR01" output="SB_RAM.RADDR[1]"/>
<direct input="BLK_TL-RAMT.RADDR[2]" name="RADDR02" output="SB_RAM.RADDR[2]"/>
<direct input="BLK_TL-RAMT.RADDR[3]" name="RADDR03" output="SB_RAM.RADDR[3]"/>
<direct input="BLK_TL-RAMT.RADDR[4]" name="RADDR04" output="SB_RAM.RADDR[4]"/>
<direct input="BLK_TL-RAMT.RADDR[5]" name="RADDR05" output="SB_RAM.RADDR[5]"/>
<direct input="BLK_TL-RAMT.RADDR[6]" name="RADDR06" output="SB_RAM.RADDR[6]"/>
<direct input="BLK_TL-RAMT.RADDR[7]" name="RADDR07" output="SB_RAM.RADDR[7]"/>
<direct input="BLK_TL-RAMT.RADDR[8]" name="RADDR08" output="SB_RAM.RADDR[8]"/>
<direct input="BLK_TL-RAMT.RADDR[9]" name="RADDR09" output="SB_RAM.RADDR[9]"/>
<direct input="BLK_TL-RAMT.RADDR[10]" name="RADDR10" output="SB_RAM.RADDR[10]"/>
<direct input="BLK_TL-RAMT.RE" name="RE" output="SB_RAM.RE"/>
<direct input="BLK_TL-RAMT.RCLKE" name="RCLKE" output="SB_RAM.RCLKE"/>
<direct input="BLK_TL-RAMT.RCLK" name="RCLK" output="SB_RAM.RCLK"/>
<direct input="BLK_TL-RAMT.WDATAT[0]" name="WDATA00" output="SB_RAM.WDATA[0]"/>
<direct input="BLK_TL-RAMT.WDATAT[1]" name="WDATA01" output="SB_RAM.WDATA[1]"/>
<direct input="BLK_TL-RAMT.WDATAT[2]" name="WDATA02" output="SB_RAM.WDATA[2]"/>
<direct input="BLK_TL-RAMT.WDATAT[3]" name="WDATA03" output="SB_RAM.WDATA[3]"/>
<direct input="BLK_TL-RAMT.WDATAT[4]" name="WDATA04" output="SB_RAM.WDATA[4]"/>
<direct input="BLK_TL-RAMT.WDATAT[5]" name="WDATA05" output="SB_RAM.WDATA[5]"/>
<direct input="BLK_TL-RAMT.WDATAT[6]" name="WDATA06" output="SB_RAM.WDATA[6]"/>
<direct input="BLK_TL-RAMT.WDATAT[7]" name="WDATA07" output="SB_RAM.WDATA[7]"/>
<direct input="BLK_TL-RAMT.WDATAB[0]" name="WDATA08" output="SB_RAM.WDATA[8]"/>
<direct input="BLK_TL-RAMT.WDATAB[1]" name="WDATA09" output="SB_RAM.WDATA[9]"/>
<direct input="BLK_TL-RAMT.WDATAB[2]" name="WDATA10" output="SB_RAM.WDATA[10]"/>
<direct input="BLK_TL-RAMT.WDATAB[3]" name="WDATA11" output="SB_RAM.WDATA[11]"/>
<direct input="BLK_TL-RAMT.WDATAB[4]" name="WDATA12" output="SB_RAM.WDATA[12]"/>
<direct input="BLK_TL-RAMT.WDATAB[5]" name="WDATA13" output="SB_RAM.WDATA[13]"/>
<direct input="BLK_TL-RAMT.WDATAB[6]" name="WDATA14" output="SB_RAM.WDATA[14]"/>
<direct input="BLK_TL-RAMT.WDATAB[7]" name="WDATA15" output="SB_RAM.WDATA[15]"/>
<direct input="BLK_TL-RAMT.MASKT[0]" name="MASK00" output="SB_RAM.MASK[0]"/>
<direct input="BLK_TL-RAMT.MASKT[1]" name="MASK01" output="SB_RAM.MASK[1]"/>
<direct input="BLK_TL-RAMT.MASKT[2]" name="MASK02" output="SB_RAM.MASK[2]"/>
<direct input="BLK_TL-RAMT.MASKT[3]" name="MASK03" output="SB_RAM.MASK[3]"/>
<direct input="BLK_TL-RAMT.MASKT[4]" name="MASK04" output="SB_RAM.MASK[4]"/>
<direct input="BLK_TL-RAMT.MASKT[5]" name="MASK05" output="SB_RAM.MASK[5]"/>
<direct input="BLK_TL-RAMT.MASKT[6]" name="MASK06" output="SB_RAM.MASK[6]"/>
<direct input="BLK_TL-RAMT.MASKT[7]" name="MASK07" output="SB_RAM.MASK[7]"/>
<direct input="BLK_TL-RAMT.MASKB[0]" name="MASK08" output="SB_RAM.MASK[8]"/>
<direct input="BLK_TL-RAMT.MASKB[1]" name="MASK09" output="SB_RAM.MASK[9]"/>
<direct input="BLK_TL-RAMT.MASKB[2]" name="MASK10" output="SB_RAM.MASK[10]"/>
<direct input="BLK_TL-RAMT.MASKB[3]" name="MASK11" output="SB_RAM.MASK[11]"/>
<direct input="BLK_TL-RAMT.MASKB[4]" name="MASK12" output="SB_RAM.MASK[12]"/>
<direct input="BLK_TL-RAMT.MASKB[5]" name="MASK13" output="SB_RAM.MASK[13]"/>
<direct input="BLK_TL-RAMT.MASKB[6]" name="MASK14" output="SB_RAM.MASK[14]"/>
<direct input="BLK_TL-RAMT.MASKB[7]" name="MASK15" output="SB_RAM.MASK[15]"/>
<direct input="BLK_TL-RAMT.WADDR[0]" name="WADDR00" output="SB_RAM.WADDR[0]"/>
<direct input="BLK_TL-RAMT.WADDR[1]" name="WADDR01" output="SB_RAM.WADDR[1]"/>
<direct input="BLK_TL-RAMT.WADDR[2]" name="WADDR02" output="SB_RAM.WADDR[2]"/>
<direct input="BLK_TL-RAMT.WADDR[3]" name="WADDR03" output="SB_RAM.WADDR[3]"/>
<direct input="BLK_TL-RAMT.WADDR[4]" name="WADDR04" output="SB_RAM.WADDR[4]"/>
<direct input="BLK_TL-RAMT.WADDR[5]" name="WADDR05" output="SB_RAM.WADDR[5]"/>
<direct input="BLK_TL-RAMT.WADDR[6]" name="WADDR06" output="SB_RAM.WADDR[6]"/>
<direct input="BLK_TL-RAMT.WADDR[7]" name="WADDR07" output="SB_RAM.WADDR[7]"/>
<direct input="BLK_TL-RAMT.WADDR[8]" name="WADDR08" output="SB_RAM.WADDR[8]"/>
<direct input="BLK_TL-RAMT.WADDR[9]" name="WADDR09" output="SB_RAM.WADDR[9]"/>
<direct input="BLK_TL-RAMT.WADDR[10]" name="WADDR10" output="SB_RAM.WADDR[10]"/>
<direct input="BLK_TL-RAMT.WE" name="WE" output="SB_RAM.WE"/>
<direct input="BLK_TL-RAMT.WCLKE" name="WCLKE" output="SB_RAM.WCLKE"/>
<direct input="BLK_TL-RAMT.WCLK" name="WCLK" output="SB_RAM.WCLK"/>
</interconnect>
<fc in_type="frac" in_val="0.5" out_type="frac" out_val="1.0">
<fc_override fc_type="abs" fc_val="2" port_name="RDATAT" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="RDATAB" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="RADDR" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="RE" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="RCLKE" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="RCLK" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WDATAT" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WDATAB" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="MASKT" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="MASKB" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WADDR" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WE" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WCLKE" segment_name="local"/>
<fc_override fc_type="abs" fc_val="2" port_name="WCLK" segment_name="local"/>
</fc>
<pinlocations pattern="custom">
<!-- RAMB Tile -->
<loc side="right" xoffset="0" yoffset="0">
BLK_TL-RAMT.RDATAB
BLK_TL-RAMT.WADDR
BLK_TL-RAMT.MASKB
BLK_TL-RAMT.WDATAB
BLK_TL-RAMT.WCLKE
BLK_TL-RAMT.WCLK
BLK_TL-RAMT.WE
BLK_TL-RAMT.RDATAT
BLK_TL-RAMT.RADDR
BLK_TL-RAMT.MASKT
BLK_TL-RAMT.WDATAT
BLK_TL-RAMT.RCLKE
BLK_TL-RAMT.RCLK
BLK_TL-RAMT.RE
</loc>
</pinlocations>
<!--
</loc>
<loc side="right" xoffset="0" yoffset="1"> -->
<switchblock_locations pattern="external_full_internal_straight"/>
</pb_type>
<!-- End RAM -->
<!-- An IO pin found on an FPGA -->
<pb_type capacity="1" name="BLK_BB-VPR_PAD">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- IO operating as an input -->
<mode name="PAD_IS_INPUT">
<pb_type blif_model=".input" name="PAD_IN-INPUT" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct input="PAD_IN-INPUT.inpad" name="INPUT" output="BLK_BB-VPR_PAD.inpad">
<delay_constant in_port="PAD_IN-INPUT.inpad" max="4.243e-11" out_port="BLK_BB-VPR_PAD.inpad"/>
</direct>
</interconnect>
</mode>
<!-- IO operating as an output -->
<mode name="PAD_IS_OUTPUT">
<pb_type blif_model=".output" name="PAD_OT-OUTPUT" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct input="BLK_BB-VPR_PAD.outpad" name="OUTPUT" output="PAD_OT-OUTPUT.outpad">
<delay_constant in_port="BLK_BB-VPR_PAD.outpad" max="1.394e-11" out_port="PAD_OT-OUTPUT.outpad"/>
</direct>
</interconnect>
</mode>
<!-- FIXME - Should have a IO operating as bi-directional -->
<!-- IO pins are never connected to the fabric, they are connected to a platform specific IO tile -->
<fc in_type="frac" in_val="1" out_type="frac" out_val="1"/>
<!--
IOs go on the periphery of the FPGA/
Currently for consistency make it physically equivalent on all sides so
that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then we need to 4
different pin definitions (one for each side of the FPGA).
-->
<pinlocations pattern="custom">
<loc side="right">BLK_BB-VPR_PAD.outpad BLK_BB-VPR_PAD.inpad</loc>
</pinlocations>
</pb_type>
</complexblocklist>
<!-- Description of the tile layouts available in the iCE40 family -->
<layout>
<!-- set: ai sw=1 ts=1 sta et -->
<fixed_layout height="6" name="test4" width="6">
<col priority="30" startx="0" type="EMPTY"/>
<col priority="10" startx="1" type="BLK_BB-VPR_PAD"/>
<region endx="3" endy="3" priority="4" startx="2" starty="2" type="BLK_TL-PLB"/>
<!-- Logic blocks 2x2 -->
<col priority="10" startx="4" type="BLK_BB-VPR_PAD"/>
<col priority="30" startx="5" type="EMPTY"/>
<row priority="31" starty="0" type="EMPTY"/>
<row priority="11" starty="1" type="BLK_BB-VPR_PAD"/>
<!-- starty="2" endy="3" -->
<row priority="11" starty="4" type="BLK_BB-VPR_PAD"/>
<row priority="31" starty="5" type="EMPTY"/>
<!-- Create empty blocks at all corners -->
<single priority="40" type="EMPTY" x="1" y="1"/>
<single priority="40" type="EMPTY" x="4" y="1"/>
<single priority="40" type="EMPTY" x="1" y="4"/>
<single priority="40" type="EMPTY" x="4" y="4"/>
</fixed_layout>
<!-- set: ai sw=1 ts=1 sta et -->
<fixed_layout height="12" name="LP384" width="12">
<col priority="30" startx="0" type="EMPTY"/>
<col priority="10" startx="1" type="BLK_BB-VPR_PAD"/>
<region endx="7" endy="9" priority="4" startx="2" starty="2" type="BLK_TL-PLB"/>
<!-- Logic blocks 8x10 -->
<col priority="10" startx="8" type="BLK_BB-VPR_PAD"/>
<col priority="30" startx="9" type="EMPTY"/>
<!-- Temp -->
<col priority="30" startx="10" type="EMPTY"/>
<col priority="30" startx="11" type="EMPTY"/>
<row priority="31" starty="0" type="EMPTY"/>
<row priority="11" starty="1" type="BLK_BB-VPR_PAD"/>
<!-- starty="2" endy="17" -->
<row priority="11" starty="10" type="BLK_BB-VPR_PAD"/>
<row priority="31" starty="11" type="EMPTY"/>
<!-- Create empty blocks at all corners -->
<single priority="40" type="EMPTY" x="1" y="1"/>
<single priority="40" type="EMPTY" x="8" y="1"/>
<single priority="40" type="EMPTY" x="1" y="10"/>
<single priority="40" type="EMPTY" x="8" y="10"/>
</fixed_layout>
<!-- set: ai sw=1 ts=1 sta et -->
<fixed_layout height="12" name="HX384" width="12">
<col priority="30" startx="0" type="EMPTY"/>
<col priority="10" startx="1" type="BLK_BB-VPR_PAD"/>
<region endx="7" endy="9" priority="4" startx="2" starty="2" type="BLK_TL-PLB"/>
<!-- Logic blocks 8x10 -->
<col priority="10" startx="8" type="BLK_BB-VPR_PAD"/>
<col priority="30" startx="9" type="EMPTY"/>
<!-- Temp -->
<col priority="30" startx="10" type="EMPTY"/>
<col priority="30" startx="11" type="EMPTY"/>
<row priority="31" starty="0" type="EMPTY"/>
<row priority="11" starty="1" type="BLK_BB-VPR_PAD"/>
<!-- starty="2" endy="17" -->
<row priority="11" starty="10" type="BLK_BB-VPR_PAD"/>
<row priority="31" starty="11" type="EMPTY"/>
<!-- Create empty blocks at all corners -->
<single priority="40" type="EMPTY" x="1" y="1"/>
<single priority="40" type="EMPTY" x="8" y="1"/>
<single priority="40" type="EMPTY" x="1" y="10"/>
<single priority="40" type="EMPTY" x="8" y="10"/>
</fixed_layout>
<!-- set: ai sw=1 ts=1 sta et -->
<fixed_layout height="20" name="LP1K" width="16">
<!--
Due to the way channels work in VPR, we need to pad the top+right edge with
extra empty tiles.
-->
<col priority="30" startx="0" type="EMPTY"/>
<col priority="10" startx="1" type="BLK_BB-VPR_PAD"/>
<region endx="13" endy="17" priority="4" startx="2" starty="2" type="BLK_TL-PLB"/>
<!-- Logic blocks 11x15 -->
<col priority="10" startx="14" type="BLK_BB-VPR_PAD"/>
<col priority="30" startx="15" type="EMPTY"/>
<row priority="31" starty="0" type="EMPTY"/>
<row priority="11" starty="1" type="BLK_BB-VPR_PAD"/>
<!-- starty="2" endy="17" -->
<row priority="11" starty="18" type="BLK_BB-VPR_PAD"/>
<row priority="31" starty="19" type="EMPTY"/>
<!-- Block RAM -->
<col priority="5" startx="4" starty="2" type="BLK_TL-RAMB"/>
<region endx="4" endy="3" priority="6" repeaty="2" startx="4" starty="3" type="BLK_TL-RAMT"/>
<col priority="5" startx="11" starty="2" type="BLK_TL-RAMB"/>
<region endx="11" endy="3" priority="6" repeaty="2" startx="11" starty="3" type="BLK_TL-RAMT"/>
<!-- Create empty blocks at all corners -->
<single priority="40" type="EMPTY" x="1" y="1"/>
<single priority="40" type="EMPTY" x="14" y="1"/>
<single priority="40" type="EMPTY" x="1" y="18"/>
<single priority="40" type="EMPTY" x="14" y="18"/>
</fixed_layout>
<!-- set: ai sw=1 ts=1 sta et -->
<fixed_layout height="20" name="HX1K" width="16">
<!--
Due to the way channels work in VPR, we need to pad the top+right edge with
extra empty tiles.
-->
<col priority="30" startx="0" type="EMPTY"/>
<col priority="10" startx="1" type="BLK_BB-VPR_PAD"/>
<region endx="13" endy="17" priority="4" startx="2" starty="2" type="BLK_TL-PLB"/>
<!-- Logic blocks 11x15 -->
<col priority="10" startx="14" type="BLK_BB-VPR_PAD"/>
<col priority="30" startx="15" type="EMPTY"/>
<row priority="31" starty="0" type="EMPTY"/>
<row priority="11" starty="1" type="BLK_BB-VPR_PAD"/>
<!-- starty="2" endy="17" -->
<row priority="11" starty="18" type="BLK_BB-VPR_PAD"/>
<row priority="31" starty="19" type="EMPTY"/>
<!-- Block RAM -->
<col priority="5" startx="4" starty="2" type="BLK_TL-RAMB"/>
<region endx="4" endy="3" priority="6" repeaty="2" startx="4" starty="3" type="BLK_TL-RAMT"/>
<col priority="5" startx="11" starty="2" type="BLK_TL-RAMB"/>
<region endx="11" endy="3" priority="6" repeaty="2" startx="11" starty="3" type="BLK_TL-RAMT"/>
<!-- Create empty blocks at all corners -->
<single priority="40" type="EMPTY" x="1" y="1"/>
<single priority="40" type="EMPTY" x="14" y="1"/>
<single priority="40" type="EMPTY" x="1" y="18"/>
<single priority="40" type="EMPTY" x="14" y="18"/>
</fixed_layout>
<!-- set: ai sw=1 ts=1 sta et -->
<fixed_layout height="20" name="LP4K" width="16">
<!-- FIXME -->
</fixed_layout>
<!-- set: ai sw=1 ts=1 sta et -->
<fixed_layout height="20" name="HX4K" width="16">
<!-- FIXME -->
</fixed_layout>
<!-- set: ai sw=1 ts=1 sta et -->
<fixed_layout height="36" name="LP8K" width="36">
<!--
Due to the way channels work in VPR, we need to pad the top+right edge with
extra empty tiles.
-->
<col priority="30" startx="0" type="EMPTY"/>
<col priority="10" startx="1" type="BLK_BB-VPR_PAD"/>
<region endx="33" endy="33" priority="4" startx="2" starty="2" type="BLK_TL-PLB"/>
<!-- Logic blocks 31x31 -->
<col priority="10" startx="34" type="BLK_BB-VPR_PAD"/>
<col priority="30" startx="35" type="EMPTY"/>
<row priority="31" starty="0" type="EMPTY"/>
<row priority="11" starty="1" type="BLK_BB-VPR_PAD"/>
<!-- starty="2" endy="33" -->
<row priority="11" starty="34" type="BLK_BB-VPR_PAD"/>
<row priority="31" starty="35" type="EMPTY"/>
<!-- Block RAM -->
<col priority="5" startx="9" starty="2" type="BLK_TL-RAMB"/>
<region endx="9" endy="2" priority="6" repeaty="2" startx="9" starty="2" type="EMPTY"/>
<col priority="5" startx="26" starty="2" type="BLK_TL-RAMB"/>
<region endx="26" endy="2" priority="6" repeaty="2" startx="26" starty="2" type="EMPTY"/>
<!-- Create empty blocks at all corners -->
<single priority="40" type="EMPTY" x="1" y="1"/>
<single priority="40" type="EMPTY" x="34" y="1"/>
<single priority="40" type="EMPTY" x="1" y="34"/>
<single priority="40" type="EMPTY" x="34" y="34"/>
</fixed_layout>
<!-- set: ai sw=1 ts=1 sta et -->
<fixed_layout height="36" name="HX8K" width="36">
<!--
Due to the way channels work in VPR, we need to pad the top+right edge with
extra empty tiles.
-->
<col priority="30" startx="0" type="EMPTY"/>
<col priority="10" startx="1" type="BLK_BB-VPR_PAD"/>
<region endx="33" endy="33" priority="4" startx="2" starty="2" type="BLK_TL-PLB"/>
<!-- Logic blocks 31x31 -->
<col priority="10" startx="34" type="BLK_BB-VPR_PAD"/>
<col priority="30" startx="35" type="EMPTY"/>
<row priority="31" starty="0" type="EMPTY"/>
<row priority="11" starty="1" type="BLK_BB-VPR_PAD"/>
<!-- starty="2" endy="33" -->
<row priority="11" starty="34" type="BLK_BB-VPR_PAD"/>
<row priority="31" starty="35" type="EMPTY"/>
<!-- Block RAM -->
<col priority="5" startx="9" starty="2" type="BLK_TL-RAMB"/>
<region endx="9" endy="2" priority="6" repeaty="2" startx="9" starty="2" type="EMPTY"/>
<col priority="5" startx="26" starty="2" type="BLK_TL-RAMB"/>
<region endx="26" endy="2" priority="6" repeaty="2" startx="26" starty="2" type="EMPTY"/>
<!-- Create empty blocks at all corners -->
<single priority="40" type="EMPTY" x="1" y="1"/>
<single priority="40" type="EMPTY" x="34" y="1"/>
<single priority="40" type="EMPTY" x="1" y="34"/>
<single priority="40" type="EMPTY" x="34" y="34"/>
</fixed_layout>
</layout>
<directlist>
<!-- Carry chain from one PLB to the next PLB -->
<direct from_pin="BLK_TL-PLB.FCOUT" name="CARRY" to_pin="BLK_TL-PLB.FCIN" x_offset="0" y_offset="-1" z_offset="0"/>
</directlist>
<device>
<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
<area grid_logic_tile_area="14813.392"/>
<connection_block input_switch_name="2"/>
<switch_block fs="3" type="wilton"/>
<chan_width_distr>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
</device>
<switchlist>
<!-- name="buffer" == name="0" -->
<!-- name="routing" == name="1" -->
<switch Cin=".77e-15" Cout="4e-15" R="551" Tdel="58e-12" buf_size="27.645901" mux_trans_size="2.630740" name="1" type="mux"/>
<switch Cin=".77e-15" Cout="4e-15" R="551" Tdel="58e-12" buf_size="27.645901" mux_trans_size="2.630740" name="2" type="mux"/>
</switchlist>
<segmentlist>
<!-- Global networks -->
<segment Cmetal="22.5e-15" Rmetal="101" freq="1.000000" length="longline" name="global" type="bidir">
<sb type="pattern">1 1</sb>
<cb type="pattern">0</cb>
<wire_switch name="1"/>
<opin_switch name="2"/>
</segment>
<!-- Span 12 vertical tracks -->
<!-- Span 12 horizontal tracks -->
<segment Cmetal="22.5e-15" Rmetal="101" freq="1.000000" length="12" name="span12" type="bidir">
<sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
<cb type="pattern">0 0 0 0 0 0 0 0 0 0 0 0</cb>
<wire_switch name="1"/>
<opin_switch name="2"/>
</segment>
<!-- Span 4 vertical tracks -->
<!-- Span 4 horizontal tracks -->
<segment Cmetal="22.5e-15" Rmetal="101" freq="1.000000" length="4" name="span4" type="bidir">
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">0 0 0 0</cb>
<wire_switch name="1"/>
<opin_switch name="2"/>
</segment>
<!-- Local tracks -->
<segment Cmetal="22.5e-15" Rmetal="101" freq="1.000000" length="1" name="local" type="bidir">
<sb type="pattern">0 1</sb>
<cb type="pattern">1</cb>
<wire_switch name="2"/>
<opin_switch name="2"/>
</segment>
<!--
Neighbourhood tracks
*
-->
<segment Cmetal="22.5e-15" Rmetal="101" freq="1.000000" length="2" name="direct" type="bidir">
<sb type="pattern">0 0 0</sb>
<cb type="pattern">1 1</cb>
<wire_switch name="1"/>
<opin_switch name="2"/>
</segment>
</segmentlist>
</architecture>
Raw
ff.blif
.model top
.inputs clk di
.outputs D1
.latch di D1 re clk 0
.end
Raw
lut.blif
.model top
.inputs I0 I1 I2 I3
.outputs O
.names I0 I1 I2 I3 O
1000 1
1001 1
1010 1
1100 1
1110 1
1111 1
.end
Raw
Makefile
VPR ?= vpr
YOSYS ?= yosys
ifeq (,$(DEVICE))
$(error "Please define $$DEVICE to a value in your architecture file.")
endif
##########################################################################
OUTPUT_DIR ?= build
$(OUTPUT_DIR):
mkdir -p $@
##########################################################################
ARCH_FILE = arch.xml
# VPR commands
VPR_CMD = $(VPR) ../$(ARCH_FILE) --device $(DEVICE) ../$(notdir $<)
VPR_FULL_CMD = cd $(OUTPUT_DIR); $(VPR_CMD)
$(OUTPUT_DIR)/%.rr_graph.xml: %.blif $(ARCH_FILE)
$(VPR_FULL_CMD) $(notdir $<) --write_rr_graph $(notdir $@)
# ------------------------------------------------------------------------
%.rr_graph.xml: $(OUTPUT_DIR)/%.rr_graph.xml | $(OUTPUT_DIR)
@true
.PRECIOUS: $(OUTPUT_DIR)/%.rr_graph.xml
# ------------------------------------------------------------------------
%.disp: %.blif $(OUTPUT_DIR) $(ARCH_FILE)
$(VPR_FULL_CMD) --disp on
%.echo: %.blif $(ARCH_FILE)
$(VPR_FULL_CMD) --echo_file on
%.gdb: %.blif $(ARCH_FILE)
cd $(OUTPUT_DIR); gdb --args $(VPR_CMD) $(notdir $<) --echo_file on --disp on
ALL_OUTPUT = $(patsubst %.v,$(OUTPUT_DIR)/%.rr_graph.xml,$(wildcard *.v)) $(patsubst %.blif,$(OUTPUT_DIR)/%.rr_graph.xml,$(wildcard *.blif))
all: $(ALL_OUTPUT)
@echo $(ALL_OUTPUT)
help:
@echo ""
@echo "For each blif file in this directory you can:"
@echo " make xx.disp - Display the vpr process."
@echo " make xx.echo - Generate useful debugging echo files."
@echo " make xx.gdb - Run vpr process under gdb."
@echo " make xx.rr_graph.xml - Generate rr_graph.xml file."
@echo ""
@echo "You can set the following"
@echo " ARCH=<directory containing merged.xml architecture definition>"
@echo " VPR=<path to vpr>"
@echo " YOSYS=<path to yosys>"
@echo ""
clean:
rm -rf build
.PHONY: all clean help %.gdb %.echo %.disp $(ARCH_FILE)
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