Convert rr_graph file from Verilog-To-Routing into GraphViz `.dot` file

rr-graph-to-dot.py

#!/usr/bin/env python3
#
# Convert rr_graph file from Verilog-To-Routing into GraphViz `.dot` file.
# https://docs.verilogtorouting.org/en/latest/vpr/file_formats/#routing-resource-graph-file-format-xml

from lxml import etree
from io import StringIO, BytesIO

tree = etree.parse('ff.rr_graph.xml')
root = tree.getroot()

import pygraphviz as pgv

G=pgv.AGraph(strict=False,directed=True,overlap="scale")

colors = {
    'SINK':   'red',
    'SOURCE': 'blue',
    'OPIN':   'yellow',
    'IPIN':   'green',
    'CHANX':  'cyan2',
    'CHANY':  'deeppink1',
}

ignored = []

nodes = {}
for n in root.iterfind('.//node'):
    s = n.findall('.//segment')
    if s:
        print(n, s, s[0].attrib['segment_id'])
        if s[0].attrib['segment_id'] == '0' and False:
            ignored.append(n.attrib['id'])
            continue
    t = n.attrib['type']
    nodes[n.attrib['id']] = n
    G.add_node(n.attrib['id'], color=colors[t])

edge_map = {}

for e in root.iterfind('.//edge'):
    ignore = False
    edge_str = "{}->{}".format(e.attrib['src_node'], e.attrib['sink_node'])
    for n in e.attrib['src_node'], e.attrib['sink_node']:
        if n in ignored:
            ignore = True
        if n not in edge_map:
            edge_map[n] = []
        edge_map[n].append(edge_str)
    G.add_edge(e.attrib['src_node'], e.attrib['sink_node'])

import pprint
print("Ignored")
print("="*75)
pprint.pprint(ignored)
print("="*75)

print("Edge Map")
print("="*75)
for k in sorted(edge_map, key=lambda k: len(edge_map[k])):
    if k in ignored:
        continue
    print("{:04d} has {:4d} edges".format(int(k), len(edge_map[k])))
    if len(edge_map[k]) > 25:
        print(" "*4, etree.tostring(nodes[k], encoding='utf8', method='xml').decode('utf-8'))
        print(" "*4, edge_map[k])
print("="*75)

G.write("rr_graph.dot")
G.draw("rr_graph.png",prog="sfdp")