XorShiftVerilogModule

rand.v

// XOR Shift
// from Wikipedia https://ja.wikipedia.org/wiki/Xorshift
module rand(
    input CLK,
    input RST,
    output reg [31:0] X
);
// XOR Shift
wire [31:0] y_1 = X ^ ({X, 13'd0});
wire [31:0] y_2 = y_1 ^ y_1[31:17];
wire [31:0] y_3 = y_2 ^ ({y_2, 15'd0});
always @(posedge CLK) begin
    if (RST) X <= 32'd2463534242;
    else X <= y_3;
end
endmodule

test1.v

module test1();
reg CLK;
reg RST;
wire [31:0] X;
rand r(.CLK(CLK), .RST(RST), .X(X));
always #10 begin
    CLK = ~CLK;
end
task tick();
begin
    @(posedge CLK);
    #1;
end
endtask

task check(input [31:0] expect_X);
begin
    if ( X !== expect_X) $stop();
    tick();
end
endtask
initial begin
    CLK = 0;
    RST = 1;
    tick();
    RST = 0;
    tick();
    check(32'd901999875);
    check(32'd3371835698);
    check(32'd2675058524);
    check(32'd1053936272);
    check(32'd3811264849);
    $display("DONE");
    $finish();
end
endmodule

test2.v

module test2();
reg CLK;
reg RST;
wire [31:0] X;
rand r(.CLK(CLK), .RST(RST), .X(X));
parameter CYCLE = 10;
always #(CYCLE/2) begin
    CLK = ~CLK;
end

initial begin
    CLK = 0;
    RST = 1;
    #CYCLE;
    RST = 0;
    #(CYCLE*20);
    $finish();
end
endmodule