- gpu/drm/panel/panel-simple.c
- mntref2-panel-innolux.patch
+static const struct drm_display_mode innolux_n125hce_gn1_mode = {
+ .clock = 162000,
+ .hdisplay = 1920,
+ .hsync_start = 1920 + 40,
+ .hsync_end = 1920 + 40 + 40,
+ .htotal = 1920 + 40 + 40 + 80,
+ .vdisplay = 1080,
+ .vsync_start = 1080 + 4,
+ .vsync_end = 1080 + 4 + 4,
+ .vtotal = 1080 + 4 + 4 + 24,
+ .vrefresh = 70,
+};
+
+static const struct panel_desc innolux_n125hce_gn1 = {
+ .modes = &innolux_n125hce_gn1_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 276,
+ .height = 155,
+ },
+};
@@ -3577,6 +3600,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "innolux,n116bge",
.data = &innolux_n116bge,
+ }, {
+ .compatible = "innolux,n125hce-gn1",
+ .data = &innolux_n125hce_gn1,
}, {
-
Add-support-for-iMX8MQ-Display-Controller-Subsystem.patch
-
dcss-patch-v4 (in email from laurentiu)
-
DCSS vs mesa: failed to load driver: imx-dcss drivers/gpu/drm/imx/dcss/dcss-kms.c: .name = "imx-dcss", -> need to replace with "imx-drm"
-
needs clock rate adjustment to fix "wandering screen" https://source.puri.sm/Librem5/linux-next/commit/9a0671ab7d83a32f7032853e94da978c286736c6
-
drivers/gpu/drm/imx/dcss/dcss-crtc.c: vm.pixelclock = mode->crtc_clock * 800; // instead of 1000
- tn56dsi86
- could add #define SN_COLOR_BAR_REG 0x3C
-
PATCH-v11-1-2-dt-bindings-display-bridge-Add-binding-for-NWL-mipi-dsi-host-controller.mbox
-
adds gpu/drm/bridge/nwl-dsi.c
-
nwl needs CONFIG_MUX_MMIO or silently fails! guido should add a dependency
-
nwl needs to disable polarity hack for DCSS: nwl_dsi_bridge_mode_fixup()
/* At least LCDIF + NWL needs active high sync */
- adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
- adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
+ //adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
+ //adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
- needs MNT patch to support internal oscillator in drivers/pci/controller/dwc/pci-imx6.c
This is mostly:
+#define IMX8MQ_ANA_PLLOUT_REG 0x74
+#define IMX8MQ_ANA_PLLOUT_CKE BIT(4)
+#define IMX8MQ_ANA_PLLOUT_SEL_MASK 0xF
+#define IMX8MQ_ANA_PLLOUT_SEL_SYSPLL1 0xB
+#define IMX8MQ_ANA_PLLOUT_DIV_REG 0x7C
+#define IMX8MQ_ANA_PLLOUT_SYSPLL1_DIV 0x7
+
+static void imx6_pcie_enable_internal_refclk(void)
+{
+ uint32_t val;
+ struct device_node* np;
+ void __iomem *base;
+
+ np = of_find_compatible_node(NULL, NULL,
+ "fsl,imx8mq-anatop");
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ val = readl(base + IMX8MQ_ANA_PLLOUT_REG);
+ val &= ~IMX8MQ_ANA_PLLOUT_SEL_MASK;
+ val |= IMX8MQ_ANA_PLLOUT_SEL_SYSPLL1;
+ writel(val, base + IMX8MQ_ANA_PLLOUT_REG);
+ /* SYS_PLL1 is 800M, PCIE REF CLK is 100M */
+ val = readl(base + IMX8MQ_ANA_PLLOUT_DIV_REG);
+ val |= IMX8MQ_ANA_PLLOUT_SYSPLL1_DIV;
+ writel(val, base + IMX8MQ_ANA_PLLOUT_DIV_REG);
+
+ val = readl(base + IMX8MQ_ANA_PLLOUT_REG);
+ val |= IMX8MQ_ANA_PLLOUT_CKE;
+ writel(val, base + IMX8MQ_ANA_PLLOUT_REG);
+
+ usleep_range(9000,10000);
+}
And:
case IMX8MQ:
- /*
- * TODO: Currently this code assumes external
- * oscillator is being used
- */
regmap_update_bits(imx6_pcie->iomuxc_gpr,
imx6_pcie_grp_offset(imx6_pcie),
IMX8MQ_GPR_PCIE_REF_USE_PAD,
- IMX8MQ_GPR_PCIE_REF_USE_PAD);
+ (ext_osc ? IMX8MQ_GPR_PCIE_REF_USE_PAD : 0));
Where ext_osc is a flag from device tree, true for PCIE1. PCIE2 has external clock synthesizer in Reform.
- PCIE1 clocks broke with 5.7. solution below.
clk-imx8mq.c needs the following clock reparenting:
clk_hw_set_parent(hws[IMX8MQ_CLK_PCIE1_CTRL], hws[IMX8MQ_SYS2_PLL_250M]);
clk_hw_set_parent(hws[IMX8MQ_CLK_PCIE1_PHY], hws[IMX8MQ_SYS2_PLL_100M]);
clk_hw_set_parent(hws[IMX8MQ_CLK_PCIE2_CTRL], hws[IMX8MQ_SYS2_PLL_250M]);
clk_hw_set_parent(hws[IMX8MQ_CLK_PCIE2_PHY], hws[IMX8MQ_SYS2_PLL_100M]);
- SAI needs a patch, or won't find a matching sampling rate. Not sure if the algorithm in the driver is correct at all.
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -352,17 +352,17 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
* Drop the source that can not be
* divided into the required rate.
*/
- if (ret != 0 && clk_rate / ret < 1000)
- continue;
- dev_dbg(dai->dev,
+ dev_info(dai->dev,
"ratio %d for freq %dHz based on clock %ldHz\n",
ratio, freq, clk_rate);
if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
ratio /= 2;
- else
- continue;
if (ret < savesub) {
savediv = ratio;