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Boot logs from Rock Pi 4
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DDR Version 1.20 20190314 | |
In | |
channel 0 | |
CS = 0 | |
MR0=0xB8 | |
MR4=0x1 | |
MR5=0xFF | |
MR8=0x10 | |
MR12=0x72 | |
MR14=0x72 | |
MR18=0x0 | |
MR19=0x0 | |
MR24=0x8 | |
MR25=0x0 | |
channel 1 | |
CS = 0 | |
MR0=0xB8 | |
MR4=0x1 | |
MR5=0xFF | |
MR8=0x10 | |
MR12=0x72 | |
MR14=0x72 | |
MR18=0x0 | |
MR19=0x0 | |
MR24=0x8 | |
MR25=0x0 | |
channel 0 training pass! | |
channel 1 training pass! | |
change freq to 400MHz 0,1 | |
channel 0 | |
CS = 0 | |
MR0=0xB8 | |
MR4=0x1 | |
MR5=0xFF | |
MR8=0x10 | |
MR12=0x72 | |
MR14=0x72 | |
MR18=0x0 | |
MR19=0x0 | |
MR24=0x8 | |
MR25=0x0 | |
channel 1 | |
CS = 0 | |
MR0=0xB8 | |
MR4=0x1 | |
MR5=0xFF | |
MR8=0x10 | |
MR12=0x72 | |
MR14=0x72 | |
MR18=0x0 | |
MR19=0x0 | |
MR24=0x8 | |
MR25=0x0 | |
channel 0 training pass! | |
channel 1 training pass! | |
change freq to 800MHz 1,0 | |
Channel 0: LPDDR4,800MHz | |
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB | |
Channel 1: LPDDR4,800MHz | |
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB | |
256B stride | |
ch 0 ddrconfig = 0x101, ddrsize = 0x40 | |
ch 1 ddrconfig = 0x101, ddrsize = 0x40 | |
pmugrf_os_reg[2] = 0x32C1F2C1, stride = 0xD | |
OUT | |
Boot1: 2018-06-26, version: 1.14 | |
CPUId = 0x0 | |
ChipType = 0x10, 220 | |
Spi_ChipId = b4016 | |
SpiBootInit:0 | |
mmc0:cmd8,32 | |
mmc0:cmd5,32 | |
mmc0:cmd55,32 | |
mmc0:cmd1,32 | |
mmc0:cmd8,32 | |
mmc0:cmd5,32 | |
mmc0:cmd55,32 | |
mmc0:cmd1,32 | |
mmc0:cmd8,32 | |
mmc0:cmd5,32 | |
mmc0:cmd55,32 | |
mmc0:cmd1,32 | |
SdmmcInit=0 1 | |
StorageInit ok = 21713 | |
SecureMode = 0 | |
SecureInit ret = 0, SecureMode = 0 | |
GPT vendor signature is wrong | |
LoadTrust Addr:0x1800 | |
No find bl30.bin | |
No find bl32.bin | |
Load uboot, ReadLba = 1000 | |
Load OK, addr=0x200000, size=0xee888 | |
RunBL31 0x10000 | |
NOTICE: BL31: v1.3(debug):0e7a845 | |
NOTICE: BL31: Built : 16:13:46, Apr 17 2019 | |
NOTICE: BL31: Rockchip release version: v1.1 | |
INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 | |
INFO: Using opteed sec cpu_context! | |
INFO: boot cpu mask: 0 | |
INFO: plat_rockchip_pmu_init(1181): pd status 3e | |
INFO: BL31: Initializing runtime services | |
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK | |
ERROR: Error initializing runtime service opteed_fast | |
INFO: BL31: Preparing for EL3 exit to normal world | |
INFO: Entry point address = 0x200000 | |
INFO: SPSR = 0x3c9 | |
U-Boot 2017.09-02676-g4490220395 (Jul 01 2019 - 07:49:56 +0000) | |
Model: Rockchip RK3399 rockpi4b Board | |
PreSerial: 2 | |
DRAM: 3.9 GiB | |
Relocation Offset is: f5be0000 | |
Sysmem: init | |
I2c speed: 400000Hz | |
PMIC: RK808 | |
vdd-center init 950000 uV | |
MMC: dwmmc@fe320000: 1, sdhci@fe330000: 0 | |
Using default environment | |
Model: Rockchip RK3399 rockpi4b Board | |
dcache off | |
Device 0: unknown device | |
dcache on | |
Card did not respond to voltage select! | |
mmc_init: -95, time 9 | |
switch to partitions #0, OK | |
mmc0(part 0) is current device | |
Bootdev: mmc 0 | |
PartType: EFI | |
boot mode: None | |
Load FDT from boot part | |
Rockchip UBOOT DRM driver version: v1.0.1 |
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