ssd1306 example with pic16f690

ssd1306.c

/*
 * File:   main.c
 * Author: neurosys
 *
 * Created on October 23, 2019, 10:27 PM
 */



#include <xc.h>
#include <pic16f690.h>

#define _XTAL_FREQ 4000000


// CONFIG
#pragma config FOSC = INTRCCLK  // Oscillator Selection bits (INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN)
#pragma config WDTE = OFF       // Watchdog Timer Enable bit (WDT disabled and can be enabled by SWDTEN bit of the WDTCON register)
#pragma config PWRTE = OFF      // Power-up Timer Enable bit (PWRT disabled)
#pragma config MCLRE = OFF      // MCLR Pin Function Select bit (MCLR pin function is digital input, MCLR internally tied to VDD)
#pragma config CP = OFF         // Code Protection bit (Program memory code protection is disabled)
#pragma config CPD = OFF        // Data Code Protection bit (Data memory code protection is disabled)
#pragma config BOREN = ON       // Brown-out Reset Selection bits (BOR enabled)
#pragma config IESO = ON        // Internal External Switchover bit (Internal External Switchover mode is enabled)
#pragma config FCMEN = ON       // Fail-Safe Clock Monitor Enabled bit (Fail-Safe Clock Monitor is enabled)

#define SSD_VCC RC0
#define SSD_RES RC1

#define SSD1306_CMD 0
#define SSD1306_DAT 1

void ssd_send(unsigned char data, unsigned char dc)
{
    if (dc) {
        PORTB |= (1 << 5);
    } else {
        PORTB &= ~(1 << 5);
    }
    SSPBUF = data;
}
    
void main(void) {
//     bank 1
    STATUSbits.RP = 1;    
    OSCCONbits.IRCF = 0b110;
    OSCCONbits.OSTS = 0;
    OSCCONbits.SCS = 1;
    
    TRISC = 0;
    TRISB = 0;
    
    STATUSbits.RP = 0;
    
    __delay_ms(1);
    // After VDD become stable, set RES# pin LOW (logic low) for at least 3us (t1) (4) and then HIGH (logic high).
    // After set RES# pin LOW (logic low), wait for at least 3us (t2). Then Power ON VCC.
    PORTC = 0;
    __delay_us(3);
    PORTC = (1 << 0) | (1 << 1);
    
    // Enable SPI
    // bank 1
    STATUSbits.RP = 1; 
    SSPSTATbits.SMP = 1;
    SSPSTATbits.CKE = 1;
    SSPCONbits.SSPEN = 1;
    
    // After VCC become stable, send command AFh for display ON. SEG/COM will be ON after 100ms (tAF)
    ssd_send(0xaf, SSD1306_CMD);
    __delay_ms(100);
    
    // set contrast
    ssd_send(0x81, SSD1306_CMD);
    ssd_send(0xff, SSD1306_CMD);
    
    // set horizontal addressing mode
    ssd_send(0x20, SSD1306_CMD);
    
    // Setup column start and end address 
    ssd_send(0x21, SSD1306_CMD);
    ssd_send(0, SSD1306_CMD);
    ssd_send(127, SSD1306_CMD);
    
    // Setup page start and end address
    ssd_send(0x22, SSD1306_CMD);
    ssd_send(0, SSD1306_CMD);
    ssd_send(7, SSD1306_CMD);
        
    int x, y, page;

    // clear screen
    for (x = 0; x < 8 * 128; x++) {
        ssd_send(0, SSD1306_DAT);
    }
    
    // draw pattern
    for (page = 0; page < 8; page++) {
        for (x = 0; x < 128; x++) {
            unsigned char seg = 0;
            for (y = 0; y < 8; y++) {
                char p = (x ^ y) % 2;

                if (p) {
                    seg |= (1 << y);
                }
            }
            ssd_send(seg, SSD1306_DAT);
        }
    }


    while (1) {}
    
    return;
}