Skip to content

Instantly share code, notes, and snippets.

@nikic

nikic/fastisel_no_xor.diff Secret

Created March 28, 2021 13:42
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save nikic/04876ffe96a5ee2ffb4be102cbbb8d60 to your computer and use it in GitHub Desktop.
Save nikic/04876ffe96a5ee2ffb4be102cbbb8d60 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
fastisel_no_xor.diff
commit ddba55a74aa5965ce0b51552e0dcb8cc4e3296a7
Author: Nikita Popov <nikita.ppv@gmail.com>
Date: Sun Mar 28 15:40:46 2021 +0200
don't use xor to zero register
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index b37cd25c7de1..9106157aaf01 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -3713,29 +3713,6 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
return 0;
uint64_t Imm = CI->getZExtValue();
- if (Imm == 0) {
- Register SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass);
- switch (VT.SimpleTy) {
- default: llvm_unreachable("Unexpected value type");
- case MVT::i1:
- case MVT::i8:
- return fastEmitInst_extractsubreg(MVT::i8, SrcReg, /*Op0IsKill=*/true,
- X86::sub_8bit);
- case MVT::i16:
- return fastEmitInst_extractsubreg(MVT::i16, SrcReg, /*Op0IsKill=*/true,
- X86::sub_16bit);
- case MVT::i32:
- return SrcReg;
- case MVT::i64: {
- Register ResultReg = createResultReg(&X86::GR64RegClass);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
- TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg)
- .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
- return ResultReg;
- }
- }
- }
-
unsigned Opc = 0;
switch (VT.SimpleTy) {
default: llvm_unreachable("Unexpected value type");
diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll
index f5eaa6f2409a..06a10aa6aada 100644
--- a/llvm/test/CodeGen/X86/atomic-unordered.ll
+++ b/llvm/test/CodeGen/X86/atomic-unordered.ll
@@ -321,7 +321,7 @@ define i256 @load_i256(i256* %ptr) {
; CHECK-O0-NEXT: movl $32, %edi
; CHECK-O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx
; CHECK-O0-NEXT: xorl %ecx, %ecx
-; CHECK-O0-NEXT: callq __atomic_load
+; CHECK-O0-NEXT: callq __atomic_load@PLT
; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload
; CHECK-O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; CHECK-O0-NEXT: movq {{[0-9]+}}(%rsp), %rcx
@@ -347,7 +347,7 @@ define i256 @load_i256(i256* %ptr) {
; CHECK-O3-NEXT: movq %rsp, %rdx
; CHECK-O3-NEXT: movl $32, %edi
; CHECK-O3-NEXT: xorl %ecx, %ecx
-; CHECK-O3-NEXT: callq __atomic_load
+; CHECK-O3-NEXT: callq __atomic_load@PLT
; CHECK-O3-NEXT: vmovups (%rsp), %ymm0
; CHECK-O3-NEXT: vmovups %ymm0, (%rbx)
; CHECK-O3-NEXT: movq %rbx, %rax
@@ -376,8 +376,8 @@ define void @store_i256(i256* %ptr, i256 %v) {
; CHECK-O0-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
; CHECK-O0-NEXT: movq %r8, {{[0-9]+}}(%rsp)
; CHECK-O0-NEXT: movl $32, %edi
-; CHECK-O0-NEXT: xorl %ecx, %ecx
-; CHECK-O0-NEXT: callq __atomic_store
+; CHECK-O0-NEXT: movl $0, %ecx
+; CHECK-O0-NEXT: callq __atomic_store@PLT
; CHECK-O0-NEXT: addq $40, %rsp
; CHECK-O0-NEXT: .cfi_def_cfa_offset 8
; CHECK-O0-NEXT: retq
@@ -395,7 +395,7 @@ define void @store_i256(i256* %ptr, i256 %v) {
; CHECK-O3-NEXT: movl $32, %edi
; CHECK-O3-NEXT: movq %rax, %rsi
; CHECK-O3-NEXT: xorl %ecx, %ecx
-; CHECK-O3-NEXT: callq __atomic_store
+; CHECK-O3-NEXT: callq __atomic_store@PLT
; CHECK-O3-NEXT: addq $40, %rsp
; CHECK-O3-NEXT: .cfi_def_cfa_offset 8
; CHECK-O3-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/avx512-calling-conv.ll b/llvm/test/CodeGen/X86/avx512-calling-conv.ll
index 515787e98ece..dad3116f832f 100644
--- a/llvm/test/CodeGen/X86/avx512-calling-conv.ll
+++ b/llvm/test/CodeGen/X86/avx512-calling-conv.ll
@@ -506,7 +506,7 @@ define i32 @test12(i32 %a1, i32 %a2, i32 %b1) {
; FASTISEL-NEXT: movl %r14d, %esi
; FASTISEL-NEXT: movl %ebx, %edx
; FASTISEL-NEXT: callq _test10
-; FASTISEL-NEXT: xorl %ecx, %ecx
+; FASTISEL-NEXT: movl $0, %ecx
; FASTISEL-NEXT: testb $1, %bl
; FASTISEL-NEXT: cmovel %ecx, %eax
; FASTISEL-NEXT: popq %rbx
diff --git a/llvm/test/CodeGen/X86/avx512-fsel.ll b/llvm/test/CodeGen/X86/avx512-fsel.ll
index 6efb66e6865e..7b7a56bb2a91 100644
--- a/llvm/test/CodeGen/X86/avx512-fsel.ll
+++ b/llvm/test/CodeGen/X86/avx512-fsel.ll
@@ -21,7 +21,7 @@ define i32 @test(float %a, float %b) {
; CHECK-NEXT: callq ___assert_rtn
; CHECK-NEXT: ud2
; CHECK-NEXT: LBB0_2: ## %L_1
-; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movl $0, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
%x10 = fcmp oeq float %a, %b
diff --git a/llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel-x86_64.ll b/llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel-x86_64.ll
index d704f38307fc..8af17dafa4b5 100644
--- a/llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel-x86_64.ll
+++ b/llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel-x86_64.ll
@@ -31,7 +31,7 @@ define i64 @test__bextr_u64(i64 %a0, i64 %a1) {
define i64 @test__blsi_u64(i64 %a0) {
; X64-LABEL: test__blsi_u64:
; X64: # %bb.0:
-; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: movl $0, %eax
; X64-NEXT: subq %rdi, %rax
; X64-NEXT: andq %rdi, %rax
; X64-NEXT: retq
@@ -110,7 +110,7 @@ define i64 @test_bextr_u64(i64 %a0, i32 %a1, i32 %a2) {
define i64 @test_blsi_u64(i64 %a0) {
; X64-LABEL: test_blsi_u64:
; X64: # %bb.0:
-; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: movl $0, %eax
; X64-NEXT: subq %rdi, %rax
; X64-NEXT: andq %rdi, %rax
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
index fc3e54e06d5f..6354e594c96f 100644
--- a/llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
@@ -62,14 +62,14 @@ define i32 @test__blsi_u32(i32 %a0) {
; X86-LABEL: test__blsi_u32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: movl $0, %eax
; X86-NEXT: subl %ecx, %eax
; X86-NEXT: andl %ecx, %eax
; X86-NEXT: retl
;
; X64-LABEL: test__blsi_u32:
; X64: # %bb.0:
-; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: movl $0, %eax
; X64-NEXT: subl %edi, %eax
; X64-NEXT: andl %edi, %eax
; X64-NEXT: retq
@@ -202,14 +202,14 @@ define i32 @test_blsi_u32(i32 %a0) {
; X86-LABEL: test_blsi_u32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: movl $0, %eax
; X86-NEXT: subl %ecx, %eax
; X86-NEXT: andl %ecx, %eax
; X86-NEXT: retl
;
; X64-LABEL: test_blsi_u32:
; X64: # %bb.0:
-; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: movl $0, %eax
; X64-NEXT: subl %edi, %eax
; X64-NEXT: andl %edi, %eax
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/crash-O0.ll b/llvm/test/CodeGen/X86/crash-O0.ll
index 1b64247d170a..69aa0e6ba4de 100644
--- a/llvm/test/CodeGen/X86/crash-O0.ll
+++ b/llvm/test/CodeGen/X86/crash-O0.ll
@@ -16,13 +16,11 @@ define i32 @div8() nounwind {
; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: ## implicit-def: $rax
; CHECK-NEXT: movb %al, %cl
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: ## kill: def $al killed $al killed $eax
+; CHECK-NEXT: movb $0, %al
; CHECK-NEXT: movzbw %al, %ax
; CHECK-NEXT: divb %cl
; CHECK-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: ## kill: def $al killed $al killed $eax
+; CHECK-NEXT: movb $0, %al
; CHECK-NEXT: movzbw %al, %ax
; CHECK-NEXT: divb %cl
; CHECK-NEXT: shrw $8, %ax
@@ -80,8 +78,7 @@ define i64 @addressModeWith32bitIndex(i32 %V) {
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: .cfi_def_cfa_register %rbp
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: movl $0, %ecx
; CHECK-NEXT: movq %rcx, %rax
; CHECK-NEXT: cqto
; CHECK-NEXT: movslq %edi, %rsi
diff --git a/llvm/test/CodeGen/X86/fast-isel-cmp-branch3.ll b/llvm/test/CodeGen/X86/fast-isel-cmp-branch3.ll
index 8f09b2e38356..43e575bdb979 100644
--- a/llvm/test/CodeGen/X86/fast-isel-cmp-branch3.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-cmp-branch3.ll
@@ -1,9 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
define i32 @fcmp_oeq1(float %x) {
-; CHECK-LABEL: fcmp_oeq1
-; CHECK: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: jp {{LBB.+_1}}
+; CHECK-LABEL: fcmp_oeq1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: ucomiss %xmm0, %xmm0
+; CHECK-NEXT: jp LBB0_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB0_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp oeq float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -13,11 +21,18 @@ bb1:
}
define i32 @fcmp_oeq2(float %x) {
-; CHECK-LABEL: fcmp_oeq2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm1, %xmm0
-; CHECK-NEXT: jne {{LBB.+_1}}
-; CHECK-NEXT: jp {{LBB.+_1}}
+; CHECK-LABEL: fcmp_oeq2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm1, %xmm0
+; CHECK-NEXT: jne LBB1_1
+; CHECK-NEXT: jp LBB1_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB1_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp oeq float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -27,9 +42,10 @@ bb1:
}
define i32 @fcmp_ogt1(float %x) {
-; CHECK-LABEL: fcmp_ogt1
-; CHECK-NOT: ucomiss
-; CHECK: movl $1, %eax
+; CHECK-LABEL: fcmp_ogt1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ogt float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -39,10 +55,17 @@ bb1:
}
define i32 @fcmp_ogt2(float %x) {
-; CHECK-LABEL: fcmp_ogt2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm1, %xmm0
-; CHECK-NEXT: jbe {{LBB.+_1}}
+; CHECK-LABEL: fcmp_ogt2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm1, %xmm0
+; CHECK-NEXT: jbe LBB3_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB3_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ogt float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -52,9 +75,16 @@ bb1:
}
define i32 @fcmp_oge1(float %x) {
-; CHECK-LABEL: fcmp_oge1
-; CHECK: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: jp {{LBB.+_1}}
+; CHECK-LABEL: fcmp_oge1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: ucomiss %xmm0, %xmm0
+; CHECK-NEXT: jp LBB4_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB4_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp oge float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -64,10 +94,17 @@ bb1:
}
define i32 @fcmp_oge2(float %x) {
-; CHECK-LABEL: fcmp_oge2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm1, %xmm0
-; CHECK-NEXT: jb {{LBB.+_1}}
+; CHECK-LABEL: fcmp_oge2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm1, %xmm0
+; CHECK-NEXT: jb LBB5_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB5_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp oge float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -77,9 +114,10 @@ bb1:
}
define i32 @fcmp_olt1(float %x) {
-; CHECK-LABEL: fcmp_olt1
-; CHECK-NOT: ucomiss
-; CHECK: movl $1, %eax
+; CHECK-LABEL: fcmp_olt1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp olt float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -89,10 +127,17 @@ bb1:
}
define i32 @fcmp_olt2(float %x) {
-; CHECK-LABEL: fcmp_olt2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm0, %xmm1
-; CHECK-NEXT: jbe {{LBB.+_1}}
+; CHECK-LABEL: fcmp_olt2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm0, %xmm1
+; CHECK-NEXT: jbe LBB7_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB7_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp olt float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -102,9 +147,16 @@ bb1:
}
define i32 @fcmp_ole1(float %x) {
-; CHECK-LABEL: fcmp_ole1
-; CHECK: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: jp {{LBB.+_1}}
+; CHECK-LABEL: fcmp_ole1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: ucomiss %xmm0, %xmm0
+; CHECK-NEXT: jp LBB8_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB8_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ole float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -114,10 +166,17 @@ bb1:
}
define i32 @fcmp_ole2(float %x) {
-; CHECK-LABEL: fcmp_ole2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm0, %xmm1
-; CHECK-NEXT: jb {{LBB.+_1}}
+; CHECK-LABEL: fcmp_ole2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm0, %xmm1
+; CHECK-NEXT: jb LBB9_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB9_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ole float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -127,9 +186,10 @@ bb1:
}
define i32 @fcmp_one1(float %x) {
-; CHECK-LABEL: fcmp_one1
-; CHECK-NOT: ucomiss
-; CHECK: movl $1, %eax
+; CHECK-LABEL: fcmp_one1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp one float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -139,10 +199,17 @@ bb1:
}
define i32 @fcmp_one2(float %x) {
-; CHECK-LABEL: fcmp_one2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm1, %xmm0
-; CHECK-NEXT: je {{LBB.+_1}}
+; CHECK-LABEL: fcmp_one2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm1, %xmm0
+; CHECK-NEXT: je LBB11_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB11_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp one float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -152,9 +219,16 @@ bb1:
}
define i32 @fcmp_ord1(float %x) {
-; CHECK-LABEL: fcmp_ord1
-; CHECK: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: jp {{LBB.+_1}}
+; CHECK-LABEL: fcmp_ord1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: ucomiss %xmm0, %xmm0
+; CHECK-NEXT: jp LBB12_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB12_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ord float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -164,9 +238,16 @@ bb1:
}
define i32 @fcmp_ord2(float %x) {
-; CHECK-LABEL: fcmp_ord2
-; CHECK: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: jp {{LBB.+_1}}
+; CHECK-LABEL: fcmp_ord2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: ucomiss %xmm0, %xmm0
+; CHECK-NEXT: jp LBB13_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB13_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ord float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -176,9 +257,16 @@ bb1:
}
define i32 @fcmp_uno1(float %x) {
-; CHECK-LABEL: fcmp_uno1
-; CHECK: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: jp {{LBB.+_2}}
+; CHECK-LABEL: fcmp_uno1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: ucomiss %xmm0, %xmm0
+; CHECK-NEXT: jp LBB14_2
+; CHECK-NEXT: ## %bb.1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB14_2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = fcmp uno float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -188,9 +276,16 @@ bb1:
}
define i32 @fcmp_uno2(float %x) {
-; CHECK-LABEL: fcmp_uno2
-; CHECK: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: jp {{LBB.+_2}}
+; CHECK-LABEL: fcmp_uno2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: ucomiss %xmm0, %xmm0
+; CHECK-NEXT: jp LBB15_2
+; CHECK-NEXT: ## %bb.1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB15_2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = fcmp uno float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -200,8 +295,10 @@ bb1:
}
define i32 @fcmp_ueq1(float %x) {
-; CHECK-LABEL: fcmp_ueq1
-; CHECK-NOT: ucomiss
+; CHECK-LABEL: fcmp_ueq1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = fcmp ueq float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -211,10 +308,17 @@ bb1:
}
define i32 @fcmp_ueq2(float %x) {
-; CHECK-LABEL: fcmp_ueq2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm1, %xmm0
-; CHECK-NEXT: je {{LBB.+_2}}
+; CHECK-LABEL: fcmp_ueq2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm1, %xmm0
+; CHECK-NEXT: je LBB17_2
+; CHECK-NEXT: ## %bb.1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB17_2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = fcmp ueq float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -224,9 +328,16 @@ bb1:
}
define i32 @fcmp_ugt1(float %x) {
-; CHECK-LABEL: fcmp_ugt1
-; CHECK: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: jnp {{LBB.+_1}}
+; CHECK-LABEL: fcmp_ugt1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: ucomiss %xmm0, %xmm0
+; CHECK-NEXT: jnp LBB18_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB18_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ugt float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -236,10 +347,17 @@ bb1:
}
define i32 @fcmp_ugt2(float %x) {
-; CHECK-LABEL: fcmp_ugt2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm0, %xmm1
-; CHECK-NEXT: jae {{LBB.+_1}}
+; CHECK-LABEL: fcmp_ugt2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm0, %xmm1
+; CHECK-NEXT: jae LBB19_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB19_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ugt float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -249,8 +367,10 @@ bb1:
}
define i32 @fcmp_uge1(float %x) {
-; CHECK-LABEL: fcmp_uge1
-; CHECK-NOT: ucomiss
+; CHECK-LABEL: fcmp_uge1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = fcmp uge float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -260,10 +380,17 @@ bb1:
}
define i32 @fcmp_uge2(float %x) {
-; CHECK-LABEL: fcmp_uge2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm0, %xmm1
-; CHECK-NEXT: ja {{LBB.+_1}}
+; CHECK-LABEL: fcmp_uge2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm0, %xmm1
+; CHECK-NEXT: ja LBB21_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB21_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp uge float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -273,9 +400,16 @@ bb1:
}
define i32 @fcmp_ult1(float %x) {
-; CHECK-LABEL: fcmp_ult1
-; CHECK: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: jnp {{LBB.+_1}}
+; CHECK-LABEL: fcmp_ult1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: ucomiss %xmm0, %xmm0
+; CHECK-NEXT: jnp LBB22_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB22_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ult float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -285,10 +419,17 @@ bb1:
}
define i32 @fcmp_ult2(float %x) {
-; CHECK-LABEL: fcmp_ult2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm1, %xmm0
-; CHECK-NEXT: jae {{LBB.+_1}}
+; CHECK-LABEL: fcmp_ult2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm1, %xmm0
+; CHECK-NEXT: jae LBB23_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB23_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ult float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -298,8 +439,10 @@ bb1:
}
define i32 @fcmp_ule1(float %x) {
-; CHECK-LABEL: fcmp_ule1
-; CHECK-NOT: ucomiss
+; CHECK-LABEL: fcmp_ule1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = fcmp ule float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -309,10 +452,17 @@ bb1:
}
define i32 @fcmp_ule2(float %x) {
-; CHECK-LABEL: fcmp_ule2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm1, %xmm0
-; CHECK-NEXT: ja {{LBB.+_1}}
+; CHECK-LABEL: fcmp_ule2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm1, %xmm0
+; CHECK-NEXT: ja LBB25_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB25_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp ule float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -322,9 +472,16 @@ bb1:
}
define i32 @fcmp_une1(float %x) {
-; CHECK-LABEL: fcmp_une1
-; CHECK: ucomiss %xmm0, %xmm0
-; CHECK-NEXT: jnp {{LBB.+_1}}
+; CHECK-LABEL: fcmp_une1:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: ucomiss %xmm0, %xmm0
+; CHECK-NEXT: jnp LBB26_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB26_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp une float %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -334,11 +491,18 @@ bb1:
}
define i32 @fcmp_une2(float %x) {
-; CHECK-LABEL: fcmp_une2
-; CHECK: xorps %xmm1, %xmm1
-; CHECK-NEXT: ucomiss %xmm1, %xmm0
-; CHECK-NEXT: jne {{LBB.+_2}}
-; CHECK-NEXT: jnp {{LBB.+_1}}
+; CHECK-LABEL: fcmp_une2:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomiss %xmm1, %xmm0
+; CHECK-NEXT: jne LBB27_2
+; CHECK-NEXT: jnp LBB27_1
+; CHECK-NEXT: LBB27_2: ## %bb1
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB27_1: ## %bb2
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = fcmp une float %x, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb2:
@@ -348,9 +512,10 @@ bb1:
}
define i32 @icmp_eq(i32 %x) {
-; CHECK-LABEL: icmp_eq
-; CHECK-NOT: cmpl
-; CHECK: xorl %eax, %eax
+; CHECK-LABEL: icmp_eq:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = icmp eq i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -360,9 +525,10 @@ bb1:
}
define i32 @icmp_ne(i32 %x) {
-; CHECK-LABEL: icmp_ne
-; CHECK-NOT: cmpl
-; CHECK: movl $1, %eax
+; CHECK-LABEL: icmp_ne:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = icmp ne i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -372,9 +538,10 @@ bb1:
}
define i32 @icmp_ugt(i32 %x) {
-; CHECK-LABEL: icmp_ugt
-; CHECK-NOT: cmpl
-; CHECK: movl $1, %eax
+; CHECK-LABEL: icmp_ugt:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = icmp ugt i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -384,9 +551,10 @@ bb1:
}
define i32 @icmp_uge(i32 %x) {
-; CHECK-LABEL: icmp_uge
-; CHECK-NOT: cmpl
-; CHECK: xorl %eax, %eax
+; CHECK-LABEL: icmp_uge:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = icmp uge i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -396,9 +564,10 @@ bb1:
}
define i32 @icmp_ult(i32 %x) {
-; CHECK-LABEL: icmp_ult
-; CHECK-NOT: cmpl
-; CHECK: movl $1, %eax
+; CHECK-LABEL: icmp_ult:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = icmp ult i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -408,9 +577,10 @@ bb1:
}
define i32 @icmp_ule(i32 %x) {
-; CHECK-LABEL: icmp_ule
-; CHECK-NOT: cmpl
-; CHECK: xorl %eax, %eax
+; CHECK-LABEL: icmp_ule:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = icmp ule i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -420,9 +590,10 @@ bb1:
}
define i32 @icmp_sgt(i32 %x) {
-; CHECK-LABEL: icmp_sgt
-; CHECK-NOT: cmpl
-; CHECK: movl $1, %eax
+; CHECK-LABEL: icmp_sgt:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = icmp sgt i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -432,9 +603,10 @@ bb1:
}
define i32 @icmp_sge(i32 %x) {
-; CHECK-LABEL: icmp_sge
-; CHECK-NOT: cmpl
-; CHECK: xorl %eax, %eax
+; CHECK-LABEL: icmp_sge:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = icmp sge i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -444,9 +616,10 @@ bb1:
}
define i32 @icmp_slt(i32 %x) {
-; CHECK-LABEL: icmp_slt
-; CHECK-NOT: cmpl
-; CHECK: movl $1, %eax
+; CHECK-LABEL: icmp_slt:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: retq
%1 = icmp slt i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
@@ -456,9 +629,10 @@ bb1:
}
define i32 @icmp_sle(i32 %x) {
-; CHECK-LABEL: icmp_sle
-; CHECK-NOT: cmpl
-; CHECK: xorl %eax, %eax
+; CHECK-LABEL: icmp_sle:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: retq
%1 = icmp sle i32 %x, %x
br i1 %1, label %bb1, label %bb2
bb2:
diff --git a/llvm/test/CodeGen/X86/fast-isel-mem.ll b/llvm/test/CodeGen/X86/fast-isel-mem.ll
index 3564c5db3567..d7ed6c664306 100644
--- a/llvm/test/CodeGen/X86/fast-isel-mem.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-mem.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -mtriple=i386-apple-darwin -mcpu=generic | FileCheck %s
; RUN: llc < %s -fast-isel -mtriple=i386-apple-darwin -mcpu=atom | FileCheck -check-prefix=ATOM %s
; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64 | FileCheck -check-prefix=ELF64 %s
@@ -6,6 +7,35 @@
; rdar://6653118
define i32 @loadgv() nounwind {
+; CHECK-LABEL: loadgv:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: movl L_src$non_lazy_ptr, %eax
+; CHECK-NEXT: movl (%eax), %eax
+; CHECK-NEXT: movl L_src$non_lazy_ptr, %ecx
+; CHECK-NEXT: addl (%ecx), %eax
+; CHECK-NEXT: movl L_src$non_lazy_ptr, %ecx
+; CHECK-NEXT: movl %eax, (%ecx)
+; CHECK-NEXT: retl
+;
+; ATOM-LABEL: loadgv:
+; ATOM: ## %bb.0: ## %entry
+; ATOM-NEXT: movl L_src$non_lazy_ptr, %eax
+; ATOM-NEXT: movl (%eax), %eax
+; ATOM-NEXT: movl L_src$non_lazy_ptr, %ecx
+; ATOM-NEXT: addl (%ecx), %eax
+; ATOM-NEXT: movl L_src$non_lazy_ptr, %ecx
+; ATOM-NEXT: movl %eax, (%ecx)
+; ATOM-NEXT: retl
+;
+; ELF64-LABEL: loadgv:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: movq src@{{.*}}(%rip), %rax
+; ELF64-NEXT: movl (%rax), %eax
+; ELF64-NEXT: movq src@{{.*}}(%rip), %rcx
+; ELF64-NEXT: addl (%rcx), %eax
+; ELF64-NEXT: movq src@{{.*}}(%rip), %rcx
+; ELF64-NEXT: movl %eax, (%rcx)
+; ELF64-NEXT: retq
entry:
%0 = load i32, i32* @src, align 4
%1 = load i32, i32* @src, align 4
@@ -13,33 +43,9 @@ entry:
store i32 %2, i32* @src
ret i32 %2
; This should fold one of the loads into the add.
-; CHECK-LABEL: loadgv:
-; CHECK: movl L_src$non_lazy_ptr, %eax
-; CHECK: movl (%eax), %eax
-; CHECK: movl L_src$non_lazy_ptr, %ecx
-; CHECK: addl (%ecx), %eax
-; CHECK: movl L_src$non_lazy_ptr, %ecx
-; CHECK: movl %eax, (%ecx)
-; CHECK: ret
-
-; ATOM: loadgv:
-; ATOM: movl L_src$non_lazy_ptr, %eax
-; ATOM: movl (%eax), %eax
-; ATOM: movl L_src$non_lazy_ptr, %ecx
-; ATOM: addl (%ecx), %eax
-; ATOM: movl L_src$non_lazy_ptr, %ecx
-; ATOM: movl %eax, (%ecx)
-; ATOM: ret
+
;; dso_preemptable src is loaded via GOT indirection.
-; ELF64-LABEL: loadgv:
-; ELF64: movq src@GOTPCREL(%rip), %rax
-; ELF64-NEXT: movl (%rax), %eax
-; ELF64-NEXT: movq src@GOTPCREL(%rip), %rcx
-; ELF64-NEXT: addl (%rcx), %eax
-; ELF64-NEXT: movq src@GOTPCREL(%rip), %rcx
-; ELF64-NEXT: movl %eax, (%rcx)
-; ELF64-NEXT: retq
}
@@ -47,15 +53,32 @@ entry:
@LotsStuff = external constant [4 x i32 (...)*]
define void @t(%stuff* %this) nounwind {
+; CHECK-LABEL: t:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: movl $0, %eax
+; CHECK-NEXT: movl L_LotsStuff$non_lazy_ptr, %ecx
+; CHECK-NEXT: addl $8, %ecx
+; CHECK-NEXT: movl %ecx, (%eax)
+; CHECK-NEXT: retl
+;
+; ATOM-LABEL: t:
+; ATOM: ## %bb.0: ## %entry
+; ATOM-NEXT: movl L_LotsStuff$non_lazy_ptr, %eax
+; ATOM-NEXT: movl $0, %ecx
+; ATOM-NEXT: addl $8, %eax
+; ATOM-NEXT: movl %eax, (%ecx)
+; ATOM-NEXT: retl
+;
+; ELF64-LABEL: t:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: movl $0, %eax
+; ELF64-NEXT: movq LotsStuff@{{.*}}(%rip), %rcx
+; ELF64-NEXT: addq $16, %rcx
+; ELF64-NEXT: movq %rcx, (%rax)
+; ELF64-NEXT: retq
entry:
store i32 (...)** getelementptr ([4 x i32 (...)*], [4 x i32 (...)*]* @LotsStuff, i32 0, i32 2), i32 (...)*** null, align 4
ret void
-; CHECK: _t:
-; CHECK: xorl %eax, %eax
-; CHECK: movl L_LotsStuff$non_lazy_ptr, %ecx
-; ATOM: _t:
-; ATOM: movl L_LotsStuff$non_lazy_ptr, %e{{..}}
-; ATOM: xorl %e{{..}}, %e{{..}}
}
diff --git a/llvm/test/CodeGen/X86/fast-isel-select.ll b/llvm/test/CodeGen/X86/fast-isel-select.ll
index 94477f3286e4..6a99c33ac164 100644
--- a/llvm/test/CodeGen/X86/fast-isel-select.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-select.ll
@@ -12,7 +12,7 @@ define i32 @fastisel_select(i1 %exchSub2211_, i1 %trunc_8766) {
; CHECK-NEXT: movb %sil, %al
; CHECK-NEXT: movb %dil, %dl
; CHECK-NEXT: subb %al, %dl
-; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movl $0, %eax
; CHECK-NEXT: movl $1204476887, %ecx ## imm = 0x47CADBD7
; CHECK-NEXT: testb $1, %dl
; CHECK-NEXT: cmovnel %ecx, %eax
diff --git a/llvm/test/CodeGen/X86/fast-isel-x86-64.ll b/llvm/test/CodeGen/X86/fast-isel-x86-64.ll
index e2de3f334385..fd78fd48d325 100644
--- a/llvm/test/CodeGen/X86/fast-isel-x86-64.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-x86-64.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mattr=-avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort=1 | FileCheck %s
; RUN: llc < %s -mattr=-avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -pass-remarks-missed=isel 2>&1 >/dev/null | FileCheck %s --check-prefix=STDERR --allow-empty
; RUN: llc < %s -mattr=+avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort=1 | FileCheck %s --check-prefix=AVX
@@ -30,9 +31,6 @@ if.then: ; preds = %entry
if.end: ; preds = %if.then, %entry
ret void
-; CHECK-LABEL: test2:
-; CHECK: movq %rdi, -8(%rsp)
-; CHECK: cmpq $42, -8(%rsp)
}
@@ -42,9 +40,6 @@ if.end: ; preds = %if.then, %entry
define i64 @test3() nounwind {
%A = ptrtoint i32* @G to i64
ret i64 %A
-; CHECK-LABEL: test3:
-; CHECK: movq _G@GOTPCREL(%rip), %rax
-; CHECK-NEXT: ret
}
@@ -58,10 +53,6 @@ define i32 @test4(i64 %idxprom9) nounwind {
%conv = zext i8 %tmp11 to i32
ret i32 %conv
-; CHECK-LABEL: test4:
-; CHECK: movq _rtx_length@GOTPCREL(%rip), %rax
-; CHECK-NEXT: movzbl (%rax,%rdi), %eax
-; CHECK-NEXT: ret
}
@@ -71,10 +62,6 @@ define void @test5(i32 %x, i32* %p) nounwind {
store i32 %y, i32* %p
ret void
-; CHECK-LABEL: test5:
-; CHECK: movl $50000, %ecx
-; CHECK: sarl %cl, %edi
-; CHECK: ret
}
; rdar://9289501 - fast isel should fold trivial multiplies to shifts.
@@ -83,16 +70,12 @@ entry:
%mul = mul nsw i64 %x, 8
ret i64 %mul
-; CHECK-LABEL: test6:
-; CHECK: shlq $3, {{%r[a-z]+}}
}
define i32 @test7(i32 %x) nounwind ssp {
entry:
%mul = mul nsw i32 %x, 8
ret i32 %mul
-; CHECK-LABEL: test7:
-; CHECK: shll $3, {{%e[a-z]+}}
}
@@ -102,31 +85,23 @@ entry:
%add = add nsw i64 %x, 7
ret i64 %add
-; CHECK-LABEL: test8:
-; CHECK: addq $7, {{%r[a-z]+}}
}
define i64 @test9(i64 %x) nounwind ssp {
entry:
%add = mul nsw i64 %x, 7
ret i64 %add
-; CHECK-LABEL: test9:
-; CHECK: imulq $7, %rdi, %rax
}
; rdar://9297011 - Don't reject udiv by a power of 2.
define i32 @test10(i32 %X) nounwind {
%Y = udiv i32 %X, 8
ret i32 %Y
-; CHECK-LABEL: test10:
-; CHECK: shrl $3,
}
define i32 @test11(i32 %X) nounwind {
%Y = sdiv exact i32 %X, 8
ret i32 %Y
-; CHECK-LABEL: test11:
-; CHECK: sarl $3,
}
@@ -142,11 +117,6 @@ if.then: ; preds = %entry
if.end: ; preds = %if.then, %entry
ret void
-; CHECK-LABEL: test12:
-; CHECK: testb $1,
-; CHECK-NEXT: je L
-; CHECK-NEXT: xorl %edi, %edi
-; CHECK-NEXT: callq
}
declare void @test13f(i1 %X)
@@ -154,9 +124,6 @@ declare void @test13f(i1 %X)
define void @test13() nounwind {
call void @test13f(i1 0)
ret void
-; CHECK-LABEL: test13:
-; CHECK: xorl %edi, %edi
-; CHECK-NEXT: callq
}
@@ -167,9 +134,6 @@ entry:
%tobool = trunc i8 %tmp to i1
call void @test13f(i1 zeroext %tobool) noredzone
ret void
-; CHECK-LABEL: test14:
-; CHECK: andb $1,
-; CHECK: callq
}
declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i1)
@@ -178,30 +142,16 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i1)
define void @test15(i8* %a, i8* %b) nounwind {
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a, i8* align 4 %b, i64 4, i1 false)
ret void
-; CHECK-LABEL: test15:
-; CHECK-NEXT: movl (%rsi), %eax
-; CHECK-NEXT: movl %eax, (%rdi)
-; CHECK-NEXT: ret
}
; Handling for varargs calls
declare void @test16callee(...) nounwind
define void @test16() nounwind {
-; CHECK-LABEL: test16:
-; CHECK: movl $1, %edi
-; CHECK: movb $0, %al
-; CHECK: callq _test16callee
call void (...) @test16callee(i32 1)
br label %block2
block2:
-; CHECK: movsd LCP{{.*}}_{{.*}}(%rip), %xmm0
-; CHECK: movb $1, %al
-; CHECK: callq _test16callee
-; AVX: vmovsd LCP{{.*}}_{{.*}}(%rip), %xmm0
-; AVX: movb $1, %al
-; AVX: callq _test16callee
call void (...) @test16callee(double 1.000000e+00)
ret void
}
@@ -223,27 +173,18 @@ if.then: ; preds = %entry
if.else: ; preds = %entry
ret i32 2
-; CHECK-LABEL: test17:
-; CHECK: movl (%rdi), %eax
-; CHECK: callq _foo
-; CHECK: cmpl $5, %eax
-; CHECK-NEXT: je
}
; Check that 0.0 is materialized using xorps
define void @test18(float* %p1) {
store float 0.0, float* %p1
ret void
-; CHECK-LABEL: test18:
-; CHECK: xorps
}
; Without any type hints, doubles use the smaller xorps instead of xorpd.
define void @test19(double* %p1) {
store double 0.0, double* %p1
ret void
-; CHECK-LABEL: test19:
-; CHECK: xorps
}
; Check that we fast-isel sret
@@ -253,9 +194,6 @@ entry:
%tmp = alloca %struct.a, align 8
call void @test20sret(%struct.a* sret(%struct.a) %tmp)
ret void
-; CHECK-LABEL: test20:
-; CHECK: movq %rsp, %rdi
-; CHECK: callq _test20sret
}
declare void @test20sret(%struct.a* sret(%struct.a))
@@ -263,9 +201,6 @@ declare void @test20sret(%struct.a* sret(%struct.a))
define void @test21(double* %p1) {
store double -0.0, double* %p1
ret void
-; CHECK-LABEL: test21:
-; CHECK-NOT: xor
-; CHECK: movsd LCPI
}
; Check that immediate arguments to a function
@@ -278,15 +213,6 @@ entry:
call void @foo22(i32 2)
call void @foo22(i32 3)
ret void
-; CHECK-LABEL: test22:
-; CHECK: xorl %edi, %edi
-; CHECK: callq _foo22
-; CHECK: movl $1, %edi
-; CHECK: callq _foo22
-; CHECK: movl $2, %edi
-; CHECK: callq _foo22
-; CHECK: movl $3, %edi
-; CHECK: callq _foo22
}
declare void @foo22(i32)
@@ -296,12 +222,6 @@ define void @test23(i8* noalias sret(i8) %result) {
%a = alloca i8
%b = call i8* @foo23()
ret void
-; CHECK-LABEL: test23:
-; CHECK: movq %rdi, [[STACK:[0-9]+\(%rsp\)]]
-; CHECK: call
-; CHECK-NEXT: movq [[STACK]], %rax
-; CHECK-NEXT: addq $24, %rsp
-; CHECK: ret
}
declare i8* @foo23()
@@ -311,7 +231,6 @@ declare void @takesi32ptr(i32* %arg)
; CHECK-LABEL: allocamaterialize
define void @allocamaterialize() {
%a = alloca i32
-; CHECK: leaq {{.*}}, %rdi
call void @takesi32ptr(i32* %a)
ret void
}
@@ -319,6 +238,5 @@ define void @allocamaterialize() {
; STDERR-NOT: FastISel missed terminator: ret void
; CHECK-LABEL: win64ccfun
define win64cc void @win64ccfun(i32 %i) {
-; CHECK: ret
ret void
}
diff --git a/llvm/test/CodeGen/X86/indirect-branch-tracking-r2.ll b/llvm/test/CodeGen/X86/indirect-branch-tracking-r2.ll
index 7c6417902c12..84d60228d48b 100644
--- a/llvm/test/CodeGen/X86/indirect-branch-tracking-r2.ll
+++ b/llvm/test/CodeGen/X86/indirect-branch-tracking-r2.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefix=X64
; RUN: llc -mtriple=i386-unknown-unknown < %s | FileCheck %s --check-prefix=X86
@@ -9,34 +10,72 @@
;; setzx is not return twice function, should not followed by endbr.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; X64: callq setjmp
-; X64-NEXT: endbr64
-; X64: callq setzx
-; X64-NEXT: xorl
-; X64: callq sigsetjmp
-; X64-NEXT: endbr64
-; X64: callq savectx
-; X64-NEXT: endbr64
-; X64: callq vfork
-; X64-NEXT: endbr64
-; X64: callq getcontext
-; X64-NEXT: endbr64
-
-; X86: calll setjmp
-; X86-NEXT: endbr32
-; X86: calll setzx
-; X86-NEXT: xorl
-; X86: calll sigsetjmp
-; X86-NEXT: endbr32
-; X86: calll savectx
-; X86-NEXT: endbr32
-; X86: calll vfork
-; X86-NEXT: endbr32
-; X86: calll getcontext
-; X86-NEXT: endbr32
-
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @foo() #0 {
+; X64-LABEL: foo:
+; X64: # %bb.0: # %entry
+; X64-NEXT: endbr64
+; X64-NEXT: pushq %rax
+; X64-NEXT: .cfi_def_cfa_offset 16
+; X64-NEXT: movl $0, %edi
+; X64-NEXT: movb $0, %al
+; X64-NEXT: callq setjmp
+; X64-NEXT: endbr64
+; X64-NEXT: movl $0, %edi
+; X64-NEXT: movb $0, %al
+; X64-NEXT: callq setzx
+; X64-NEXT: movl $0, %edi
+; X64-NEXT: movb $0, %al
+; X64-NEXT: callq sigsetjmp
+; X64-NEXT: endbr64
+; X64-NEXT: movl $0, %edi
+; X64-NEXT: movb $0, %al
+; X64-NEXT: callq setzx
+; X64-NEXT: movl $0, %edi
+; X64-NEXT: movb $0, %al
+; X64-NEXT: callq savectx
+; X64-NEXT: endbr64
+; X64-NEXT: callq vfork
+; X64-NEXT: endbr64
+; X64-NEXT: movl $0, %edi
+; X64-NEXT: movb $0, %al
+; X64-NEXT: callq setzx
+; X64-NEXT: movl $0, %edi
+; X64-NEXT: movb $0, %al
+; X64-NEXT: callq getcontext
+; X64-NEXT: endbr64
+; X64-NEXT: popq %rax
+; X64-NEXT: .cfi_def_cfa_offset 8
+; X64-NEXT: retq
+;
+; X86-LABEL: foo:
+; X86: # %bb.0: # %entry
+; X86-NEXT: endbr32
+; X86-NEXT: pushl %eax
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: movl $0, (%esp)
+; X86-NEXT: calll setjmp
+; X86-NEXT: endbr32
+; X86-NEXT: movl $0, (%esp)
+; X86-NEXT: calll setzx
+; X86-NEXT: movl $0, (%esp)
+; X86-NEXT: calll sigsetjmp
+; X86-NEXT: endbr32
+; X86-NEXT: movl $0, (%esp)
+; X86-NEXT: calll setzx
+; X86-NEXT: movl $0, (%esp)
+; X86-NEXT: calll savectx
+; X86-NEXT: endbr32
+; X86-NEXT: calll vfork
+; X86-NEXT: endbr32
+; X86-NEXT: movl $0, (%esp)
+; X86-NEXT: calll setzx
+; X86-NEXT: movl $0, (%esp)
+; X86-NEXT: calll getcontext
+; X86-NEXT: endbr32
+; X86-NEXT: popl %eax
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl
entry:
%call = call i32 (i32, ...) bitcast (i32 (...)* @setjmp to i32 (i32, ...)*)(i32 0) #1
%call1 = call i32 (i32, ...) bitcast (i32 (...)* @setzx to i32 (i32, ...)*)(i32 0)
diff --git a/llvm/test/CodeGen/X86/membarrier.ll b/llvm/test/CodeGen/X86/membarrier.ll
index b70a0a03d609..c2434360bc68 100644
--- a/llvm/test/CodeGen/X86/membarrier.ll
+++ b/llvm/test/CodeGen/X86/membarrier.ll
@@ -9,7 +9,7 @@ define i32 @t() {
; CHECK-NEXT: mfence
; CHECK-NEXT: lock decl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: mfence
-; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movl $0, %eax
; CHECK-NEXT: retq
%i = alloca i32, align 4
store i32 1, i32* %i, align 4
diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
index 76f775b834e0..5492b930bcdc 100644
--- a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
@@ -125,17 +125,29 @@ entry:
; Test that null can be passed as a 32-bit pointer.
define dso_local void @test_null_arg(%struct.Foo* %f) {
-; ALL-LABEL: test_null_arg:
-; ALL: # %bb.0: # %entry
-; ALL-NEXT: subq $40, %rsp
-; ALL-NEXT: .seh_stackalloc 40
-; ALL-NEXT: .seh_endprologue
-; ALL-NEXT: xorl %edx, %edx
-; ALL-NEXT: callq test_noop1
-; ALL-NEXT: nop
-; ALL-NEXT: addq $40, %rsp
-; ALL-NEXT: retq
-; ALL-NEXT: .seh_endproc
+; CHECK-LABEL: test_null_arg:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subq $40, %rsp
+; CHECK-NEXT: .seh_stackalloc 40
+; CHECK-NEXT: .seh_endprologue
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: callq test_noop1
+; CHECK-NEXT: nop
+; CHECK-NEXT: addq $40, %rsp
+; CHECK-NEXT: retq
+; CHECK-NEXT: .seh_endproc
+;
+; CHECK-O0-LABEL: test_null_arg:
+; CHECK-O0: # %bb.0: # %entry
+; CHECK-O0-NEXT: subq $40, %rsp
+; CHECK-O0-NEXT: .seh_stackalloc 40
+; CHECK-O0-NEXT: .seh_endprologue
+; CHECK-O0-NEXT: movl $0, %edx
+; CHECK-O0-NEXT: callq test_noop1
+; CHECK-O0-NEXT: nop
+; CHECK-O0-NEXT: addq $40, %rsp
+; CHECK-O0-NEXT: retq
+; CHECK-O0-NEXT: .seh_endproc
entry:
call void @test_noop1(%struct.Foo* %f, i32 addrspace(270)* null)
ret void
diff --git a/llvm/test/CodeGen/X86/patchpoint.ll b/llvm/test/CodeGen/X86/patchpoint.ll
index abdf37549fd3..d10cda57131c 100644
--- a/llvm/test/CodeGen/X86/patchpoint.ll
+++ b/llvm/test/CodeGen/X86/patchpoint.ll
@@ -1,19 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
; Trivial patchpoint codegen
;
define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
-entry:
; CHECK-LABEL: trivial_patchpoint_codegen:
-; CHECK: movabsq $-559038736, %r11
-; CHECK-NEXT: callq *%r11
-; CHECK-NEXT: xchgw %ax, %ax
-; CHECK: movq %rax, %[[REG:r.+]]
-; CHECK: callq *%r11
-; CHECK-NEXT: xchgw %ax, %ax
-; CHECK: movq %[[REG]], %rax
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq %rsp, %rbp
+; CHECK-NEXT: .cfi_def_cfa_register %rbp
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: .cfi_offset %rbx, -32
+; CHECK-NEXT: .cfi_offset %r14, -24
+; CHECK-NEXT: movq %rdi, %r14
+; CHECK-NEXT: Ltmp0:
+; CHECK-NEXT: movabsq $-559038736, %r11 ## imm = 0xDEADBEF0
+; CHECK-NEXT: callq *%r11
+; CHECK-NEXT: xchgw %ax, %ax
+; CHECK-NEXT: movq %rax, %rbx
+; CHECK-NEXT: movq %r14, %rdi
+; CHECK-NEXT: movq %rax, %rsi
+; CHECK-NEXT: Ltmp1:
+; CHECK-NEXT: movabsq $-559038737, %r11 ## imm = 0xDEADBEEF
+; CHECK-NEXT: callq *%r11
+; CHECK-NEXT: xchgw %ax, %ax
+; CHECK-NEXT: movq %rbx, %rax
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+entry:
%resolveCall2 = inttoptr i64 -559038736 to i8*
%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
%resolveCall3 = inttoptr i64 -559038737 to i8*
@@ -26,12 +46,20 @@ entry:
declare i64 @foo(i64 %p1, i64 %p2)
define i64 @trivial_symbolic_patchpoint_codegen(i64 %p1, i64 %p2) {
-entry:
; CHECK-LABEL: trivial_symbolic_patchpoint_codegen:
-; CHECK: movabsq $_foo, %r11
-; CHECK-NEXT: callq *%r11
-; CHECK-NEXT: xchgw %ax, %ax
-; CHECK: retq
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq %rsp, %rbp
+; CHECK-NEXT: .cfi_def_cfa_register %rbp
+; CHECK-NEXT: Ltmp2:
+; CHECK-NEXT: movabsq $_foo, %r11
+; CHECK-NEXT: callq *%r11
+; CHECK-NEXT: xchgw %ax, %ax
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+entry:
%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 9, i32 15, i8* bitcast (i64 (i64, i64)* @foo to i8*), i32 2, i64 %p1, i64 %p2)
ret i64 %result
}
@@ -60,6 +88,47 @@ entry:
; There is no way to verify this, since it depends on memory allocation.
; But I think it's useful to include as a working example.
define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64 %tmp79) {
+; CHECK-LABEL: testLowerConstant:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq %rsp, %rbp
+; CHECK-NEXT: .cfi_def_cfa_register %rbp
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: .cfi_offset %rbx, -40
+; CHECK-NEXT: .cfi_offset %r14, -32
+; CHECK-NEXT: .cfi_offset %r15, -24
+; CHECK-NEXT: movq %rcx, %r14
+; CHECK-NEXT: movq %rdx, %r15
+; CHECK-NEXT: movq %rdi, %rbx
+; CHECK-NEXT: movq -16(%r8), %rdx
+; CHECK-NEXT: Ltmp4:
+; CHECK-NEXT: movq %r15, %rsi
+; CHECK-NEXT: xchgw %ax, %ax
+; CHECK-NEXT: Ltmp5:
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)
+; CHECK-NEXT: movq (%r14), %rax
+; CHECK-NEXT: movq -24(%rax), %rdx
+; CHECK-NEXT: Ltmp6:
+; CHECK-NEXT: movq %rbx, %rdi
+; CHECK-NEXT: movq %r15, %rsi
+; CHECK-NEXT: Ltmp7:
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)
+; CHECK-NEXT: nopw %cs:512(%rax,%rax)
+; CHECK-NEXT: movl $10, %eax
+; CHECK-NEXT: addq $8, %rsp
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
entry:
%tmp80 = add i64 %tmp79, -16
%tmp81 = inttoptr i64 %tmp80 to i64*
@@ -77,22 +146,38 @@ entry:
; Test small patchpoints that don't emit calls.
define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
-entry:
; CHECK-LABEL: small_patchpoint_codegen:
-; CHECK: Ltmp
-; CHECK: nopl 8(%rax,%rax)
-; CHECK-NEXT: popq
-; CHECK-NEXT: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq %rsp, %rbp
+; CHECK-NEXT: .cfi_def_cfa_register %rbp
+; CHECK-NEXT: Ltmp8:
+; CHECK-NEXT: nopl 8(%rax,%rax)
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+entry:
%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)
ret void
}
; Test large target address.
define i64 @large_target_address_patchpoint_codegen() {
-entry:
; CHECK-LABEL: large_target_address_patchpoint_codegen:
-; CHECK: movabsq $6153737369414576827, %r11
-; CHECK-NEXT: callq *%r11
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq %rsp, %rbp
+; CHECK-NEXT: .cfi_def_cfa_register %rbp
+; CHECK-NEXT: Ltmp9:
+; CHECK-NEXT: movabsq $6153737369414576827, %r11 ## imm = 0x556677889900AABB
+; CHECK-NEXT: callq *%r11
+; CHECK-NEXT: xchgw %ax, %ax
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+entry:
%resolveCall2 = inttoptr i64 6153737369414576827 to i8*
%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 0)
ret i64 %result
@@ -101,14 +186,6 @@ entry:
declare i64 @consume_attributes(i64, i8* nest, i64)
define i64 @test_patchpoint_with_attributes() {
entry:
-; CHECK-LABEL: test_patchpoint_with_attributes:
-; CHECK: movl $42, %edi
-; CHECK: movl $17, %esi
-; CHECK: xorl %r10d, %r10d
-; CHECK: movabsq $_consume_attributes, %r11
-; CHECK-NEXT: callq *%r11
-; CHECK-NEXT: xchgw %ax, %ax
-; CHECK: retq
%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 21, i32 15, i8* bitcast (i64 (i64, i8*, i64)* @consume_attributes to i8*), i32 3, i64 42, i8* nest null, i64 17)
ret i64 %result
}
diff --git a/llvm/test/CodeGen/X86/pr32241.ll b/llvm/test/CodeGen/X86/pr32241.ll
index 3664455d7299..4777aa20b3a0 100644
--- a/llvm/test/CodeGen/X86/pr32241.ll
+++ b/llvm/test/CodeGen/X86/pr32241.ll
@@ -16,8 +16,7 @@ define i32 @_Z3foov() {
; CHECK-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1: # %lor.rhs
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: movb $0, %al
; CHECK-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .LBB0_2: # %lor.end
@@ -35,8 +34,7 @@ define i32 @_Z3foov() {
; CHECK-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
; CHECK-NEXT: jne .LBB0_4
; CHECK-NEXT: # %bb.3: # %lor.rhs4
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: movb $0, %al
; CHECK-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
; CHECK-NEXT: jmp .LBB0_4
; CHECK-NEXT: .LBB0_4: # %lor.end5
diff --git a/llvm/test/CodeGen/X86/pr32256.ll b/llvm/test/CodeGen/X86/pr32256.ll
index ab51eedff32b..26cd31b3b1a2 100644
--- a/llvm/test/CodeGen/X86/pr32256.ll
+++ b/llvm/test/CodeGen/X86/pr32256.ll
@@ -11,15 +11,13 @@ define void @_Z1av() {
; CHECK-NEXT: .cfi_def_cfa_offset 6
; CHECK-NEXT: movb c, %cl
; CHECK-NEXT: xorb $-1, %cl
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: movb $0, %al
; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: movb %al, (%esp) # 1-byte Spill
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .LBB0_1: # %land.rhs
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: movb $0, %al
; CHECK-NEXT: movb %al, (%esp) # 1-byte Spill
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .LBB0_2: # %land.end
diff --git a/llvm/test/CodeGen/X86/pr32284.ll b/llvm/test/CodeGen/X86/pr32284.ll
index a4417a517421..178378ede7ed 100644
--- a/llvm/test/CodeGen/X86/pr32284.ll
+++ b/llvm/test/CodeGen/X86/pr32284.ll
@@ -10,11 +10,10 @@ define void @foo() {
; X86-O0-LABEL: foo:
; X86-O0: # %bb.0: # %entry
; X86-O0-NEXT: movzbl c, %ecx
-; X86-O0-NEXT: xorl %eax, %eax
+; X86-O0-NEXT: movl $0, %eax
; X86-O0-NEXT: subl %ecx, %eax
; X86-O0-NEXT: movslq %eax, %rcx
-; X86-O0-NEXT: xorl %eax, %eax
-; X86-O0-NEXT: # kill: def $rax killed $eax
+; X86-O0-NEXT: movl $0, %eax
; X86-O0-NEXT: subq %rcx, %rax
; X86-O0-NEXT: # kill: def $al killed $al killed $rax
; X86-O0-NEXT: cmpb $0, %al
diff --git a/llvm/test/CodeGen/X86/pr32340.ll b/llvm/test/CodeGen/X86/pr32340.ll
index 668af706524f..b7c230fb7658 100644
--- a/llvm/test/CodeGen/X86/pr32340.ll
+++ b/llvm/test/CodeGen/X86/pr32340.ll
@@ -39,8 +39,7 @@ define void @foo() {
; X64-NEXT: orq %rcx, %rax
; X64-NEXT: # kill: def $ax killed $ax killed $rax
; X64-NEXT: movw %ax, var_900
-; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: # kill: def $rax killed $eax
+; X64-NEXT: movl $0, %eax
; X64-NEXT: cmpq var_28, %rax
; X64-NEXT: setne %al
; X64-NEXT: andb $1, %al
diff --git a/llvm/test/CodeGen/X86/pr49587.ll b/llvm/test/CodeGen/X86/pr49587.ll
index 343f1a0149c0..859d64347249 100644
--- a/llvm/test/CodeGen/X86/pr49587.ll
+++ b/llvm/test/CodeGen/X86/pr49587.ll
@@ -6,7 +6,7 @@ define i32 @test(i64 %arg) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $1, %rdi
; CHECK-NEXT: setb %al
-; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movl $0, %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; CHECK-NEXT: jb .LBB0_2
; CHECK-NEXT: # %bb.1: # %no_overflow
diff --git a/llvm/test/CodeGen/X86/x86-no_callee_saved_registers.ll b/llvm/test/CodeGen/X86/x86-no_callee_saved_registers.ll
index 620a7ce49614..e7bb9e666bd9 100644
--- a/llvm/test/CodeGen/X86/x86-no_callee_saved_registers.ll
+++ b/llvm/test/CodeGen/X86/x86-no_callee_saved_registers.ll
@@ -154,7 +154,7 @@ define i32 @test3() personality i8* undef {
; CHECK-O0-NEXT: .LBB3_2: # %lpad
; CHECK-O0-NEXT: .cfi_def_cfa_offset 64
; CHECK-O0-NEXT: .Ltmp2:
-; CHECK-O0-NEXT: xorl %eax, %eax
+; CHECK-O0-NEXT: movl $0, %eax
; CHECK-O0-NEXT: addq $8, %rsp
; CHECK-O0-NEXT: .cfi_def_cfa_offset 56
; CHECK-O0-NEXT: popq %rbx
diff --git a/llvm/test/CodeGen/X86/xaluo.ll b/llvm/test/CodeGen/X86/xaluo.ll
index 0de8bdeddd6f..8ff33e772419 100644
--- a/llvm/test/CodeGen/X86/xaluo.ll
+++ b/llvm/test/CodeGen/X86/xaluo.ll
@@ -736,16 +736,15 @@ define zeroext i1 @saddobri32(i32 %v1, i32 %v2) {
; FAST: ## %bb.0:
; FAST-NEXT: addl %esi, %edi
; FAST-NEXT: jo LBB31_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB31_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB31_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB31_2
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -774,16 +773,15 @@ define zeroext i1 @saddobri64(i64 %v1, i64 %v2) {
; FAST: ## %bb.0:
; FAST-NEXT: addq %rsi, %rdi
; FAST-NEXT: jo LBB32_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB32_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB32_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB32_2
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -812,16 +810,15 @@ define zeroext i1 @uaddobri32(i32 %v1, i32 %v2) {
; FAST: ## %bb.0:
; FAST-NEXT: addl %esi, %edi
; FAST-NEXT: jb LBB33_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB33_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB33_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB33_2
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -850,16 +847,15 @@ define zeroext i1 @uaddobri64(i64 %v1, i64 %v2) {
; FAST: ## %bb.0:
; FAST-NEXT: addq %rsi, %rdi
; FAST-NEXT: jb LBB34_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB34_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB34_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB34_2
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -888,16 +884,15 @@ define zeroext i1 @ssubobri32(i32 %v1, i32 %v2) {
; FAST: ## %bb.0:
; FAST-NEXT: cmpl %esi, %edi
; FAST-NEXT: jo LBB35_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB35_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB35_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB35_2
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -926,16 +921,15 @@ define zeroext i1 @ssubobri64(i64 %v1, i64 %v2) {
; FAST: ## %bb.0:
; FAST-NEXT: cmpq %rsi, %rdi
; FAST-NEXT: jo LBB36_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB36_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB36_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB36_2
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -964,16 +958,15 @@ define zeroext i1 @usubobri32(i32 %v1, i32 %v2) {
; FAST: ## %bb.0:
; FAST-NEXT: cmpl %esi, %edi
; FAST-NEXT: jb LBB37_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB37_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB37_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB37_2
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -1002,16 +995,15 @@ define zeroext i1 @usubobri64(i64 %v1, i64 %v2) {
; FAST: ## %bb.0:
; FAST-NEXT: cmpq %rsi, %rdi
; FAST-NEXT: jb LBB38_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB38_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB38_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB38_2
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
diff --git a/llvm/test/CodeGen/X86/xmulo.ll b/llvm/test/CodeGen/X86/xmulo.ll
index f6c36f5afd99..7e25ff51aba2 100644
--- a/llvm/test/CodeGen/X86/xmulo.ll
+++ b/llvm/test/CodeGen/X86/xmulo.ll
@@ -330,16 +330,15 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) {
; FAST-NEXT: seto %al
; FAST-NEXT: testb $1, %al
; FAST-NEXT: jne LBB15_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB15_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB15_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB15_2
%t = call {i8, i1} @llvm.smul.with.overflow.i8(i8 %v1, i8 %v2)
%val = extractvalue {i8, i1} %t, 0
%obit = extractvalue {i8, i1} %t, 1
@@ -370,16 +369,15 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) {
; FAST-NEXT: seto %al
; FAST-NEXT: testb $1, %al
; FAST-NEXT: jne LBB16_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB16_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB16_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB16_2
%t = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %v1, i16 %v2)
%val = extractvalue {i16, i1} %t, 0
%obit = extractvalue {i16, i1} %t, 1
@@ -408,16 +406,15 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) {
; FAST: ## %bb.0:
; FAST-NEXT: imull %esi, %edi
; FAST-NEXT: jo LBB17_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB17_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB17_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB17_2
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -446,16 +443,15 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) {
; FAST: ## %bb.0:
; FAST-NEXT: imulq %rsi, %rdi
; FAST-NEXT: jo LBB18_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB18_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB18_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB18_2
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -490,16 +486,15 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) {
; FAST-NEXT: seto %al
; FAST-NEXT: testb $1, %al
; FAST-NEXT: jne LBB19_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB19_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB19_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB19_2
%t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 %v1, i8 %v2)
%val = extractvalue {i8, i1} %t, 0
%obit = extractvalue {i8, i1} %t, 1
@@ -534,16 +529,15 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) {
; FAST-NEXT: seto %al
; FAST-NEXT: testb $1, %al
; FAST-NEXT: jne LBB20_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB20_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB20_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB20_2
%t = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %v1, i16 %v2)
%val = extractvalue {i16, i1} %t, 0
%obit = extractvalue {i16, i1} %t, 1
@@ -574,16 +568,15 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) {
; FAST-NEXT: movl %edi, %eax
; FAST-NEXT: mull %esi
; FAST-NEXT: jo LBB21_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB21_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB21_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB21_2
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -614,16 +607,15 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) {
; FAST-NEXT: movq %rdi, %rax
; FAST-NEXT: mulq %rsi
; FAST-NEXT: jo LBB22_1
-; FAST-NEXT: ## %bb.2: ## %continue
+; FAST-NEXT: ## %bb.3: ## %continue
; FAST-NEXT: movb $1, %al
+; FAST-NEXT: LBB22_2: ## %overflow
; FAST-NEXT: andb $1, %al
; FAST-NEXT: movzbl %al, %eax
; FAST-NEXT: retq
; FAST-NEXT: LBB22_1: ## %overflow
-; FAST-NEXT: xorl %eax, %eax
-; FAST-NEXT: andb $1, %al
-; FAST-NEXT: movzbl %al, %eax
-; FAST-NEXT: retq
+; FAST-NEXT: movb $0, %al
+; FAST-NEXT: jmp LBB22_2
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment