openedev

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 1b4192ed6ab5..b3e794a4aadf 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -167,7 +167,7 @@ static struct ccu_nkm pll_mipi_clk = {
        .n              = _SUNXI_CCU_MULT(8, 4),
        .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
        .m              = _SUNXI_CCU_DIV(0, 4),
-       .min_rate       = 500000000,
+       .min_rate       = 300000000,

openedev

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
index e4d19431fa0e..31f74477b5f6 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
@@ -86,6 +86,9 @@ int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes)
 	reset_control_deassert(dphy->reset);
 	clk_prepare_enable(dphy->mod_clk);
 	clk_set_rate_exclusive(dphy->mod_clk, 150000000);
+	clk_prepare_enable(dphy->pll_mipi_clk);
+	clk_set_rate_exclusive(dphy->pll_mipi_clk, 180000000);

openedev

	diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
	index 9bf040cb40..490a27b038 100644
	--- a/drivers/mmc/sunxi_mmc.c
	+++ b/drivers/mmc/sunxi_mmc.c
	@@ -19,6 +19,13 @@
	 #include <asm/arch/mmc.h>
	 #include <asm-generic/gpio.h>
	 
	+#ifdef CONFIG_DM_MMC
	+struct sunxi_mmc_variant {

openedev

	diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
	index 9bf040cb40..490a27b038 100644
	--- a/drivers/mmc/sunxi_mmc.c
	+++ b/drivers/mmc/sunxi_mmc.c
	@@ -19,6 +19,13 @@
	 #include <asm/arch/mmc.h>
	 #include <asm-generic/gpio.h>
	 
	+#ifdef CONFIG_DM_MMC
	+struct sunxi_mmc_variant {

openedev

unsigned int *p = 0x1c20000;
        unsigned int *q;
        unsigned char ch = 0x60;

        q = p + ch;
//      q = (void *)p + ch;

        printf("%p\n", q);

openedev

commit 8427f6b2b471ed7a05d922b17f96bf5510a7add2
Author: Jagan Teki <jagan@amarulasolutions.com>
Date:   Fri Jan 11 18:00:56 2019 +0530

    media: sun6i: Add mod_rate quirk
    
    Unfortunately default CSI_SCLK rate cannot work properly to
    drive the connected sensor interface, particularly on few
    Allwinner SoC's like A64.
    

openedev

+       printf("MMC%d: %p = 0x%x, %p = 0x%x, %p = 0x%x\n", priv->mmc_no, gate_reg,
+               readl(gate_reg), priv->mclkreg, readl(priv->mclkreg),
+               reset_reg, readl(reset_reg));
+
        ret = mmc_set_mod_clk(priv, 24000000);

openedev

diff --git a/drivers/video/sunxi/disp2/disp/de/disp_lcd.c b/drivers/video/sunxi/disp2/disp/de/disp_lcd.c
index e8b651e1571..d6a76e51283 100755
--- a/drivers/video/sunxi/disp2/disp/de/disp_lcd.c
+++ b/drivers/video/sunxi/disp2/disp/de/disp_lcd.c
@@ -790,18 +790,29 @@ static s32 lcd_clk_config(struct disp_device* lcd)
 	}
 	dsi_rate = pll_rate / clk_info.dsi_div;
 
+	printk("lcd_clk_config: dsi_div = %d, tcon_div = %d, lcd_div = %d\n",
+		clk_info.dsi_div, clk_info.tcon_div, clk_info.lcd_div);

openedev

[   10.364112] lcd_clk_config: dsi_div = 6, tcon_div = 4, lcd_div = 1
[   10.364119] lcd_clk_config: lcd_dclk_freq = 148, dclk_rate = 148000000
[   10.364125] lcd_clk_config: lcd_rate = 888000000, pll_rate = 888000000, dsi_rate = 148000000
[   10.364134] get_factors_pll_mipi: rate = 888000000, parent = 297000000
[   10.364139] get_factors_pll_mipi: tmp_rate = 888000000
[   10.364143] get_factors_pll_mipi: want_rate = 888
[   10.364158] n=0, k=2, m=0
[   10.364167] get_factors_pll_mipi: rate = 891000000, parent = 297000000
[   10.364172] get_factors_pll_mipi: tmp_rate = 891000000
[   10.364176] get_factors_pll_mipi: want_rate = 891

openedev

diff --git a/Makefile b/Makefile
index 92e04dd689..e7f68d63c7 100644
--- a/Makefile
+++ b/Makefile
@@ -851,6 +851,11 @@ ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy)
 ALL-y += u-boot-sunxi-with-spl.bin
 endif
 
+# Build a combined spl + u-boot image for rockchip
+ifdef CONFIG_ROCKCHIP_RK3399