transmitter.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity uArtTx is 
generic(
    constant waiting : std_logic_vector (1 downto 0) := "00";
    constant startBit : std_logic_vector (1 downto 0) := "01";
    constant transmission : std_logic_vector (1 downto 0) := "10";
    constant stopBit : std_logic_vector (1 downto 0) := "11"
);
port(
    data : in std_logic_vector(6 downto 0) := (others => '0');
    clk : in std_logic;
    startTransmit : in std_logic := '0';
    serial : out std_logic := '0'
);

end uArtTx;

architecture send of uArtTx is

    signal stateMachine : std_logic_vector(1 downto 0) := (others => '0');
    signal dataReg : std_logic_vector(7 downto 0) := (others => '0');
    signal clkCount : integer := 0;
    signal bitIndex : integer := 0;

begin
    process(clk)  
    begin  
        if(clk'event and clk = '1') then
            case stateMachine is
                when waiting => --waiting
                    serial <= '0';
                    if(startTransmit = '1') then
                        dataReg <= "0" & data; --load input data into data register
                        stateMachine <= startBit; --advance to the next state
                    else
                        stateMachine <= waiting; --stay at current state
                    end if;
                when startBit => --startBit
                    dataReg(7) <= (data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6)); --odd parity
                    serial <= '1'; --start bit
                    if(clkCount < 10) then --artificial delay
                        clkCount <= clkCount + 1;
                        stateMachine <= startBit; --return to current state
                    else
                        clkCount <= 0;
                        stateMachine <= transmission; --advance to next state
                    end if;
                when transmission => --transmission
                    serial <= dataReg(bitIndex); --send the nth bit, LSB first
                    if(clkCount < 10) then
                        clkCount <= clkCount + 1;
                        stateMachine <= transmission;
                    else
                        clkCount <= 0;
                        --transmitting data bits 
                        if(bitIndex < 7) then
                            bitIndex <= bitIndex + 1;
                            stateMachine <= transmission;
                        else
                            bitIndex <= 0;
                            stateMachine <= stopBit;
                        end if;
                    end if;
                when stopBit => --stopBit
                    serial <= '1'; --stop bit
                    if(clkCount < 10) then
                        clkCount <= clkCount + 1;
                        stateMachine <= stopBit;
                    else
                        clkCount <= 0;
                        stateMachine <= waiting; --return to first state to await next batch of data
                    end if;
                    when others => stateMachine <= waiting;
            end case;            
        end if;
    end process;
end send;