Created
November 14, 2016 16:59
-
-
Save perillamint/b2c146e4b31cff3139e304c241fa4c0a to your computer and use it in GitHub Desktop.
WeVO W2914NS v2 bootlog
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| =================================================================== | |
| MT7621 stage1 code Mar 12 2015 14:43:30 (ASIC) | |
| CPU=500000000 HZ BUS=166666666 HZ | |
| ================================================================== | |
| Change MPLL source from XTAL to CR... | |
| do MEMPLL setting.. | |
| MEMPLL Config : 0x11100000 | |
| 3PLL mode + External loopback | |
| === XTAL-40Mhz === DDR-1200Mhz === | |
| PLL2 FB_DL: 0x11, 1/0 = 596/428 45000000 | |
| PLL4 FB_DL: 0x15, 1/0 = 616/408 55000000 | |
| PLL3 FB_DL: 0x16, 1/0 = 561/463 59000000 | |
| do DDR setting..[01F40000] | |
| Apply DDR3 Setting...(use customer AC) | |
| 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 | |
| -------------------------------------------------------------------------------- | |
| 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | |
| 000E:| 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 | |
| 000F:| 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 | |
| 0010:| 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 | |
| 0011:| 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
| DRAMC_DQSCTL1[0e0]=13000000 | |
| DRAMC_DQSGCTL[124]=80000033 | |
| rank 0 coarse = 15 | |
| rank 0 fine = 72 | |
| B:| 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 | |
| opt_dle value:8 | |
| DRAMC_DDR2CTL[07c]=C287220D | |
| DRAMC_PADCTL4[0e4]=000022B3 | |
| DRAMC_DQIDLY1[210]=0D0C0B0C | |
| DRAMC_DQIDLY2[214]=090B0A09 | |
| DRAMC_DQIDLY3[218]=09060505 | |
| DRAMC_DQIDLY4[21c]=07050807 | |
| DRAMC_R0DELDLY[018]=00001E20 | |
| ================================================================== | |
| RX DQS perbit delay software calibration | |
| ================================================================== | |
| 1.0-15 bit dq delay value | |
| ================================================================== | |
| bit| 0 1 2 3 4 5 6 7 8 9 | |
| -------------------------------------- | |
| 0 | 11 10 11 13 9 10 10 9 3 4 | |
| 10 | 5 7 6 7 5 6 | |
| -------------------------------------- | |
| ================================================================== | |
| 2.dqs window | |
| x=pass dqs delay value (min~max)center | |
| y=0-7bit DQ of every group | |
| input delay:DQS0 =32 DQS1 = 30 | |
| ================================================================== | |
| bit DQS0 bit DQS1 | |
| 0 (1~62)31 8 (1~55)28 | |
| 1 (1~62)31 9 (1~57)29 | |
| 2 (1~62)31 10 (1~58)29 | |
| 3 (1~63)32 11 (1~56)28 | |
| 4 (1~64)32 12 (1~58)29 | |
| 5 (1~63)32 13 (1~57)29 | |
| 6 (1~62)31 14 (1~60)30 | |
| 7 (1~64)32 15 (1~57)29 | |
| ================================================================== | |
| 3.dq delay value last | |
| ================================================================== | |
| bit| 0 1 2 3 4 5 6 7 8 9 | |
| -------------------------------------- | |
| 0 | 12 11 12 13 9 10 11 9 5 5 | |
| 10 | 6 9 7 8 5 7 | |
| ================================================================== | |
| ================================================================== | |
| TX perbyte calibration | |
| ================================================================== | |
| DQS loop = 15, cmp_err_1 = ffff0000 | |
| dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1 | |
| dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2 | |
| DQ loop=15, cmp_err_1 = ffff0002 | |
| dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=1 | |
| DQ loop=14, cmp_err_1 = ffff0000 | |
| dqs_perbyte_dly.last_dqdly_pass[0]=14, finish count=2 | |
| byte:0, (DQS,DQ)=(8,8) | |
| byte:1, (DQS,DQ)=(8,8) | |
| DRAMC_DQODLY1[200]=88888888 | |
| DRAMC_DQODLY2[204]=88888888 | |
| 20,data:88 | |
| [EMI] DRAMC calibration passed | |
| =================================================================== | |
| MT7621 stage1 code done | |
| CPU=500000000 HZ BUS=166666666 HZ | |
| =================================================================== | |
| U-Boot 1.1.3 (Jan 11 2016 - 17:02:37) | |
| Board: Ralink APSoC DRAM: 256 MB | |
| relocate_code Pointer at: 8ff64000 | |
| Config XHCI 40M PLL | |
| flash manufacture id: c2, device id 20 18 | |
| find flash: MX25L12805D | |
| *** Warning - bad CRC, using default environment | |
| ============================================ | |
| Ralink UBoot Version: 4.3.0.0 | |
| -------------------------------------------- | |
| ASIC MT7621A DualCore (MAC to MT7530 Mode) | |
| DRAM_CONF_FROM: Auto-Detection | |
| DRAM_TYPE: DDR3 | |
| DRAM bus: 16 bit | |
| Xtal Mode=3 OCP Ratio=1/3 | |
| Flash component: SPI Flash | |
| Date:Jan 11 2016 Time:17:02:37 | |
| ============================================ | |
| icache: sets:256, ways:4, linesz:32 ,total:32768 | |
| dcache: sets:256, ways:4, linesz:32 ,total:32768 | |
| ##### The CPU freq = 880 MHZ #### | |
| estimate memory size =256 Mbytes | |
| #Reset_MT7530 | |
| set LAN/WAN LLLLW | |
| Please choose the operation: | |
| 1: Load system code to SDRAM via TFTP. | |
| 2: Load system code then write to Flash via TFTP. | |
| 3: Boot system code via Flash (default). | |
| 4: Entr boot command line interface. | |
| 7: Load Boot Loader code then write to Flash via Serial. | |
| 9: Load Boot Loader code then write to Flash via TFTP. | |
| 0 | |
| 3: System Boot system code via Flash. | |
| ## Booting image at bc050000 ... | |
| Image Name: 11AC-NAS-Router(1.1.9) | |
| Image Type: MIPS Linux Kernel Image (lzma compressed) | |
| Data Size: 4523083 Bytes = 4.3 MB | |
| Load Address: 80001000 | |
| Entry Point: 8000f500 | |
| Verifying Checksum ... OK | |
| Uncompressing Kernel Image ... OK | |
| No initrd | |
| ## Transferring control to Linux (at address 8000f500) ... | |
| ## Giving linux memsize in MB, 256 | |
| Starting kernel ... | |
| LINUX started... | |
| THIS IS ASIC | |
| Linux version 2.6.36 (bestsi@bestsi-ubuntu) (gcc version 4.6.3 (Buildroot 2012.11.1) ) #148 SMP Thu Jul 7 15:43:34 KST 2016 | |
| The CPU feqenuce set to 880 MHz | |
| GCMP present | |
| CPU revision is: 0001992f (MIPS 1004Kc) | |
| Software DMA cache coherency | |
| Determined physical RAM map: | |
| memory: 10000000 @ 00000000 (usable) | |
| Initrd not found or empty - disabling initrd | |
| Zone PFN ranges: | |
| Normal 0x00000000 -> 0x00010000 | |
| Movable zone start PFN for each node | |
| early_node_map[1] active PFN ranges | |
| 0: 0x00000000 -> 0x00010000 | |
| Detected 3 available secondary CPU(s) | |
| PERCPU: Embedded 7 pages/cpu @81203000 s6848 r8192 d13632 u65536 | |
| pcpu-alloc: s6848 r8192 d13632 u65536 alloc=16*4096 | |
| pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 | |
| Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024 | |
| Kernel command line: console=ttyS1,57600n8 root=/dev/ram0 console=ttyS1,57600 root=/dev/ram0 rootfstype=squashfs,jffs2 | |
| PID hash table entries: 1024 (order: 0, 4096 bytes) | |
| Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) | |
| Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) | |
| Primary instruction cache 32kB, VIPT, , 4-waylinesize 32 bytes. | |
| Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | |
| MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | |
| Writing ErrCtl register=00002404 | |
| Readback ErrCtl register=00002404 | |
| Memory: 251844k/262144k available (3613k kernel code, 10300k reserved, 1023k data, 2988k init, 0k highmem) | |
| Hierarchical RCU implementation. | |
| Verbose stalled-CPUs detection is disabled. | |
| NR_IRQS:128 | |
| Trying to install interrupt handler for IRQ24 | |
| Trying to install interrupt handler for IRQ25 | |
| Trying to install interrupt handler for IRQ22 | |
| Trying to install interrupt handler for IRQ9 | |
| Trying to install interrupt handler for IRQ10 | |
| Trying to install interrupt handler for IRQ11 | |
| Trying to install interrupt handler for IRQ12 | |
| Trying to install interrupt handler for IRQ13 | |
| Trying to install interrupt handler for IRQ14 | |
| Trying to install interrupt handler for IRQ16 | |
| Trying to install interrupt handler for IRQ17 | |
| Trying to install interrupt handler for IRQ18 | |
| Trying to install interrupt handler for IRQ19 | |
| Trying to install interrupt handler for IRQ20 | |
| Trying to install interrupt handler for IRQ21 | |
| Trying to install interrupt handler for IRQ23 | |
| Trying to install interrupt handler for IRQ26 | |
| Trying to install interrupt handler for IRQ27 | |
| Trying to install interrupt handler for IRQ28 | |
| Trying to install interrupt handler for IRQ15 | |
| Trying to install interrupt handler for IRQ8 | |
| Trying to install interrupt handler for IRQ29 | |
| Trying to install interrupt handler for IRQ30 | |
| Trying to install interrupt handler for IRQ31 | |
| console [ttyS1] enabled | |
| Calibrating delay loop... 575.48 BogoMIPS (lpj=1150976) | |
| pid_max: default: 32768 minimum: 301 | |
| Mount-cache hash table entries: 512 | |
| launch: starting cpu1 | |
| launch: cpu1 gone! | |
| CPU revision is: 0001992f (MIPS 1004Kc) | |
| Primary instruction cache 32kB, VIPT, , 4-waylinesize 32 bytes. | |
| Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | |
| MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | |
| launch: starting cpu2 | |
| launch: cpu2 gone! | |
| CPU revision is: 0001992f (MIPS 1004Kc) | |
| Primary instruction cache 32kB, VIPT, , 4-waylinesize 32 bytes. | |
| Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | |
| MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | |
| launch: starting cpu3 | |
| launch: cpu3 gone! | |
| CPU revision is: 0001992f (MIPS 1004Kc) | |
| Primary instruction cache 32kB, VIPT, , 4-waylinesize 32 bytes. | |
| Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes | |
| MIPS secondary cache 256kB, 8-way, linesize 32 bytes. | |
| Brought up 4 CPUs | |
| Synchronize counters across 4 CPUs: done. | |
| NET: Registered protocol family 16 | |
| release PCIe RST: RALINK_RSTCTRL = 7000000 | |
| PCIE PHY initialize | |
| ***** Xtal 40MHz ***** | |
| start MT7621 PCIe register access | |
| RALINK_RSTCTRL = 7000000 | |
| RALINK_CLKCFG1 = 77ffeff8 | |
| *************** MT7621 PCIe RC mode ************* | |
| PCIE2 no card, disable it(RST&CLK) | |
| pcie_link status = 0x3 | |
| RALINK_RSTCTRL= 3000000 | |
| *** Configure Device number setting of Virtual PCI-PCI bridge *** | |
| RALINK_PCI_PCICFG_ADDR = 21007f2 -> 21007f2 | |
| PCIE0 enabled | |
| PCIE1 enabled | |
| interrupt enable status: 300000 | |
| Port 1 N_FTS = 1b105000 | |
| Port 0 N_FTS = 1b105000 | |
| config reg done | |
| init_rt2880pci done | |
| bio: create slab <bio-0> at 0 | |
| SCSI subsystem initialized | |
| usbcore: registered new interface driver usbfs | |
| usbcore: registered new interface driver hub | |
| usbcore: registered new device driver usb | |
| pci 0000:00:00.0: BAR 0: can't assign mem (size 0x80000000) | |
| pci 0000:00:01.0: BAR 0: can't assign mem (size 0x80000000) | |
| pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff] | |
| pci 0000:00:01.0: BAR 8: assigned [mem 0x60100000-0x601fffff] | |
| pci 0000:00:01.0: BAR 9: assigned [mem 0x60200000-0x602fffff pref] | |
| pci 0000:00:00.0: BAR 1: assigned [mem 0x60300000-0x6030ffff] | |
| pci 0000:00:00.0: BAR 1: set to [mem 0x60300000-0x6030ffff] (PCI address [0x60300000-0x6030ffff] | |
| pci 0000:00:01.0: BAR 1: assigned [mem 0x60310000-0x6031ffff] | |
| pci 0000:00:01.0: BAR 1: set to [mem 0x60310000-0x6031ffff] (PCI address [0x60310000-0x6031ffff] | |
| pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff] | |
| pci 0000:01:00.0: BAR 0: set to [mem 0x60000000-0x600fffff] (PCI address [0x60000000-0x600fffff] | |
| pci 0000:00:00.0: PCI bridge to [bus 01-01] | |
| pci 0000:00:00.0: bridge window [io disabled] | |
| pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff] | |
| pci 0000:00:00.0: bridge window [mem pref disabled] | |
| pci 0000:02:00.0: BAR 0: assigned [mem 0x60100000-0x601fffff 64bit] | |
| pci 0000:02:00.0: BAR 0: set to [mem 0x60100000-0x601fffff 64bit] (PCI address [0x60100000-0x601fffff] | |
| pci 0000:02:00.0: BAR 6: assigned [mem 0x60200000-0x6020ffff pref] | |
| pci 0000:00:01.0: PCI bridge to [bus 02-02] | |
| pci 0000:00:01.0: bridge window [io disabled] | |
| pci 0000:00:01.0: bridge window [mem 0x60100000-0x601fffff] | |
| pci 0000:00:01.0: bridge window [mem 0x60200000-0x602fffff pref] | |
| PCI: Enabling device 0000:00:00.0 (0004 -> 0006) | |
| PCI: Enabling device 0000:00:01.0 (0004 -> 0006) | |
| BAR0 at slot 0 = 0 | |
| bus=0x0, slot = 0x0 | |
| res[0]->start = 0 | |
| res[0]->end = 0 | |
| res[1]->start = 60300000 | |
| res[1]->end = 6030ffff | |
| res[2]->start = 0 | |
| res[2]->end = 0 | |
| res[3]->start = 0 | |
| res[3]->end = 0 | |
| res[4]->start = 0 | |
| res[4]->end = 0 | |
| res[5]->start = 0 | |
| res[5]->end = 0 | |
| BAR0 at slot 1 = 0 | |
| bus=0x0, slot = 0x1 | |
| res[0]->start = 0 | |
| res[0]->end = 0 | |
| res[1]->start = 60310000 | |
| res[1]->end = 6031ffff | |
| res[2]->start = 0 | |
| res[2]->end = 0 | |
| res[3]->start = 0 | |
| res[3]->end = 0 | |
| res[4]->start = 0 | |
| res[4]->end = 0 | |
| res[5]->start = 0 | |
| res[5]->end = 0 | |
| bus=0x1, slot = 0x0, irq=0x4 | |
| res[0]->start = 60000000 | |
| res[0]->end = 600fffff | |
| res[1]->start = 0 | |
| res[1]->end = 0 | |
| res[2]->start = 0 | |
| res[2]->end = 0 | |
| res[3]->start = 0 | |
| res[3]->end = 0 | |
| res[4]->start = 0 | |
| res[4]->end = 0 | |
| res[5]->start = 0 | |
| res[5]->end = 0 | |
| bus=0x2, slot = 0x1, irq=0x18 | |
| res[0]->start = 60100000 | |
| res[0]->end = 601fffff | |
| res[1]->start = 0 | |
| res[1]->end = 0 | |
| res[2]->start = 0 | |
| res[2]->end = 0 | |
| res[3]->start = 0 | |
| res[3]->end = 0 | |
| res[4]->start = 0 | |
| res[4]->end = 0 | |
| res[5]->start = 0 | |
| res[5]->end = 0 | |
| Switching to clocksource Ralink Systick timer | |
| NET: Registered protocol family 2 | |
| IP route cache hash table entries: 2048 (order: 1, 8192 bytes) | |
| TCP established hash table entries: 8192 (order: 4, 65536 bytes) | |
| TCP bind hash table entries: 8192 (order: 4, 65536 bytes) | |
| TCP: Hash tables configured (established 8192 bind 8192) | |
| TCP reno registered | |
| UDP hash table entries: 128 (order: 0, 4096 bytes) | |
| UDP-Lite hash table entries: 128 (order: 0, 4096 bytes) | |
| NET: Registered protocol family 1 | |
| 4 CPUs re-calibrate udelay(lpj = 1167360) | |
| Load Kernel WDG Timer Module | |
| Load Ralink Timer0 Module | |
| Load Ralink Timer2 Module | |
| squashfs: version 4.0 (2009/01/31) Phillip Lougher | |
| msgmni has been set to 491 | |
| io scheduler noop registered (default) | |
| Ralink gpio driver initialized | |
| Enable Ralink HS_DMA Controller Module | |
| reg_int_mask=0, INT_MASK= 10000 | |
| HSDMA_init function | |
| phy_tx_ring0 = 0x0fdd2000, tx_ring0 = 0xafdd2000 | |
| phy_rx_ring0 = 0x0fdd3000, rx_ring0 = 0xafdd3000 | |
| TX_CTX_IDX0 = 0 | |
| TX_DTX_IDX0 = 0 | |
| RX_CRX_IDX0 = ff | |
| RX_DRX_IDX0 = 0 | |
| HSDMA_GLO_CFG = 475 | |
| Enable Ralink GDMA Controller Module | |
| GDMA IP Version=3 | |
| Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled | |
| serial8250: ttyS0 at MMIO 0x1e000d00 (irq = 27) is a 16550A | |
| serial8250: ttyS1 at MMIO 0x1e000c00 (irq = 26) is a 16550A | |
| brd: module loaded | |
| flash manufacture id: c2, device id 20 18 | |
| MX25L12805D(c2 2018c220) (16384 Kbytes) | |
| mtd .name = raspi, .size = 0x01000000 (16M) .erasesize = 0x00010000 (64K) .numeraseregions = 0 | |
| Creating 9 MTD partitions on "raspi": | |
| 0x000000000000-0x000001000000 : "ALL" | |
| 0x000000000000-0x000000030000 : "Bootloader" | |
| 0x000000030000-0x000000040000 : "Config" | |
| 0x000000040000-0x000000050000 : "Factory" | |
| 0x000000050000-0x000000d60000 : "Kernel" | |
| 0x000000d60000-0x000000e60000 : "DLNA" | |
| 0x000000e60000-0x000000f60000 : "P2P" | |
| 0x000000f60000-0x000000f80000 : "PVS" | |
| 0x000000f80000-0x000001000000 : "UDAT" | |
| rdm_major = 253 | |
| GMAC1_MAC_ADRH -- : 0x000020c0 | |
| GMAC1_MAC_ADRL -- : 0x6d99ebe8 | |
| Ralink APSoC Ethernet Driver Initilization. v3.1 512 rx/tx descriptors allocated, mtu = 1500! | |
| GMAC1_MAC_ADRH -- : 0x000020c0 | |
| GMAC1_MAC_ADRL -- : 0x6d99ebe8 | |
| PROC INIT OK! | |
| PPP generic driver version 2.4.2 | |
| PPP MPPE Compression module registered | |
| NET: Registered protocol family 24 | |
| IMQ driver loaded successfully. | |
| Hooking IMQ after NAT on PREROUTING. | |
| Hooking IMQ before NAT on POSTROUTING. | |
| register mt_drv | |
| === pAd = c0282000, size = 1004888 === | |
| <-- RTMPAllocTxRxRingMemory, Status=0 | |
| <-- RTMPAllocAdapterBlock, Status=0 | |
| pAd->CSRBaseAddress =0xc0180000, csr_addr=0xc0180000! | |
| device_id =0x7603 | |
| RtmpChipOpsHook(502): Not support for HIF_MT yet! | |
| mt7603_init()--> | |
| mt_bcn_buf_init(224): Not support for HIF_MT yet! | |
| <--mt7603_init() | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| FM_OUT value: u4FmOut = 0(0x00000000) | |
| xhc_mtk xhc_mtk: xHCI Host Controller | |
| xhc_mtk xhc_mtk: new USB bus registered, assigned bus number 1 | |
| xhc_mtk xhc_mtk: irq 22, io mem 0x1e1c0000 | |
| hub 1-0:1.0: USB hub found | |
| hub 1-0:1.0: 2 ports detected | |
| xhc_mtk xhc_mtk: xHCI Host Controller | |
| xhc_mtk xhc_mtk: new USB bus registered, assigned bus number 2 | |
| hub 2-0:1.0: USB hub found | |
| hub 2-0:1.0: 1 port detected | |
| Initializing USB Mass Storage driver... | |
| usbcore: registered new interface driver usb-storage | |
| USB Mass Storage support registered. | |
| Netfilter messages via NETLINK v0.30. | |
| nf_conntrack version 0.5.0 (3935 buckets, 15740 max) | |
| nf_conntrack_rtsp v0.6.21 loading | |
| matchsize=264 | |
| xt_time: kernel timezone is -0000 | |
| GRE over IPv4 demultiplexor drivernf_nat_rtsp v0.6.21 loading | |
| ip_tables: (C) 2000-2006 Netfilter Core Team, Type=Linux | |
| arp_tables: (C) 2002 David S. Miller | |
| TCP cubic registered | |
| NET: Registered protocol family 17 | |
| L2TP core driver, V2.0 | |
| 802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> | |
| All bugs added by David S. Miller <davem@redhat.com> | |
| Warning: unable to open an initial console. | |
| Freeing unused kernel memory: 2988k freed | |
| Algorithmics/MIPS FPU Emulator v1.5 | |
| tntfs: module license 'Commercial. For support email ntfs-support@tuxera.com.' taints kernel. | |
| Disabling lock debugging due to kernel taint | |
| Tuxera NTFS driver 3015.1.29 [Flags: R/W MODULE]. | |
| register rt2860 | |
| === pAd = c0982000, size = 1660720 === | |
| <-- RTMPAllocTxRxRingMemory, Status=0 | |
| <-- RTMPAllocAdapterBlock, Status=0 | |
| pAd->CSRBaseAddress =0xc0880000, csr_addr=0xc0880000! | |
| device_id =0x7662 | |
| ==>rlt_wlan_chip_onoff(): OnOff:1, Reset= 1, pAd->WlanFunCtrl:0x0, Reg-WlanFunCtrl=0x20a | |
| RtmpChipOpsEepromHook::e2p_type=0, inf_Type=5 | |
| RtmpEepromGetDefault::e2p_dafault=2 | |
| NVM is FLASH mode | |
| build time = | |
| 20140408060640a | |
| rom patch for E3 IC | |
| platform = | |
| ALPS | |
| hw/sw version = | |
| patch version = | |
| FW Version:0.0.00 Build:1 | |
| Build Time:201406241830____ | |
| fw for E3 IC | |
| RX[0] DESC ae448000 size = 4096 | |
| RX[1] DESC ae449000 size = 4096 | |
| RTMP_TimerListAdd: add timer obj c0a8c004! | |
| RTMP_TimerListAdd: add timer obj c0a1a910! | |
| RTMP_TimerListAdd: add timer obj c0a1a8e4! | |
| RTMP_TimerListAdd: add timer obj c0a1a93c! | |
| RTMP_TimerListAdd: add timer obj c0a1a8b8! | |
| RTMP_TimerListAdd: add timer obj c09960c8! | |
| RTMP_TimerListAdd: add timer obj c0995cbc! | |
| RTMP_TimerListAdd: add timer obj c0996098! | |
| RTMP_TimerListAdd: add timer obj c0996444! | |
| RTMP_TimerListAdd: add timer obj c0996190! | |
| RTMP_TimerListAdd: add timer obj c09961c0! | |
| RTMP_TimerListAdd: add timer obj c0996380! | |
| RTMP_TimerListAdd: add timer obj c09963b0! | |
| RTMP_TimerListAdd: add timer obj c09993cc! | |
| RTMP_TimerListAdd: add timer obj c0998fc0! | |
| RTMP_TimerListAdd: add timer obj c099939c! | |
| RTMP_TimerListAdd: add timer obj c0999748! | |
| RTMP_TimerListAdd: add timer obj c0999494! | |
| RTMP_TimerListAdd: add timer obj c09994c4! | |
| RTMP_TimerListAdd: add timer obj c0999684! | |
| RTMP_TimerListAdd: add timer obj c09996b4! | |
| RTMP_TimerListAdd: add timer obj c099c6d0! | |
| RTMP_TimerListAdd: add timer obj c099c2c4! | |
| RTMP_TimerListAdd: add timer obj c099c6a0! | |
| RTMP_TimerListAdd: add timer obj c099ca4c! | |
| RTMP_TimerListAdd: add timer obj c099c798! | |
| RTMP_TimerListAdd: add timer obj c099c7c8! | |
| RTMP_TimerListAdd: add timer obj c099c988! | |
| RTMP_TimerListAdd: add timer obj c099c9b8! | |
| RTMP_TimerListAdd: add timer obj c099f9d4! | |
| RTMP_TimerListAdd: add timer obj c099f5c8! | |
| RTMP_TimerListAdd: add timer obj c099f9a4! | |
| RTMP_TimerListAdd: add timer obj c099fd50! | |
| RTMP_TimerListAdd: add timer obj c099fa9c! | |
| RTMP_TimerListAdd: add timer obj c099facc! | |
| RTMP_TimerListAdd: add timer obj c099fc8c! | |
| RTMP_TimerListAdd: add timer obj c099fcbc! | |
| RTMP_TimerListAdd: add timer obj c09a2cd8! | |
| RTMP_TimerListAdd: add timer obj c09a28cc! | |
| RTMP_TimerListAdd: add timer obj c09a2ca8! | |
| RTMP_TimerListAdd: add timer obj c09a3054! | |
| RTMP_TimerListAdd: add timer obj c09a2da0! | |
| RTMP_TimerListAdd: add timer obj c09a2dd0! | |
| RTMP_TimerListAdd: add timer obj c09a2f90! | |
| RTMP_TimerListAdd: add timer obj c09a2fc0! | |
| RTMP_TimerListAdd: add timer obj c09a5fdc! | |
| RTMP_TimerListAdd: add timer obj c09a5bd0! | |
| RTMP_TimerListAdd: add timer obj c09a5fac! | |
| RTMP_TimerListAdd: add timer obj c09a6358! | |
| RTMP_TimerListAdd: add timer obj c09a60a4! | |
| RTMP_TimerListAdd: add timer obj c09a60d4! | |
| RTMP_TimerListAdd: add timer obj c09a6294! | |
| RTMP_TimerListAdd: add timer obj c09a62c4! | |
| RTMP_TimerListAdd: add timer obj c09a92e0! | |
| RTMP_TimerListAdd: add timer obj c09a8ed4! | |
| RTMP_TimerListAdd: add timer obj c09a92b0! | |
| RTMP_TimerListAdd: add timer obj c09a965c! | |
| RTMP_TimerListAdd: add timer obj c09a93a8! | |
| RTMP_TimerListAdd: add timer obj c09a93d8! | |
| RTMP_TimerListAdd: add timer obj c09a9598! | |
| RTMP_TimerListAdd: add timer obj c09a95c8! | |
| RTMP_TimerListAdd: add timer obj c09ac5e4! | |
| RTMP_TimerListAdd: add timer obj c09ac1d8! | |
| RTMP_TimerListAdd: add timer obj c09ac5b4! | |
| RTMP_TimerListAdd: add timer obj c09ac960! | |
| RTMP_TimerListAdd: add timer obj c09ac6ac! | |
| RTMP_TimerListAdd: add timer obj c09ac6dc! | |
| RTMP_TimerListAdd: add timer obj c09ac89c! | |
| RTMP_TimerListAdd: add timer obj c09ac8cc! | |
| RTMP_TimerListAdd: add timer obj c0a1cd7c! | |
| RTMP_TimerListAdd: add timer obj c0a1c970! | |
| RTMP_TimerListAdd: add timer obj c0a1cd4c! | |
| RTMP_TimerListAdd: add timer obj c0a1d0f8! | |
| RTMP_TimerListAdd: add timer obj c0a1ce44! | |
| RTMP_TimerListAdd: add timer obj c0a1ce74! | |
| RTMP_TimerListAdd: add timer obj c0a1cdac! | |
| RTMP_TimerListAdd: add timer obj c0a1cddc! | |
| RTMP_TimerListAdd: add timer obj c0a1ce0c! | |
| RTMP_TimerListAdd: add timer obj c0a37d54! | |
| RTMP_TimerListAdd: add timer obj c0a37e70! | |
| RTMP_TimerListAdd: add timer obj c0a37d80! | |
| RTMP_TimerListAdd: add timer obj c0a1d45c! | |
| E2pAccessMode=0 | |
| cfg_mode=14 | |
| cfg_mode=14 | |
| wmode_band_equal(): Band Not Equal! | |
| APSDCapable[0]=0 | |
| APSDCapable[1]=0 | |
| APSDCapable[2]=0 | |
| APSDCapable[3]=0 | |
| APSDCapable[4]=0 | |
| APSDCapable[5]=0 | |
| APSDCapable[6]=0 | |
| APSDCapable[7]=0 | |
| APSDCapable[8]=0 | |
| APSDCapable[9]=0 | |
| APSDCapable[10]=0 | |
| APSDCapable[11]=0 | |
| APSDCapable[12]=0 | |
| APSDCapable[13]=0 | |
| APSDCapable[14]=0 | |
| APSDCapable[15]=0 | |
| default ApCliAPSDCapable[0]=0 | |
| Key1Str is Invalid key length(0) or Type(0) | |
| Key2Str is Invalid key length(0) or Type(0) | |
| Key3Str is Invalid key length(0) or Type(0) | |
| Key4Str is Invalid key length(0) or Type(0) | |
| 1. Phy Mode = 49 | |
| get_chl_grp:illegal channel (167) | |
| get_chl_grp:illegal channel (167) | |
| get_chl_grp:illegal channel (169) | |
| get_chl_grp:illegal channel (169) | |
| get_chl_grp:illegal channel (171) | |
| get_chl_grp:illegal channel (171) | |
| get_chl_grp:illegal channel (173) | |
| get_chl_grp:illegal channel (173) | |
| Country Region from e2p = ffff | |
| mt76x2_read_temp_info_from_eeprom:: is_temp_tx_alc=0, temp_tx_alc_enable=0 | |
| mt76x2_read_tx_alc_info_from_eeprom:: is_ePA_mode=1, ePA_type=0 | |
| mt76x2_read_tx_alc_info_from_eeprom:: [5G band] high_temp_slope=15, low_temp_slope=9 | |
| mt76x2_read_tx_alc_info_from_eeprom:: [2G band] high_temp_slope=13, low_temp_slope=16 | |
| mt76x2_read_tx_alc_info_from_eeprom:: [5G band] tc_lower_bound=-7, tc_upper_bound=4 | |
| mt76x2_read_tx_alc_info_from_eeprom:: [2G band] tc_lower_bound=-7, tc_upper_bound=5 | |
| mt76x2_get_external_lna_gain::LNA type=0x0, BLNAGain=0xffffff8c, ALNAGain0=0xffffff8c, ALNAGain1=0xffffff8c, ALNAGain2=0xffffff8c | |
| 2. Phy Mode = 49 | |
| RTMP_TimerListAdd: add timer obj c0993528! | |
| RTMP_TimerListAdd: add timer obj c099682c! | |
| RTMP_TimerListAdd: add timer obj c0999b30! | |
| RTMP_TimerListAdd: add timer obj c099ce34! | |
| RTMP_TimerListAdd: add timer obj c09a0138! | |
| RTMP_TimerListAdd: add timer obj c09a343c! | |
| RTMP_TimerListAdd: add timer obj c09a6740! | |
| RTMP_TimerListAdd: add timer obj c09a9a44! | |
| RTMP_TimerListAdd: add timer obj c0a1d16c! | |
| 3. Phy Mode = 49 | |
| andes_pci_fw_init | |
| 0x1300 = 00073200 | |
| AntCfgInit: primary/secondary ant 0/1 | |
| andes_load_cr:cr_type(2) | |
| ChipStructAssign(): MT76x2 hook ! | |
| MCS Set = ff ff 00 00 01 | |
| RTMP_TimerListAdd: add timer obj c0a1dbe0! | |
| mt76x2_bbp_adjust():rf_bw=2, ext_ch=1, PrimCh=149, HT-CentCh=151, VHT-CentCh=155 | |
| APStartUp(): AP Set CentralFreq at 155(Prim=149, HT-CentCh=151, VHT-CentCh=155, BBP_BW=2) | |
| mt76x2_calibration(channel = 155) | |
| Main bssid = 20:c0:6d:99:eb:e4 | |
| mt76x2_reinit_agc_gain:original agc_vga0 = 0x48, agc_vga1 = 0x48 | |
| mt76x2_reinit_agc_gain:updated agc_vga0 = 0x48, agc_vga1 = 0x48 | |
| mt76x2_reinit_hi_lna_gain:original hi_lna0 = 0x33, hi_lna1 = 0x33 | |
| mt76x2_reinit_hi_lna_gain:updated hi_lna0 = 0x33, hi_lna1 = 0x33 | |
| original vga value(chain0) = 48 | |
| original vga value(chain1) = 48 | |
| <==== rt28xx_init, Status=0 | |
| RTMPDrvOpen(1):Check if PDMA is idle! | |
| RTMPDrvOpen(2):Check if PDMA is idle! | |
| TX_BCN DESC ae94c000 size = 320 | |
| RX[0] DESC ae94e000 size = 2048 | |
| RX[1] DESC ae94f000 size = 2048 | |
| E2pAccessMode=2 | |
| cfg_mode=9 | |
| cfg_mode=9 | |
| wmode_band_equal(): Band Equal! | |
| APSDCapable[0]=0 | |
| APSDCapable[1]=0 | |
| APSDCapable[2]=0 | |
| APSDCapable[3]=0 | |
| APSDCapable[4]=0 | |
| APSDCapable[5]=0 | |
| APSDCapable[6]=0 | |
| APSDCapable[7]=0 | |
| APSDCapable[8]=0 | |
| APSDCapable[9]=0 | |
| APSDCapable[10]=0 | |
| APSDCapable[11]=0 | |
| APSDCapable[12]=0 | |
| APSDCapable[13]=0 | |
| APSDCapable[14]=0 | |
| APSDCapable[15]=0 | |
| default ApCliAPSDCapable[0]=0 | |
| Key1Str is Invalid key length(0) or Type(0) | |
| Key2Str is Invalid key length(0) or Type(0) | |
| Key3Str is Invalid key length(0) or Type(0) | |
| Key4Str is Invalid key length(0) or Type(0) | |
| 20140814CmdAddressLenReq:(ret = 0) | |
| CmdFwStartReq: override = 1, address = 1048576 | |
| CmdStartDLRsp: WiFI FW Download Success | |
| AsicDMASchedulerInit(): DMA Scheduler Mode=0(LMAC) | |
| CmdPsRetrieveRsp Disable FW PS Supportstatus:1 !!!!! | |
| RtmpChipOpsEepromHook::e2p_type=0, inf_Type=5 | |
| efuse_probe: efuse = 10000002 | |
| RtmpEepromGetDefault::e2p_dafault=1 | |
| RtmpChipOpsEepromHook: E2P type(2), E2pAccessMode = 2, E2P default = 1 | |
| NVM is FLASH mode | |
| 1. Phy Mode = 14 | |
| Country Region from e2p = ffff | |
| tssi_1_target_pwr_g_band = 34 | |
| 2. Phy Mode = 14 | |
| 3. Phy Mode = 14 | |
| NICInitPwrPinCfg(13): Not support for HIF_MT yet! | |
| NICInitializeAsic(586): Not support rtmp_mac_sys_reset () for HIF_MT yet! | |
| mt_mac_init()--> | |
| mt7603_init_mac_cr()--> | |
| AsicSetMacMaxLen(1561): Set the Max RxPktLen=1024! | |
| <--mt_mac_init() | |
| WTBL Segment 1 info: | |
| MemBaseAddr/FID:0x28000/0 | |
| EntrySize/Cnt:32/128 | |
| WTBL Segment 2 info: | |
| MemBaseAddr/FID:0x40000/0 | |
| EntrySize/Cnt:64/128 | |
| WTBL Segment 3 info: | |
| MemBaseAddr/FID:0x42000/64 | |
| EntrySize/Cnt:64/128 | |
| WTBL Segment 4 info: | |
| MemBaseAddr/FID:0x44000/128 | |
| EntrySize/Cnt:32/128 | |
| AntCfgInit(2368): Not support for HIF_MT yet! | |
| AsicSendCommandToMcu(3385): Not support for HIF_MT yet! | |
| AsicSendCommandToMcu(3385): Not support for HIF_MT yet! | |
| AsicSendCommandToMcu(3385): Not support for HIF_MT yet! | |
| AsicSendCommandToMcu(3385): Not support for HIF_MT yet! | |
| MCS Set = ff ff 00 00 01 | |
| AsicSetChBusyStat(877): Not support for HIF_MT yet! | |
| AsicSetRalinkBurstMode(3699): Not support for HIF_MT yet! | |
| RTMPSetPiggyBack(797): Not support for HIF_MT yet! | |
| CmdChannelSwitch: control_chl = 1, central_chl = 3, BW = 1, TXStream = 2, RXStream = 2 | |
| mt7603_switch_channel(): Switch to Ch#3(2T2R), BBP_BW=1 | |
| AsicSetTxPreamble(3685): Not support for HIF_MT yet! | |
| AsicAddSharedKeyEntry(1725): Not support for HIF_MT yet! | |
| AsicSetPreTbtt(): bss_idx=0, PreTBTT timeout = 0xf0 | |
| Main bssid = 20:c0:6d:99:eb:e0 | |
| <==== rt28xx_init, Status=0 | |
| flush result = ffffff | |
| check pse fid Q7:set_get_fid, q_idx:7 empty!! | |
| Raeth v3.1 (Tasklet,SkbRecycle) | |
| phy_free_head is 0xde9a000!!! | |
| phy_free_tail_phy is 0xde9bff0!!! | |
| txd_pool=ade9c000 phy_txd_pool=0DE9C000 | |
| ei_local->skb_free start address is 0x8fd49494. | |
| free_txd: ade9c010, ei_local->cpu_ptr: 0DE9C000 | |
| POOL HEAD_PTR | DMA_PTR | CPU_PTR | |
| ----------------+---------+-------- | |
| 0xade9c000 0x0DE9C000 0x0DE9C000 | |
| phy_qrx_ring = 0x0de9e000, qrx_ring = 0xade9e000 | |
| phy_rx_ring0 = 0x0deae000, rx_ring0 = 0xadeae000 | |
| change HW-TRAP to 0x17ccf | |
| set LAN/WAN LLLLW | |
| GMAC1_MAC_ADRH -- : 0x000020c0 | |
| GMAC1_MAC_ADRL -- : 0x6d99ebe8 | |
| CDMA_CSG_CFG = 81000000 | |
| GDMA1_FWD_CFG = 20710000 | |
| device eth2 entered promiscuous mode | |
| device ra0 entered promiscuous mode | |
| device eth2.1 entered promiscuous mode | |
| device rai0 entered promiscuous mode | |
| br0: port 3(rai0) entering learning state | |
| br0: port 3(rai0) entering learning state | |
| br0: port 2(eth2.1) entering learning state | |
| br0: port 2(eth2.1) entering learning state | |
| br0: port 1(ra0) entering learning state | |
| br0: port 1(ra0) entering learning state | |
| br0: port 3(rai0) entering forwarding state | |
| br0: port 2(eth2.1) entering forwarding state | |
| br0: port 1(ra0) entering forwarding state | |
| ESW: Link Status Changed - Port4 Link UP | |
| Jan 1 00:00:14 miniupnpd[1453]: WPS listening on port 7777 | |
| Jan 1 00:00:14 miniupnpd[1456]: WPS listening on port 8888 | |
| Ralink APSoC Hardware Watchdog Timer | |
| Started WatchDog Timer. | |
| Jan 1 00:00:15 miniupnpd[1984]: WPS listening on port 7777 | |
| Jan 1 00:00:15 miniupnpd[1987]: WPS listening on port 8888 | |
| Jan 1 00:00:16 miniupnpd[3014]: WPS listening on port 7777 | |
| Jan 1 00:00:16 miniupnpd[3019]: WPS listening on port 8888 | |
| Stopped WatchDog Timer. | |
| Ralink APSoC Hardware Watchdog Timer | |
| Started WatchDog Timer. | |
| init: can't log to /dev/tty5 | |
| starting pid 5371, tty '/dev/ttyS1': '/bin/ntop_login' | |
| login: |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment