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@promach
promach / PKGBUILD
Created Aug 29, 2019
PKGBUILD for SonnetSuite Professional
View PKGBUILD
# Maintainer: Your Name <youremail@domain.com>
pkgname=sonnetsuite
pkgver=17.52.1
pkgrel=1
epoch=
pkgdesc="A 3D Planar High-Frequency Electromagnetic Software"
arch=("x86_64")
url="http://www.sonnetsoftware.com/products/sonnet-suites/"
license=('unknown')
groups=('lib32')
@promach
promach / planar_marchand_balun.anf
Last active Sep 4, 2019
A planar marchand balun from the paper : New Design Formulas for Impedance-Transforming 3-dB Marchand Baluns
View planar_marchand_balun.anf
$begin 'AnsoftNeutralFile'
Version(4, 0)
Source('Ansoft Designer', '2018.2.0')
Date='Mon Aug 19 14:26:50 2019'
DefaultUnits='m'
$begin 'PadShapes'
'Circle0.00085'(Circle(0.00085))
$end 'PadShapes'
$begin 'Padstacks'
$begin 'Round 0.85mm/0.75mm'
View Multi-Section_Coupled_Line_Balun.anf
$begin 'AnsoftNeutralFile'
Version(4, 0)
Source('Ansoft Designer', '2018.2.0')
Date='Mon Aug 19 00:02:00 2019'
DefaultUnits='m'
$begin 'Symbols'
$begin 'Multi-Section_Coupled_Line_Balun'
$begin 'SymPins'
$begin 'SymPinDef'
SymPin('Port1', -0.00508, 0, 0, 0, 0.00254, false, false, '')
@promach
promach / LNA1.asc
Last active Aug 16, 2019
a LNA circuit from the book "Design of CMOS RF Integrated Circuits and Systems"
View LNA1.asc
Version 4
SHEET 1 1172 852
WIRE 144 80 0 80
WIRE 256 80 144 80
WIRE 368 80 256 80
WIRE 480 80 368 80
WIRE 592 80 480 80
WIRE 0 128 0 80
WIRE 144 144 144 80
WIRE 480 144 480 80
@promach
promach / clock_gate.v
Last active Aug 14, 2019
A formally verified synchronous fifo with clock gating feature
View clock_gate.v
// Credits : https://github.com/YosysHQ/yosys-bigsim/blob/master/openmsp430/rtl/omsp_clock_gate.v
module clock_gate (
// OUTPUTs
gclk, // Gated clock
// INPUTs
clk, // Clock
enable_in // Clock enable
@promach
promach / dff.sby
Last active Sep 2, 2019
D flip-flop with asynchronous reset
View dff.sby
[tasks]
proof
cover
[options]
proof: mode prove
proof: depth 50
cover: mode cover
cover: depth 30
View mosfet_018.lib
* modified for use with LTSpice; DM 8/19/2008
*
* 0.18u CMOS process
*
* NMOS transistor model name: NM
* PMOS transistor model name: PM
*-----------------------------------------------------------------------
.subckt NM D G S B
@promach
promach / mosfet_018.lib
Created Mar 29, 2019
gilbert cell mixer circuit
View mosfet_018.lib
* modified for use with LTSpice; DM 8/19/2008
*
* 0.18u CMOS process
*
* NMOS transistor model name: NM
* PMOS transistor model name: PM
*-----------------------------------------------------------------------
.subckt NM D G S B
@promach
promach / arbiter.sby
Last active Sep 9, 2019
Spidergon Networks On Chip
View arbiter.sby
[tasks]
proof
cover
[options]
proof: mode prove
proof: depth 10
cover: mode cover
cover: depth 20
@promach
promach / multiply.sby
Last active Feb 20, 2019
A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm
View multiply.sby
[tasks]
proof
cover
[options]
proof: mode prove
proof: depth 5
cover: mode cover
cover: depth 20
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