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AXI4 verilog coding for interfacing with DDR AXI controller
#sby results
load_data_from_bram_prf/
load_data_from_bram_cvr/
#yosys synthesis result
load_data_from_bram.json
`define LOOPBACK 1
module address_generator(clk, reset,
i_axi_awready, o_axi_awid, o_axi_awaddr, o_axi_awlen, o_axi_awsize, o_axi_awburst,
o_axi_awlock, o_axi_awcache, o_axi_awprot, o_axi_awqos, o_axi_awvalid,
i_axi_wready, o_axi_wdata, o_axi_wstrb, o_axi_wlast, o_axi_wvalid,
i_axi_bid, i_axi_bresp, i_axi_bvalid, o_axi_bready,
i_axi_arready, o_axi_arid, o_axi_araddr, o_axi_arlen, o_axi_arsize, o_axi_arburst,
o_axi_arlock, o_axi_arcache, o_axi_arprot, o_axi_arqos, o_axi_arvalid,
i_axi_rid, i_axi_rresp, i_axi_rvalid, i_axi_rdata, i_axi_rlast, o_axi_rready); // An axi master that generates DDR address for the slave DDR axi controller
parameter TILE_LENGTH = 10; // a tile is symmetrical, so TILE_LENGTH = TILE_WIDTH
parameter MAX_J = 10;
parameter MAX_K = 10;
parameter N = 4; // number of input feature maps
parameter n = 1; // input feature map index (just to identify map)
parameter Tn = 4; // number of tiles for input feature maps (divide and conquer due to resource limits)
`ifdef FORMAL
parameter r = 8; // FEATURE_SIZE_WIDTH
parameter c = 8; // FEATURE_SIZE_HEIGHT
`else
parameter r = 256; // FEATURE_SIZE_WIDTH
parameter c = 256; // FEATURE_SIZE_HEIGHT
`endif
parameter IDX_N_WIDTH = ($clog2(N*TILE_LENGTH*TILE_LENGTH));
parameter IDX_R_WIDTH = ($clog2((r+MAX_J)*TILE_LENGTH));
parameter IDX_K_WIDTH = ($clog2(c+MAX_K));
parameter Tn_WIDTH = $clog2(Tn);
parameter r_WIDTH = $clog2(r);
// AXI Address width (log wordsize) for DDR
parameter C_AXI_ADDR_WIDTH = ((IDX_N_WIDTH >= IDX_R_WIDTH) && (IDX_N_WIDTH >= IDX_K_WIDTH)) ?
IDX_N_WIDTH :
(IDX_R_WIDTH >= IDX_K_WIDTH) ? IDX_R_WIDTH : IDX_K_WIDTH;
`ifdef FORMAL
parameter C_AXI_DATA_WIDTH = 8; // related to AxSIZE
parameter C_SIZE_OF_CACHE = 4; // for storing weights and biases parameters of neural network
`else
parameter C_AXI_DATA_WIDTH = 128; // related to AxSIZE
parameter C_SIZE_OF_CACHE = 64; // for storing weights and biases parameters of neural network
`endif
parameter C_AXI_ID_WIDTH = 1;
localparam NUM_OF_BITS_PER_BYTES = 8;
localparam INCR_BURST_TYPE = 2'b01; // AxBURST[2:0] , see 'burst type' section in AXI spec
// AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers.
// Support for all other burst types in AXI4 remains at 1 to 16 transfers.
// for wrapping bursts, the burst length must be 2, 4, 8, or 16
// a burst must not cross a 4KB address boundary
// early termination of bursts is not supported
localparam MAX_BURST_LENGTH = 256;
localparam BURST_SIZE_ENCODING_WIDTH = 3; // AxSIZE[2:0] , see 'burst size' section in AXI spec
localparam SUBWORD_SMALLEST_UNIT = 8; // smallest granularity in AXI protocol : 8 bit
localparam PROT_BITWIDTH = 3;
localparam QOS_BITWIDTH = 4;
localparam CACHE_BITWIDTH = 4;
input clk, reset;
// AXI write address channel signals
input wire i_axi_awready; // Slave is ready to accept
output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid; // Write ID
output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr; // Write address
output wire [$clog2(MAX_BURST_LENGTH)-1:0] o_axi_awlen; // Write Burst Length
output wire [BURST_SIZE_ENCODING_WIDTH-1:0] o_axi_awsize; // Write Burst size
output wire [1:0] o_axi_awburst; // Write Burst type
output wire [0:0] o_axi_awlock; // Write lock type
output wire [CACHE_BITWIDTH-1:0] o_axi_awcache; // Write Cache type
output wire [PROT_BITWIDTH-1:0] o_axi_awprot; // Write Protection type
output wire [QOS_BITWIDTH-1:0] o_axi_awqos; // Write Quality of Svc
output reg o_axi_awvalid; // Write address valid
// AXI write data channel signals
input wire i_axi_wready; // Write data ready
output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata; // Write data
output reg [C_AXI_DATA_WIDTH/SUBWORD_SMALLEST_UNIT-1:0] o_axi_wstrb; // Write strobes
output reg o_axi_wlast; // Last write transaction
output reg o_axi_wvalid; // Write valid
// AXI write response channel signals
/* verilator lint_off UNUSED */
input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid; // Response ID
/* verilator lint_on UNUSED */
input wire [1:0] i_axi_bresp; // Write response
input wire i_axi_bvalid; // Write reponse valid
output wire o_axi_bready; // Response ready
// AXI read address channel signals
input wire i_axi_arready; // Read address ready
output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid; // Read ID
output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr; // Read address
output wire [$clog2(MAX_BURST_LENGTH)-1:0] o_axi_arlen; // Read Burst Length
output wire [BURST_SIZE_ENCODING_WIDTH-1:0] o_axi_arsize; // Read Burst size
output wire [1:0] o_axi_arburst; // Read Burst type
output wire [0:0] o_axi_arlock; // Read lock type
output wire [CACHE_BITWIDTH-1:0] o_axi_arcache; // Read Cache type
output wire [PROT_BITWIDTH-1:0] o_axi_arprot; // Read Protection type
output wire [QOS_BITWIDTH-1:0] o_axi_arqos; // Read Quality of Svc
output reg o_axi_arvalid; // Read address valid
/* verilator lint_off UNUSED */
// AXI read data channel signals
input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid; // Response ID
/* verilator lint_on UNUSED */
input wire [1:0] i_axi_rresp; // Read response
input wire i_axi_rvalid; // Read reponse valid
input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata; // Read data
input wire i_axi_rlast; // Read last
output wire o_axi_rready; // Read Response ready
always @(posedge clk)
begin
if(reset) o_axi_wstrb <= 0;
// burst alignment mechanism, see https://i.imgur.com/jKbzfFo.png
// o_axi_wstrb <= (~0) << (o_axi_awaddr % (o_axi_awlen+1));
// all the bracket variables are for removing verilator width warnings
else o_axi_wstrb <= ((~0) << (o_axi_awaddr %
{{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}},
(o_axi_awlen+1'b1)}));
end
wire write_response_is_ok = i_axi_bvalid && ((i_axi_bresp == 'b00) || (i_axi_bresp == 'b01));
// need to implement data re-transmission
wire write_response_is_not_ok = i_axi_bvalid && !((i_axi_bresp == 'b00) || (i_axi_bresp == 'b01));
always @(posedge clk)
begin
if(reset)
begin
o_axi_wvalid <= 0;
end
else if(!(o_axi_wvalid && !i_axi_wready))
begin
// Note that both o_axi_awsize , o_axi_awlen are of hardware constants, so no multiply hardware
// since this is for testing, WDATA just uses some values up to the total size of the write address space
// Note: a master must not wait for AWREADY to be asserted before driving WVALID
o_axi_wvalid <= (o_axi_wlast) ? 0 :
(o_axi_wdata < (o_axi_awsize*o_axi_awlen));
end
end
wire ddr_write_address_range_is_valid = (o_axi_awaddr < (1 << C_AXI_ADDR_WIDTH));
always @(posedge clk)
begin
if(reset) o_axi_awvalid <= 0;
// AXI specification: A3.3.1 Dependencies between channel handshake signal
// the VALID signal of the AXI interface sending information must not be dependent on
// the READY signal of the AXI interface receiving that information
// this is to prevent deadlock
// since AXI slave could wait for i_axi_awvalid to be true before setting o_axi_awready true.
// Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
// Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
// VALID signal needs to be set (initially) independent of READY signal,
// and then only ever adjusted if !(VALID && !READY)
// Note: the master must not wait for the slave to assert AWREADY before asserting AWVALID
// Note: (!(o_axi_awvalid && !i_axi_awready)) == (!awvalid || awready)
// == (!awvalid || (awvalid && awready)).
// it means "no transaction in progress or transaction accepted"
else if(!(o_axi_awvalid && !i_axi_awready))
o_axi_awvalid <= /*i_axi_awready &&*/ (ddr_write_address_range_is_valid);
end
wire write_transaction_is_accepted = (o_axi_wvalid) && (i_axi_wready);
wire address_write_transaction_is_accepted = (o_axi_awvalid) && (i_axi_awready);
always @(posedge clk)
begin
if(reset)
begin
o_axi_awaddr <= 0;
//o_axi_wdata <= 0;
end
else if(address_write_transaction_is_accepted)
begin
o_axi_awaddr <= o_axi_awaddr +
{{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, (o_axi_awlen+1'b1)};
//o_axi_wdata <= o_axi_wdata + 1;
end
end
always @(posedge clk)
begin
if(reset)
begin
//o_axi_awaddr <= 0;
o_axi_wdata <= 0;
end
else if(write_transaction_is_accepted)
begin
//o_axi_awaddr <= o_axi_awaddr + 1;
o_axi_wdata <= o_axi_wdata + 1;
end
end
`ifdef LOOPBACK
wire data_had_been_written_successfully = write_response_is_ok && o_axi_bready;
wire read_address_contains_loopback_data = data_had_been_written_successfully &&
(o_axi_awaddr >= (idx_n + idx_r + idx_k + {{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, o_axi_awlen}));
`endif
wire not_yet_the_end_of_neural_network_addresses =
(idx_n + idx_r + idx_k) < ((N * TILE_LENGTH * TILE_LENGTH) +
((r + MAX_J) * TILE_LENGTH) +
(c + MAX_K));
always @(posedge clk)
begin
if(reset) o_axi_arvalid <= 0;
// AXI specification: A3.3.1 Dependencies between channel handshake signal
// the VALID signal of the AXI interface sending information must not be dependent on
// the READY signal of the AXI interface receiving that information
// this is to prevent deadlock
// since AXI slave could wait for i_axi_arvalid to be true before setting o_axi_arready true.
// Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
// Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
// VALID signal needs to be set (initially) independent of READY signal,
// and then only ever adjusted if !(VALID && !READY)
// Note: the master must not wait for the slave to assert ARREADY before asserting ARVALID
// Note: (!(o_axi_arvalid && !i_axi_arready)) == (!arvalid || arready)
// == (!arvalid || (arvalid && arready)).
// it means "no transaction in progress or transaction accepted"
else if(!(o_axi_arvalid && !i_axi_arready))
`ifdef LOOPBACK
o_axi_arvalid <= /*i_axi_arready &&*/ (not_yet_the_end_of_neural_network_addresses) &&
(read_address_contains_loopback_data) &&
(o_axi_bready && i_axi_bvalid && write_response_is_ok);
`else
o_axi_arvalid <= /*i_axi_arready &&*/ (not_yet_the_end_of_neural_network_addresses);
`endif
end
reg [$clog2(MAX_BURST_LENGTH)-1:0] num_of_write_transactions;
always @(posedge clk)
begin
if(reset) num_of_write_transactions <= 0;
else if(o_axi_wvalid && i_axi_wready)
num_of_write_transactions <= (o_axi_wlast) ? 0 : num_of_write_transactions + 1;
end
always @(posedge clk)
begin
if(reset) o_axi_wlast <= 0;
else o_axi_wlast <= (num_of_write_transactions == (o_axi_awlen - 1));
end
//assign o_axi_wlast = 0;
assign o_axi_awid = 0;
assign o_axi_awlen = 15; // each burst has (Burst_Length = AxLEN[7:0] + 1) data transfers
/* verilator lint_off WIDTH */
assign o_axi_awsize = $clog2(C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES); // 128 bits (16 bytes) of data when AxSIZE[2:0] = 3'b100
// Burst_Length = AxLEN[7:0] + 1, to accommodate the extended burst length of the INCR burst type in AXI4.
/* verilator lint_on WIDTH */
assign o_axi_awburst = INCR_BURST_TYPE;
assign o_axi_awlock = 0;
assign o_axi_awcache = 0;
assign o_axi_awprot = 0;
assign o_axi_awqos = 0; // no priority or QoS concept
assign o_axi_arqos = 0; // no priority or QoS concept
assign o_axi_arburst = INCR_BURST_TYPE;
/* verilator lint_off WIDTH */
assign o_axi_arsize = $clog2(C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES); // 128 bits (16 bytes) of data when AxSIZE[2:0] = 3'b100
// Burst_Length = AxLEN[7:0] + 1, to accommodate the extended burst length of the INCR burst type in AXI4.
/* verilator lint_on WIDTH */
assign o_axi_arlen = 15; // each burst has (Burst_Length = AxLEN[7:0] + 1) data transfers
assign o_axi_arprot = 3'b010; // {data access, non-secure access, unprivileged access}
assign o_axi_arlock = 0; // AXI4 does not support locked transactions.
assign o_axi_arcache = 0; // mostly used for HPS (hard processor system) such as ARM hard CPU IP
assign o_axi_arid = 0; // there is one AXI slave which is the DDR memory (A, B, or C) ?
// what situations will render data requester (AXI master) busy to receive read response ??
// such as AXI interconnect where arbitration will fail to acquire the data transfer priority
// such as the internal cache storage to store the data from external DDR memory is now full
// So, let's use a random value that is $anyseq in formal verification
assign o_axi_rready = (reset) ? 1 : `ifdef FORMAL $anyseq `else (!cache_is_full) `endif;
// The master can assert BREADY before BVALID is asserted.
assign o_axi_bready = (reset) ? 1 : `ifdef FORMAL $anyseq `else (i_axi_bvalid) `endif;
wire address_read_transaction_is_accepted = (o_axi_arvalid) && (i_axi_arready);
always @(posedge clk)
begin
if(reset) o_axi_araddr <= 0;
else if(address_read_transaction_is_accepted)
o_axi_araddr <= idx_n + idx_r + idx_k; // the DDR address to read data from
end
// used for generating address (o_axi_araddr) indexes
reg [C_AXI_ADDR_WIDTH-1:0] idx_n;
reg [C_AXI_ADDR_WIDTH-1:0] idx_r;
reg [C_AXI_ADDR_WIDTH-1:0] idx_k;
wire not_max_limit_of_idx_n = idx_n < (N * TILE_LENGTH * TILE_LENGTH);
wire not_max_limit_of_idx_r = idx_r < ((r + MAX_J) * TILE_LENGTH);
wire not_max_limit_of_idx_k = idx_k < (c + MAX_K);
localparam NUM_OF_INCREMENT_STATES = 3;
localparam STATE_N = 1;
localparam STATE_R = 2;
localparam STATE_K = 3;
reg [$clog2(NUM_OF_INCREMENT_STATES)-1:0] increment_states;
reg [$clog2(NUM_OF_INCREMENT_STATES)-1:0] previous_increment_states;
always @(posedge clk) previous_increment_states <= increment_states;
// no multiply in actual synthesized hardware since
// 'N', 'n', 'Tn', 'r', 'MAX_J' and 'TILE_LENGTH' are constants
always @(posedge clk)
begin
if(reset)
begin
increment_states <= STATE_N;
idx_n <= n * TILE_LENGTH * TILE_LENGTH;
idx_r <= r * TILE_LENGTH;
idx_k <= c;
end
else if(address_read_transaction_is_accepted) begin
case(increment_states)
STATE_N:
begin
if(not_max_limit_of_idx_n)
begin
increment_states <= STATE_K;
idx_k <= idx_k + 1;
if(previous_increment_states == STATE_R)
idx_n <= idx_n + Tn * TILE_LENGTH * TILE_LENGTH;
end
else increment_states <= STATE_N;
end
STATE_R:
begin
if(not_max_limit_of_idx_r)
begin
increment_states <= STATE_K;
idx_k <= idx_k + 1;
if(previous_increment_states == STATE_K)
idx_r <= idx_r + TILE_LENGTH;
end
else begin
increment_states <= STATE_N;
idx_r <= r * TILE_LENGTH;
end
end
STATE_K:
begin
if(not_max_limit_of_idx_k)
begin
increment_states <= STATE_K;
idx_k <= idx_k + 1;
end
else begin
increment_states <= STATE_R;
idx_k <= c;
end
end
default:
begin
increment_states <= STATE_N;
idx_n <= n * TILE_LENGTH * TILE_LENGTH;
idx_r <= r * TILE_LENGTH;
idx_k <= c;
end
endcase
end
end
/* verilator lint_off UNUSED */
wire arm_write_feature_enable;
wire [C_AXI_DATA_WIDTH-1:0] arm_write_feature_data;
wire cache_is_empty;
wire [$clog2(C_SIZE_OF_CACHE)-1:0] cache_address_for_reading;
assign cache_address_for_reading = 0; // for testing only
/* verilator lint_on UNUSED */
wire valid_read_response_does_not_contain_error_messages = i_axi_rvalid && (i_axi_rresp == 0);
wire cache_is_full; // needed since C_SIZE_OF_CACHE is always smaller than SIZE_OF_DDR_MEMORY
// for storing neural network parameters (weights and biases) at destination side,
// so this bram acts as intermediate cache (much smaller size than DDR memory) for the neural network
// no need AXI protocol in order to save logic usage, thus lesser area and power consumption
cache_controller #(.C_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_SIZE_OF_CACHE(C_SIZE_OF_CACHE)) nn_features_cache
(
.clk(clk), .reset(reset),
.i_data(i_axi_rdata), // NN params coming from DDR memory
.i_data_is_valid
((o_axi_rready && valid_read_response_does_not_contain_error_messages)), // DDR data is valid
.i_addr(cache_address_for_reading),
.full(cache_is_full), // NN params cache is full
.o_data(arm_write_feature_data), // NN params going to neural network layers
.o_data_is_valid(arm_write_feature_enable), // neural network layers to start another intermediate computations
.empty(cache_is_empty) // no NN params to feed into the neural network layers
);
`ifdef FORMAL
initial assume(reset);
reg first_clock_had_passed = 0;
always @(posedge clk) first_clock_had_passed <= 1;
always @(posedge clk)
if(first_clock_had_passed)
cover((o_axi_araddr != 0) && transaction_is_accepted && $past(i_axi_arready) &&
$past(o_axi_rready) && !o_axi_rready);
`endif
endmodule
-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
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-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
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-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 14
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_14;
USE axi_bram_ctrl_v4_0_14.axi_bram_ctrl;
ENTITY axi_bram_ctrl_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END axi_bram_ctrl_0;
ARCHITECTURE axi_bram_ctrl_0_arch OF axi_bram_ctrl_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_bram_ctrl_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(127 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awid: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 14, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_" &
"BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "INTERNAL",
C_MEMORY_DEPTH => 1024,
C_BRAM_ADDR_WIDTH => 10,
C_S_AXI_ADDR_WIDTH => 14,
C_S_AXI_DATA_WIDTH => 128,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_SELECT_XPM => 1,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rddata_a => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128)),
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 128))
);
END axi_bram_ctrl_0_arch;
This file has been truncated, but you can view the full file.
-------------------------------------------------------------------------------
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the user’s sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2001-05-11 First Version
-- KC 2001-06-20 Added Addr as an output port, for use as an occupancy
-- value
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- DET 1/17/2008 v4_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
-------------------------------------------------------------------------------
-- axi_bram_ctrl_funcs.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_funcs.vhd
--
-- Description: Support functions for axi_bram_ctrl library modules.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
--
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/16/2011 v1.03a
-- ~~~~~~
-- Update ECC size on 128-bit data width configuration.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Add MIG functions for Hsiao ECC.
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Add Find_ECC_Size function.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Add REDUCTION_OR function.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Recode Create_Size_Max with a case statement.
-- ^^^^^^
-- JLJ 3/31/2011 v1.03a
-- ~~~~~~
-- Add coverage tags.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Remove Family_To_LUT_Size function.
-- Remove String_To_Family function.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package axi_bram_ctrl_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
SPARTAN3,
VIRTEX4,
VIRTEX5,
SPARTAN3E,
SPARTAN3A,
SPARTAN3AN,
SPARTAN3Adsp,
SPARTAN6,
VIRTEX6,
VIRTEX7,
KINTEX7,
-- pragma xilinx_rtl_on
RTL
);
-- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
-- Get the maximum number of inputs to a LUT.
-- function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN;
function log2(x : natural) return integer;
function Int_ECC_Size (i: integer) return integer;
function Find_ECC_Size (i: integer; j: integer) return integer;
function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer;
function Create_Size_Max (i: integer) return std_logic_vector;
function REDUCTION_OR (A: in std_logic_vector) return std_logic;
function REDUCTION_XOR (A: in std_logic_vector) return std_logic;
function REDUCTION_NOR (A: in std_logic_vector) return std_logic;
function BOOLEAN_TO_STD_LOGIC (A: in BOOLEAN) return std_logic;
end package axi_bram_ctrl_funcs;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body axi_bram_ctrl_funcs is
-------------------------------------------------------------------------------
-- Function: Int_ECC_Size
-- Purpose: Determine internal size of ECC when enabled.
-------------------------------------------------------------------------------
function Int_ECC_Size (i: integer) return integer is
begin
--coverage off
if (i = 32) then
return 7; -- 7-bits ECC for 32-bit data
-- ECC port size fixed @ 8-bits
elsif (i = 64) then
return 8;
elsif (i = 128) then
return 9; -- Hsiao is 9-bits for 128-bit data.
else
return 0;
end if;
--coverage on
end Int_ECC_Size;
-------------------------------------------------------------------------------
-- Function: Find_ECC_Size
-- Purpose: Determine external size of ECC signals when enabled.
-------------------------------------------------------------------------------
function Find_ECC_Size (i: integer; j: integer) return integer is
begin
--coverage off
if (i = 1) then
if (j = 32) then
return 8; -- Keep at 8 for port size matchings
-- Only 7-bits ECC per 32-bit data
elsif (j = 64) then
return 8;
elsif (j = 128) then
return 9;
else
return 0;
end if;
else
return 0;
-- ECC data width = 0 when C_ECC = 0 (disabled)
end if;
--coverage on
end Find_ECC_Size;
-------------------------------------------------------------------------------
-- Function: Find_ECC_Full_Bit_Size
-- Purpose: Determine external size of ECC signals when enabled in bytes.
-------------------------------------------------------------------------------
function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer is
begin
--coverage off
if (i = 1) then
if (j = 32) then
return 8;
elsif (j = 64) then
return 8;
elsif (j = 128) then
return 16;
else
return 0;
end if;
else
return 0;
-- ECC data width = 0 when C_ECC = 0 (disabled)
end if;
--coverage on
end Find_ECC_Full_Bit_Size;
-------------------------------------------------------------------------------
-- Function: Create_Size_Max
-- Purpose: Create maximum value for AxSIZE based on AXI data bus width.
-------------------------------------------------------------------------------
function Create_Size_Max (i: integer)
return std_logic_vector is
variable size_vector : std_logic_vector (2 downto 0);
begin
case (i) is
when 32 => size_vector := "010"; -- 2h (4 bytes)
when 64 => size_vector := "011"; -- 3h (8 bytes)
when 128 => size_vector := "100"; -- 4h (16 bytes)
when 256 => size_vector := "101"; -- 5h (32 bytes)
when 512 => size_vector := "110"; -- 5h (32 bytes)
when 1024 => size_vector := "111"; -- 5h (32 bytes)
--coverage off
when others => size_vector := "000"; -- 0h
--coverage on
end case;
return (size_vector);
end function Create_Size_Max;
-------------------------------------------------------------------------------
-- Function: REDUCTION_OR
-- Purpose: New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_OR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
-------------------------------------------------------------------------------
-- Function: REDUCTION_XOR
-- Purpose: Derived from MIG v3.7 ecc_gen module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_XOR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp xor A(i);
end loop;
return tmp;
end function REDUCTION_XOR;
-------------------------------------------------------------------------------
-- Function: REDUCTION_NOR
-- Purpose: Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_NOR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return not tmp;
end function REDUCTION_NOR;
-------------------------------------------------------------------------------
-- Function: BOOLEAN_TO_STD_LOGIC
-- Purpose: Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function BOOLEAN_TO_STD_LOGIC (A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
-------------------------------------------------------------------------------
function LowerCase_Char(char : character) return character is
begin
--coverage off
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
--coverage on
end LowerCase_Char;
-------------------------------------------------------------------------------
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String ( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
--coverage off
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
--coverage on
RETURN equal;
END Equal_String;
-------------------------------------------------------------------------------
-- Remove usage of C_FAMILY.
-- Remove usage of String_To_Family function.
--
--
-- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
-- begin -- function String_To_Family
--
-- --coverage off
--
-- if ((Select_RTL) or Equal_String(S, "rtl")) then
-- return RTL;
-- elsif Equal_String(S, "spartan3") or Equal_String(S, "aspartan3") then
-- return SPARTAN3;
-- elsif Equal_String(S, "spartan3E") or Equal_String(S, "aspartan3E") then
-- return SPARTAN3E;
-- elsif Equal_String(S, "spartan3A") or Equal_String(S, "aspartan3A") then
-- return SPARTAN3A;
-- elsif Equal_String(S, "spartan3AN") then
-- return SPARTAN3AN;
-- elsif Equal_String(S, "spartan3Adsp") or Equal_String(S, "aspartan3Adsp") then
-- return SPARTAN3Adsp;
-- elsif Equal_String(S, "spartan6") or Equal_String(S, "spartan6l") or
-- Equal_String(S, "qspartan6") or Equal_String(S, "aspartan6") or Equal_String(S, "qspartan6l") then
-- return SPARTAN6;
-- elsif Equal_String(S, "virtex4") or Equal_String(S, "qvirtex4")
-- or Equal_String(S, "qrvirtex4") then
-- return VIRTEX4;
-- elsif Equal_String(S, "virtex5") or Equal_String(S, "qrvirtex5") then
-- return VIRTEX5;
-- elsif Equal_String(S, "virtex6") or Equal_String(S, "virtex6l") or Equal_String(S, "qvirtex6") then
-- return VIRTEX6;
-- elsif Equal_String(S, "virtex7") then
-- return VIRTEX7;
-- elsif Equal_String(S, "kintex7") then
-- return KINTEX7;
--
-- --coverage on
--
-- else
-- -- assert (false) report "No known target family" severity failure;
-- return RTL;
-- end if;
--
-- end function String_To_Family;
-------------------------------------------------------------------------------
-- Remove usage of C_FAMILY.
-- Remove usage of Family_To_LUT_Size function.
--
-- function Family_To_LUT_Size (Family : TARGET_FAMILY_TYPE) return integer is
-- begin
--
-- --coverage off
--
-- if (Family = SPARTAN3) or (Family = SPARTAN3E) or (Family = SPARTAN3A) or
-- (Family = SPARTAN3AN) or (Family = SPARTAN3Adsp) or (Family = VIRTEX4) then
-- return 4;
-- end if;
--
-- return 6;
--
-- --coverage on
--
-- end function Family_To_LUT_Size;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
--coverage off
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
--coverage on
end function log2;
-------------------------------------------------------------------------------
end package body axi_bram_ctrl_funcs;
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the user’s sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and AXI BRAM CTRL when XST elaborated the client core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE coregen_comp_defs IS
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_3_6
-- Component declaration for blk_mem_gen_v8_3_6 pulled from the blk_mem_gen_v8_3_6.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_3_6
generic (
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY : STRING := "virtex4";
C_XDEVICEFAMILY : STRING := "virtex4";
-- C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_AXI_TYPE : INTEGER := 1;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
--General Memory Parameters:
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 9;
C_ALGORITHM : INTEGER := 0;
C_PRIM_TYPE : INTEGER := 3;
--Memory Initialization Parameters:
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "111111111";
C_RST_TYPE : STRING := "SYNC";
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A : INTEGER := 4;
C_READ_WIDTH_A : INTEGER := 4;
C_WRITE_DEPTH_A : INTEGER := 4096;
C_READ_DEPTH_A : INTEGER := 4096;
C_ADDRA_WIDTH : INTEGER := 12;
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B : INTEGER := 4;
C_READ_WIDTH_B : INTEGER := 4;
C_WRITE_DEPTH_B : INTEGER := 4096;
C_READ_DEPTH_B : INTEGER := 4096;
C_ADDRB_WIDTH : INTEGER := 12;
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
--ECC Parameters
C_USE_ECC : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 0;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '0';
REGCEA : IN STD_LOGIC := '0';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
--Port B:
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '0';
REGCEB : IN STD_LOGIC := '0';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
--ECC:
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT; --blk_mem_gen_v8_3_6
END coregen_comp_defs;
-------------------------------------------------------------------------------
-- axi_lite_if.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_if.vhd
--
-- Description: Derived AXI-Lite interface module.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity axi_lite_if is
generic (
-- AXI4-Lite slave generics
-- C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
-- C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 4; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- lmb_bram_if_cntlr signals
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end entity axi_lite_if;
library unisim;
use unisim.vcomponents.all;
architecture IMP of axi_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal ongoing_write : std_logic;
signal ongoing_read : std_logic;
signal S_AXI_RVALID_i : std_logic;
signal RegRdData_i : std_logic_vector(C_DWIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Only allow one access at a time
new_write_access <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID;
new_read_access <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Store register address and write data
Reg: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
RegAddr <= (others => '0');
RegWrData <= (others => '0');
elsif new_write_access = '1' then
RegAddr <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2);
RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
elsif new_read_access = '1' then
RegAddr <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2);
end if;
end if;
end process Reg;
-- Handle write access.
WriteAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_write <= '0';
elsif new_write_access = '1' then
ongoing_write <= '1';
elsif ongoing_write = '1' and S_AXI_BREADY = '1' then
ongoing_write <= '0';
end if;
RegWr <= new_write_access;
end if;
end process WriteAccess;
S_AXI_BVALID <= ongoing_write;
S_AXI_BRESP <= (others => '0');
-- Handle read access
ReadAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
elsif new_read_access = '1' then
ongoing_read <= '1';
S_AXI_RVALID_i <= '0';
elsif ongoing_read = '1' then
if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
else
S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA
end if;
end if;
end if;
end process ReadAccess;
S_AXI_RVALID <= S_AXI_RVALID_i;
S_AXI_RRESP <= (others => '0');
Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_Bits_Are_Used;
RegRdData_i <= RegRdData; -- Swap to - downto
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : FDRE
port map (
Q => S_AXI_RDATA(I),
C => LMB_Clk,
CE => ongoing_read,
D => RegRdData_i(I),
R => LMB_Rst);
end generate S_AXI_RDATA_DFF;
end architecture IMP;
-------------------------------------------------------------------------------
-- checkbit_handler_64.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: checkbit_handler_64.vhd
--
-- Description: Generates the ECC checkbits for the input vector of
-- 64-bit data widths.
--
-- VHDL-Standard: VHDL'93/02
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity checkbit_handler_64 is
generic (
C_ENCODE : boolean := true;
C_REG : boolean := false;
C_USE_LUT6 : boolean := true);
port (
Clk : in std_logic;
DataIn : in std_logic_vector (63 downto 0);
CheckIn : in std_logic_vector (7 downto 0);
CheckOut : out std_logic_vector (7 downto 0);
Syndrome : out std_logic_vector (7 downto 0);
Syndrome_7 : out std_logic_vector (11 downto 0);
Syndrome_Chk : in std_logic_vector (0 to 7);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler_64;
library unisim;
use unisim.vcomponents.all;
-- library axi_bram_ctrl_v1_02_a;
-- use axi_bram_ctrl_v1_02_a.all;
architecture IMP of checkbit_handler_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
-- component ParityEnable
-- generic (
-- C_USE_LUT6 : boolean;
-- C_SIZE : integer);
-- port (
-- InA : in std_logic_vector(0 to C_SIZE - 1);
-- Enable : in std_logic;
-- Res : out std_logic);
-- end component ParityEnable;
signal data_chk0 : std_logic_vector(0 to 34);
signal data_chk1 : std_logic_vector(0 to 34);
signal data_chk2 : std_logic_vector(0 to 34);
signal data_chk3 : std_logic_vector(0 to 30);
signal data_chk4 : std_logic_vector(0 to 30);
signal data_chk5 : std_logic_vector(0 to 30);
signal data_chk6 : std_logic_vector(0 to 6);
signal data_chk6_xor : std_logic;
-- signal data_chk7_a : std_logic_vector(0 to 17);
-- signal data_chk7_b : std_logic_vector(0 to 17);
-- signal data_chk7_i : std_logic;
-- signal data_chk7_xor : std_logic;
-- signal data_chk7_i_xor : std_logic;
-- signal data_chk7_a_xor : std_logic;
-- signal data_chk7_b_xor : std_logic;
begin -- architecture IMP
-- Add bits for 64-bit ECC
-- 0 <= 0 1 3 4 6 8 10 11 13 17 19 21 23 25 26 28 30
-- 32 34 36 38 40 42 44 46 48 50 52 54 56 57 59 61 63
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30) &
DataIn(32) & DataIn(34) & DataIn(36) & DataIn(38) & DataIn(40) &
DataIn(42) & DataIn(44) & DataIn(46) & DataIn(48) & DataIn(50) &
DataIn(52) & DataIn(54) & DataIn(56) & DataIn(57) & DataIn(59) &
DataIn(61) & DataIn(63) ;
-- 18 + 17 = 35
---------------------------------------------------------------------------
-- 1 <= 0 2 3 5 6 9 10 12 13 16 17 20 21 24 25 27 28 31
-- 32 35 36 39 40 43 44 47 48 51 52 55 56 58 59 62 63
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31) &
DataIn(32) & DataIn(35) & DataIn(36) & DataIn(39) & DataIn(40) &
DataIn(43) & DataIn(44) & DataIn(47) & DataIn(48) & DataIn(51) &
DataIn(52) & DataIn(55) & DataIn(56) & DataIn(58) & DataIn(59) &
DataIn(62) & DataIn(63) ;
-- 18 + 17 = 35
---------------------------------------------------------------------------
-- 2 <= 1 2 3 7 8 9 10 14 15 16 17 22 23 24 25 29 30 31
-- 32 37 38 39 40 45 46 47 48 53 54 55 56 60 61 62 63
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31) &
DataIn(32) & DataIn(37) & DataIn(38) & DataIn(39) & DataIn(40) & DataIn(45) &
DataIn(46) & DataIn(47) & DataIn(48) & DataIn(53) & DataIn(54) & DataIn(55) &
DataIn(56) & DataIn(60) & DataIn(61) & DataIn(62) & DataIn(63) ;
-- 18 + 17 = 35
---------------------------------------------------------------------------
-- 3 <= 4 5 6 7 8 9 10 18 19 20 21 22 23 24 25
-- 33 34 35 36 37 38 39 40 49 50 51 52 53 54 55 56
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) &
DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) & DataIn(38) & DataIn(39) &
DataIn(40) & DataIn(49) & DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) &
DataIn(55) & DataIn(56) ;
-- 15 + 16 = 31
---------------------------------------------------------------------------
-- 4 <= 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
-- 41-56
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) &
DataIn(41) & DataIn(42) & DataIn(43) & DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) &
DataIn(48) & DataIn(49) & DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) &
DataIn(55) & DataIn(56) ;
-- 15 + 16 = 31
---------------------------------------------------------------------------
-- 5 <= 26 - 31
-- 32 - 56
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31) &
DataIn(32) & DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) &
DataIn(38) & DataIn(39) & DataIn(40) & DataIn(41) & DataIn(42) & DataIn(43) &
DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) & DataIn(48) & DataIn(49) &
DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) & DataIn(55) &
DataIn(56) ;
-- 18 + 13 = 31
---------------------------------------------------------------------------
-- New additional checkbit for 64-bit data
-- 6 <= 57 - 63
data_chk6 <= DataIn(57) & DataIn(58) & DataIn(59) & DataIn(60) & DataIn(61) & DataIn(62) &
DataIn(63) ;
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
-- signal data_chk0_i : std_logic_vector(0 to 17);
-- signal data_chk0_xor : std_logic;
-- signal data_chk0_i_xor : std_logic;
-- signal data_chk1_i : std_logic_vector(0 to 17);
-- signal data_chk1_xor : std_logic;
-- signal data_chk1_i_xor : std_logic;
-- signal data_chk2_i : std_logic_vector(0 to 17);
-- signal data_chk2_xor : std_logic;
-- signal data_chk2_i_xor : std_logic;
-- signal data_chk3_i : std_logic_vector(0 to 17);
-- signal data_chk3_xor : std_logic;
-- signal data_chk3_i_xor : std_logic;
-- signal data_chk4_i : std_logic_vector(0 to 17);
-- signal data_chk4_xor : std_logic;
-- signal data_chk4_i_xor : std_logic;
-- signal data_chk5_i : std_logic_vector(0 to 17);
-- signal data_chk5_xor : std_logic;
-- signal data_chk5_i_xor : std_logic;
-- signal data_chk6_i : std_logic;
-- signal data_chk0_xor_reg : std_logic;
-- signal data_chk0_i_xor_reg : std_logic;
-- signal data_chk1_xor_reg : std_logic;
-- signal data_chk1_i_xor_reg : std_logic;
-- signal data_chk2_xor_reg : std_logic;
-- signal data_chk2_i_xor_reg : std_logic;
-- signal data_chk3_xor_reg : std_logic;
-- signal data_chk3_i_xor_reg : std_logic;
-- signal data_chk4_xor_reg : std_logic;
-- signal data_chk4_i_xor_reg : std_logic;
-- signal data_chk5_xor_reg : std_logic;
-- signal data_chk5_i_xor_reg : std_logic;
-- signal data_chk6_i_reg : std_logic;
-- signal data_chk7_a_xor_reg : std_logic;
-- signal data_chk7_b_xor_reg : std_logic;
-- Checkbit (0)
signal data_chk0_a : std_logic_vector (0 to 5);
signal data_chk0_b : std_logic_vector (0 to 5);
signal data_chk0_c : std_logic_vector (0 to 5);
signal data_chk0_d : std_logic_vector (0 to 5);
signal data_chk0_e : std_logic_vector (0 to 5);
signal data_chk0_f : std_logic_vector (0 to 4);
signal data_chk0_a_xor : std_logic;
signal data_chk0_b_xor : std_logic;
signal data_chk0_c_xor : std_logic;
signal data_chk0_d_xor : std_logic;
signal data_chk0_e_xor : std_logic;
signal data_chk0_f_xor : std_logic;
signal data_chk0_a_xor_reg : std_logic;
signal data_chk0_b_xor_reg : std_logic;
signal data_chk0_c_xor_reg : std_logic;
signal data_chk0_d_xor_reg : std_logic;
signal data_chk0_e_xor_reg : std_logic;
signal data_chk0_f_xor_reg : std_logic;
-- Checkbit (1)
signal data_chk1_a : std_logic_vector (0 to 5);
signal data_chk1_b : std_logic_vector (0 to 5);
signal data_chk1_c : std_logic_vector (0 to 5);
signal data_chk1_d : std_logic_vector (0 to 5);
signal data_chk1_e : std_logic_vector (0 to 5);
signal data_chk1_f : std_logic_vector (0 to 4);
signal data_chk1_a_xor : std_logic;
signal data_chk1_b_xor : std_logic;
signal data_chk1_c_xor : std_logic;
signal data_chk1_d_xor : std_logic;
signal data_chk1_e_xor : std_logic;
signal data_chk1_f_xor : std_logic;
signal data_chk1_a_xor_reg : std_logic;
signal data_chk1_b_xor_reg : std_logic;
signal data_chk1_c_xor_reg : std_logic;
signal data_chk1_d_xor_reg : std_logic;
signal data_chk1_e_xor_reg : std_logic;
signal data_chk1_f_xor_reg : std_logic;
-- Checkbit (2)
signal data_chk2_a : std_logic_vector (0 to 5);
signal data_chk2_b : std_logic_vector (0 to 5);
signal data_chk2_c : std_logic_vector (0 to 5);
signal data_chk2_d : std_logic_vector (0 to 5);
signal data_chk2_e : std_logic_vector (0 to 5);
signal data_chk2_f : std_logic_vector (0 to 4);
signal data_chk2_a_xor : std_logic;
signal data_chk2_b_xor : std_logic;
signal data_chk2_c_xor : std_logic;
signal data_chk2_d_xor : std_logic;
signal data_chk2_e_xor : std_logic;
signal data_chk2_f_xor : std_logic;
signal data_chk2_a_xor_reg : std_logic;
signal data_chk2_b_xor_reg : std_logic;
signal data_chk2_c_xor_reg : std_logic;
signal data_chk2_d_xor_reg : std_logic;
signal data_chk2_e_xor_reg : std_logic;
signal data_chk2_f_xor_reg : std_logic;
-- Checkbit (3)
signal data_chk3_a : std_logic_vector (0 to 5);
signal data_chk3_b : std_logic_vector (0 to 5);
signal data_chk3_c : std_logic_vector (0 to 5);
signal data_chk3_d : std_logic_vector (0 to 5);
signal data_chk3_e : std_logic_vector (0 to 5);
signal data_chk3_a_xor : std_logic;
signal data_chk3_b_xor : std_logic;
signal data_chk3_c_xor : std_logic;
signal data_chk3_d_xor : std_logic;
signal data_chk3_e_xor : std_logic;
signal data_chk3_f_xor : std_logic;
signal data_chk3_a_xor_reg : std_logic;
signal data_chk3_b_xor_reg : std_logic;
signal data_chk3_c_xor_reg : std_logic;
signal data_chk3_d_xor_reg : std_logic;
signal data_chk3_e_xor_reg : std_logic;
signal data_chk3_f_xor_reg : std_logic;
-- Checkbit (4)
signal data_chk4_a : std_logic_vector (0 to 5);
signal data_chk4_b : std_logic_vector (0 to 5);
signal data_chk4_c : std_logic_vector (0 to 5);
signal data_chk4_d : std_logic_vector (0 to 5);
signal data_chk4_e : std_logic_vector (0 to 5);
signal data_chk4_a_xor : std_logic;
signal data_chk4_b_xor : std_logic;
signal data_chk4_c_xor : std_logic;
signal data_chk4_d_xor : std_logic;
signal data_chk4_e_xor : std_logic;
signal data_chk4_f_xor : std_logic;
signal data_chk4_a_xor_reg : std_logic;
signal data_chk4_b_xor_reg : std_logic;
signal data_chk4_c_xor_reg : std_logic;
signal data_chk4_d_xor_reg : std_logic;
signal data_chk4_e_xor_reg : std_logic;
signal data_chk4_f_xor_reg : std_logic;
-- Checkbit (5)
signal data_chk5_a : std_logic_vector (0 to 5);
signal data_chk5_b : std_logic_vector (0 to 5);
signal data_chk5_c : std_logic_vector (0 to 5);
signal data_chk5_d : std_logic_vector (0 to 5);
signal data_chk5_e : std_logic_vector (0 to 5);
signal data_chk5_a_xor : std_logic;
signal data_chk5_b_xor : std_logic;
signal data_chk5_c_xor : std_logic;
signal data_chk5_d_xor : std_logic;
signal data_chk5_e_xor : std_logic;
signal data_chk5_f_xor : std_logic;
signal data_chk5_a_xor_reg : std_logic;
signal data_chk5_b_xor_reg : std_logic;
signal data_chk5_c_xor_reg : std_logic;
signal data_chk5_d_xor_reg : std_logic;
signal data_chk5_e_xor_reg : std_logic;
signal data_chk5_f_xor_reg : std_logic;
-- Checkbit (6)
signal data_chk6_a : std_logic;
signal data_chk6_b : std_logic;
signal data_chk6_a_reg : std_logic;
signal data_chk6_b_reg : std_logic;
-- Checkbit (7)
signal data_chk7_a : std_logic_vector (0 to 5);
signal data_chk7_b : std_logic_vector (0 to 5);
signal data_chk7_c : std_logic_vector (0 to 5);
signal data_chk7_d : std_logic_vector (0 to 5);
signal data_chk7_e : std_logic_vector (0 to 5);
signal data_chk7_f : std_logic_vector (0 to 4);
signal data_chk7_a_xor : std_logic;
signal data_chk7_b_xor : std_logic;
signal data_chk7_c_xor : std_logic;
signal data_chk7_d_xor : std_logic;
signal data_chk7_e_xor : std_logic;
signal data_chk7_f_xor : std_logic;
signal data_chk7_a_xor_reg : std_logic;
signal data_chk7_b_xor_reg : std_logic;
signal data_chk7_c_xor_reg : std_logic;
signal data_chk7_d_xor_reg : std_logic;
signal data_chk7_e_xor_reg : std_logic;
signal data_chk7_f_xor_reg : std_logic;
begin
-----------------------------------------------------------------------------
-- For timing improvements, if check bit XOR logic
-- needs to be pipelined. Add register level here
-- after 1st LUT level.
REG_BITS : if (C_REG) generate
begin
REG_CHK: process (Clk)
begin
if (Clk'event and Clk = '1' ) then
-- Checkbit (0)
-- data_chk0_xor_reg <= data_chk0_xor;
-- data_chk0_i_xor_reg <= data_chk0_i_xor;
data_chk0_a_xor_reg <= data_chk0_a_xor;
data_chk0_b_xor_reg <= data_chk0_b_xor;
data_chk0_c_xor_reg <= data_chk0_c_xor;
data_chk0_d_xor_reg <= data_chk0_d_xor;
data_chk0_e_xor_reg <= data_chk0_e_xor;
data_chk0_f_xor_reg <= data_chk0_f_xor;
-- Checkbit (1)
-- data_chk1_xor_reg <= data_chk1_xor;
-- data_chk1_i_xor_reg <= data_chk1_i_xor;
data_chk1_a_xor_reg <= data_chk1_a_xor;
data_chk1_b_xor_reg <= data_chk1_b_xor;
data_chk1_c_xor_reg <= data_chk1_c_xor;
data_chk1_d_xor_reg <= data_chk1_d_xor;
data_chk1_e_xor_reg <= data_chk1_e_xor;
data_chk1_f_xor_reg <= data_chk1_f_xor;
-- Checkbit (2)
-- data_chk2_xor_reg <= data_chk2_xor;
-- data_chk2_i_xor_reg <= data_chk2_i_xor;
data_chk2_a_xor_reg <= data_chk2_a_xor;
data_chk2_b_xor_reg <= data_chk2_b_xor;
data_chk2_c_xor_reg <= data_chk2_c_xor;
data_chk2_d_xor_reg <= data_chk2_d_xor;
data_chk2_e_xor_reg <= data_chk2_e_xor;
data_chk2_f_xor_reg <= data_chk2_f_xor;
-- Checkbit (3)
-- data_chk3_xor_reg <= data_chk3_xor;
-- data_chk3_i_xor_reg <= data_chk3_i_xor;
data_chk3_a_xor_reg <= data_chk3_a_xor;
data_chk3_b_xor_reg <= data_chk3_b_xor;
data_chk3_c_xor_reg <= data_chk3_c_xor;
data_chk3_d_xor_reg <= data_chk3_d_xor;
data_chk3_e_xor_reg <= data_chk3_e_xor;
data_chk3_f_xor_reg <= data_chk3_f_xor;
-- Checkbit (4)
-- data_chk4_xor_reg <= data_chk4_xor;
-- data_chk4_i_xor_reg <= data_chk4_i_xor;
data_chk4_a_xor_reg <= data_chk4_a_xor;
data_chk4_b_xor_reg <= data_chk4_b_xor;
data_chk4_c_xor_reg <= data_chk4_c_xor;
data_chk4_d_xor_reg <= data_chk4_d_xor;
data_chk4_e_xor_reg <= data_chk4_e_xor;
data_chk4_f_xor_reg <= data_chk4_f_xor;
-- Checkbit (5)
-- data_chk5_xor_reg <= data_chk5_xor;
-- data_chk5_i_xor_reg <= data_chk5_i_xor;
data_chk5_a_xor_reg <= data_chk5_a_xor;
data_chk5_b_xor_reg <= data_chk5_b_xor;
data_chk5_c_xor_reg <= data_chk5_c_xor;
data_chk5_d_xor_reg <= data_chk5_d_xor;
data_chk5_e_xor_reg <= data_chk5_e_xor;
data_chk5_f_xor_reg <= data_chk5_f_xor;
-- Checkbit (6)
-- data_chk6_i_reg <= data_chk6_i;
data_chk6_a_reg <= data_chk6_a;
data_chk6_b_reg <= data_chk6_b;
-- Checkbit (7)
-- data_chk7_a_xor_reg <= data_chk7_a_xor;
-- data_chk7_b_xor_reg <= data_chk7_b_xor;
data_chk7_a_xor_reg <= data_chk7_a_xor;
data_chk7_b_xor_reg <= data_chk7_b_xor;
data_chk7_c_xor_reg <= data_chk7_c_xor;
data_chk7_d_xor_reg <= data_chk7_d_xor;
data_chk7_e_xor_reg <= data_chk7_e_xor;
data_chk7_f_xor_reg <= data_chk7_f_xor;
end if;
end process REG_CHK;
-- Perform the last XOR after the register stage
-- CheckOut(0) <= data_chk0_xor_reg xor data_chk0_i_xor_reg;
CheckOut(0) <= data_chk0_a_xor_reg xor
data_chk0_b_xor_reg xor
data_chk0_c_xor_reg xor
data_chk0_d_xor_reg xor
data_chk0_e_xor_reg xor
data_chk0_f_xor_reg;
-- CheckOut(1) <= data_chk1_xor_reg xor data_chk1_i_xor_reg;
CheckOut(1) <= data_chk1_a_xor_reg xor
data_chk1_b_xor_reg xor
data_chk1_c_xor_reg xor
data_chk1_d_xor_reg xor
data_chk1_e_xor_reg xor
data_chk1_f_xor_reg;
-- CheckOut(2) <= data_chk2_xor_reg xor data_chk2_i_xor_reg;
CheckOut(2) <= data_chk2_a_xor_reg xor
data_chk2_b_xor_reg xor
data_chk2_c_xor_reg xor
data_chk2_d_xor_reg xor
data_chk2_e_xor_reg xor
data_chk2_f_xor_reg;
-- CheckOut(3) <= data_chk3_xor_reg xor data_chk3_i_xor_reg;
CheckOut(3) <= data_chk3_a_xor_reg xor
data_chk3_b_xor_reg xor
data_chk3_c_xor_reg xor
data_chk3_d_xor_reg xor
data_chk3_e_xor_reg xor
data_chk3_f_xor_reg;
-- CheckOut(4) <= data_chk4_xor_reg xor data_chk4_i_xor_reg;
CheckOut(4) <= data_chk4_a_xor_reg xor
data_chk4_b_xor_reg xor
data_chk4_c_xor_reg xor
data_chk4_d_xor_reg xor
data_chk4_e_xor_reg xor
data_chk4_f_xor_reg;
-- CheckOut(5) <= data_chk5_xor_reg xor data_chk5_i_xor_reg;
CheckOut(5) <= data_chk5_a_xor_reg xor
data_chk5_b_xor_reg xor
data_chk5_c_xor_reg xor
data_chk5_d_xor_reg xor
data_chk5_e_xor_reg xor
data_chk5_f_xor_reg;
-- CheckOut(6) <= data_chk6_i_reg;
CheckOut(6) <= data_chk6_a_reg xor data_chk6_b_reg;
-- CheckOut(7) <= data_chk7_a_xor_reg xor data_chk7_b_xor_reg;
CheckOut(7) <= data_chk7_a_xor_reg xor
data_chk7_b_xor_reg xor
data_chk7_c_xor_reg xor
data_chk7_d_xor_reg xor
data_chk7_e_xor_reg xor
data_chk7_f_xor_reg;
end generate REG_BITS;
NO_REG_BITS: if (not C_REG) generate
begin
-- CheckOut(0) <= data_chk0_xor xor data_chk0_i_xor;
CheckOut(0) <= data_chk0_a_xor xor
data_chk0_b_xor xor
data_chk0_c_xor xor
data_chk0_d_xor xor
data_chk0_e_xor xor
data_chk0_f_xor;
-- CheckOut(1) <= data_chk1_xor xor data_chk1_i_xor;
CheckOut(1) <= data_chk1_a_xor xor
data_chk1_b_xor xor
data_chk1_c_xor xor
data_chk1_d_xor xor
data_chk1_e_xor xor
data_chk1_f_xor;
-- CheckOut(2) <= data_chk2_xor xor data_chk2_i_xor;
CheckOut(2) <= data_chk2_a_xor xor
data_chk2_b_xor xor
data_chk2_c_xor xor
data_chk2_d_xor xor
data_chk2_e_xor xor
data_chk2_f_xor;
-- CheckOut(3) <= data_chk3_xor xor data_chk3_i_xor;
CheckOut(3) <= data_chk3_a_xor xor
data_chk3_b_xor xor
data_chk3_c_xor xor
data_chk3_d_xor xor
data_chk3_e_xor xor
data_chk3_f_xor;
-- CheckOut(4) <= data_chk4_xor xor data_chk4_i_xor;
CheckOut(4) <= data_chk4_a_xor xor
data_chk4_b_xor xor