Skip to content

Instantly share code, notes, and snippets.

@promach promach/.gitignore
Last active Mar 31, 2020

Embed
What would you like to do?
AXI4 verilog coding for interfacing with DDR AXI controller
#sby results
load_data_from_bram_prf/
load_data_from_bram_cvr/
#yosys synthesis result
load_data_from_bram.json
`define LOOPBACK 1
module address_generator(clk, reset,
i_axi_awready, o_axi_awid, o_axi_awaddr, o_axi_awlen, o_axi_awsize, o_axi_awburst,
o_axi_awlock, o_axi_awcache, o_axi_awprot, o_axi_awqos, o_axi_awvalid,
i_axi_wready, o_axi_wdata, o_axi_wstrb, o_axi_wlast, o_axi_wvalid,
i_axi_bid, i_axi_bresp, i_axi_bvalid, o_axi_bready,
i_axi_arready, o_axi_arid, o_axi_araddr, o_axi_arlen, o_axi_arsize, o_axi_arburst,
o_axi_arlock, o_axi_arcache, o_axi_arprot, o_axi_arqos, o_axi_arvalid,
i_axi_rid, i_axi_rresp, i_axi_rvalid, i_axi_rdata, i_axi_rlast, o_axi_rready); // An axi master that generates DDR address for the slave DDR axi controller
parameter TILE_LENGTH = 10; // a tile is symmetrical, so TILE_LENGTH = TILE_WIDTH
parameter MAX_J = 10;
parameter MAX_K = 10;
parameter N = 4; // number of input feature maps
parameter n = 1; // input feature map index (just to identify map)
parameter Tn = 4; // number of tiles for input feature maps (divide and conquer due to resource limits)
`ifdef FORMAL
parameter r = 8; // FEATURE_SIZE_WIDTH
parameter c = 8; // FEATURE_SIZE_HEIGHT
`else
parameter r = 256; // FEATURE_SIZE_WIDTH
parameter c = 256; // FEATURE_SIZE_HEIGHT
`endif
parameter IDX_N_WIDTH = ($clog2(N*TILE_LENGTH*TILE_LENGTH));
parameter IDX_R_WIDTH = ($clog2((r+MAX_J)*TILE_LENGTH));
parameter IDX_K_WIDTH = ($clog2(c+MAX_K));
parameter Tn_WIDTH = $clog2(Tn);
parameter r_WIDTH = $clog2(r);
// AXI Address width (log wordsize) for DDR
parameter C_AXI_ADDR_WIDTH = ((IDX_N_WIDTH >= IDX_R_WIDTH) && (IDX_N_WIDTH >= IDX_K_WIDTH)) ?
IDX_N_WIDTH :
(IDX_R_WIDTH >= IDX_K_WIDTH) ? IDX_R_WIDTH : IDX_K_WIDTH;
`ifdef FORMAL
parameter C_AXI_DATA_WIDTH = 8; // related to AxSIZE
parameter C_SIZE_OF_CACHE = 4; // for storing weights and biases parameters of neural network
`else
parameter C_AXI_DATA_WIDTH = 128; // related to AxSIZE
parameter C_SIZE_OF_CACHE = 64; // for storing weights and biases parameters of neural network
`endif
parameter C_AXI_ID_WIDTH = 1;
localparam NUM_OF_BITS_PER_BYTES = 8;
localparam INCR_BURST_TYPE = 2'b01; // AxBURST[2:0] , see 'burst type' section in AXI spec
// AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers.
// Support for all other burst types in AXI4 remains at 1 to 16 transfers.
// for wrapping bursts, the burst length must be 2, 4, 8, or 16
// a burst must not cross a 4KB address boundary
// early termination of bursts is not supported
localparam MAX_BURST_LENGTH = 255;
localparam BURST_SIZE_ENCODING_WIDTH = 3; // AxSIZE[2:0] , see 'burst size' section in AXI spec
localparam SUBWORD_SMALLEST_UNIT = 8; // smallest granularity in AXI protocol : 8 bit
localparam PROT_BITWIDTH = 3;
localparam QOS_BITWIDTH = 4;
localparam CACHE_BITWIDTH = 4;
input clk, reset;
// AXI write address channel signals
input wire i_axi_awready; // Slave is ready to accept
output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid; // Write ID
output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr; // Write address
output wire [$clog2(MAX_BURST_LENGTH)-1:0] o_axi_awlen; // Write Burst Length
output wire [BURST_SIZE_ENCODING_WIDTH-1:0] o_axi_awsize; // Write Burst size
output wire [1:0] o_axi_awburst; // Write Burst type
output wire [0:0] o_axi_awlock; // Write lock type
output wire [CACHE_BITWIDTH-1:0] o_axi_awcache; // Write Cache type
output wire [PROT_BITWIDTH-1:0] o_axi_awprot; // Write Protection type
output wire [QOS_BITWIDTH-1:0] o_axi_awqos; // Write Quality of Svc
output reg o_axi_awvalid; // Write address valid
// AXI write data channel signals
input wire i_axi_wready; // Write data ready
output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata; // Write data
output reg [C_AXI_DATA_WIDTH/SUBWORD_SMALLEST_UNIT-1:0] o_axi_wstrb; // Write strobes
output reg o_axi_wlast; // Last write transaction
output reg o_axi_wvalid; // Write valid
// AXI write response channel signals
/* verilator lint_off UNUSED */
input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid; // Response ID
/* verilator lint_on UNUSED */
input wire [1:0] i_axi_bresp; // Write response
input wire i_axi_bvalid; // Write reponse valid
output wire o_axi_bready; // Response ready
// AXI read address channel signals
input wire i_axi_arready; // Read address ready
output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid; // Read ID
output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr; // Read address
output wire [$clog2(MAX_BURST_LENGTH)-1:0] o_axi_arlen; // Read Burst Length
output wire [BURST_SIZE_ENCODING_WIDTH-1:0] o_axi_arsize; // Read Burst size
output wire [1:0] o_axi_arburst; // Read Burst type
output wire [0:0] o_axi_arlock; // Read lock type
output wire [CACHE_BITWIDTH-1:0] o_axi_arcache; // Read Cache type
output wire [PROT_BITWIDTH-1:0] o_axi_arprot; // Read Protection type
output wire [QOS_BITWIDTH-1:0] o_axi_arqos; // Read Quality of Svc
output reg o_axi_arvalid; // Read address valid
/* verilator lint_off UNUSED */
// AXI read data channel signals
input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid; // Response ID
/* verilator lint_on UNUSED */
input wire [1:0] i_axi_rresp; // Read response
input wire i_axi_rvalid; // Read reponse valid
input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata; // Read data
input wire i_axi_rlast; // Read last
output wire o_axi_rready; // Read Response ready
always @(posedge clk)
begin
if(reset) o_axi_wstrb <= 0;
// burst alignment mechanism, see https://i.imgur.com/jKbzfFo.png
// o_axi_wstrb <= (~0) << (o_axi_awaddr % (o_axi_awlen+1));
// all the bracket variables are for removing verilator width warnings
else o_axi_wstrb <= ((~0) << (o_axi_awaddr %
{{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}},
(o_axi_awlen+1'b1)}));
end
wire write_response_is_ok = i_axi_bvalid && ((i_axi_bresp == 'b00) || (i_axi_bresp == 'b01));
// need to implement data re-transmission
wire write_response_is_not_ok = i_axi_bvalid && !((i_axi_bresp == 'b00) || (i_axi_bresp == 'b01));
always @(posedge clk)
begin
if(reset)
begin
o_axi_wvalid <= 0;
end
else if(!(o_axi_wvalid && !i_axi_wready))
begin
// Note that both o_axi_awsize , o_axi_awlen are of hardware constants, so no multiply hardware
// since this is for testing, WDATA just uses some values up to the total size of the write address space
// Note: a master must not wait for AWREADY to be asserted before driving WVALID
o_axi_wvalid <= (o_axi_wlast) ? 0 :
(o_axi_wdata < (o_axi_awsize*o_axi_awlen));
end
end
wire ddr_write_address_range_is_valid = (o_axi_awaddr < (1 << C_AXI_ADDR_WIDTH));
always @(posedge clk)
begin
if(reset) o_axi_awvalid <= 0;
// AXI specification: A3.3.1 Dependencies between channel handshake signal
// the VALID signal of the AXI interface sending information must not be dependent on
// the READY signal of the AXI interface receiving that information
// this is to prevent deadlock
// since AXI slave could wait for i_axi_awvalid to be true before setting o_axi_awready true.
// Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
// Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
// VALID signal needs to be set (initially) independent of READY signal,
// and then only ever adjusted if !(VALID && !READY)
// Note: the master must not wait for the slave to assert AWREADY before asserting AWVALID
// Note: (!(o_axi_awvalid && !i_axi_awready)) == (!awvalid || awready)
// == (!awvalid || (awvalid && awready)).
// it means "no transaction in progress or transaction accepted"
else if(!(o_axi_awvalid && !i_axi_awready))
o_axi_awvalid <= /*i_axi_awready &&*/ (ddr_write_address_range_is_valid);
end
wire write_transaction_is_accepted = (o_axi_wvalid) && (i_axi_wready);
wire address_write_transaction_is_accepted = (o_axi_awvalid) && (i_axi_awready);
always @(posedge clk)
begin
if(reset)
begin
o_axi_awaddr <= 0;
//o_axi_wdata <= 0;
end
else if(address_write_transaction_is_accepted)
begin
o_axi_awaddr <= o_axi_awaddr +
{{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, (o_axi_awlen+1'b1)};
//o_axi_wdata <= o_axi_wdata + 1;
end
end
always @(posedge clk)
begin
if(reset)
begin
//o_axi_awaddr <= 0;
o_axi_wdata <= 0;
end
else if(write_transaction_is_accepted)
begin
//o_axi_awaddr <= o_axi_awaddr + 1;
o_axi_wdata <= o_axi_wdata + 1;
end
end
`ifdef LOOPBACK
wire data_had_been_written_successfully = write_response_is_ok && o_axi_bready;
wire read_address_contains_loopback_data = data_had_been_written_successfully &&
(o_axi_awaddr >= (idx_n + idx_r + idx_k + {{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, o_axi_awlen}));
`endif
wire not_yet_the_end_of_neural_network_addresses =
(idx_n + idx_r + idx_k) < ((N * TILE_LENGTH * TILE_LENGTH) +
((r + MAX_J) * TILE_LENGTH) +
(c + MAX_K));
always @(posedge clk)
begin
if(reset) o_axi_arvalid <= 0;
// AXI specification: A3.3.1 Dependencies between channel handshake signal
// the VALID signal of the AXI interface sending information must not be dependent on
// the READY signal of the AXI interface receiving that information
// this is to prevent deadlock
// since AXI slave could wait for i_axi_arvalid to be true before setting o_axi_arready true.
// Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
// Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
// VALID signal needs to be set (initially) independent of READY signal,
// and then only ever adjusted if !(VALID && !READY)
// Note: the master must not wait for the slave to assert ARREADY before asserting ARVALID
// Note: (!(o_axi_arvalid && !i_axi_arready)) == (!arvalid || arready)
// == (!arvalid || (arvalid && arready)).
// it means "no transaction in progress or transaction accepted"
else if(!(o_axi_arvalid && !i_axi_arready))
`ifdef LOOPBACK
o_axi_arvalid <= /*i_axi_arready &&*/ (not_yet_the_end_of_neural_network_addresses) &&
(read_address_contains_loopback_data) &&
(o_axi_bready && i_axi_bvalid && write_response_is_ok);
`else
o_axi_arvalid <= /*i_axi_arready &&*/ (not_yet_the_end_of_neural_network_addresses);
`endif
end
reg [$clog2(MAX_BURST_LENGTH)-1:0] num_of_write_transactions;
always @(posedge clk)
begin
if(reset) num_of_write_transactions <= 0;
else if(o_axi_wvalid && i_axi_wready)
num_of_write_transactions <= (o_axi_wlast) ? 0 : num_of_write_transactions + 1;
end
always @(posedge clk)
begin
if(reset) o_axi_wlast <= 0;
else o_axi_wlast <= (num_of_write_transactions == (o_axi_awlen - 1));
end
//assign o_axi_wlast = 0;
assign o_axi_awid = 0;
assign o_axi_awlen = 15; // each burst has (Burst_Length = AxLEN[7:0] + 1) data transfers
/* verilator lint_off WIDTH */
assign o_axi_awsize = $clog2(C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES); // 128 bits (16 bytes) of data when AxSIZE[2:0] = 3'b100
// Burst_Length = AxLEN[7:0] + 1, to accommodate the extended burst length of the INCR burst type in AXI4.
/* verilator lint_on WIDTH */
assign o_axi_awburst = INCR_BURST_TYPE;
assign o_axi_awlock = 0;
assign o_axi_awcache = 0;
assign o_axi_awprot = 0;
assign o_axi_awqos = 0; // no priority or QoS concept
assign o_axi_arqos = 0; // no priority or QoS concept
assign o_axi_arburst = INCR_BURST_TYPE;
/* verilator lint_off WIDTH */
assign o_axi_arsize = $clog2(C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES); // 128 bits (16 bytes) of data when AxSIZE[2:0] = 3'b100
// Burst_Length = AxLEN[7:0] + 1, to accommodate the extended burst length of the INCR burst type in AXI4.
/* verilator lint_on WIDTH */
assign o_axi_arlen = 15; // each burst has (Burst_Length = AxLEN[7:0] + 1) data transfers
assign o_axi_arprot = 3'b010; // {data access, non-secure access, unprivileged access}
assign o_axi_arlock = 0; // AXI4 does not support locked transactions.
assign o_axi_arcache = 0; // mostly used for HPS (hard processor system) such as ARM hard CPU IP
assign o_axi_arid = 0; // there is one AXI slave which is the DDR memory (A, B, or C) ?
// what situations will render data requester (AXI master) busy to receive read response ??
// such as AXI interconnect where arbitration will fail to acquire the data transfer priority
// such as the internal cache storage to store the data from external DDR memory is now full
// So, let's use a random value that is $anyseq in formal verification
assign o_axi_rready = (reset) ? 1 : `ifdef FORMAL $anyseq `else (!cache_is_full) `endif;
// The master can assert BREADY before BVALID is asserted.
assign o_axi_bready = (reset) ? 1 : `ifdef FORMAL $anyseq `else (i_axi_bvalid) `endif;
wire address_read_transaction_is_accepted = (o_axi_arvalid) && (i_axi_arready);
always @(posedge clk)
begin
if(reset) o_axi_araddr <= 0;
else if(address_read_transaction_is_accepted)
o_axi_araddr <= idx_n + idx_r + idx_k; // the DDR address to read data from
end
// used for generating address (o_axi_araddr) indexes
reg [C_AXI_ADDR_WIDTH-1:0] idx_n;
reg [C_AXI_ADDR_WIDTH-1:0] idx_r;
reg [C_AXI_ADDR_WIDTH-1:0] idx_k;
wire not_max_limit_of_idx_n = idx_n < (N * TILE_LENGTH * TILE_LENGTH);
wire not_max_limit_of_idx_r = idx_r < ((r + MAX_J) * TILE_LENGTH);
wire not_max_limit_of_idx_k = idx_k < (c + MAX_K);
localparam NUM_OF_INCREMENT_STATES = 3;
localparam STATE_N = 1;
localparam STATE_R = 2;
localparam STATE_K = 3;
reg [$clog2(NUM_OF_INCREMENT_STATES)-1:0] increment_states;
reg [$clog2(NUM_OF_INCREMENT_STATES)-1:0] previous_increment_states;
always @(posedge clk) previous_increment_states <= increment_states;
// no multiply in actual synthesized hardware since
// 'N', 'n', 'Tn', 'r', 'MAX_J' and 'TILE_LENGTH' are constants
always @(posedge clk)
begin
if(reset)
begin
increment_states <= STATE_N;
idx_n <= n * TILE_LENGTH * TILE_LENGTH;
idx_r <= r * TILE_LENGTH;
idx_k <= c;
end
else if(address_read_transaction_is_accepted) begin
case(increment_states)
STATE_N:
begin
if(not_max_limit_of_idx_n)
begin
increment_states <= STATE_K;
idx_k <= idx_k + 1;
if(previous_increment_states == STATE_R)
idx_n <= idx_n + Tn * TILE_LENGTH * TILE_LENGTH;
end
else increment_states <= STATE_N;
end
STATE_R:
begin
if(not_max_limit_of_idx_r)
begin
increment_states <= STATE_K;
idx_k <= idx_k + 1;
if(previous_increment_states == STATE_K)
idx_r <= idx_r + TILE_LENGTH;
end
else begin
increment_states <= STATE_N;
idx_r <= r * TILE_LENGTH;
end
end
STATE_K:
begin
if(not_max_limit_of_idx_k)
begin
increment_states <= STATE_K;
idx_k <= idx_k + 1;
end
else begin
increment_states <= STATE_R;
idx_k <= c;
end
end
default:
begin
increment_states <= STATE_N;
idx_n <= n * TILE_LENGTH * TILE_LENGTH;
idx_r <= r * TILE_LENGTH;
idx_k <= c;
end
endcase
end
end
/* verilator lint_off UNUSED */
wire arm_write_feature_enable;
wire [C_AXI_DATA_WIDTH-1:0] arm_write_feature_data;
wire cache_is_empty;
wire [$clog2(C_SIZE_OF_CACHE)-1:0] cache_address_for_reading;
assign cache_address_for_reading = 0; // for testing only
/* verilator lint_on UNUSED */
wire valid_read_response_does_not_contain_error_messages = i_axi_rvalid && (i_axi_rresp == 0);
wire cache_is_full; // needed since C_SIZE_OF_CACHE is always smaller than SIZE_OF_DDR_MEMORY
// for storing neural network parameters (weights and biases) at destination side,
// so this bram acts as intermediate cache (much smaller size than DDR memory) for the neural network
// no need AXI protocol in order to save logic usage, thus lesser area and power consumption
cache_controller #(.C_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_SIZE_OF_CACHE(C_SIZE_OF_CACHE)) nn_features_cache
(
.clk(clk), .reset(reset),
.i_data(i_axi_rdata), // NN params coming from DDR memory
.i_data_is_valid
((o_axi_rready && valid_read_response_does_not_contain_error_messages)), // DDR data is valid
.i_addr(cache_address_for_reading),
.full(cache_is_full), // NN params cache is full
.o_data(arm_write_feature_data), // NN params going to neural network layers
.o_data_is_valid(arm_write_feature_enable), // neural network layers to start another intermediate computations
.empty(cache_is_empty) // no NN params to feed into the neural network layers
);
`ifdef FORMAL
initial assume(reset);
reg first_clock_had_passed = 0;
always @(posedge clk) first_clock_had_passed <= 1;
always @(posedge clk)
if(first_clock_had_passed)
cover((o_axi_araddr != 0) && transaction_is_accepted && $past(i_axi_arready) &&
$past(o_axi_rready) && !o_axi_rready);
`endif
endmodule
module bram_axi_controller(clk, reset,
o_axi_awready, i_axi_awid, i_axi_awaddr, i_axi_awlen, i_axi_awsize, i_axi_awburst,
i_axi_awlock, i_axi_awcache, i_axi_awprot, i_axi_awqos, i_axi_awvalid,
o_axi_wready, i_axi_wdata, i_axi_wstrb, i_axi_wlast, i_axi_wvalid,
o_axi_bid, o_axi_bresp, o_axi_bvalid, i_axi_bready,
o_axi_arready, i_axi_arid, i_axi_araddr, i_axi_arlen, i_axi_arsize, i_axi_arburst,
i_axi_arlock, i_axi_arcache, i_axi_arprot, i_axi_arqos, i_axi_arvalid,
o_axi_rid, o_axi_rresp, o_axi_rvalid, o_axi_rdata, o_axi_rlast, i_axi_rready);
input clk, reset;
parameter TILE_LENGTH = 10; // a tile is symmetrical, so TILE_LENGTH = TILE_WIDTH
parameter MAX_J = 10;
parameter MAX_K = 10;
parameter N = 4; // number of input feature maps
parameter n = 1; // input feature map index (just to identify map)
parameter Tn = 4; // number of tiles for input feature maps (divide and conquer due to resource limits)
`ifdef FORMAL
parameter r = 8; // FEATURE_SIZE_WIDTH
parameter c = 8; // FEATURE_SIZE_HEIGHT
`else
parameter r = 256; // FEATURE_SIZE_WIDTH
parameter c = 256; // FEATURE_SIZE_HEIGHT
`endif
parameter IDX_N_WIDTH = ($clog2(N*TILE_LENGTH*TILE_LENGTH));
parameter IDX_R_WIDTH = ($clog2((r+MAX_J)*TILE_LENGTH));
parameter IDX_K_WIDTH = ($clog2(c+MAX_K));
// AXI Address width (log wordsize) for DDR
parameter C_AXI_ADDR_WIDTH = ((IDX_N_WIDTH >= IDX_R_WIDTH) && (IDX_N_WIDTH >= IDX_K_WIDTH)) ?
IDX_N_WIDTH :
(IDX_R_WIDTH >= IDX_K_WIDTH) ? IDX_R_WIDTH : IDX_K_WIDTH;
`ifdef FORMAL
parameter C_AXI_DATA_WIDTH = 8; // related to AxSIZE
`else
parameter C_AXI_DATA_WIDTH = 128; // related to AxSIZE
`endif
parameter C_AXI_ID_WIDTH = 1;
parameter SIZE_OF_DDR_MEMORY = (1 << C_AXI_ADDR_WIDTH);
localparam INCR_BURST_TYPE = 2'b01; // AxBURST[2:0] , see 'burst type' section in AXI spec
// AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers.
// Support for all other burst types in AXI4 remains at 1 to 16 transfers.
// for wrapping bursts, the burst length must be 2, 4, 8, or 16
// a burst must not cross a 4KB address boundary
// early termination of bursts is not supported
localparam MAX_BURST_LENGTH = 255;
localparam BURST_SIZE_ENCODING_WIDTH = 3; // AxSIZE[2:0] , see 'burst size' section in AXI spec
localparam SUBWORD_SMALLEST_UNIT = 8; // smallest granularity in AXI protocol : 8 bit
localparam PROT_BITWIDTH = 3;
localparam QOS_BITWIDTH = 4;
localparam CACHE_BITWIDTH = 4;
/* verilator lint_off UNUSED */
// AXI write address channel signals
output wire o_axi_awready; // Slave is ready to accept
input wire [C_AXI_ID_WIDTH-1:0] i_axi_awid; // Write ID
input wire [C_AXI_ADDR_WIDTH-1:0] i_axi_awaddr; // Write address
input wire [$clog2(MAX_BURST_LENGTH)-1:0] i_axi_awlen; // Write Burst Length
input wire [BURST_SIZE_ENCODING_WIDTH-1:0] i_axi_awsize; // Write Burst size
input wire [1:0] i_axi_awburst; // Write Burst type
input wire [0:0] i_axi_awlock; // Write lock type
input wire [CACHE_BITWIDTH-1:0] i_axi_awcache; // Write Cache type
input wire [PROT_BITWIDTH-1:0] i_axi_awprot; // Write Protection type
input wire [QOS_BITWIDTH-1:0] i_axi_awqos; // Write Quality of Svc
input wire i_axi_awvalid; // Write address valid
// AXI write data channel signals
output wire o_axi_wready; // Write data ready
input wire [C_AXI_DATA_WIDTH-1:0] i_axi_wdata; // Write data
input wire [C_AXI_DATA_WIDTH/SUBWORD_SMALLEST_UNIT-1:0] i_axi_wstrb; // Write strobes
input wire i_axi_wlast; // Last write transaction
input wire i_axi_wvalid; // Write valid
// AXI write response channel signals
output wire [C_AXI_ID_WIDTH-1:0] o_axi_bid; // Response ID
output wire [1:0] o_axi_bresp; // Write response
output wire o_axi_bvalid; // Write reponse valid
input wire i_axi_bready; // Response ready
/* verilator lint_on UNUSED */
// AXI read address channel signals
output reg o_axi_arready; // Read address ready
input [C_AXI_ADDR_WIDTH-1:0] i_axi_araddr; // Read address
/* verilator lint_off UNUSED */
input wire [C_AXI_ID_WIDTH-1:0] i_axi_arid; // Read ID
input wire [$clog2(MAX_BURST_LENGTH)-1:0] i_axi_arlen; // Read Burst Length
input wire [BURST_SIZE_ENCODING_WIDTH-1:0] i_axi_arsize; // Read Burst size
input wire [1:0] i_axi_arburst; // Read Burst type
input wire [0:0] i_axi_arlock; // Read lock type
input wire [CACHE_BITWIDTH-1:0] i_axi_arcache; // Read Cache type
input wire [PROT_BITWIDTH-1:0] i_axi_arprot; // Read Protection type
input wire [QOS_BITWIDTH-1:0] i_axi_arqos; // Read Quality of Svc
/* verilator lint_on UNUSED */
input wire i_axi_arvalid; // Read address valid
// AXI read data channel signals
output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid; // Response ID
output wire [1:0] o_axi_rresp; // Read response
output reg o_axi_rvalid; // Read reponse valid
output reg [C_AXI_DATA_WIDTH-1:0] o_axi_rdata; // Read data
output wire o_axi_rlast; // Read last
input wire i_axi_rready; // Read Response ready
/*no data writing into DDR*/
assign o_axi_awready = 0;
assign o_axi_wready = 0;
assign o_axi_bid = 0;
assign o_axi_bresp = 0;
assign o_axi_bvalid = 0;
/*no data writing into DDR*/
// assign o_axi_arready = (reset) ? 0 : 1; // I suppose DDR memory hardware has periodic precharging ?
assign o_axi_rid = 0;
assign o_axi_rresp = 0; // normal access success, I do not foresee any slave error OR decode error
reg [$clog2(MAX_BURST_LENGTH)-1:0] num_of_data_sent;
always @(posedge clk)
begin
if(reset) num_of_data_sent <= 0;
else if(o_axi_rvalid) num_of_data_sent <= (o_axi_rlast) ? 1: num_of_data_sent + 1;
end
assign o_axi_rlast = (i_axi_arlen == 0) ? 1 : ((num_of_data_sent-1) == i_axi_arlen);
// According to 'Read transaction dependencies' in section A3.3.1 of AXI spec,
// ARREADY and ARVALID must be of clocked-reg type
always @(posedge clk)
begin
if(reset) o_axi_arready <= 1;
// I suppose DDR memory hardware has periodic precharging and auto-refresh operations
// that renders DDR memory to be not ready for accepting new read address input ?
// So, let's use a random value that is $anyseq in formal verification
`ifdef FORMAL
else o_axi_arready <= $anyseq;
`else
else o_axi_arready <= 1;
`endif
end
reg [C_AXI_DATA_WIDTH-1:0] mem [SIZE_OF_DDR_MEMORY-1:0]; // in Xilinx vivado, this infers BRAM
always @(posedge clk)
begin
if(reset) o_axi_rdata <= 0;
// the following assumes that (i_axi_arlen = 0) && (i_axi_arsize = C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES)
// If (i_axi_arlen = 0), then value of i_axi_arburst does not matter at all
// memory data is read out correctly one clock cycle after data request
// memory data is valid only when requested with valid read address
else if(!(o_axi_rvalid && !i_axi_rready)) o_axi_rdata <= skid_output_data;
end
always @(posedge clk)
begin
if(reset) o_axi_rvalid <= 0;
// AXI specification: A3.3.1 Dependencies between channel handshake signal
// the VALID signal of the AXI interface sending information must not be dependent on
// the READY signal of the AXI interface receiving that information
// this is to prevent deadlock
// since AXI slave could wait for i_axi_arvalid to be true before setting o_axi_arready true.
// Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
// Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
// VALID signal needs to be set (initially) independent of READY signal,
// and then only ever adjusted if !(VALID && !READY)
// Note: the slave must not wait for the master to assert RREADY before asserting RVALID
// Note: (!(o_axi_rvalid && !i_axi_rready)) == (!rvalid || rready)
// == (!rvalid || (rvalid && rready)).
// it means "no transaction in progress or transaction accepted"
// Note: the slave must wait for both ARVALID and ARREADY to be asserted before
// it asserts RVALID to indicate that valid data is available
else if(!(o_axi_rvalid && !i_axi_rready))
o_axi_rvalid <= i_axi_arvalid && o_axi_arready;
end
genvar mem_index;
generate // BRAM data initialization
for(mem_index = 0; mem_index < SIZE_OF_DDR_MEMORY; mem_index = mem_index + 1)
begin
always @(posedge clk)
begin
if(reset) mem[mem_index] <= 0;
else mem[mem_index] <= mem_index;
end
end
endgenerate
// as of why skid buffer size is designed to be '1', see https://i.imgur.com/SQ0ucA4.png and
// Note the cycle difference between o_axi_rvalid and o_axi_rready
// thus the number of o_axi_rdata (d2) being dropped if there is no buffer to store d2
localparam SKID_BUFFER_SIZE = 2;
reg skid_buffer_is_enabled;
wire enable_skid_buffer;
wire [C_AXI_DATA_WIDTH-1:0] skid_input_data = mem[i_axi_araddr];
wire [C_AXI_DATA_WIDTH-1:0] skid_output_data;
wire skid_buffer_is_full;
wire skid_buffer_is_empty;
always @(posedge clk)
begin
if(reset) skid_buffer_is_enabled <= 0;
else skid_buffer_is_enabled <= enable_skid_buffer;
end
skid_buffer #(.WIDTH(C_AXI_DATA_WIDTH), .SIZE(SKID_BUFFER_SIZE)) skid_param
(
.clk(clk), .reset(reset),
.full(skid_buffer_is_full), .enqueue_en(enable_skid_buffer), .enqueue_value(skid_input_data),
.empty(skid_buffer_is_empty), .dequeue_en(i_axi_rready), .dequeue_value(skid_output_data)
);
endmodule
module cache_controller(clk, reset, i_addr, i_data, o_data, i_data_is_valid, o_data_is_valid, full, empty);
`ifdef FORMAL
parameter C_DATA_WIDTH = 8;
parameter C_SIZE_OF_CACHE = 4;
`else
parameter C_DATA_WIDTH = 128;
parameter C_SIZE_OF_CACHE = 64;
`endif
input clk, reset;
input i_data_is_valid; // input data is valid
input [C_DATA_WIDTH-1:0] i_data;
input [$clog2(C_SIZE_OF_CACHE)-1:0] i_addr; // address for reading cache content
output full;
output empty;
output reg o_data_is_valid; // output data is valid
output reg [C_DATA_WIDTH-1:0] o_data;
reg [C_DATA_WIDTH-1:0] cache [C_SIZE_OF_CACHE-1:0]; // in Xilinx vivado, this infers BRAM
reg [$clog2(C_SIZE_OF_CACHE)-1:0] cache_index;
localparam INTEGER_BITWIDTH = 32;
integer cache_entry_index; // address for writing cache content
always @(posedge clk)
begin
if(reset)
begin
cache_index <= 0;
for(cache_entry_index = 0; cache_entry_index < C_SIZE_OF_CACHE;
cache_entry_index = cache_entry_index + 1)
begin
`ifdef FORMAL
cache[cache_entry_index] <= cache_entry_index[C_DATA_WIDTH-1:0]; // acts as random initialization
`else
cache[cache_entry_index] <= {{(C_DATA_WIDTH-INTEGER_BITWIDTH){1'b0}}, cache_entry_index}; // acts as random initialization
`endif
end
end
else if(i_data_is_valid && !full)
begin
cache[cache_index] <= i_data;
cache_index <= cache_index + 1;
end
end
always @(posedge clk)
begin
if(reset)
begin
o_data <= 0;
o_data_is_valid <= 0;
end
else if(!empty)
begin
o_data <= cache[i_addr];
o_data_is_valid <= 1;
end
end
localparam SKID_BUFFER_BACKPRESSURE_SPACE = 1;
assign empty = (reset) ? 1 : (cache_index == 0);
assign full = (reset) ? 0 : (cache_index == (C_SIZE_OF_CACHE[$clog2(C_SIZE_OF_CACHE)-1:0]-1));
endmodule
[tasks]
prf
cvr
[options]
prf: mode prove
prf: depth 26
cvr: mode cover
cvr: depth 40
cvr: append 13
[engines]
smtbmc
[script]
read -formal load_data_from_bram.v
read -formal read_instructions.v
read -formal address_generator.v
read -formal cache_controller.v
read -formal bram_axi_controller.v
read -formal skid_buffer.v
prep -top load_data_from_bram
[files]
load_data_from_bram.v
read_instructions.v
address_generator.v
cache_controller.v
bram_axi_controller.v
skid_buffer.v
//`define XILINX 1
`define LOOPBACK 1
`define AXI_VIP 1
module load_data_from_bram(clk, reset, done, error);
input clk, reset;
output reg [1:0] done;
output reg [1:0] error;
parameter TILE_LENGTH = 10; // a tile is symmetrical, so TILE_LENGTH = TILE_WIDTH
parameter MAX_J = 10;
parameter MAX_K = 10;
parameter N = 4; // number of input feature maps
parameter n = 1; // input feature map index (just to identify map)
parameter Tn = 4; // number of tiles for input feature maps (divide and conquer due to resource limits)
`ifdef FORMAL
parameter r = 8; // FEATURE_SIZE_WIDTH
parameter c = 8; // FEATURE_SIZE_HEIGHT
`else
parameter r = 256; // FEATURE_SIZE_WIDTH
parameter c = 256; // FEATURE_SIZE_HEIGHT
`endif
parameter IDX_N_WIDTH = ($clog2(N*TILE_LENGTH*TILE_LENGTH));
parameter IDX_R_WIDTH = ($clog2((r+MAX_J)*TILE_LENGTH));
parameter IDX_K_WIDTH = ($clog2(c+MAX_K));
// AXI Address width (log wordsize) for DDR memory storing features
parameter C_AXI_ADDR_WIDTH = ((IDX_N_WIDTH >= IDX_R_WIDTH) && (IDX_N_WIDTH >= IDX_K_WIDTH)) ?
IDX_N_WIDTH :
(IDX_R_WIDTH >= IDX_K_WIDTH) ? IDX_R_WIDTH : IDX_K_WIDTH;
`ifdef FORMAL
parameter C_AXI_DATA_WIDTH = 8; // related to AxSIZE
parameter C_SIZE_OF_CACHE = 4; // for storing weights and biases parameters of neural network
`else
parameter C_AXI_DATA_WIDTH = 128; // related to AxSIZE
parameter C_SIZE_OF_CACHE = 64; // for storing weights and biases parameters of neural network
`endif
parameter C_AXI_ID_WIDTH = 1;
parameter SIZE_OF_DDR_MEMORY = (1 << C_AXI_ADDR_WIDTH);
localparam INCR_BURST_TYPE = 2'b01; // AxBURST[2:0] , see 'burst type' section in AXI spec
// AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers.
// Support for all other burst types in AXI4 remains at 1 to 16 transfers.
// for wrapping bursts, the burst length must be 2, 4, 8, or 16
// a burst must not cross a 4KB address boundary
// early termination of bursts is not supported
localparam MAX_BURST_LENGTH = 255;
localparam BURST_SIZE_ENCODING_WIDTH = 3; // AxSIZE[2:0] , see 'burst size' section in AXI spec
localparam SUBWORD_SMALLEST_UNIT = 8; // smallest granularity in AXI protocol : 8 bit
localparam PROT_BITWIDTH = 3;
localparam QOS_BITWIDTH = 4;
localparam CACHE_BITWIDTH = 4;
/* verilator lint_off UNUSED */
// AXI write address channel signals
wire axi_awready[1:0]; // Slave is ready to accept
wire [C_AXI_ID_WIDTH-1:0] axi_awid[1:0]; // Write ID
wire [C_AXI_ADDR_WIDTH-1:0] axi_awaddr[1:0]; // Write address
wire [$clog2(MAX_BURST_LENGTH)-1:0] axi_awlen[1:0]; // Write Burst Length
wire [BURST_SIZE_ENCODING_WIDTH-1:0] axi_awsize[1:0]; // Write Burst size
wire [1:0] axi_awburst[1:0]; // Write Burst type
wire [0:0] axi_awlock[1:0]; // Write lock type
wire [CACHE_BITWIDTH-1:0] axi_awcache[1:0]; // Write Cache type
wire [PROT_BITWIDTH-1:0] axi_awprot[1:0]; // Write Protection type
wire [QOS_BITWIDTH-1:0] axi_awqos[1:0]; // Write Quality of Svc
wire axi_awvalid[1:0]; // Write address valid
// AXI write data channel signals
wire axi_wready[1:0]; // Write data ready
wire [C_AXI_DATA_WIDTH-1:0] axi_wdata[1:0]; // Write data
wire [C_AXI_DATA_WIDTH/SUBWORD_SMALLEST_UNIT-1:0] axi_wstrb[1:0]; // Write strobes
wire axi_wlast[1:0]; // Last write transaction
wire axi_wvalid[1:0]; // Write valid
// AXI write response channel signals
wire [C_AXI_ID_WIDTH-1:0] axi_bid[1:0]; // Response ID
wire [1:0] axi_bresp[1:0]; // Write response
wire axi_bvalid[1:0]; // Write reponse valid
wire axi_bready[1:0]; // Response ready
/* verilator lint_on UNUSED */
// AXI read address channel signals
wire axi_arready[1:0]; // Read address ready
wire [C_AXI_ID_WIDTH-1:0] axi_arid[1:0]; // Read ID
wire [C_AXI_ADDR_WIDTH-1:0] axi_araddr[1:0]; // Read address
wire [$clog2(MAX_BURST_LENGTH)-1:0] axi_arlen[1:0]; // Read Burst Length
wire [BURST_SIZE_ENCODING_WIDTH-1:0] axi_arsize[1:0]; // Read Burst size
wire [1:0] axi_arburst[1:0]; // Read Burst type
wire [0:0] axi_arlock[1:0]; // Read lock type
wire [CACHE_BITWIDTH-1:0] axi_arcache[1:0]; // Read Cache type
wire [PROT_BITWIDTH-1:0] axi_arprot[1:0]; // Read Protection type
wire [QOS_BITWIDTH-1:0] axi_arqos[1:0]; // Read Quality of Svc
wire axi_arvalid[1:0]; // Read address valid
// AXI read data channel signals
wire [C_AXI_ID_WIDTH-1:0] axi_rid[1:0]; // Response ID
wire [1:0] axi_rresp[1:0]; // Read response
wire axi_rvalid[1:0]; // Read reponse valid
wire [C_AXI_DATA_WIDTH-1:0] axi_rdata[1:0]; // Read data
wire axi_rlast[1:0]; // Read last
wire axi_rready[1:0]; // Read Response ready
`ifdef XILINX
// https://www.xilinx.com/products/intellectual-property/axi_protocol_checker.html
// We have two AXI protocol checkers IP to verify the AXI transactions correctness
// of two DDR axi controllers
localparam PC_STATUS_BITWIDTH = 160;
wire [PC_STATUS_BITWIDTH-1:0] pc_status [1:0];
wire [1:0] pc_asserted;
axi_protocol_checker_0 axi_pc0(
.pc_status(pc_status[0]),
.pc_asserted(pc_asserted[0]),
.aclk(clk),
.aresetn(!reset),
.pc_axi_awaddr(axi_awaddr[0]),
.pc_axi_awlen(axi_awlen[0]),
.pc_axi_awsize(axi_awsize[0]),
.pc_axi_awburst(axi_awburst[0]),
.pc_axi_awlock(axi_awlock[0]),
.pc_axi_awcache(axi_awcache[0]),
.pc_axi_awprot(axi_awprot[0]),
.pc_axi_awqos(axi_awqos[0]),
.pc_axi_awregion(0), // not used
.pc_axi_awvalid(axi_awvalid[0]),
.pc_axi_awready(axi_awready[0]),
.pc_axi_wlast(axi_wlast[0]),
.pc_axi_wdata(axi_wdata[0]),
.pc_axi_wstrb(axi_wstrb[0]),
.pc_axi_wvalid(axi_wvalid[0]),
.pc_axi_wready(axi_wready[0]),
.pc_axi_bresp(axi_bresp[0]),
.pc_axi_bvalid(axi_bvalid[0]),
.pc_axi_bready(axi_bready[0]),
.pc_axi_araddr(axi_araddr[0]),
.pc_axi_arlen(axi_arlen[0]),
.pc_axi_arsize(axi_arsize[0]),
.pc_axi_arburst(axi_arburst[0]),
.pc_axi_arlock(axi_arlock[0]),
.pc_axi_arcache(axi_arcache[0]),
.pc_axi_arprot(axi_arprot[0]),
.pc_axi_arqos(axi_arqos[0]),
.pc_axi_arregion(0), // not used
.pc_axi_arvalid(axi_arvalid[0]),
.pc_axi_arready(axi_arready[0]),
.pc_axi_rlast(axi_rlast[0]),
.pc_axi_rdata(axi_rdata[0]),
.pc_axi_rresp(axi_rresp[0]),
.pc_axi_rvalid(axi_rvalid[0]),
.pc_axi_rready(axi_rready[0])
);
axi_protocol_checker_1 axi_pc1(
.pc_status(pc_status[1]),
.pc_asserted(pc_asserted[1]),
.aclk(clk),
.aresetn(!reset),
.pc_axi_awaddr(axi_awaddr[1]),
.pc_axi_awlen(axi_awlen[1]),
.pc_axi_awsize(axi_awsize[1]),
.pc_axi_awburst(axi_awburst[1]),
.pc_axi_awlock(axi_awlock[1]),
.pc_axi_awcache(axi_awcache[1]),
.pc_axi_awprot(axi_awprot[1]),
.pc_axi_awqos(axi_awqos[1]),
.pc_axi_awregion(1), // not used
.pc_axi_awvalid(axi_awvalid[1]),
.pc_axi_awready(axi_awready[1]),
.pc_axi_wlast(axi_wlast[1]),
.pc_axi_wdata(axi_wdata[1]),
.pc_axi_wstrb(axi_wstrb[1]),
.pc_axi_wvalid(axi_wvalid[1]),
.pc_axi_wready(axi_wready[1]),
.pc_axi_bresp(axi_bresp[1]),
.pc_axi_bvalid(axi_bvalid[1]),
.pc_axi_bready(axi_bready[1]),
.pc_axi_araddr(axi_araddr[1]),
.pc_axi_arlen(axi_arlen[1]),
.pc_axi_arsize(axi_arsize[1]),
.pc_axi_arburst(axi_arburst[1]),
.pc_axi_arlock(axi_arlock[1]),
.pc_axi_arcache(axi_arcache[1]),
.pc_axi_arprot(axi_arprot[1]),
.pc_axi_arqos(axi_arqos[1]),
.pc_axi_arregion(1), // not used
.pc_axi_arvalid(axi_arvalid[1]),
.pc_axi_arready(axi_arready[1]),
.pc_axi_rlast(axi_rlast[1]),
.pc_axi_rdata(axi_rdata[1]),
.pc_axi_rresp(axi_rresp[1]),
.pc_axi_rvalid(axi_rvalid[1]),
.pc_axi_rready(axi_rready[1])
);
`endif
// there is no need of address generator logic for hard-coded instructions
// (we have fixed DSP block, similar to overlay which is a smaller version of CPU)
read_instructions #(.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH)) hardcoded_nn_params
(
.clk(clk), .reset(reset),
.i_axi_awready(axi_awready[0]), .o_axi_awid(axi_awid[0]), .o_axi_awaddr(axi_awaddr[0]),
.o_axi_awlen(axi_awlen[0]), .o_axi_awsize(axi_awsize[0]), .o_axi_awburst(axi_awburst[0]),
.o_axi_awlock(axi_awlock[0]), .o_axi_awcache(axi_awcache[0]), .o_axi_awprot(axi_awprot[0]),
.o_axi_awqos(axi_awqos[0]), .o_axi_awvalid(axi_awvalid[0]), .i_axi_wready(axi_wready[0]),
.o_axi_wdata(axi_wdata[0]), .o_axi_wstrb(axi_wstrb[0]), .o_axi_wlast(axi_wlast[0]),
.o_axi_wvalid(axi_wvalid[0]), .i_axi_bid(axi_bid[0]), .i_axi_bresp(axi_bresp[0]),
.i_axi_bvalid(axi_bvalid[0]), .o_axi_bready(axi_bready[0]), .i_axi_arready(axi_arready[0]),
.o_axi_arid(axi_arid[0]), .o_axi_araddr(axi_araddr[0]), .o_axi_arlen(axi_arlen[0]),
.o_axi_arsize(axi_arsize[0]), .o_axi_arburst(axi_arburst[0]), .o_axi_arlock(axi_arlock[0]),
.o_axi_arcache(axi_arcache[0]), .o_axi_arprot(axi_arprot[0]), .o_axi_arqos(axi_arqos[0]),
.o_axi_arvalid(axi_arvalid[0]), .i_axi_rid(axi_rid[0]), .i_axi_rresp(axi_rresp[0]),
.i_axi_rvalid(axi_rvalid[0]), .i_axi_rdata(axi_rdata[0]), .i_axi_rlast(axi_rlast[0]),
.o_axi_rready(axi_rready[0])
);
address_generator #(.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH)) addr_gen_nn_features
(
.clk(clk), .reset(reset),
.i_axi_awready(axi_awready[1]), .o_axi_awid(axi_awid[1]), .o_axi_awaddr(axi_awaddr[1]),
.o_axi_awlen(axi_awlen[1]), .o_axi_awsize(axi_awsize[1]), .o_axi_awburst(axi_awburst[1]),
.o_axi_awlock(axi_awlock[1]), .o_axi_awcache(axi_awcache[1]), .o_axi_awprot(axi_awprot[1]),
.o_axi_awqos(axi_awqos[1]), .o_axi_awvalid(axi_awvalid[1]), .i_axi_wready(axi_wready[1]),
.o_axi_wdata(axi_wdata[1]), .o_axi_wstrb(axi_wstrb[1]), .o_axi_wlast(axi_wlast[1]),
.o_axi_wvalid(axi_wvalid[1]), .i_axi_bid(axi_bid[1]), .i_axi_bresp(axi_bresp[1]),
.i_axi_bvalid(axi_bvalid[1]), .o_axi_bready(axi_bready[1]), .i_axi_arready(axi_arready[1]),
.o_axi_arid(axi_arid[1]), .o_axi_araddr(axi_araddr[1]), .o_axi_arlen(axi_arlen[1]),
.o_axi_arsize(axi_arsize[1]), .o_axi_arburst(axi_arburst[1]), .o_axi_arlock(axi_arlock[1]),
.o_axi_arcache(axi_arcache[1]), .o_axi_arprot(axi_arprot[1]), .o_axi_arqos(axi_arqos[1]),
.o_axi_arvalid(axi_arvalid[1]), .i_axi_rid(axi_rid[1]), .i_axi_rresp(axi_rresp[1]),
.i_axi_rvalid(axi_rvalid[1]), .i_axi_rdata(axi_rdata[1]), .i_axi_rlast(axi_rlast[1]),
.o_axi_rready(axi_rready[1])
);
// since we store features and NN params in two separate external DDR memory,
// we need two separate DDR axi controllers
// for storing NN params at source side (the source is a DDR memory device which is accessible using AXI)
`ifdef XILINX
`ifdef AXI_VIP
axi_vip_0 vip_nn_params(
.aclk(clk),
.aresetn(!reset),
.s_axi_awid(axi_awid[0]),
.s_axi_awaddr(axi_awaddr[0]),
.s_axi_awlen(axi_awlen[0]),
.s_axi_awsize(axi_awsize[0]),
.s_axi_awburst(axi_awburst[0]),
.s_axi_awlock(axi_awlock[0]),
.s_axi_awcache(axi_awcache[0]),
.s_axi_awprot(axi_awprot[0]),
.s_axi_awvalid(axi_awvalid[0]),
.s_axi_awready(axi_awready[0]),
.s_axi_wdata(axi_wdata[0]),
.s_axi_wstrb(axi_wstrb[0]),
.s_axi_wlast(axi_wlast[0]),
.s_axi_wvalid(axi_wvalid[0]),
.s_axi_wready(axi_wready[0]),
.s_axi_bid(axi_bid[0]),
.s_axi_bresp(axi_bresp[0]),
.s_axi_bvalid(axi_bvalid[0]),
.s_axi_bready(axi_bready[0]),
.s_axi_arid(axi_arid[0]),
.s_axi_araddr(axi_araddr[0]),
.s_axi_arlen(axi_arlen[0]),
.s_axi_arsize(axi_arsize[0]),
.s_axi_arburst(axi_arburst[0]),
.s_axi_arlock(axi_arlock[0]),
.s_axi_arcache(axi_arcache[0]),
.s_axi_arprot(axi_arprot[0]),
.s_axi_arvalid(axi_arvalid[0]),
.s_axi_arready(axi_arready[0]),
.s_axi_rid(axi_rid[0]),
.s_axi_rdata(axi_rdata[0]),
.s_axi_rresp(axi_rresp[0]),
.s_axi_rlast(axi_rlast[0]),
.s_axi_rvalid(axi_rvalid[0]),
.s_axi_rready(axi_rready[0])
);
`else
axi_bram_ctrl_0 ddr_nn_params(
.s_axi_aclk(clk),
.s_axi_aresetn(!reset),
.s_axi_awid(axi_awid[0]),
.s_axi_awaddr(axi_awaddr[0]),
.s_axi_awlen(axi_awlen[0]),
.s_axi_awsize(axi_awsize[0]),
.s_axi_awburst(axi_awburst[0]),
.s_axi_awlock(axi_awlock[0]),
.s_axi_awcache(axi_awcache[0]),
.s_axi_awprot(axi_awprot[0]),
.s_axi_awvalid(axi_awvalid[0]),
.s_axi_awready(axi_awready[0]),
.s_axi_wdata(axi_wdata[0]),
.s_axi_wstrb(axi_wstrb[0]),
.s_axi_wlast(axi_wlast[0]),
.s_axi_wvalid(axi_wvalid[0]),
.s_axi_wready(axi_wready[0]),
.s_axi_bid(axi_bid[0]),
.s_axi_bresp(axi_bresp[0]),
.s_axi_bvalid(axi_bvalid[0]),
.s_axi_bready(axi_bready[0]),
.s_axi_arid(axi_arid[0]),
.s_axi_araddr(axi_araddr[0]),
.s_axi_arlen(axi_arlen[0]),
.s_axi_arsize(axi_arsize[0]),
.s_axi_arburst(axi_arburst[0]),
.s_axi_arlock(axi_arlock[0]),
.s_axi_arcache(axi_arcache[0]),
.s_axi_arprot(axi_arprot[0]),
.s_axi_arvalid(axi_arvalid[0]),
.s_axi_arready(axi_arready[0]),
.s_axi_rid(axi_rid[0]),
.s_axi_rdata(axi_rdata[0]),
.s_axi_rresp(axi_rresp[0]),
.s_axi_rlast(axi_rlast[0]),
.s_axi_rvalid(axi_rvalid[0]),
.s_axi_rready(axi_rready[0])
);
`endif
axi_bram_ctrl_1 ddr_nn_features(
.s_axi_aclk(clk),
.s_axi_aresetn(!reset),
.s_axi_awid(axi_awid[1]),
.s_axi_awaddr(axi_awaddr[1]),
.s_axi_awlen(axi_awlen[1]),
.s_axi_awsize(axi_awsize[1]),
.s_axi_awburst(axi_awburst[1]),
.s_axi_awlock(axi_awlock[1]),
.s_axi_awcache(axi_awcache[1]),
.s_axi_awprot(axi_awprot[1]),
.s_axi_awvalid(axi_awvalid[1]),
.s_axi_awready(axi_awready[1]),
.s_axi_wdata(axi_wdata[1]),
.s_axi_wstrb(axi_wstrb[1]),
.s_axi_wlast(axi_wlast[1]),
.s_axi_wvalid(axi_wvalid[1]),
.s_axi_wready(axi_wready[1]),
.s_axi_bid(axi_bid[1]),
.s_axi_bresp(axi_bresp[1]),
.s_axi_bvalid(axi_bvalid[1]),
.s_axi_bready(axi_bready[1]),
.s_axi_arid(axi_arid[1]),
.s_axi_araddr(axi_araddr[1]),
.s_axi_arlen(axi_arlen[1]),
.s_axi_arsize(axi_arsize[1]),
.s_axi_arburst(axi_arburst[1]),
.s_axi_arlock(axi_arlock[1]),
.s_axi_arcache(axi_arcache[1]),
.s_axi_arprot(axi_arprot[1]),
.s_axi_arvalid(axi_arvalid[1]),
.s_axi_arready(axi_arready[1]),
.s_axi_rid(axi_rid[1]),
.s_axi_rdata(axi_rdata[1]),
.s_axi_rresp(axi_rresp[1]),
.s_axi_rlast(axi_rlast[1]),
.s_axi_rvalid(axi_rvalid[1]),
.s_axi_rready(axi_rready[1])
);
`else
bram_axi_controller #(.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH)) ddr_nn_params
(
.clk(clk), .reset(reset),
.o_axi_awready(axi_awready[0]), .i_axi_awid(axi_awid[0]), .i_axi_awaddr(axi_awaddr[0]),
.i_axi_awlen(axi_awlen[0]), .i_axi_awsize(axi_awsize[0]), .i_axi_awburst(axi_awburst[0]),
.i_axi_awlock(axi_awlock[0]), .i_axi_awcache(axi_awcache[0]), .i_axi_awprot(axi_awprot[0]),
.i_axi_awqos(axi_awqos[0]), .i_axi_awvalid(axi_awvalid[0]), .o_axi_wready(axi_wready[0]),
.i_axi_wdata(axi_wdata[0]), .i_axi_wstrb(axi_wstrb[0]), .i_axi_wlast(axi_wlast[0]),
.i_axi_wvalid(axi_wvalid[0]), .o_axi_bid(axi_bid[0]), .o_axi_bresp(axi_bresp[0]),
.o_axi_bvalid(axi_bvalid[0]), .i_axi_bready(axi_bready[0]), .o_axi_arready(axi_arready[0]),
.i_axi_arid(axi_arid[0]), .i_axi_araddr(axi_araddr[0]), .i_axi_arlen(axi_arlen[0]),
.i_axi_arsize(axi_arsize[0]), .i_axi_arburst(axi_arburst[0]), .i_axi_arlock(axi_arlock[0]),
.i_axi_arcache(axi_arcache[0]), .i_axi_arprot(axi_arprot[0]), .i_axi_arqos(axi_arqos[0]),
.i_axi_arvalid(axi_arvalid[0]), .o_axi_rid(axi_rid[0]), .o_axi_rresp(axi_rresp[0]),
.o_axi_rvalid(axi_rvalid[0]), .o_axi_rdata(axi_rdata[0]), .o_axi_rlast(axi_rlast[0]),
.i_axi_rready(axi_rready[0])
);
// for storing features at source side (the source is a DDR memory device which is accessible using AXI)
bram_axi_controller #(.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH)) ddr_nn_features
(
.clk(clk), .reset(reset),
.o_axi_awready(axi_awready[1]), .i_axi_awid(axi_awid[1]), .i_axi_awaddr(axi_awaddr[1]),
.i_axi_awlen(axi_awlen[1]), .i_axi_awsize(axi_awsize[1]), .i_axi_awburst(axi_awburst[1]),
.i_axi_awlock(axi_awlock[1]), .i_axi_awcache(axi_awcache[1]), .i_axi_awprot(axi_awprot[1]),
.i_axi_awqos(axi_awqos[1]), .i_axi_awvalid(axi_awvalid[1]), .o_axi_wready(axi_wready[1]),
.i_axi_wdata(axi_wdata[1]), .i_axi_wstrb(axi_wstrb[1]), .i_axi_wlast(axi_wlast[1]),
.i_axi_wvalid(axi_wvalid[1]), .o_axi_bid(axi_bid[1]), .o_axi_bresp(axi_bresp[1]),
.o_axi_bvalid(axi_bvalid[1]), .i_axi_bready(axi_bready[1]), .o_axi_arready(axi_arready[1]),
.i_axi_arid(axi_arid[1]), .i_axi_araddr(axi_araddr[1]), .i_axi_arlen(axi_arlen[1]),
.i_axi_arsize(axi_arsize[1]), .i_axi_arburst(axi_arburst[1]), .i_axi_arlock(axi_arlock[1]),
.i_axi_arcache(axi_arcache[1]), .i_axi_arprot(axi_arprot[1]), .i_axi_arqos(axi_arqos[1]),
.i_axi_arvalid(axi_arvalid[1]), .o_axi_rid(axi_rid[1]), .o_axi_rresp(axi_rresp[1]),
.o_axi_rvalid(axi_rvalid[1]), .o_axi_rdata(axi_rdata[1]), .o_axi_rlast(axi_rlast[1]),
.i_axi_rready(axi_rready[1])
);
`endif
// each read transaction only read one particular piece of data at one unique, non-consecutive address
reg [$clog2(SIZE_OF_DDR_MEMORY)-1:0] num_of_bram_data_read_transaction [1:0];
wire valid_read_response_contains_error_messages [1:0];
assign valid_read_response_contains_error_messages[0] = (axi_rvalid[0] && (axi_rresp[0] != 0));
assign valid_read_response_contains_error_messages[1] = (axi_rvalid[1] && (axi_rresp[1] != 0));
genvar axi_interface_number;
generate
for(axi_interface_number = 0; axi_interface_number <= 1;
axi_interface_number = axi_interface_number + 1)
begin: bram_data_read_transaction
always @(posedge clk)
begin
if(reset) num_of_bram_data_read_transaction[axi_interface_number] <= 0;
else if(axi_rvalid[axi_interface_number] && (axi_rresp[axi_interface_number] == 0))
num_of_bram_data_read_transaction[axi_interface_number] <=
num_of_bram_data_read_transaction[axi_interface_number] + 1;
end
always @(posedge clk)
begin
if(reset) error[axi_interface_number] <= 0;
else error[axi_interface_number] <=
((valid_read_response_contains_error_messages[axi_interface_number])
`ifdef XILINX
| (pc_asserted[axi_interface_number])
`endif
);
end
always @(posedge clk)
begin
if(reset) done[axi_interface_number] <= 0;
else if(num_of_bram_data_read_transaction[axi_interface_number] == SIZE_OF_DDR_MEMORY-1)
done[axi_interface_number] <= 1;
end
end
endgenerate
endmodule
read_verilog load_data_from_bram.v
read_verilog read_instructions.v
read_verilog address_generator.v
read_verilog cache_controller.v
read_verilog bram_axi_controller.v
synth_ice40 -flatten -top load_data_from_bram -json load_data_from_bram.json
abc -g NAND
ltp t:SB_DFF* %n
stat
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Tue Mar 3 09:00:41 2020
[*]
[dumpfile] "/home/chengfei/Downloads/Open-Dnn/in_buf_load/load_data_from_bram_cvr/engine_0/trace10.vcd"
[dumpfile_mtime] "Tue Mar 3 08:52:25 2020"
[dumpfile_size] 497679
[savefile] "/home/chengfei/Downloads/Open-Dnn/in_buf_load/load_data_from_bram_cover.gtkw"
[timestart] 0
[size] 1920 1004
[pos] -1 -1
*-4.920879 100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 43
[signals_width] 662
[sst_expanded] 0
[sst_vpaned_height] 152
@28
smt_clock
@420
smt_step
@28
load_data_from_bram.addr_gen_nn_features.cache_is_full
load_data_from_bram.addr_gen_nn_features.clk
load_data_from_bram.addr_gen_nn_features.first_clock_had_passed
@29
load_data_from_bram.addr_gen_nn_features.i_axi_arready
@28
load_data_from_bram.addr_gen_nn_features.i_axi_awready
load_data_from_bram.addr_gen_nn_features.i_axi_bid
load_data_from_bram.addr_gen_nn_features.i_axi_bresp[1:0]
load_data_from_bram.addr_gen_nn_features.i_axi_bvalid
@23
load_data_from_bram.addr_gen_nn_features.i_axi_rdata[7:0]
@28
load_data_from_bram.addr_gen_nn_features.i_axi_rid
load_data_from_bram.addr_gen_nn_features.i_axi_rlast
load_data_from_bram.addr_gen_nn_features.i_axi_rresp[1:0]
@29
load_data_from_bram.addr_gen_nn_features.i_axi_rvalid
@28
load_data_from_bram.addr_gen_nn_features.i_axi_wready
@22
load_data_from_bram.addr_gen_nn_features.idx_k[8:0]
load_data_from_bram.addr_gen_nn_features.idx_n[8:0]
load_data_from_bram.addr_gen_nn_features.idx_r[8:0]
@23
load_data_from_bram.addr_gen_nn_features.o_axi_araddr[8:0]
@28
load_data_from_bram.addr_gen_nn_features.o_axi_arburst[1:0]
@22
load_data_from_bram.addr_gen_nn_features.o_axi_arcache[3:0]
@28
load_data_from_bram.addr_gen_nn_features.o_axi_arid
@22
load_data_from_bram.addr_gen_nn_features.o_axi_arlen[7:0]
@28
load_data_from_bram.addr_gen_nn_features.o_axi_arlock
load_data_from_bram.addr_gen_nn_features.o_axi_arprot[2:0]
@22
load_data_from_bram.addr_gen_nn_features.o_axi_arqos[3:0]
@28
load_data_from_bram.addr_gen_nn_features.o_axi_arsize[2:0]
@29
load_data_from_bram.addr_gen_nn_features.o_axi_arvalid
@22
load_data_from_bram.addr_gen_nn_features.o_axi_awaddr[8:0]
@28
load_data_from_bram.addr_gen_nn_features.o_axi_awburst[1:0]
@22
load_data_from_bram.addr_gen_nn_features.o_axi_awcache[3:0]
@28
load_data_from_bram.addr_gen_nn_features.o_axi_awid
@22
load_data_from_bram.addr_gen_nn_features.o_axi_awlen[7:0]
@28
load_data_from_bram.addr_gen_nn_features.o_axi_awlock
load_data_from_bram.addr_gen_nn_features.o_axi_awprot[2:0]
@22
load_data_from_bram.addr_gen_nn_features.o_axi_awqos[3:0]
@28
load_data_from_bram.addr_gen_nn_features.o_axi_awsize[2:0]
load_data_from_bram.addr_gen_nn_features.o_axi_awvalid
load_data_from_bram.addr_gen_nn_features.o_axi_bready
@29
load_data_from_bram.addr_gen_nn_features.o_axi_rready
@22
load_data_from_bram.addr_gen_nn_features.o_axi_wdata[7:0]
@28
load_data_from_bram.addr_gen_nn_features.o_axi_wlast
load_data_from_bram.addr_gen_nn_features.o_axi_wstrb
load_data_from_bram.addr_gen_nn_features.o_axi_wvalid
load_data_from_bram.addr_gen_nn_features.reset
load_data_from_bram.addr_gen_nn_features.transaction_is_accepted
@22
load_data_from_bram.arm_write_feature_data[7:0]
@28
load_data_from_bram.arm_write_feature_enable
@22
load_data_from_bram.arm_write_param_data[7:0]
@28
load_data_from_bram.arm_write_param_enable
@22
load_data_from_bram.axi_araddr<0>[8:0]
load_data_from_bram.axi_araddr<1>[8:0]
@28
load_data_from_bram.axi_arburst<0>[1:0]
load_data_from_bram.axi_arburst<1>[1:0]
@22
load_data_from_bram.axi_arcache<0>[3:0]
load_data_from_bram.axi_arcache<1>[3:0]
@28
load_data_from_bram.axi_arid<0>
load_data_from_bram.axi_arid<1>
@22
load_data_from_bram.axi_arlen<0>[7:0]
load_data_from_bram.axi_arlen<1>[7:0]
@28
load_data_from_bram.axi_arlock<0>
load_data_from_bram.axi_arlock<1>
load_data_from_bram.axi_arprot<0>[2:0]
load_data_from_bram.axi_arprot<1>[2:0]
@22
load_data_from_bram.axi_arqos<0>[3:0]
load_data_from_bram.axi_arqos<1>[3:0]
@28
load_data_from_bram.axi_arready<0>
load_data_from_bram.axi_arready<1>
load_data_from_bram.axi_arsize<0>[2:0]
load_data_from_bram.axi_arsize<1>[2:0]
load_data_from_bram.axi_arvalid<0>
load_data_from_bram.axi_arvalid<1>
@22
load_data_from_bram.axi_awaddr<0>[8:0]
load_data_from_bram.axi_awaddr<1>[8:0]
@28
load_data_from_bram.axi_awburst<0>[1:0]
load_data_from_bram.axi_awburst<1>[1:0]
@22
load_data_from_bram.axi_awcache<0>[3:0]
load_data_from_bram.axi_awcache<1>[3:0]
@28
load_data_from_bram.axi_awid<0>
load_data_from_bram.axi_awid<1>
@22
load_data_from_bram.axi_awlen<0>[7:0]
load_data_from_bram.axi_awlen<1>[7:0]
@28
load_data_from_bram.axi_awlock<0>
load_data_from_bram.axi_awlock<1>
load_data_from_bram.axi_awprot<0>[2:0]
load_data_from_bram.axi_awprot<1>[2:0]
@22
load_data_from_bram.axi_awqos<0>[3:0]
load_data_from_bram.axi_awqos<1>[3:0]
@28
load_data_from_bram.axi_awready<0>
load_data_from_bram.axi_awready<1>
load_data_from_bram.axi_awsize<0>[2:0]
load_data_from_bram.axi_awsize<1>[2:0]
load_data_from_bram.axi_awvalid<0>
load_data_from_bram.axi_awvalid<1>
load_data_from_bram.axi_bid<0>
load_data_from_bram.axi_bid<1>
load_data_from_bram.axi_bready<0>
load_data_from_bram.axi_bready<1>
load_data_from_bram.axi_bresp<0>[1:0]
load_data_from_bram.axi_bresp<1>[1:0]
load_data_from_bram.axi_bvalid<0>
load_data_from_bram.axi_bvalid<1>
@22
load_data_from_bram.axi_rdata<0>[7:0]
load_data_from_bram.axi_rdata<1>[7:0]
@28
load_data_from_bram.axi_rid<0>
load_data_from_bram.axi_rid<1>
load_data_from_bram.axi_rlast<0>
load_data_from_bram.axi_rlast<1>
load_data_from_bram.axi_rready<0>
load_data_from_bram.axi_rready<1>
load_data_from_bram.axi_rresp<0>[1:0]
load_data_from_bram.axi_rresp<1>[1:0]
load_data_from_bram.axi_rvalid<0>
load_data_from_bram.axi_rvalid<1>
@22
load_data_from_bram.axi_wdata<0>[7:0]
load_data_from_bram.axi_wdata<1>[7:0]
@28
load_data_from_bram.axi_wlast<0>
load_data_from_bram.axi_wlast<1>
load_data_from_bram.axi_wready<0>
load_data_from_bram.axi_wready<1>
load_data_from_bram.axi_wstrb<0>
load_data_from_bram.axi_wstrb<1>
load_data_from_bram.axi_wvalid<0>
load_data_from_bram.axi_wvalid<1>
load_data_from_bram.cache_address_for_reading<0>[1:0]
load_data_from_bram.cache_address_for_reading<1>[1:0]
@22
load_data_from_bram.cache_input_data<0>[7:0]
load_data_from_bram.cache_input_data<1>[7:0]
@28
load_data_from_bram.cache_is_empty[1:0]
load_data_from_bram.cache_is_full[1:0]
load_data_from_bram.clk
load_data_from_bram.ddr_nn_features.clk
@23
load_data_from_bram.ddr_nn_features.i_axi_araddr[8:0]
@28
load_data_from_bram.ddr_nn_features.i_axi_arburst[1:0]
@22
load_data_from_bram.ddr_nn_features.i_axi_arcache[3:0]
@28
load_data_from_bram.ddr_nn_features.i_axi_arid
@22
load_data_from_bram.ddr_nn_features.i_axi_arlen[7:0]
@28
load_data_from_bram.ddr_nn_features.i_axi_arlock
load_data_from_bram.ddr_nn_features.i_axi_arprot[2:0]
@22
load_data_from_bram.ddr_nn_features.i_axi_arqos[3:0]
@28
load_data_from_bram.ddr_nn_features.i_axi_arsize[2:0]
@29
load_data_from_bram.ddr_nn_features.i_axi_arvalid
@22
load_data_from_bram.ddr_nn_features.i_axi_awaddr[8:0]
@28
load_data_from_bram.ddr_nn_features.i_axi_awburst[1:0]
@22
load_data_from_bram.ddr_nn_features.i_axi_awcache[3:0]
@28
load_data_from_bram.ddr_nn_features.i_axi_awid
@22
load_data_from_bram.ddr_nn_features.i_axi_awlen[7:0]
@28
load_data_from_bram.ddr_nn_features.i_axi_awlock
load_data_from_bram.ddr_nn_features.i_axi_awprot[2:0]
@22
load_data_from_bram.ddr_nn_features.i_axi_awqos[3:0]
@28
load_data_from_bram.ddr_nn_features.i_axi_awsize[2:0]
load_data_from_bram.ddr_nn_features.i_axi_awvalid
load_data_from_bram.ddr_nn_features.i_axi_bready
@29
load_data_from_bram.ddr_nn_features.i_axi_rready
@22
load_data_from_bram.ddr_nn_features.i_axi_wdata[7:0]
@28
load_data_from_bram.ddr_nn_features.i_axi_wlast
load_data_from_bram.ddr_nn_features.i_axi_wstrb
load_data_from_bram.ddr_nn_features.i_axi_wvalid
@22
load_data_from_bram.ddr_nn_features.mem<0>[7:0]
@28
load_data_from_bram.ddr_nn_features.mem<1>
@22
load_data_from_bram.ddr_nn_features.mem<10>[3:0]
load_data_from_bram.ddr_nn_features.mem<11>[3:0]
load_data_from_bram.ddr_nn_features.mem<14>[7:0]
load_data_from_bram.ddr_nn_features.mem<15>[7:0]
load_data_from_bram.ddr_nn_features.mem<18>[7:0]
load_data_from_bram.ddr_nn_features.mem<21>[7:0]
load_data_from_bram.ddr_nn_features.mem<22>[7:0]
load_data_from_bram.ddr_nn_features.mem<23>[7:0]
load_data_from_bram.ddr_nn_features.mem<24>[7:0]
load_data_from_bram.ddr_nn_features.mem<25>[7:0]
load_data_from_bram.ddr_nn_features.mem<26>[7:0]
load_data_from_bram.ddr_nn_features.mem<28>[7:0]
load_data_from_bram.ddr_nn_features.mem<30>[7:0]
load_data_from_bram.ddr_nn_features.mem<31>[7:0]
load_data_from_bram.ddr_nn_features.mem<32>[7:0]
load_data_from_bram.ddr_nn_features.mem<34>[7:0]
load_data_from_bram.ddr_nn_features.mem<37>[7:0]
load_data_from_bram.ddr_nn_features.mem<38>[7:0]
load_data_from_bram.ddr_nn_features.mem<39>[7:0]
load_data_from_bram.ddr_nn_features.mem<40>[7:0]
load_data_from_bram.ddr_nn_features.mem<41>[7:0]
load_data_from_bram.ddr_nn_features.mem<42>[7:0]
load_data_from_bram.ddr_nn_features.mem<43>[7:0]
load_data_from_bram.ddr_nn_features.mem<44>[7:0]
load_data_from_bram.ddr_nn_features.mem<45>[7:0]
load_data_from_bram.ddr_nn_features.mem<46>[7:0]
load_data_from_bram.ddr_nn_features.mem<47>[7:0]
load_data_from_bram.ddr_nn_features.mem<48>[7:0]
load_data_from_bram.ddr_nn_features.mem<49>[7:0]
load_data_from_bram.ddr_nn_features.mem<50>[7:0]
load_data_from_bram.ddr_nn_features.mem<51>[7:0]
load_data_from_bram.ddr_nn_features.mem<52>[7:0]
load_data_from_bram.ddr_nn_features.mem<53>[7:0]
load_data_from_bram.ddr_nn_features.mem<54>[7:0]
load_data_from_bram.ddr_nn_features.mem<55>[7:0]
load_data_from_bram.ddr_nn_features.mem<60>[7:0]
load_data_from_bram.ddr_nn_features.mem<61>[7:0]
load_data_from_bram.ddr_nn_features.mem<63>[7:0]
load_data_from_bram.ddr_nn_features.mem<64>[7:0]
load_data_from_bram.ddr_nn_features.mem<65>[7:0]
load_data_from_bram.ddr_nn_features.mem<66>[7:0]
load_data_from_bram.ddr_nn_features.mem<68>[7:0]
load_data_from_bram.ddr_nn_features.mem<69>[7:0]
load_data_from_bram.ddr_nn_features.mem<70>[7:0]
load_data_from_bram.ddr_nn_features.mem<71>[7:0]
load_data_from_bram.ddr_nn_features.mem<72>[7:0]
load_data_from_bram.ddr_nn_features.mem<73>[7:0]
load_data_from_bram.ddr_nn_features.mem<74>[7:0]
load_data_from_bram.ddr_nn_features.mem<75>[7:0]
load_data_from_bram.ddr_nn_features.mem<77>[7:0]
load_data_from_bram.ddr_nn_features.mem<78>[7:0]
load_data_from_bram.ddr_nn_features.mem<79>[7:0]
load_data_from_bram.ddr_nn_features.mem<80>[7:0]
load_data_from_bram.ddr_nn_features.mem<81>[7:0]
load_data_from_bram.ddr_nn_features.mem<82>[7:0]
load_data_from_bram.ddr_nn_features.mem<83>[7:0]
load_data_from_bram.ddr_nn_features.mem<84>[7:0]
load_data_from_bram.ddr_nn_features.mem<85>[7:0]
load_data_from_bram.ddr_nn_features.mem<86>[7:0]
load_data_from_bram.ddr_nn_features.mem<87>[7:0]
load_data_from_bram.ddr_nn_features.mem<88>[7:0]
load_data_from_bram.ddr_nn_features.mem<89>[7:0]
load_data_from_bram.ddr_nn_features.mem<90>[7:0]
load_data_from_bram.ddr_nn_features.mem<91>[7:0]
load_data_from_bram.ddr_nn_features.mem<92>[7:0]
load_data_from_bram.ddr_nn_features.mem<93>[7:0]
load_data_from_bram.ddr_nn_features.mem<94>[7:0]
load_data_from_bram.ddr_nn_features.mem<95>[7:0]
load_data_from_bram.ddr_nn_features.mem<96>[7:0]
load_data_from_bram.ddr_nn_features.mem<98>[7:0]
load_data_from_bram.ddr_nn_features.mem<99>[7:0]
load_data_from_bram.ddr_nn_features.mem<100>[6:0]
load_data_from_bram.ddr_nn_features.mem<101>[6:0]
load_data_from_bram.ddr_nn_features.mem<102>[7:0]
load_data_from_bram.ddr_nn_features.mem<104>[7:0]
load_data_from_bram.ddr_nn_features.mem<106>[7:0]
load_data_from_bram.ddr_nn_features.mem<108>[7:0]
load_data_from_bram.ddr_nn_features.mem<109>[7:0]
load_data_from_bram.ddr_nn_features.mem<110>[7:0]
load_data_from_bram.ddr_nn_features.mem<111>[7:0]
load_data_from_bram.ddr_nn_features.mem<112>[7:0]
load_data_from_bram.ddr_nn_features.mem<114>[7:0]
load_data_from_bram.ddr_nn_features.mem<117>[7:0]
load_data_from_bram.ddr_nn_features.mem<118>[7:0]
load_data_from_bram.ddr_nn_features.mem<119>[7:0]
load_data_from_bram.ddr_nn_features.mem<120>[7:0]
load_data_from_bram.ddr_nn_features.mem<121>[7:0]
load_data_from_bram.ddr_nn_features.mem<122>[7:0]
load_data_from_bram.ddr_nn_features.mem<123>[7:0]
load_data_from_bram.ddr_nn_features.mem<124>[7:0]
load_data_from_bram.ddr_nn_features.mem<125>[7:0]
load_data_from_bram.ddr_nn_features.mem<126>[7:0]
load_data_from_bram.ddr_nn_features.mem<127>[7:0]
load_data_from_bram.ddr_nn_features.mem<128>[7:0]
load_data_from_bram.ddr_nn_features.mem<129>[7:0]
load_data_from_bram.ddr_nn_features.mem<130>[7:0]
load_data_from_bram.ddr_nn_features.mem<131>[7:0]
load_data_from_bram.ddr_nn_features.mem<132>[7:0]
load_data_from_bram.ddr_nn_features.mem<133>[7:0]
load_data_from_bram.ddr_nn_features.mem<134>[7:0]
load_data_from_bram.ddr_nn_features.mem<135>[7:0]
load_data_from_bram.ddr_nn_features.mem<136>[7:0]
load_data_from_bram.ddr_nn_features.mem<137>[7:0]
load_data_from_bram.ddr_nn_features.mem<138>[7:0]
load_data_from_bram.ddr_nn_features.mem<139>[7:0]
load_data_from_bram.ddr_nn_features.mem<140>[7:0]
load_data_from_bram.ddr_nn_features.mem<141>[7:0]
load_data_from_bram.ddr_nn_features.mem<142>[7:0]
load_data_from_bram.ddr_nn_features.mem<143>[7:0]
load_data_from_bram.ddr_nn_features.mem<144>[7:0]
load_data_from_bram.ddr_nn_features.mem<145>[7:0]
load_data_from_bram.ddr_nn_features.mem<146>[7:0]
load_data_from_bram.ddr_nn_features.mem<147>[7:0]
load_data_from_bram.ddr_nn_features.mem<148>[7:0]
load_data_from_bram.ddr_nn_features.mem<149>[7:0]
load_data_from_bram.ddr_nn_features.mem<150>[7:0]
load_data_from_bram.ddr_nn_features.mem<151>[7:0]
load_data_from_bram.ddr_nn_features.mem<152>[7:0]
load_data_from_bram.ddr_nn_features.mem<153>[7:0]
load_data_from_bram.ddr_nn_features.mem<154>[7:0]
load_data_from_bram.ddr_nn_features.mem<155>[7:0]
load_data_from_bram.ddr_nn_features.mem<156>[7:0]
load_data_from_bram.ddr_nn_features.mem<157>[7:0]
load_data_from_bram.ddr_nn_features.mem<158>[7:0]
load_data_from_bram.ddr_nn_features.mem<159>[7:0]
load_data_from_bram.ddr_nn_features.mem<160>[7:0]
load_data_from_bram.ddr_nn_features.mem<161>[7:0]
load_data_from_bram.ddr_nn_features.mem<162>[7:0]
load_data_from_bram.ddr_nn_features.mem<163>[7:0]
load_data_from_bram.ddr_nn_features.mem<164>[7:0]
load_data_from_bram.ddr_nn_features.mem<165>[7:0]
load_data_from_bram.ddr_nn_features.mem<166>[7:0]
load_data_from_bram.ddr_nn_features.mem<167>[7:0]
load_data_from_bram.ddr_nn_features.mem<168>[7:0]
load_data_from_bram.ddr_nn_features.mem<169>[7:0]
load_data_from_bram.ddr_nn_features.mem<170>[7:0]
load_data_from_bram.ddr_nn_features.mem<171>[7:0]
load_data_from_bram.ddr_nn_features.mem<172>[7:0]
load_data_from_bram.ddr_nn_features.mem<173>[7:0]
load_data_from_bram.ddr_nn_features.mem<174>[7:0]
load_data_from_bram.ddr_nn_features.mem<175>[7:0]
load_data_from_bram.ddr_nn_features.mem<176>[7:0]
load_data_from_bram.ddr_nn_features.mem<177>[7:0]
load_data_from_bram.ddr_nn_features.mem<178>[7:0]
load_data_from_bram.ddr_nn_features.mem<179>[7:0]
load_data_from_bram.ddr_nn_features.mem<180>[7:0]
load_data_from_bram.ddr_nn_features.mem<181>[7:0]
load_data_from_bram.ddr_nn_features.mem<182>[7:0]
load_data_from_bram.ddr_nn_features.mem<183>[7:0]
load_data_from_bram.ddr_nn_features.mem<184>[7:0]
load_data_from_bram.ddr_nn_features.mem<185>[7:0]
load_data_from_bram.ddr_nn_features.mem<186>[7:0]
load_data_from_bram.ddr_nn_features.mem<187>[7:0]
load_data_from_bram.ddr_nn_features.mem<188>[7:0]
load_data_from_bram.ddr_nn_features.mem<189>[7:0]
load_data_from_bram.ddr_nn_features.mem<190>[7:0]
load_data_from_bram.ddr_nn_features.mem<191>[7:0]
load_data_from_bram.ddr_nn_features.mem<192>[7:0]
load_data_from_bram.ddr_nn_features.mem<193>[7:0]
load_data_from_bram.ddr_nn_features.mem<194>[7:0]
load_data_from_bram.ddr_nn_features.mem<195>[7:0]
load_data_from_bram.ddr_nn_features.mem<196>[7:0]
load_data_from_bram.ddr_nn_features.mem<197>[7:0]
load_data_from_bram.ddr_nn_features.mem<198>[7:0]
load_data_from_bram.ddr_nn_features.mem<199>[7:0]
load_data_from_bram.ddr_nn_features.mem<200>[7:0]
load_data_from_bram.ddr_nn_features.mem<201>[7:0]
load_data_from_bram.ddr_nn_features.mem<202>[7:0]
load_data_from_bram.ddr_nn_features.mem<203>[7:0]
load_data_from_bram.ddr_nn_features.mem<204>[7:0]
load_data_from_bram.ddr_nn_features.mem<205>[7:0]
load_data_from_bram.ddr_nn_features.mem<206>[7:0]
load_data_from_bram.ddr_nn_features.mem<207>[7:0]
load_data_from_bram.ddr_nn_features.mem<208>[7:0]
load_data_from_bram.ddr_nn_features.mem<209>[7:0]
load_data_from_bram.ddr_nn_features.mem<210>[7:0]
load_data_from_bram.ddr_nn_features.mem<211>[7:0]
load_data_from_bram.ddr_nn_features.mem<212>[7:0]
load_data_from_bram.ddr_nn_features.mem<213>[7:0]
load_data_from_bram.ddr_nn_features.mem<214>[7:0]
load_data_from_bram.ddr_nn_features.mem<215>[7:0]
load_data_from_bram.ddr_nn_features.mem<216>[7:0]
load_data_from_bram.ddr_nn_features.mem<217>[7:0]
load_data_from_bram.ddr_nn_features.mem<218>[7:0]
load_data_from_bram.ddr_nn_features.mem<219>[7:0]
load_data_from_bram.ddr_nn_features.mem<220>[7:0]
load_data_from_bram.ddr_nn_features.mem<221>[7:0]
load_data_from_bram.ddr_nn_features.mem<222>[7:0]
load_data_from_bram.ddr_nn_features.mem<223>[7:0]
load_data_from_bram.ddr_nn_features.mem<224>[7:0]
load_data_from_bram.ddr_nn_features.mem<225>[7:0]
load_data_from_bram.ddr_nn_features.mem<226>[7:0]
load_data_from_bram.ddr_nn_features.mem<227>[7:0]
load_data_from_bram.ddr_nn_features.mem<228>[7:0]
load_data_from_bram.ddr_nn_features.mem<229>[7:0]
load_data_from_bram.ddr_nn_features.mem<230>[7:0]
load_data_from_bram.ddr_nn_features.mem<231>[7:0]
load_data_from_bram.ddr_nn_features.mem<232>[7:0]
load_data_from_bram.ddr_nn_features.mem<233>[7:0]
load_data_from_bram.ddr_nn_features.mem<234>[7:0]
load_data_from_bram.ddr_nn_features.mem<235>[7:0]
load_data_from_bram.ddr_nn_features.mem<236>[7:0]
load_data_from_bram.ddr_nn_features.mem<237>[7:0]
load_data_from_bram.ddr_nn_features.mem<238>[7:0]
load_data_from_bram.ddr_nn_features.mem<239>[7:0]
load_data_from_bram.ddr_nn_features.mem<240>[7:0]
load_data_from_bram.ddr_nn_features.mem<241>[7:0]
load_data_from_bram.ddr_nn_features.mem<242>[7:0]
load_data_from_bram.ddr_nn_features.mem<243>[7:0]
load_data_from_bram.ddr_nn_features.mem<244>[7:0]
load_data_from_bram.ddr_nn_features.mem<245>[7:0]
load_data_from_bram.ddr_nn_features.mem<246>[7:0]
load_data_from_bram.ddr_nn_features.mem<247>[7:0]
load_data_from_bram.ddr_nn_features.mem<248>[7:0]
load_data_from_bram.ddr_nn_features.mem<249>[7:0]
load_data_from_bram.ddr_nn_features.mem<250>[7:0]
load_data_from_bram.ddr_nn_features.mem<251>[7:0]
load_data_from_bram.ddr_nn_features.mem<252>[7:0]
load_data_from_bram.ddr_nn_features.mem<253>[7:0]
load_data_from_bram.ddr_nn_features.mem<254>[7:0]
load_data_from_bram.ddr_nn_features.mem<255>[7:0]
load_data_from_bram.ddr_nn_features.mem<256>[7:0]
@28
load_data_from_bram.ddr_nn_features.mem<258>[1:0]
load_data_from_bram.ddr_nn_features.mem<260>[2:0]
load_data_from_bram.ddr_nn_features.mem<262>[2:0]
load_data_from_bram.ddr_nn_features.mem<263>[2:0]
@22
load_data_from_bram.ddr_nn_features.mem<264>[3:0]
load_data_from_bram.ddr_nn_features.mem<265>[3:0]
load_data_from_bram.ddr_nn_features.mem<266>[7:0]
load_data_from_bram.ddr_nn_features.mem<267>[7:0]
load_data_from_bram.ddr_nn_features.mem<268>[7:0]
load_data_from_bram.ddr_nn_features.mem<269>[7:0]
load_data_from_bram.ddr_nn_features.mem<270>[7:0]
load_data_from_bram.ddr_nn_features.mem<271>[7:0]
load_data_from_bram.ddr_nn_features.mem<272>[7:0]
load_data_from_bram.ddr_nn_features.mem<273>[7:0]
load_data_from_bram.ddr_nn_features.mem<274>[7:0]
load_data_from_bram.ddr_nn_features.mem<275>[7:0]
load_data_from_bram.ddr_nn_features.mem<276>[7:0]
load_data_from_bram.ddr_nn_features.mem<277>[7:0]
load_data_from_bram.ddr_nn_features.mem<278>[7:0]
load_data_from_bram.ddr_nn_features.mem<279>[7:0]
load_data_from_bram.ddr_nn_features.mem<280>[7:0]
load_data_from_bram.ddr_nn_features.mem<281>[7:0]
load_data_from_bram.ddr_nn_features.mem<282>[7:0]
load_data_from_bram.ddr_nn_features.mem<283>[7:0]
load_data_from_bram.ddr_nn_features.mem<286>[7:0]
load_data_from_bram.ddr_nn_features.mem<287>[7:0]
load_data_from_bram.ddr_nn_features.mem<288>[7:0]
load_data_from_bram.ddr_nn_features.mem<292>[5:0]
load_data_from_bram.ddr_nn_features.mem<293>[5:0]
load_data_from_bram.ddr_nn_features.mem<294>[5:0]
load_data_from_bram.ddr_nn_features.mem<295>[5:0]
load_data_from_bram.ddr_nn_features.mem<296>[5:0]
load_data_from_bram.ddr_nn_features.mem<297>[5:0]
load_data_from_bram.ddr_nn_features.mem<298>[5:0]
load_data_from_bram.ddr_nn_features.mem<299>[5:0]
load_data_from_bram.ddr_nn_features.mem<300>[5:0]
load_data_from_bram.ddr_nn_features.mem<301>[5:0]
load_data_from_bram.ddr_nn_features.mem<302>[5:0]
load_data_from_bram.ddr_nn_features.mem<303>[5:0]
load_data_from_bram.ddr_nn_features.mem<304>[5:0]
load_data_from_bram.ddr_nn_features.mem<305>[5:0]
load_data_from_bram.ddr_nn_features.mem<306>[5:0]
load_data_from_bram.ddr_nn_features.mem<307>[5:0]
load_data_from_bram.ddr_nn_features.mem<308>[5:0]
load_data_from_bram.ddr_nn_features.mem<309>[5:0]
load_data_from_bram.ddr_nn_features.mem<310>[5:0]
load_data_from_bram.ddr_nn_features.mem<311>[5:0]
load_data_from_bram.ddr_nn_features.mem<312>[5:0]
load_data_from_bram.ddr_nn_features.mem<313>[5:0]
load_data_from_bram.ddr_nn_features.mem<314>[5:0]
load_data_from_bram.ddr_nn_features.mem<315>[5:0]
load_data_from_bram.ddr_nn_features.mem<316>[5:0]
load_data_from_bram.ddr_nn_features.mem<317>[5:0]
load_data_from_bram.ddr_nn_features.mem<318>[5:0]
load_data_from_bram.ddr_nn_features.mem<319>[5:0]
load_data_from_bram.ddr_nn_features.mem<320>[6:0]
load_data_from_bram.ddr_nn_features.mem<321>[6:0]
load_data_from_bram.ddr_nn_features.mem<322>[6:0]
load_data_from_bram.ddr_nn_features.mem<323>[6:0]
load_data_from_bram.ddr_nn_features.mem<324>[6:0]
load_data_from_bram.ddr_nn_features.mem<325>[6:0]
load_data_from_bram.ddr_nn_features.mem<326>[6:0]
load_data_from_bram.ddr_nn_features.mem<327>[6:0]
load_data_from_bram.ddr_nn_features.mem<328>[6:0]
load_data_from_bram.ddr_nn_features.mem<329>[6:0]
load_data_from_bram.ddr_nn_features.mem<330>[6:0]
load_data_from_bram.ddr_nn_features.mem<331>[6:0]
load_data_from_bram.ddr_nn_features.mem<332>[6:0]
load_data_from_bram.ddr_nn_features.mem<333>[6:0]
load_data_from_bram.ddr_nn_features.mem<334>[6:0]
load_data_from_bram.ddr_nn_features.mem<335>[6:0]
load_data_from_bram.ddr_nn_features.mem<336>[6:0]
load_data_from_bram.ddr_nn_features.mem<337>[6:0]
load_data_from_bram.ddr_nn_features.mem<338>[6:0]
load_data_from_bram.ddr_nn_features.mem<339>[6:0]
load_data_from_bram.ddr_nn_features.mem<353>[6:0]
load_data_from_bram.ddr_nn_features.mem<354>[6:0]
load_data_from_bram.ddr_nn_features.mem<355>[6:0]
load_data_from_bram.ddr_nn_features.mem<356>[7:0]
load_data_from_bram.ddr_nn_features.mem<357>[7:0]
load_data_from_bram.ddr_nn_features.mem<358>[7:0]
load_data_from_bram.ddr_nn_features.mem<359>[7:0]
load_data_from_bram.ddr_nn_features.mem<360>[7:0]
load_data_from_bram.ddr_nn_features.mem<361>[7:0]
load_data_from_bram.ddr_nn_features.mem<362>[7:0]
load_data_from_bram.ddr_nn_features.mem<363>[7:0]
load_data_from_bram.ddr_nn_features.mem<364>[7:0]
load_data_from_bram.ddr_nn_features.mem<365>[7:0]
load_data_from_bram.ddr_nn_features.mem<366>[7:0]
load_data_from_bram.ddr_nn_features.mem<367>[7:0]
load_data_from_bram.ddr_nn_features.mem<368>[7:0]
load_data_from_bram.ddr_nn_features.mem<369>[7:0]
load_data_from_bram.ddr_nn_features.mem<370>[7:0]
load_data_from_bram.ddr_nn_features.mem<371>[7:0]
load_data_from_bram.ddr_nn_features.mem<372>[7:0]
load_data_from_bram.ddr_nn_features.mem<373>[7:0]
load_data_from_bram.ddr_nn_features.mem<374>[7:0]
load_data_from_bram.ddr_nn_features.mem<375>[7:0]
load_data_from_bram.ddr_nn_features.mem<376>[7:0]
load_data_from_bram.ddr_nn_features.mem<377>[7:0]
load_data_from_bram.ddr_nn_features.mem<378>[7:0]
load_data_from_bram.ddr_nn_features.mem<379>[7:0]
load_data_from_bram.ddr_nn_features.mem<380>[7:0]
load_data_from_bram.ddr_nn_features.mem<381>[7:0]
load_data_from_bram.ddr_nn_features.mem<382>[7:0]
load_data_from_bram.ddr_nn_features.mem<383>[7:0]
load_data_from_bram.ddr_nn_features.mem<384>[7:0]
load_data_from_bram.ddr_nn_features.mem<385>[7:0]
load_data_from_bram.ddr_nn_features.mem<386>[7:0]
load_data_from_bram.ddr_nn_features.mem<387>[7:0]
load_data_from_bram.ddr_nn_features.mem<388>[7:0]
load_data_from_bram.ddr_nn_features.mem<389>[7:0]
load_data_from_bram.ddr_nn_features.mem<390>[7:0]
load_data_from_bram.ddr_nn_features.mem<391>[7:0]
load_data_from_bram.ddr_nn_features.mem<392>[7:0]
load_data_from_bram.ddr_nn_features.mem<393>[7:0]
load_data_from_bram.ddr_nn_features.mem<394>[7:0]
load_data_from_bram.ddr_nn_features.mem<395>[7:0]
load_data_from_bram.ddr_nn_features.mem<396>[7:0]
load_data_from_bram.ddr_nn_features.mem<397>[7:0]
load_data_from_bram.ddr_nn_features.mem<398>[7:0]
load_data_from_bram.ddr_nn_features.mem<399>[7:0]
load_data_from_bram.ddr_nn_features.mem<400>[7:0]
load_data_from_bram.ddr_nn_features.mem<401>[7:0]
load_data_from_bram.ddr_nn_features.mem<402>[7:0]
load_data_from_bram.ddr_nn_features.mem<403>[7:0]
load_data_from_bram.ddr_nn_features.mem<404>[7:0]
load_data_from_bram.ddr_nn_features.mem<405>[7:0]
load_data_from_bram.ddr_nn_features.mem<406>[7:0]
load_data_from_bram.ddr_nn_features.mem<407>[7:0]
load_data_from_bram.ddr_nn_features.mem<408>[7:0]
load_data_from_bram.ddr_nn_features.mem<409>[7:0]
load_data_from_bram.ddr_nn_features.mem<410>[7:0]
load_data_from_bram.ddr_nn_features.mem<411>[7:0]
load_data_from_bram.ddr_nn_features.mem<412>[7:0]
load_data_from_bram.ddr_nn_features.mem<413>[7:0]
load_data_from_bram.ddr_nn_features.mem<414>[7:0]
load_data_from_bram.ddr_nn_features.mem<415>[7:0]
load_data_from_bram.ddr_nn_features.mem<416>[7:0]
load_data_from_bram.ddr_nn_features.mem<417>[7:0]
load_data_from_bram.ddr_nn_features.mem<418>[7:0]
load_data_from_bram.ddr_nn_features.mem<419>[7:0]
load_data_from_bram.ddr_nn_features.mem<420>[7:0]
load_data_from_bram.ddr_nn_features.mem<421>[7:0]
load_data_from_bram.ddr_nn_features.mem<422>[7:0]
load_data_from_bram.ddr_nn_features.mem<423>[7:0]
load_data_from_bram.ddr_nn_features.mem<424>[7:0]
load_data_from_bram.ddr_nn_features.mem<425>[7:0]
load_data_from_bram.ddr_nn_features.mem<426>[7:0]
load_data_from_bram.ddr_nn_features.mem<427>[7:0]
load_data_from_bram.ddr_nn_features.mem<428>[7:0]
load_data_from_bram.ddr_nn_features.mem<429>[7:0]
load_data_from_bram.ddr_nn_features.mem<430>[7:0]
load_data_from_bram.ddr_nn_features.mem<431>[7:0]
load_data_from_bram.ddr_nn_features.mem<432>[7:0]
load_data_from_bram.ddr_nn_features.mem<433>[7:0]
load_data_from_bram.ddr_nn_features.mem<434>[7:0]
load_data_from_bram.ddr_nn_features.mem<435>[7:0]
load_data_from_bram.ddr_nn_features.mem<436>[7:0]
load_data_from_bram.ddr_nn_features.mem<437>[7:0]
load_data_from_bram.ddr_nn_features.mem<438>[7:0]
load_data_from_bram.ddr_nn_features.mem<439>[7:0]
load_data_from_bram.ddr_nn_features.mem<440>[7:0]
load_data_from_bram.ddr_nn_features.mem<441>[7:0]
load_data_from_bram.ddr_nn_features.mem<442>[7:0]
load_data_from_bram.ddr_nn_features.mem<443>[7:0]
load_data_from_bram.ddr_nn_features.mem<444>[7:0]
load_data_from_bram.ddr_nn_features.mem<445>[7:0]
load_data_from_bram.ddr_nn_features.mem<446>[7:0]
load_data_from_bram.ddr_nn_features.mem<447>[7:0]
load_data_from_bram.ddr_nn_features.mem<448>[7:0]
load_data_from_bram.ddr_nn_features.mem<449>[7:0]
load_data_from_bram.ddr_nn_features.mem<450>[7:0]
load_data_from_bram.ddr_nn_features.mem<451>[7:0]
load_data_from_bram.ddr_nn_features.mem<452>[7:0]
load_data_from_bram.ddr_nn_features.mem<453>[7:0]
load_data_from_bram.ddr_nn_features.mem<454>[7:0]
load_data_from_bram.ddr_nn_features.mem<455>[7:0]
load_data_from_bram.ddr_nn_features.mem<456>[7:0]
load_data_from_bram.ddr_nn_features.mem<457>[7:0]
load_data_from_bram.ddr_nn_features.mem<458>[7:0]
load_data_from_bram.ddr_nn_features.mem<459>[7:0]
load_data_from_bram.ddr_nn_features.mem<460>[7:0]
load_data_from_bram.ddr_nn_features.mem<461>[7:0]
load_data_from_bram.ddr_nn_features.mem<462>[7:0]
load_data_from_bram.ddr_nn_features.mem<463>[7:0]
load_data_from_bram.ddr_nn_features.mem<464>[7:0]
load_data_from_bram.ddr_nn_features.mem<465>[7:0]
load_data_from_bram.ddr_nn_features.mem<466>[7:0]
load_data_from_bram.ddr_nn_features.mem<467>[7:0]
load_data_from_bram.ddr_nn_features.mem<468>[7:0]
load_data_from_bram.ddr_nn_features.mem<469>[7:0]
load_data_from_bram.ddr_nn_features.mem<470>[7:0]
load_data_from_bram.ddr_nn_features.mem<471>[7:0]
load_data_from_bram.ddr_nn_features.mem<472>[7:0]
load_data_from_bram.ddr_nn_features.mem<473>[7:0]
load_data_from_bram.ddr_nn_features.mem<474>[7:0]
load_data_from_bram.ddr_nn_features.mem<475>[7:0]
load_data_from_bram.ddr_nn_features.mem<476>[7:0]
load_data_from_bram.ddr_nn_features.mem<477>[7:0]
load_data_from_bram.ddr_nn_features.mem<478>[7:0]
load_data_from_bram.ddr_nn_features.mem<479>[7:0]
load_data_from_bram.ddr_nn_features.mem<480>[7:0]
load_data_from_bram.ddr_nn_features.mem<481>[7:0]
load_data_from_bram.ddr_nn_features.mem<482>[7:0]
load_data_from_bram.ddr_nn_features.mem<483>[7:0]
load_data_from_bram.ddr_nn_features.mem<484>[7:0]
load_data_from_bram.ddr_nn_features.mem<485>[7:0]
load_data_from_bram.ddr_nn_features.mem<486>[7:0]
load_data_from_bram.ddr_nn_features.mem<487>[7:0]
load_data_from_bram.ddr_nn_features.mem<488>[7:0]
load_data_from_bram.ddr_nn_features.mem<489>[7:0]
load_data_from_bram.ddr_nn_features.mem<490>[7:0]
load_data_from_bram.ddr_nn_features.mem<491>[7:0]
load_data_from_bram.ddr_nn_features.mem<492>[7:0]
load_data_from_bram.ddr_nn_features.mem<493>[7:0]
load_data_from_bram.ddr_nn_features.mem<494>[7:0]
load_data_from_bram.ddr_nn_features.mem<495>[7:0]
load_data_from_bram.ddr_nn_features.mem<496>[7:0]
load_data_from_bram.ddr_nn_features.mem<497>[7:0]
load_data_from_bram.ddr_nn_features.mem<498>[7:0]
load_data_from_bram.ddr_nn_features.mem<499>[7:0]
load_data_from_bram.ddr_nn_features.mem<500>[7:0]
load_data_from_bram.ddr_nn_features.mem<501>[7:0]
load_data_from_bram.ddr_nn_features.mem<502>[7:0]
load_data_from_bram.ddr_nn_features.mem<503>[7:0]
load_data_from_bram.ddr_nn_features.mem<504>[7:0]
load_data_from_bram.ddr_nn_features.mem<505>[7:0]
load_data_from_bram.ddr_nn_features.mem<506>[7:0]
load_data_from_bram.ddr_nn_features.mem<507>[7:0]
load_data_from_bram.ddr_nn_features.mem<508>[7:0]
load_data_from_bram.ddr_nn_features.mem<509>[7:0]
load_data_from_bram.ddr_nn_features.mem<510>[7:0]
load_data_from_bram.ddr_nn_features.mem<511>[7:0]
@28
load_data_from_bram.ddr_nn_features.o_axi_arready
load_data_from_bram.ddr_nn_features.o_axi_awready
load_data_from_bram.ddr_nn_features.o_axi_bid
load_data_from_bram.ddr_nn_features.o_axi_bresp[1:0]
load_data_from_bram.ddr_nn_features.o_axi_bvalid
@22
load_data_from_bram.ddr_nn_features.o_axi_rdata[7:0]
@28
load_data_from_bram.ddr_nn_features.o_axi_rid
load_data_from_bram.ddr_nn_features.o_axi_rlast
load_data_from_bram.ddr_nn_features.o_axi_rresp[1:0]
load_data_from_bram.ddr_nn_features.o_axi_rvalid
load_data_from_bram.ddr_nn_features.o_axi_wready
load_data_from_bram.ddr_nn_features.reset
load_data_from_bram.ddr_nn_params.clk
@22
load_data_from_bram.ddr_nn_params.i_axi_araddr[8:0]
@28
load_data_from_bram.ddr_nn_params.i_axi_arburst[1:0]
@22
load_data_from_bram.ddr_nn_params.i_axi_arcache[3:0]
@28
load_data_from_bram.ddr_nn_params.i_axi_arid
@22
load_data_from_bram.ddr_nn_params.i_axi_arlen[7:0]
@28
load_data_from_bram.ddr_nn_params.i_axi_arlock
load_data_from_bram.ddr_nn_params.i_axi_arprot[2:0]
@22
load_data_from_bram.ddr_nn_params.i_axi_arqos[3:0]
@28
load_data_from_bram.ddr_nn_params.i_axi_arsize[2:0]
load_data_from_bram.ddr_nn_params.i_axi_arvalid
@22
load_data_from_bram.ddr_nn_params.i_axi_awaddr[8:0]
@28
load_data_from_bram.ddr_nn_params.i_axi_awburst[1:0]
@22
load_data_from_bram.ddr_nn_params.i_axi_awcache[3:0]
@28
load_data_from_bram.ddr_nn_params.i_axi_awid
@22
load_data_from_bram.ddr_nn_params.i_axi_awlen[7:0]
@28
load_data_from_bram.ddr_nn_params.i_axi_awlock
load_data_from_bram.ddr_nn_params.i_axi_awprot[2:0]
@22
load_data_from_bram.ddr_nn_params.i_axi_awqos[3:0]
@28
load_data_from_bram.ddr_nn_params.i_axi_awsize[2:0]
load_data_from_bram.ddr_nn_params.i_axi_awvalid
load_data_from_bram.ddr_nn_params.i_axi_bready
load_data_from_bram.ddr_nn_params.i_axi_rready
@22
load_data_from_bram.ddr_nn_params.i_axi_wdata[7:0]
@28
load_data_from_bram.ddr_nn_params.i_axi_wlast
load_data_from_bram.ddr_nn_params.i_axi_wstrb
load_data_from_bram.ddr_nn_params.i_axi_wvalid
@22
load_data_from_bram.ddr_nn_params.mem<0>[7:0]
@28
load_data_from_bram.ddr_nn_params.mem<1>
@22
load_data_from_bram.ddr_nn_params.mem<10>[3:0]
load_data_from_bram.ddr_nn_params.mem<11>[3:0]
load_data_from_bram.ddr_nn_params.mem<14>[7:0]
load_data_from_bram.ddr_nn_params.mem<15>[7:0]
load_data_from_bram.ddr_nn_params.mem<18>[7:0]
load_data_from_bram.ddr_nn_params.mem<21>[7:0]
load_data_from_bram.ddr_nn_params.mem<22>[7:0]
load_data_from_bram.ddr_nn_params.mem<23>[7:0]
load_data_from_bram.ddr_nn_params.mem<24>[7:0]
load_data_from_bram.ddr_nn_params.mem<25>[7:0]
load_data_from_bram.ddr_nn_params.mem<26>[7:0]
load_data_from_bram.ddr_nn_params.mem<28>[7:0]
load_data_from_bram.ddr_nn_params.mem<30>[7:0]
load_data_from_bram.ddr_nn_params.mem<31>[7:0]
load_data_from_bram.ddr_nn_params.mem<32>[7:0]
load_data_from_bram.ddr_nn_params.mem<34>[7:0]
load_data_from_bram.ddr_nn_params.mem<37>[7:0]
load_data_from_bram.ddr_nn_params.mem<38>[7:0]
load_data_from_bram.ddr_nn_params.mem<39>[7:0]
load_data_from_bram.ddr_nn_params.mem<40>[7:0]
load_data_from_bram.ddr_nn_params.mem<41>[7:0]
load_data_from_bram.ddr_nn_params.mem<42>[7:0]
load_data_from_bram.ddr_nn_params.mem<43>[7:0]
load_data_from_bram.ddr_nn_params.mem<44>[7:0]
load_data_from_bram.ddr_nn_params.mem<45>[7:0]
load_data_from_bram.ddr_nn_params.mem<46>[7:0]
load_data_from_bram.ddr_nn_params.mem<47>[7:0]
load_data_from_bram.ddr_nn_params.mem<48>[7:0]
load_data_from_bram.ddr_nn_params.mem<49>[7:0]
load_data_from_bram.ddr_nn_params.mem<50>[7:0]
load_data_from_bram.ddr_nn_params.mem<51>[7:0]
load_data_from_bram.ddr_nn_params.mem<52>[7:0]
load_data_from_bram.ddr_nn_params.mem<53>[7:0]
load_data_from_bram.ddr_nn_params.mem<54>[7:0]
load_data_from_bram.ddr_nn_params.mem<55>[7:0]
load_data_from_bram.ddr_nn_params.mem<60>[7:0]
load_data_from_bram.ddr_nn_params.mem<61>[7:0]
load_data_from_bram.ddr_nn_params.mem<63>[7:0]
load_data_from_bram.ddr_nn_params.mem<64>[7:0]
load_data_from_bram.ddr_nn_params.mem<65>[7:0]
load_data_from_bram.ddr_nn_params.mem<66>[7:0]
load_data_from_bram.ddr_nn_params.mem<68>[7:0]
load_data_from_bram.ddr_nn_params.mem<69>[7:0]
load_data_from_bram.ddr_nn_params.mem<70>[7:0]
load_data_from_bram.ddr_nn_params.mem<71>[7:0]
load_data_from_bram.ddr_nn_params.mem<72>[7:0]
load_data_from_bram.ddr_nn_params.mem<73>[7:0]
load_data_from_bram.ddr_nn_params.mem<74>[7:0]
load_data_from_bram.ddr_nn_params.mem<75>[7:0]
load_data_from_bram.ddr_nn_params.mem<77>[7:0]
load_data_from_bram.ddr_nn_params.mem<78>[7:0]
load_data_from_bram.ddr_nn_params.mem<79>[7:0]
load_data_from_bram.ddr_nn_params.mem<80>[7:0]
load_data_from_bram.ddr_nn_params.mem<81>[7:0]
load_data_from_bram.ddr_nn_params.mem<82>[7:0]
load_data_from_bram.ddr_nn_params.mem<83>[7:0]
load_data_from_bram.ddr_nn_params.mem<84>[7:0]
load_data_from_bram.ddr_nn_params.mem<85>[7:0]
load_data_from_bram.ddr_nn_params.mem<86>[7:0]
load_data_from_bram.ddr_nn_params.mem<87>[7:0]
load_data_from_bram.ddr_nn_params.mem<88>[7:0]
load_data_from_bram.ddr_nn_params.mem<89>[7:0]
load_data_from_bram.ddr_nn_params.mem<90>[7:0]
load_data_from_bram.ddr_nn_params.mem<91>[7:0]
load_data_from_bram.ddr_nn_params.mem<92>[7:0]
load_data_from_bram.ddr_nn_params.mem<93>[7:0]
load_data_from_bram.ddr_nn_params.mem<94>[7:0]
load_data_from_bram.ddr_nn_params.mem<95>[7:0]
load_data_from_bram.ddr_nn_params.mem<96>[7:0]
load_data_from_bram.ddr_nn_params.mem<98>[7:0]
load_data_from_bram.ddr_nn_params.mem<99>[7:0]
load_data_from_bram.ddr_nn_params.mem<100>[6:0]
load_data_from_bram.ddr_nn_params.mem<101>[6:0]
load_data_from_bram.ddr_nn_params.mem<102>[7:0]
load_data_from_bram.ddr_nn_params.mem<104>[7:0]
load_data_from_bram.ddr_nn_params.mem<106>[7:0]
load_data_from_bram.ddr_nn_params.mem<108>[7:0]
load_data_from_bram.ddr_nn_params.mem<109>[7:0]
load_data_from_bram.ddr_nn_params.mem<110>[7:0]
load_data_from_bram.ddr_nn_params.mem<111>[7:0]
load_data_from_bram.ddr_nn_params.mem<112>[7:0]
load_data_from_bram.ddr_nn_params.mem<114>[7:0]
load_data_from_bram.ddr_nn_params.mem<117>[7:0]
load_data_from_bram.ddr_nn_params.mem<118>[7:0]
load_data_from_bram.ddr_nn_params.mem<119>[7:0]
load_data_from_bram.ddr_nn_params.mem<120>[7:0]
load_data_from_bram.ddr_nn_params.mem<121>[7:0]
load_data_from_bram.ddr_nn_params.mem<122>[7:0]
load_data_from_bram.ddr_nn_params.mem<123>[7:0]
load_data_from_bram.ddr_nn_params.mem<124>[7:0]
load_data_from_bram.ddr_nn_params.mem<125>[7:0]
load_data_from_bram.ddr_nn_params.mem<126>[7:0]
load_data_from_bram.ddr_nn_params.mem<127>[7:0]
load_data_from_bram.ddr_nn_params.mem<128>[7:0]
load_data_from_bram.ddr_nn_params.mem<129>[7:0]
load_data_from_bram.ddr_nn_params.mem<130>[7:0]
load_data_from_bram.ddr_nn_params.mem<131>[7:0]
load_data_from_bram.ddr_nn_params.mem<132>[7:0]
load_data_from_bram.ddr_nn_params.mem<133>[7:0]
load_data_from_bram.ddr_nn_params.mem<134>[7:0]
load_data_from_bram.ddr_nn_params.mem<135>[7:0]
load_data_from_bram.ddr_nn_params.mem<136>[7:0]
load_data_from_bram.ddr_nn_params.mem<137>[7:0]
load_data_from_bram.ddr_nn_params.mem<138>[7:0]
load_data_from_bram.ddr_nn_params.mem<139>[7:0]
load_data_from_bram.ddr_nn_params.mem<140>[7:0]
load_data_from_bram.ddr_nn_params.mem<141>[7:0]
load_data_from_bram.ddr_nn_params.mem<142>[7:0]
load_data_from_bram.ddr_nn_params.mem<143>[7:0]
load_data_from_bram.ddr_nn_params.mem<144>[7:0]
load_data_from_bram.ddr_nn_params.mem<145>[7:0]
load_data_from_bram.ddr_nn_params.mem<146>[7:0]
load_data_from_bram.ddr_nn_params.mem<147>[7:0]
load_data_from_bram.ddr_nn_params.mem<148>[7:0]
load_data_from_bram.ddr_nn_params.mem<149>[7:0]
load_data_from_bram.ddr_nn_params.mem<150>[7:0]
load_data_from_bram.ddr_nn_params.mem<151>[7:0]
load_data_from_bram.ddr_nn_params.mem<152>[7:0]
load_data_from_bram.ddr_nn_params.mem<153>[7:0]
load_data_from_bram.ddr_nn_params.mem<154>[7:0]
load_data_from_bram.ddr_nn_params.mem<155>[7:0]
load_data_from_bram.ddr_nn_params.mem<156>[7:0]
load_data_from_bram.ddr_nn_params.mem<157>[7:0]
load_data_from_bram.ddr_nn_params.mem<158>[7:0]
load_data_from_bram.ddr_nn_params.mem<159>[7:0]
load_data_from_bram.ddr_nn_params.mem<160>[7:0]
load_data_from_bram.ddr_nn_params.mem<161>[7:0]
load_data_from_bram.ddr_nn_params.mem<162>[7:0]
load_data_from_bram.ddr_nn_params.mem<163>[7:0]
load_data_from_bram.ddr_nn_params.mem<164>[7:0]
load_data_from_bram.ddr_nn_params.mem<165>[7:0]
load_data_from_bram.ddr_nn_params.mem<166>[7:0]
load_data_from_bram.ddr_nn_params.mem<167>[7:0]
load_data_from_bram.ddr_nn_params.mem<168>[7:0]
load_data_from_bram.ddr_nn_params.mem<169>[7:0]
load_data_from_bram.ddr_nn_params.mem<170>[7:0]
load_data_from_bram.ddr_nn_params.mem<171>[7:0]
load_data_from_bram.ddr_nn_params.mem<172>[7:0]
load_data_from_bram.ddr_nn_params.mem<173>[7:0]
load_data_from_bram.ddr_nn_params.mem<174>[7:0]
load_data_from_bram.ddr_nn_params.mem<175>[7:0]
load_data_from_bram.ddr_nn_params.mem<176>[7:0]
load_data_from_bram.ddr_nn_params.mem<177>[7:0]
load_data_from_bram.ddr_nn_params.mem<178>[7:0]
load_data_from_bram.ddr_nn_params.mem<179>[7:0]
load_data_from_bram.ddr_nn_params.mem<180>[7:0]
load_data_from_bram.ddr_nn_params.mem<181>[7:0]
load_data_from_bram.ddr_nn_params.mem<182>[7:0]
load_data_from_bram.ddr_nn_params.mem<183>[7:0]
load_data_from_bram.ddr_nn_params.mem<184>[7:0]
load_data_from_bram.ddr_nn_params.mem<185>[7:0]
load_data_from_bram.ddr_nn_params.mem<186>[7:0]
load_data_from_bram.ddr_nn_params.mem<187>[7:0]
load_data_from_bram.ddr_nn_params.mem<188>[7:0]
load_data_from_bram.ddr_nn_params.mem<189>[7:0]
load_data_from_bram.ddr_nn_params.mem<190>[7:0]
load_data_from_bram.ddr_nn_params.mem<191>[7:0]
load_data_from_bram.ddr_nn_params.mem<192>[7:0]
load_data_from_bram.ddr_nn_params.mem<193>[7:0]
load_data_from_bram.ddr_nn_params.mem<194>[7:0]
load_data_from_bram.ddr_nn_params.mem<195>[7:0]
load_data_from_bram.ddr_nn_params.mem<196>[7:0]
load_data_from_bram.ddr_nn_params.mem<197>[7:0]
load_data_from_bram.ddr_nn_params.mem<198>[7:0]
load_data_from_bram.ddr_nn_params.mem<199>[7:0]
load_data_from_bram.ddr_nn_params.mem<200>[7:0]
load_data_from_bram.ddr_nn_params.mem<201>[7:0]
load_data_from_bram.ddr_nn_params.mem<202>[7:0]
load_data_from_bram.ddr_nn_params.mem<203>[7:0]
load_data_from_bram.ddr_nn_params.mem<204>[7:0]
load_data_from_bram.ddr_nn_params.mem<205>[7:0]
load_data_from_bram.ddr_nn_params.mem<206>[7:0]
load_data_from_bram.ddr_nn_params.mem<207>[7:0]
load_data_from_bram.ddr_nn_params.mem<208>[7:0]
load_data_from_bram.ddr_nn_params.mem<209>[7:0]
load_data_from_bram.ddr_nn_params.mem<210>[7:0]
load_data_from_bram.ddr_nn_params.mem<211>[7:0]
load_data_from_bram.ddr_nn_params.mem<212>[7:0]
load_data_from_bram.ddr_nn_params.mem<213>[7:0]
load_data_from_bram.ddr_nn_params.mem<214>[7:0]
load_data_from_bram.ddr_nn_params.mem<215>[7:0]
load_data_from_bram.ddr_nn_params.mem<216>[7:0]
load_data_from_bram.ddr_nn_params.mem<217>[7:0]
load_data_from_bram.ddr_nn_params.mem<218>[7:0]
load_data_from_bram.ddr_nn_params.mem<219>[7:0]
load_data_from_bram.ddr_nn_params.mem<220>[7:0]
load_data_from_bram.ddr_nn_params.mem<221>[7:0]
load_data_from_bram.ddr_nn_params.mem<222>[7:0]
load_data_from_bram.ddr_nn_params.mem<223>[7:0]
load_data_from_bram.ddr_nn_params.mem<224>[7:0]
load_data_from_bram.ddr_nn_params.mem<225>[7:0]
load_data_from_bram.ddr_nn_params.mem<226>[7:0]
load_data_from_bram.ddr_nn_params.mem<227>[7:0]
load_data_from_bram.ddr_nn_params.mem<228>[7:0]
load_data_from_bram.ddr_nn_params.mem<229>[7:0]
load_data_from_bram.ddr_nn_params.mem<230>[7:0]
load_data_from_bram.ddr_nn_params.mem<231>[7:0]
load_data_from_bram.ddr_nn_params.mem<232>[7:0]
load_data_from_bram.ddr_nn_params.mem<233>[7:0]
load_data_from_bram.ddr_nn_params.mem<234>[7:0]
load_data_from_bram.ddr_nn_params.mem<235>[7:0]
load_data_from_bram.ddr_nn_params.mem<236>[7:0]
load_data_from_bram.ddr_nn_params.mem<237>[7:0]
load_data_from_bram.ddr_nn_params.mem<238>[7:0]
load_data_from_bram.ddr_nn_params.mem<239>[7:0]
load_data_from_bram.ddr_nn_params.mem<240>[7:0]
load_data_from_bram.ddr_nn_params.mem<241>[7:0]
load_data_from_bram.ddr_nn_params.mem<242>[7:0]
load_data_from_bram.ddr_nn_params.mem<243>[7:0]
load_data_from_bram.ddr_nn_params.mem<244>[7:0]
load_data_from_bram.ddr_nn_params.mem<245>[7:0]
load_data_from_bram.ddr_nn_params.mem<246>[7:0]
load_data_from_bram.ddr_nn_params.mem<247>[7:0]
load_data_from_bram.ddr_nn_params.mem<248>[7:0]
load_data_from_bram.ddr_nn_params.mem<249>[7:0]
load_data_from_bram.ddr_nn_params.mem<250>[7:0]
load_data_from_bram.ddr_nn_params.mem<251>[7:0]
load_data_from_bram.ddr_nn_params.mem<252>[7:0]
load_data_from_bram.ddr_nn_params.mem<253>[7:0]
load_data_from_bram.ddr_nn_params.mem<254>[7:0]
load_data_from_bram.ddr_nn_params.mem<255>[7:0]
load_data_from_bram.ddr_nn_params.mem<256>[7:0]
@28
load_data_from_bram.ddr_nn_params.mem<258>[1:0]
load_data_from_bram.ddr_nn_params.mem<260>[2:0]
load_data_from_bram.ddr_nn_params.mem<262>[2:0]
load_data_from_bram.ddr_nn_params.mem<263>[2:0]
@22
load_data_from_bram.ddr_nn_params.mem<264>[3:0]
load_data_from_bram.ddr_nn_params.mem<265>[3:0]
load_data_from_bram.ddr_nn_params.mem<266>[7:0]
load_data_from_bram.ddr_nn_params.mem<267>[7:0]
load_data_from_bram.ddr_nn_params.mem<268>[7:0]
load_data_from_bram.ddr_nn_params.mem<269>[7:0]
load_data_from_bram.ddr_nn_params.mem<270>[7:0]
load_data_from_bram.ddr_nn_params.mem<271>[7:0]
load_data_from_bram.ddr_nn_params.mem<272>[7:0]
load_data_from_bram.ddr_nn_params.mem<273>[7:0]
load_data_from_bram.ddr_nn_params.mem<274>[7:0]
load_data_from_bram.ddr_nn_params.mem<275>[7:0]
load_data_from_bram.ddr_nn_params.mem<276>[7:0]
load_data_from_bram.ddr_nn_params.mem<277>[7:0]
load_data_from_bram.ddr_nn_params.mem<278>[7:0]
load_data_from_bram.ddr_nn_params.mem<279>[7:0]
load_data_from_bram.ddr_nn_params.mem<280>[7:0]
load_data_from_bram.ddr_nn_params.mem<281>[7:0]
load_data_from_bram.ddr_nn_params.mem<282>[7:0]
load_data_from_bram.ddr_nn_params.mem<283>[7:0]
load_data_from_bram.ddr_nn_params.mem<286>[7:0]
load_data_from_bram.ddr_nn_params.mem<287>[7:0]
load_data_from_bram.ddr_nn_params.mem<288>[7:0]
load_data_from_bram.ddr_nn_params.mem<292>[5:0]
load_data_from_bram.ddr_nn_params.mem<293>[5:0]
load_data_from_bram.ddr_nn_params.mem<294>[5:0]
load_data_from_bram.ddr_nn_params.mem<295>[5:0]
load_data_from_bram.ddr_nn_params.mem<296>[5:0]
load_data_from_bram.ddr_nn_params.mem<297>[5:0]
load_data_from_bram.ddr_nn_params.mem<298>[5:0]
load_data_from_bram.ddr_nn_params.mem<299>[5:0]
load_data_from_bram.ddr_nn_params.mem<300>[5:0]
load_data_from_bram.ddr_nn_params.mem<301>[5:0]
load_data_from_bram.ddr_nn_params.mem<302>[5:0]
load_data_from_bram.ddr_nn_params.mem<303>[5:0]
load_data_from_bram.ddr_nn_params.mem<304>[5:0]
load_data_from_bram.ddr_nn_params.mem<305>[5:0]
load_data_from_bram.ddr_nn_params.mem<306>[5:0]
load_data_from_bram.ddr_nn_params.mem<307>[5:0]
load_data_from_bram.ddr_nn_params.mem<308>[5:0]
load_data_from_bram.ddr_nn_params.mem<309>[5:0]
load_data_from_bram.ddr_nn_params.mem<310>[5:0]
load_data_from_bram.ddr_nn_params.mem<311>[5:0]
load_data_from_bram.ddr_nn_params.mem<312>[5:0]
load_data_from_bram.ddr_nn_params.mem<313>[5:0]
load_data_from_bram.ddr_nn_params.mem<314>[5:0]
load_data_from_bram.ddr_nn_params.mem<315>[5:0]
load_data_from_bram.ddr_nn_params.mem<316>[5:0]
load_data_from_bram.ddr_nn_params.mem<317>[5:0]
load_data_from_bram.ddr_nn_params.mem<318>[5:0]
load_data_from_bram.ddr_nn_params.mem<319>[5:0]
load_data_from_bram.ddr_nn_params.mem<320>[6:0]
load_data_from_bram.ddr_nn_params.mem<321>[6:0]
load_data_from_bram.ddr_nn_params.mem<322>[6:0]
load_data_from_bram.ddr_nn_params.mem<323>[6:0]
load_data_from_bram.ddr_nn_params.mem<324>[6:0]
load_data_from_bram.ddr_nn_params.mem<325>[6:0]
load_data_from_bram.ddr_nn_params.mem<326>[6:0]
load_data_from_bram.ddr_nn_params.mem<327>[6:0]
load_data_from_bram.ddr_nn_params.mem<328>[6:0]
load_data_from_bram.ddr_nn_params.mem<329>[6:0]
load_data_from_bram.ddr_nn_params.mem<330>[6:0]
load_data_from_bram.ddr_nn_params.mem<331>[6:0]
load_data_from_bram.ddr_nn_params.mem<332>[6:0]
load_data_from_bram.ddr_nn_params.mem<333>[6:0]
load_data_from_bram.ddr_nn_params.mem<334>[6:0]
load_data_from_bram.ddr_nn_params.mem<335>[6:0]
load_data_from_bram.ddr_nn_params.mem<336>[6:0]
load_data_from_bram.ddr_nn_params.mem<337>[6:0]
load_data_from_bram.ddr_nn_params.mem<338>[6:0]
load_data_from_bram.ddr_nn_params.mem<339>[6:0]
load_data_from_bram.ddr_nn_params.mem<353>[6:0]
load_data_from_bram.ddr_nn_params.mem<354>[6:0]
load_data_from_bram.ddr_nn_params.mem<355>[6:0]
load_data_from_bram.ddr_nn_params.mem<356>[7:0]
load_data_from_bram.ddr_nn_params.mem<357>[7:0]
load_data_from_bram.ddr_nn_params.mem<358>[7:0]
load_data_from_bram.ddr_nn_params.mem<359>[7:0]
load_data_from_bram.ddr_nn_params.mem<360>[7:0]
load_data_from_bram.ddr_nn_params.mem<361>[7:0]
load_data_from_bram.ddr_nn_params.mem<362>[7:0]
load_data_from_bram.ddr_nn_params.mem<363>[7:0]
load_data_from_bram.ddr_nn_params.mem<364>[7:0]
load_data_from_bram.ddr_nn_params.mem<365>[7:0]
load_data_from_bram.ddr_nn_params.mem<366>[7:0]
load_data_from_bram.ddr_nn_params.mem<367>[7:0]
load_data_from_bram.ddr_nn_params.mem<368>[7:0]
load_data_from_bram.ddr_nn_params.mem<369>[7:0]
load_data_from_bram.ddr_nn_params.mem<370>[7:0]
load_data_from_bram.ddr_nn_params.mem<371>[7:0]
load_data_from_bram.ddr_nn_params.mem<372>[7:0]
load_data_from_bram.ddr_nn_params.mem<373>[7:0]
load_data_from_bram.ddr_nn_params.mem<374>[7:0]
load_data_from_bram.ddr_nn_params.mem<375>[7:0]
load_data_from_bram.ddr_nn_params.mem<376>[7:0]
load_data_from_bram.ddr_nn_params.mem<377>[7:0]
load_data_from_bram.ddr_nn_params.mem<378>[7:0]
load_data_from_bram.ddr_nn_params.mem<379>[7:0]
load_data_from_bram.ddr_nn_params.mem<380>[7:0]
load_data_from_bram.ddr_nn_params.mem<381>[7:0]
load_data_from_bram.ddr_nn_params.mem<382>[7:0]
load_data_from_bram.ddr_nn_params.mem<383>[7:0]
load_data_from_bram.ddr_nn_params.mem<384>[7:0]
load_data_from_bram.ddr_nn_params.mem<385>[7:0]
load_data_from_bram.ddr_nn_params.mem<386>[7:0]
load_data_from_bram.ddr_nn_params.mem<387>[7:0]
load_data_from_bram.ddr_nn_params.mem<388>[7:0]
load_data_from_bram.ddr_nn_params.mem<389>[7:0]
load_data_from_bram.ddr_nn_params.mem<390>[7:0]
load_data_from_bram.ddr_nn_params.mem<391>[7:0]
load_data_from_bram.ddr_nn_params.mem<392>[7:0]
load_data_from_bram.ddr_nn_params.mem<393>[7:0]
load_data_from_bram.ddr_nn_params.mem<394>[7:0]
load_data_from_bram.ddr_nn_params.mem<395>[7:0]
load_data_from_bram.ddr_nn_params.mem<396>[7:0]
load_data_from_bram.ddr_nn_params.mem<397>[7:0]
load_data_from_bram.ddr_nn_params.mem<398>[7:0]
load_data_from_bram.ddr_nn_params.mem<399>[7:0]
load_data_from_bram.ddr_nn_params.mem<400>[7:0]
load_data_from_bram.ddr_nn_params.mem<401>[7:0]
load_data_from_bram.ddr_nn_params.mem<402>[7:0]
load_data_from_bram.ddr_nn_params.mem<403>[7:0]
load_data_from_bram.ddr_nn_params.mem<404>[7:0]
load_data_from_bram.ddr_nn_params.mem<405>[7:0]
load_data_from_bram.ddr_nn_params.mem<406>[7:0]
load_data_from_bram.ddr_nn_params.mem<407>[7:0]
load_data_from_bram.ddr_nn_params.mem<408>[7:0]
load_data_from_bram.ddr_nn_params.mem<409>[7:0]
load_data_from_bram.ddr_nn_params.mem<410>[7:0]
load_data_from_bram.ddr_nn_params.mem<411>[7:0]
load_data_from_bram.ddr_nn_params.mem<412>[7:0]
load_data_from_bram.ddr_nn_params.mem<413>[7:0]
load_data_from_bram.ddr_nn_params.mem<414>[7:0]
load_data_from_bram.ddr_nn_params.mem<415>[7:0]
load_data_from_bram.ddr_nn_params.mem<416>[7:0]
load_data_from_bram.ddr_nn_params.mem<417>[7:0]
load_data_from_bram.ddr_nn_params.mem<418>[7:0]
load_data_from_bram.ddr_nn_params.mem<419>[7:0]
load_data_from_bram.ddr_nn_params.mem<420>[7:0]
load_data_from_bram.ddr_nn_params.mem<421>[7:0]
load_data_from_bram.ddr_nn_params.mem<422>[7:0]
load_data_from_bram.ddr_nn_params.mem<423>[7:0]
load_data_from_bram.ddr_nn_params.mem<424>[7:0]
load_data_from_bram.ddr_nn_params.mem<425>[7:0]
load_data_from_bram.ddr_nn_params.mem<426>[7:0]
load_data_from_bram.ddr_nn_params.mem<427>[7:0]
load_data_from_bram.ddr_nn_params.mem<428>[7:0]
load_data_from_bram.ddr_nn_params.mem<429>[7:0]
load_data_from_bram.ddr_nn_params.mem<430>[7:0]
load_data_from_bram.ddr_nn_params.mem<431>[7:0]
load_data_from_bram.ddr_nn_params.mem<432>[7:0]
load_data_from_bram.ddr_nn_params.mem<433>[7:0]
load_data_from_bram.ddr_nn_params.mem<434>[7:0]
load_data_from_bram.ddr_nn_params.mem<435>[7:0]
load_data_from_bram.ddr_nn_params.mem<436>[7:0]
load_data_from_bram.ddr_nn_params.mem<437>[7:0]
load_data_from_bram.ddr_nn_params.mem<438>[7:0]
load_data_from_bram.ddr_nn_params.mem<439>[7:0]
load_data_from_bram.ddr_nn_params.mem<440>[7:0]
load_data_from_bram.ddr_nn_params.mem<441>[7:0]
load_data_from_bram.ddr_nn_params.mem<442>[7:0]
load_data_from_bram.ddr_nn_params.mem<443>[7:0]
load_data_from_bram.ddr_nn_params.mem<444>[7:0]
load_data_from_bram.ddr_nn_params.mem<445>[7:0]
load_data_from_bram.ddr_nn_params.mem<446>[7:0]
load_data_from_bram.ddr_nn_params.mem<447>[7:0]
load_data_from_bram.ddr_nn_params.mem<448>[7:0]
load_data_from_bram.ddr_nn_params.mem<449>[7:0]
load_data_from_bram.ddr_nn_params.mem<450>[7:0]
load_data_from_bram.ddr_nn_params.mem<451>[7:0]
load_data_from_bram.ddr_nn_params.mem<452>[7:0]
load_data_from_bram.ddr_nn_params.mem<453>[7:0]
load_data_from_bram.ddr_nn_params.mem<454>[7:0]
load_data_from_bram.ddr_nn_params.mem<455>[7:0]
load_data_from_bram.ddr_nn_params.mem<456>[7:0]
load_data_from_bram.ddr_nn_params.mem<457>[7:0]
load_data_from_bram.ddr_nn_params.mem<458>[7:0]
load_data_from_bram.ddr_nn_params.mem<459>[7:0]
load_data_from_bram.ddr_nn_params.mem<460>[7:0]
load_data_from_bram.ddr_nn_params.mem<461>[7:0]
load_data_from_bram.ddr_nn_params.mem<462>[7:0]
load_data_from_bram.ddr_nn_params.mem<463>[7:0]
load_data_from_bram.ddr_nn_params.mem<464>[7:0]
load_data_from_bram.ddr_nn_params.mem<465>[7:0]
load_data_from_bram.ddr_nn_params.mem<466>[7:0]
load_data_from_bram.ddr_nn_params.mem<467>[7:0]
load_data_from_bram.ddr_nn_params.mem<468>[7:0]
load_data_from_bram.ddr_nn_params.mem<469>[7:0]
load_data_from_bram.ddr_nn_params.mem<470>[7:0]
load_data_from_bram.ddr_nn_params.mem<471>[7:0]
load_data_from_bram.ddr_nn_params.mem<472>[7:0]
load_data_from_bram.ddr_nn_params.mem<473>[7:0]
load_data_from_bram.ddr_nn_params.mem<474>[7:0]
load_data_from_bram.ddr_nn_params.mem<475>[7:0]
load_data_from_bram.ddr_nn_params.mem<476>[7:0]
load_data_from_bram.ddr_nn_params.mem<477>[7:0]
load_data_from_bram.ddr_nn_params.mem<478>[7:0]
load_data_from_bram.ddr_nn_params.mem<479>[7:0]
load_data_from_bram.ddr_nn_params.mem<480>[7:0]
load_data_from_bram.ddr_nn_params.mem<481>[7:0]
load_data_from_bram.ddr_nn_params.mem<482>[7:0]
load_data_from_bram.ddr_nn_params.mem<483>[7:0]
load_data_from_bram.ddr_nn_params.mem<484>[7:0]
load_data_from_bram.ddr_nn_params.mem<485>[7:0]
load_data_from_bram.ddr_nn_params.mem<486>[7:0]
load_data_from_bram.ddr_nn_params.mem<487>[7:0]
load_data_from_bram.ddr_nn_params.mem<488>[7:0]
load_data_from_bram.ddr_nn_params.mem<489>[7:0]
load_data_from_bram.ddr_nn_params.mem<490>[7:0]
load_data_from_bram.ddr_nn_params.mem<491>[7:0]
load_data_from_bram.ddr_nn_params.mem<492>[7:0]
load_data_from_bram.ddr_nn_params.mem<493>[7:0]
load_data_from_bram.ddr_nn_params.mem<494>[7:0]
load_data_from_bram.ddr_nn_params.mem<495>[7:0]
load_data_from_bram.ddr_nn_params.mem<496>[7:0]
load_data_from_bram.ddr_nn_params.mem<497>[7:0]
load_data_from_bram.ddr_nn_params.mem<498>[7:0]
load_data_from_bram.ddr_nn_params.mem<499>[7:0]
load_data_from_bram.ddr_nn_params.mem<500>[7:0]
load_data_from_bram.ddr_nn_params.mem<501>[7:0]
load_data_from_bram.ddr_nn_params.mem<502>[7:0]
load_data_from_bram.ddr_nn_params.mem<503>[7:0]
load_data_from_bram.ddr_nn_params.mem<504>[7:0]
load_data_from_bram.ddr_nn_params.mem<505>[7:0]
load_data_from_bram.ddr_nn_params.mem<506>[7:0]
load_data_from_bram.ddr_nn_params.mem<507>[7:0]
load_data_from_bram.ddr_nn_params.mem<508>[7:0]
load_data_from_bram.ddr_nn_params.mem<509>[7:0]
load_data_from_bram.ddr_nn_params.mem<510>[7:0]
load_data_from_bram.ddr_nn_params.mem<511>[7:0]
@29
load_data_from_bram.ddr_nn_params.o_axi_arready
@28
load_data_from_bram.ddr_nn_params.o_axi_awready
load_data_from_bram.ddr_nn_params.o_axi_bid
load_data_from_bram.ddr_nn_params.o_axi_bresp[1:0]
load_data_from_bram.ddr_nn_params.o_axi_bvalid
@23
load_data_from_bram.ddr_nn_params.o_axi_rdata[7:0]
@28
load_data_from_bram.ddr_nn_params.o_axi_rid
load_data_from_bram.ddr_nn_params.o_axi_rlast
load_data_from_bram.ddr_nn_params.o_axi_rresp[1:0]
@29
load_data_from_bram.ddr_nn_params.o_axi_rvalid
@28
load_data_from_bram.ddr_nn_params.o_axi_wready
load_data_from_bram.ddr_nn_params.reset
load_data_from_bram.done
load_data_from_bram.enable_skid_buffer[1:0]
load_data_from_bram.error
@29
load_data_from_bram.hardcoded_nn_params.cache_is_full
@28
load_data_from_bram.hardcoded_nn_params.clk
load_data_from_bram.hardcoded_nn_params.ddr_address_range_is_valid
@29
load_data_from_bram.hardcoded_nn_params.i_axi_arready
@28
load_data_from_bram.hardcoded_nn_params.i_axi_awready
load_data_from_bram.hardcoded_nn_params.i_axi_bid
load_data_from_bram.hardcoded_nn_params.i_axi_bresp[1:0]
load_data_from_bram.hardcoded_nn_params.i_axi_bvalid
@23
load_data_from_bram.hardcoded_nn_params.i_axi_rdata[7:0]
@28
load_data_from_bram.hardcoded_nn_params.i_axi_rid
load_data_from_bram.hardcoded_nn_params.i_axi_rlast
load_data_from_bram.hardcoded_nn_params.i_axi_rresp[1:0]
@29
load_data_from_bram.hardcoded_nn_params.i_axi_rvalid
@28
load_data_from_bram.hardcoded_nn_params.i_axi_wready
@22
load_data_from_bram.hardcoded_nn_params.o_axi_araddr[8:0]
@28
load_data_from_bram.hardcoded_nn_params.o_axi_arburst[1:0]
@22
load_data_from_bram.hardcoded_nn_params.o_axi_arcache[3:0]
@28
load_data_from_bram.hardcoded_nn_params.o_axi_arid
@22
load_data_from_bram.hardcoded_nn_params.o_axi_arlen[7:0]
@28
load_data_from_bram.hardcoded_nn_params.o_axi_arlock
load_data_from_bram.hardcoded_nn_params.o_axi_arprot[2:0]
@22
load_data_from_bram.hardcoded_nn_params.o_axi_arqos[3:0]
@28
load_data_from_bram.hardcoded_nn_params.o_axi_arsize[2:0]
@29
load_data_from_bram.hardcoded_nn_params.o_axi_arvalid
@22
load_data_from_bram.hardcoded_nn_params.o_axi_awaddr[8:0]
@28
load_data_from_bram.hardcoded_nn_params.o_axi_awburst[1:0]
@22
load_data_from_bram.hardcoded_nn_params.o_axi_awcache[3:0]
@28
load_data_from_bram.hardcoded_nn_params.o_axi_awid
@22
load_data_from_bram.hardcoded_nn_params.o_axi_awlen[7:0]
@28
load_data_from_bram.hardcoded_nn_params.o_axi_awlock
load_data_from_bram.hardcoded_nn_params.o_axi_awprot[2:0]
@22
load_data_from_bram.hardcoded_nn_params.o_axi_awqos[3:0]
@28
load_data_from_bram.hardcoded_nn_params.o_axi_awsize[2:0]
load_data_from_bram.hardcoded_nn_params.o_axi_awvalid
load_data_from_bram.hardcoded_nn_params.o_axi_bready
@29
load_data_from_bram.hardcoded_nn_params.o_axi_rready
@22
load_data_from_bram.hardcoded_nn_params.o_axi_wdata[7:0]
@28
load_data_from_bram.hardcoded_nn_params.o_axi_wlast
load_data_from_bram.hardcoded_nn_params.o_axi_wstrb
load_data_from_bram.hardcoded_nn_params.o_axi_wvalid
load_data_from_bram.hardcoded_nn_params.reset
@22
load_data_from_bram.nn_features_cache.cache<0>[7:0]
load_data_from_bram.nn_features_cache.cache<1>[7:0]
load_data_from_bram.nn_features_cache.cache<2>[7:0]
load_data_from_bram.nn_features_cache.cache<3>[7:0]
@28
load_data_from_bram.nn_features_cache.cache_index[1:0]
load_data_from_bram.nn_features_cache.clk
load_data_from_bram.nn_features_cache.empty
load_data_from_bram.nn_features_cache.full
load_data_from_bram.nn_features_cache.i_addr[1:0]
@22
load_data_from_bram.nn_features_cache.i_data[7:0]
@29
load_data_from_bram.nn_features_cache.i_data_is_valid
@22
load_data_from_bram.nn_features_cache.o_data[7:0]
@28
load_data_from_bram.nn_features_cache.o_data_is_valid
load_data_from_bram.nn_features_cache.reset
@22
load_data_from_bram.nn_params_cache.cache<0>[7:0]
load_data_from_bram.nn_params_cache.cache<1>[7:0]
load_data_from_bram.nn_params_cache.cache<2>[7:0]
load_data_from_bram.nn_params_cache.cache<3>[7:0]
@28
load_data_from_bram.nn_params_cache.cache_index[1:0]
load_data_from_bram.nn_params_cache.clk
load_data_from_bram.nn_params_cache.empty
load_data_from_bram.nn_params_cache.full
load_data_from_bram.nn_params_cache.i_addr[1:0]
@22
load_data_from_bram.nn_params_cache.i_data[7:0]
@29
load_data_from_bram.nn_params_cache.i_data_is_valid
@22
load_data_from_bram.nn_params_cache.o_data[7:0]
@28
load_data_from_bram.nn_params_cache.o_data_is_valid
load_data_from_bram.nn_params_cache.reset
@22
load_data_from_bram.num_of_bram_data_read_transaction[8:0]
@28
load_data_from_bram.reset
load_data_from_bram.skid_buffer_is_empty[1:0]
load_data_from_bram.skid_buffer_is_full[1:0]
load_data_from_bram.skid_feature.clk
@22
load_data_from_bram.skid_feature.data<0>[7:0]
@29
load_data_from_bram.skid_feature.dequeue_en
@23
load_data_from_bram.skid_feature.dequeue_value[7:0]
@29
load_data_from_bram.skid_feature.empty
load_data_from_bram.skid_feature.enqueue_en
@23
load_data_from_bram.skid_feature.enqueue_value[7:0]
@28
load_data_from_bram.skid_feature.f_first_addr_in_fifo
load_data_from_bram.skid_feature.f_second_addr_in_fifo
load_data_from_bram.skid_feature.f_state[1:0]
load_data_from_bram.skid_feature.first_clock_had_passed
@22
load_data_from_bram.skid_feature.first_data[7:0]
@29
load_data_from_bram.skid_feature.full
@28
load_data_from_bram.skid_feature.rd
load_data_from_bram.skid_feature.reset
@22
load_data_from_bram.skid_feature.second_data[7:0]
@28
load_data_from_bram.skid_feature.wr
@22
load_data_from_bram.skid_output_data<0>[7:0]
load_data_from_bram.skid_output_data<1>[7:0]
@28
load_data_from_bram.skid_param.clk
@22
load_data_from_bram.skid_param.data<0>[7:0]
@29
load_data_from_bram.skid_param.dequeue_en
@23
load_data_from_bram.skid_param.dequeue_value[7:0]
@29
load_data_from_bram.skid_param.empty
load_data_from_bram.skid_param.enqueue_en
@23
load_data_from_bram.skid_param.enqueue_value[7:0]
@28
load_data_from_bram.skid_param.f_first_addr_in_fifo
load_data_from_bram.skid_param.f_second_addr_in_fifo
load_data_from_bram.skid_param.f_state[1:0]
load_data_from_bram.skid_param.first_clock_had_passed
@22
load_data_from_bram.skid_param.first_data[7:0]
@29
load_data_from_bram.skid_param.full
@28
load_data_from_bram.skid_param.rd
load_data_from_bram.skid_param.reset
@22
load_data_from_bram.skid_param.second_data[7:0]
@28
load_data_from_bram.skid_param.wr
load_data_from_bram.valid_read_response_contains_error_messages[1:0]
load_data_from_bram.valid_read_response_does_not_contain_error_messages[1:0]
[pattern_trace] 1
[pattern_trace] 0
`timescale 1ns/1ns
module load_data_from_bram_tb();
reg clk, reset;
wire [1:0] done;
wire [1:0] error;
load_data_from_bram ldfb (.clk(clk), .reset(reset), .done(done), .error(error));
initial begin
$dumpfile("load_data_from_bram_tb.vcd");
$dumpvars(0, load_data_from_bram_tb);
clk = 0;
reset = 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
reset = 1;
@(posedge clk);
@(posedge clk);
reset = 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
$finish;
end
localparam clk_period = 5;
always @(*) #clk_period clk <= !clk;
endmodule
`define LOOPBACK 1
module read_instructions(clk, reset,
i_axi_awready, o_axi_awid, o_axi_awaddr, o_axi_awlen, o_axi_awsize, o_axi_awburst,
o_axi_awlock, o_axi_awcache, o_axi_awprot, o_axi_awqos, o_axi_awvalid,
i_axi_wready, o_axi_wdata, o_axi_wstrb, o_axi_wlast, o_axi_wvalid,
i_axi_bid, i_axi_bresp, i_axi_bvalid, o_axi_bready,
i_axi_arready, o_axi_arid, o_axi_araddr, o_axi_arlen, o_axi_arsize, o_axi_arburst,
o_axi_arlock, o_axi_arcache, o_axi_arprot, o_axi_arqos, o_axi_arvalid,
i_axi_rid, i_axi_rresp, i_axi_rvalid, i_axi_rdata, i_axi_rlast, o_axi_rready);
`ifdef FORMAL
// AXI Address width (log wordsize) for DDR
parameter C_AXI_ADDR_WIDTH = 9; // just for random test, need to change for actual neural network
parameter C_AXI_DATA_WIDTH = 8; // related to AxSIZE
parameter C_SIZE_OF_CACHE = 4; // for storing weights and biases parameters of neural network
`else
// AXI Address width (log wordsize) for DDR
parameter C_AXI_ADDR_WIDTH = 12; // just for random test, need to change for actual neural network
parameter C_AXI_DATA_WIDTH = 128; // related to AxSIZE
parameter C_SIZE_OF_CACHE = 64; // for storing weights and biases parameters of neural network
`endif
parameter C_AXI_ID_WIDTH = 1;
localparam NUM_OF_BITS_PER_BYTES = 8;
localparam INCR_BURST_TYPE = 2'b01; // AxBURST[2:0] , see 'burst type' section in AXI spec
// AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers.
// Support for all other burst types in AXI4 remains at 1 to 16 transfers.
// for wrapping bursts, the burst length must be 2, 4, 8, or 16
// a burst must not cross a 4KB address boundary
// early termination of bursts is not supported
localparam MAX_BURST_LENGTH = 255;
localparam BURST_SIZE_ENCODING_WIDTH = 3; // AxSIZE[2:0] , see 'burst size' section in AXI spec
localparam SUBWORD_SMALLEST_UNIT = 8; // smallest granularity in AXI protocol : 8 bit
localparam PROT_BITWIDTH = 3;
localparam QOS_BITWIDTH = 4;
localparam CACHE_BITWIDTH = 4;
input clk, reset;
// AXI write address channel signals
input wire i_axi_awready; // Slave is ready to accept
output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid; // Write ID
output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr; // Write address
output wire [$clog2(MAX_BURST_LENGTH)-1:0] o_axi_awlen; // Write Burst Length
output wire [BURST_SIZE_ENCODING_WIDTH-1:0] o_axi_awsize; // Write Burst size
output wire [1:0] o_axi_awburst; // Write Burst type
output wire [0:0] o_axi_awlock; // Write lock type
output wire [CACHE_BITWIDTH-1:0] o_axi_awcache; // Write Cache type
output wire [PROT_BITWIDTH-1:0] o_axi_awprot; // Write Protection type
output wire [QOS_BITWIDTH-1:0] o_axi_awqos; // Write Quality of Svc
output reg o_axi_awvalid; // Write address valid
// AXI write data channel signals
input wire i_axi_wready; // Write data ready
output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata; // Write data
output reg [C_AXI_DATA_WIDTH/SUBWORD_SMALLEST_UNIT-1:0] o_axi_wstrb; // Write strobes
output reg o_axi_wlast; // Last write transaction
output reg o_axi_wvalid; // Write valid
// AXI write response channel signals
/* verilator lint_off UNUSED */
input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid; // Response ID
/* verilator lint_on UNUSED */
input wire [1:0] i_axi_bresp; // Write response
input wire i_axi_bvalid; // Write reponse valid
output wire o_axi_bready; // Response ready
// AXI read address channel signals
input wire i_axi_arready; // Read address ready
output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid; // Read ID
output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr; // Read address
output wire [$clog2(MAX_BURST_LENGTH)-1:0] o_axi_arlen; // Read Burst Length
output wire [BURST_SIZE_ENCODING_WIDTH-1:0] o_axi_arsize; // Read Burst size
output wire [1:0] o_axi_arburst; // Read Burst type
output wire [0:0] o_axi_arlock; // Read lock type
output wire [CACHE_BITWIDTH-1:0] o_axi_arcache; // Read Cache type
output wire [PROT_BITWIDTH-1:0] o_axi_arprot; // Read Protection type
output wire [QOS_BITWIDTH-1:0] o_axi_arqos; // Read Quality of Svc
output reg o_axi_arvalid; // Read address valid
/* verilator lint_off UNUSED */
// AXI read data channel signals
input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid; // Response ID
/* verilator lint_on UNUSED */
input wire [1:0] i_axi_rresp; // Read response
input wire i_axi_rvalid; // Read reponse valid
input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata; // Read data
input wire i_axi_rlast; // Read last
output wire o_axi_rready; // Read Response ready
always @(posedge clk)
begin
if(reset) o_axi_wstrb <= 0;
// burst alignment mechanism, see https://i.imgur.com/jKbzfFo.png
// o_axi_wstrb <= (~0) << (o_axi_awaddr % (o_axi_awlen+1));
// all the bracket variables are for removing verilator width warnings
else o_axi_wstrb <= ((~0) << (o_axi_awaddr %
{{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}},
(o_axi_awlen+1'b1)}));
end
wire write_response_is_ok = i_axi_bvalid && ((i_axi_bresp == 'b00) || (i_axi_bresp == 'b01));
// need to implement data re-transmission
wire write_response_is_not_ok = i_axi_bvalid && !((i_axi_bresp == 'b00) || (i_axi_bresp == 'b01));
always @(posedge clk)
begin
if(reset)
begin
o_axi_wvalid <= 0;
end
else if(!(o_axi_wvalid && !i_axi_wready))
begin
// Note that both o_axi_awsize , o_axi_awlen are of hardware constants, so no multiply hardware
// since this is for testing, WDATA just uses some values up to the total size of the write address space
// Note: a master must not wait for AWREADY to be asserted before driving WVALID
o_axi_wvalid <= (o_axi_wlast) ? 0 :
(o_axi_wdata < (o_axi_awsize*o_axi_awlen));
end
end
wire ddr_write_address_range_is_valid = (o_axi_awaddr < (1 << C_AXI_ADDR_WIDTH));
always @(posedge clk)
begin
if(reset) o_axi_awvalid <= 0;
// AXI specification: A3.3.1 Dependencies between channel handshake signal
// the VALID signal of the AXI interface sending information must not be dependent on
// the READY signal of the AXI interface receiving that information
// this is to prevent deadlock
// since AXI slave could wait for i_axi_awvalid to be true before setting o_axi_awready true.
// Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
// Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
// VALID signal needs to be set (initially) independent of READY signal,
// and then only ever adjusted if !(VALID && !READY)
// Note: the master must not wait for the slave to assert AWREADY before asserting AWVALID
// Note: (!(o_axi_awvalid && !i_axi_awready)) == (!awvalid || awready)
// == (!awvalid || (awvalid && awready)).
// it means "no transaction in progress or transaction accepted"
else if(!(o_axi_awvalid && !i_axi_awready))
o_axi_awvalid <= /*i_axi_awready &&*/ (ddr_write_address_range_is_valid);
end
wire write_transaction_is_accepted = (o_axi_wvalid) && (i_axi_wready);
wire address_write_transaction_is_accepted = (o_axi_awvalid) && (i_axi_awready);
always @(posedge clk)
begin
if(reset)
begin
o_axi_awaddr <= 0;
//o_axi_wdata <= 0;
end
else if(address_write_transaction_is_accepted)
begin
o_axi_awaddr <= o_axi_awaddr +
{{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, (o_axi_awlen+1'b1)};
//o_axi_wdata <= o_axi_wdata + 1;
end
end
always @(posedge clk)
begin
if(reset)
begin
//o_axi_awaddr <= 0;
o_axi_wdata <= 0;
end
else if(write_transaction_is_accepted)
begin
//o_axi_awaddr <= o_axi_awaddr + 1;
o_axi_wdata <= o_axi_wdata + 1;
end
end
`ifdef LOOPBACK
wire data_had_been_written_successfully = write_response_is_ok && o_axi_bready;
wire read_address_contains_loopback_data = data_had_been_written_successfully &&
(o_axi_awaddr >= (o_axi_araddr + {{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, o_axi_awlen}));
`endif
wire ddr_read_address_range_is_valid = (o_axi_araddr < (1 << C_AXI_ADDR_WIDTH));
always @(posedge clk)
begin
if(reset) o_axi_arvalid <= 0;
// AXI specification: A3.3.1 Dependencies between channel handshake signal
// the VALID signal of the AXI interface sending information must not be dependent on
// the READY signal of the AXI interface receiving that information
// this is to prevent deadlock
// since AXI slave could wait for i_axi_arvalid to be true before setting o_axi_arready true.
// Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
// Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
// VALID signal needs to be set (initially) independent of READY signal,
// and then only ever adjusted if !(VALID && !READY)
// Note: the master must not wait for the slave to assert ARREADY before asserting ARVALID
// Note: (!(o_axi_arvalid && !i_axi_arready)) == (!arvalid || arready)
// == (!arvalid || (arvalid && arready)).
// it means "no transaction in progress or transaction accepted"
// Note: o_axi_rready is used for backpressure mechanism
else if(!(o_axi_arvalid && !i_axi_arready))
`ifdef LOOPBACK
o_axi_arvalid <= /*i_axi_arready &&*/ (ddr_read_address_range_is_valid) &&
(read_address_contains_loopback_data) &&
(o_axi_bready && i_axi_bvalid && write_response_is_ok);
`else
o_axi_arvalid <= /*i_axi_arready &&*/ (ddr_read_address_range_is_valid);
`endif
end
reg [$clog2(MAX_BURST_LENGTH)-1:0] num_of_write_transactions;
always @(posedge clk)
begin
if(reset) num_of_write_transactions <= 0;
else if(o_axi_wvalid && i_axi_wready)
num_of_write_transactions <= (o_axi_wlast) ? 0 : num_of_write_transactions + 1;
end
always @(posedge clk)
begin
if(reset) o_axi_wlast <= 0;
else o_axi_wlast <= (num_of_write_transactions == (o_axi_awlen - 1));
end
//assign o_axi_wlast = 0;
assign o_axi_awid = 0;
assign o_axi_awlen = 15; // each burst has (Burst_Length = AxLEN[7:0] + 1) data transfers
/* verilator lint_off WIDTH */
assign o_axi_awsize = $clog2(C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES); // 128 bits (16 bytes) of data when AxSIZE[2:0] = 3'b100
// Burst_Length = AxLEN[7:0] + 1, to accommodate the extended burst length of the INCR burst type in AXI4.
/* verilator lint_on WIDTH */
assign o_axi_awburst = INCR_BURST_TYPE;
assign o_axi_awlock = 0;
assign o_axi_awcache = 0;
assign o_axi_awprot = 0;
assign o_axi_awqos = 0; // no priority or QoS concept
assign o_axi_arqos = 0; // no priority or QoS concept
assign o_axi_arburst = INCR_BURST_TYPE;
/* verilator lint_off WIDTH */
assign o_axi_arsize = $clog2(C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES); // 128 bits (16 bytes) of data when AxSIZE[2:0] = 3'b100
// Burst_Length = AxLEN[7:0] + 1, to accommodate the extended burst length of the INCR burst type in AXI4.
/* verilator lint_on WIDTH */
assign o_axi_arlen = 15; // each burst has (Burst_Length = AxLEN[7:0] + 1) data transfers
assign o_axi_arprot = 3'b010; // {data access, non-secure access, unprivileged access}
assign o_axi_arlock = 0; // AXI4 does not support locked transactions.
assign o_axi_arcache = 0; // mostly used for HPS (hard processor system) such as ARM hard CPU IP
assign o_axi_arid = 0; // there is one AXI slave which is the DDR memory (A, B, or C) ?
// what situations will render data requester (AXI master) busy to receive read response ??
// such as AXI interconnect where arbitration will fail to acquire the data transfer priority
// such as the internal cache storage to store the data from external DDR memory is now full
// So, let's use a random value that is $anyseq in formal verification
assign o_axi_rready = (reset) ? 1 : `ifdef FORMAL $anyseq `else (!cache_is_full) `endif;
// The master can assert BREADY before BVALID is asserted.
assign o_axi_bready = (reset) ? 1 : `ifdef FORMAL $anyseq `else (i_axi_bvalid) `endif;
wire address_read_transaction_is_accepted = (o_axi_arvalid) && (i_axi_arready);
reg [C_AXI_ADDR_WIDTH-1:0] araddr;
always @(posedge clk)
begin
if(reset) araddr <= {{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, (o_axi_awlen+1'b1)};
else if(address_read_transaction_is_accepted)
araddr <= araddr + {{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, (o_axi_awlen+1'b1)};
end
always @(posedge clk)
begin
if(reset) o_axi_araddr <= 0;
// When ARVALID & ARREADY are both high the next ARADDR can be generated
// because the current address for the current transfer is now complete (ARVALID & ARREADY).
else if(address_read_transaction_is_accepted)
o_axi_araddr <= araddr; // increments DDR address to read instructions from
end
/* verilator lint_off UNUSED */
wire arm_write_param_enable;
wire [C_AXI_DATA_WIDTH-1:0] arm_write_param_data;
wire cache_is_empty;
wire [$clog2(C_SIZE_OF_CACHE)-1:0] cache_address_for_reading;
assign cache_address_for_reading = 0; // for testing only
/* verilator lint_on UNUSED */
wire valid_read_response_does_not_contain_error_messages = i_axi_rvalid && (i_axi_rresp == 0);
wire cache_is_full; // needed since C_SIZE_OF_CACHE is always smaller than SIZE_OF_DDR_MEMORY
// for storing neural network parameters (weights and biases) at destination side,
// so this bram acts as intermediate cache (much smaller size than DDR memory) for the neural network
// no need AXI protocol in order to save logic usage, thus lesser area and power consumption
cache_controller #(.C_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_SIZE_OF_CACHE(C_SIZE_OF_CACHE)) nn_feature_cache
(
.clk(clk), .reset(reset),
.i_data(i_axi_rdata), // NN params coming from DDR memory
.i_data_is_valid
((o_axi_rready && valid_read_response_does_not_contain_error_messages)), // DDR data is valid
.i_addr(cache_address_for_reading),
.full(cache_is_full), // NN params cache is full
.o_data(arm_write_param_data), // NN params going to neural network layers
.o_data_is_valid(arm_write_param_enable), // neural network layers to start another intermediate computations
.empty(cache_is_empty) // no NN params to feed into the neural network layers
);
`ifdef FORMAL
localparam SIXTH_ADDRESS_IN_REQUEST = 6;
initial assume(reset);
reg first_clock_had_passed = 0;
always @(posedge clk) first_clock_had_passed <= 1;
always @(posedge clk)
if(first_clock_had_passed)
cover((o_axi_araddr > SIXTH_ADDRESS_IN_REQUEST) && address_read_transaction_is_accepted &&
$past(i_axi_arready) && $past(o_axi_rready) && !o_axi_rready);
`endif
endmodule
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
module skid_buffer
#(
`ifdef FORMAL
parameter WIDTH = 4,
`else
parameter WIDTH = 128,
`endif
parameter SIZE = 2
//parameter ALMOST_FULL_THRESHOLD = SIZE,
//parameter ALMOST_EMPTY_THRESHOLD = 1
)
(input clk,
input reset,
output full,
//output reg almost_full,
input enqueue_en,
input [WIDTH - 1:0] enqueue_value,
output empty,
//output reg almost_empty,
input dequeue_en,
output [WIDTH - 1:0] dequeue_value);
parameter ADDR_WIDTH = $clog2(SIZE);
// read and write pointers need one extra MSB bit to differentiate between empty and full
// you can confirm this using count = wr_addr - rd_addr;
reg[ADDR_WIDTH:0] rd_addr;
reg[ADDR_WIDTH:0] wr_addr;
reg[WIDTH - 1:0] data[SIZE - 1:0];
`ifdef FORMAL
initial rd_addr = 0;
initial wr_addr = 0;
`endif
wire[ADDR_WIDTH:0] count = wr_addr - rd_addr;
//assign almost_full = count >= (ADDR_WIDTH + 1)'(ALMOST_FULL_THRESHOLD);
//assign almost_empty = count <= (ADDR_WIDTH + 1)'(ALMOST_EMPTY_THRESHOLD);
assign full = (count == SIZE[ADDR_WIDTH:0]);
assign empty = count == 0;
assign dequeue_value = data[rd_addr[ADDR_WIDTH-1:0]]; // passed verilator width warning
integer index;
always @(posedge clk)
begin
if (reset)
begin
rd_addr <= 0;
wr_addr <= 0;
for(index=0; index<SIZE; index=index+1)
data[index] <= 0;
end
else begin
// https://twitter.com/zipcpu/status/1143134086950789120
// if enqueue_en and dequeue_en and full at the same time, nothing is added, one item is removed,
// but count is not modified. Same for empty.
// https://zipcpu.com/blog/2017/07/29/fifo.html