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Last active Apr 24, 2020

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* ARM PrimeCell Color LCD Controller PL110/PL111
See also Documentation/devicetree/bindings/arm/primecell.txt
Required properties:
- compatible: must be one of:
"arm,pl110", "arm,primecell"
"arm,pl111", "arm,primecell"
- reg: base address and size of the control registers block
- interrupt-names: either the single entry "combined" representing a
combined interrupt output (CLCDINTR), or the four entries
"mbe", "vcomp", "lnbu", "fuf" representing the individual
CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts
- interrupts: contains an interrupt specifier for each entry in
interrupt-names
- clock-names: should contain "clcdclk" and "apb_pclk"
- clocks: contains phandle and clock specifier pairs for the entries
in the clock-names property. See
Documentation/devicetree/bindings/clock/clock-bindings.txt
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
to be used for the framebuffer; if not present, the framebuffer
may be located anywhere in the memory
- max-memory-bandwidth: maximum bandwidth in bytes per second that the
cell's memory interface can handle; if not present, the memory
interface is fast enough to handle all possible video modes
Required sub-nodes:
- port: describes LCD panel signals, following the common binding
for video transmitter interfaces; see
Documentation/devicetree/bindings/media/video-interfaces.txt;
when it is a TFT panel, the port's endpoint must define the
following property:
- arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
defining the way CLD pads are wired up; first value
contains index of the "CLD" external pin (pad) used
as R0 (first bit of the red component), second value
index of the pad used as G0, third value index of the
pad used as B0, see also "LCD panel signal multiplexing
details" paragraphs in the PL110/PL111 Technical
Reference Manuals; this implicitly defines available
color modes, for example:
- PL111 TFT 4:4:4 panel:
arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
- PL110 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
- PL111 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
- PL111 TFT 5:6:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
- PL110 and PL111 TFT 8:8:8 panel:
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
Example:
clcd@10020000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x10020000 0x1000>;
interrupt-names = "combined";
interrupts = <0 44 4>;
clocks = <&oscclk1>, <&oscclk2>;
clock-names = "clcdclk", "apb_pclk";
max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
port {
clcd_pads: endpoint {
remote-endpoint = <&clcd_panel>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
};
panel {
compatible = "panel-dpi";
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <40>;
hfront-porch = <24>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <2>;
};
};
/dts-v1/;
/ {
#address-cells = < 0x01 >;
#size-cells = < 0x01 >;
model = "ARM Versatile PB";
compatible = "arm,versatile-pb";
interrupt-parent = < 0x01 >;
chosen {
stdout-path = "/amba/uart@101f1000";
};
aliases {
serial0 = "/amba/uart@101f1000";
serial1 = "/amba/uart@101f2000";
serial2 = "/amba/uart@101f3000";
i2c0 = "/i2c@10002000";
};
memory {
device_type = "memory";
reg = < 0x00 0x8000000 >;
};
xtal24mhz@24M {
#clock-cells = < 0x00 >;
compatible = "fixed-clock";
clock-frequency = < 0x16e3600 >;
linux,phandle = < 0x02 >;
phandle = < 0x02 >;
};
bridge {
compatible = "dumb-vga-dac";
ports {
#address-cells = < 0x01 >;
#size-cells = < 0x00 >;
port@0 {
reg = < 0x00 >;
endpoint {
remote-endpoint = < 0x07 >;
phandle = < 0x0a >;
};
};
port@1 {
reg = < 0x01 >;
endpoint {
remote-endpoint = < 0x08 >;
phandle = < 0x09 >;
};
};
};
};
vga {
compatible = "vga-connector";
port {
endpoint {
remote-endpoint = < 0x09 >;
phandle = < 0x08 >;
};
};
};
core-module@10000000 {
compatible = "arm,core-module-versatile\0syscon\0simple-mfd";
reg = < 0x10000000 0x200 >;
led@08.0 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x01 >;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x02 >;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x04 >;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x08 >;
label = "versatile:3";
default-state = "off";
};
led@08.4 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x10 >;
label = "versatile:4";
default-state = "off";
};
led@08.5 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x20 >;
label = "versatile:5";
default-state = "off";
};
led@08.6 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x40 >;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x80 >;
label = "versatile:7";
default-state = "off";
};
cm_aux_osc@24M {
#clock-cells = < 0x00 >;
compatible = "arm,versatile-cm-auxosc";
clocks = < 0x02 >;
linux,phandle = < 0x04 >;
phandle = < 0x04 >;
};
timclk@1M {
#clock-cells = < 0x00 >;
compatible = "fixed-factor-clock";
clock-div = < 0x18 >;
clock-mult = < 0x01 >;
clocks = < 0x02 >;
linux,phandle = < 0x05 >;
phandle = < 0x05 >;
};
pclk@24M {
#clock-cells = < 0x00 >;
compatible = "fixed-factor-clock";
clock-div = < 0x01 >;
clock-mult = < 0x01 >;
clocks = < 0x02 >;
linux,phandle = < 0x03 >;
phandle = < 0x03 >;
};
};
flash@34000000 {
compatible = "arm,versatile-flash\0cfi-flash";
reg = < 0x34000000 0x4000000 >;
bank-width = < 0x04 >;
};
i2c@10002000 {
#address-cells = < 0x01 >;
#size-cells = < 0x00 >;
compatible = "arm,versatile-i2c";
reg = < 0x10002000 0x1000 >;
rtc@68 {
compatible = "dallas,ds1338";
reg = < 0x68 >;
};
};
net@10010000 {
compatible = "smsc,lan91c111";
reg = < 0x10010000 0x10000 >;
interrupts = < 0x19 >;
};
lcd@10008000 {
compatible = "arm,versatile-lcd";
reg = < 0x10008000 0x1000 >;
};
amba {
compatible = "simple-bus";
#address-cells = < 0x01 >;
#size-cells = < 0x01 >;
ranges;
intc@10140000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = < 0x01 >;
reg = < 0x10140000 0x1000 >;
clear-mask = < 0xffffffff >;
valid-mask = < 0xffffffff >;
linux,phandle = < 0x01 >;
phandle = < 0x01 >;
};
intc@10003000 {
compatible = "arm,versatile-sic";
interrupt-controller;
#interrupt-cells = < 0x01 >;
reg = < 0x10003000 0x1000 >;
interrupt-parent = < 0x01 >;
interrupts = < 0x1f >;
clear-mask = < 0xffffffff >;
valid-mask = < 0x7fe003ff >;
linux,phandle = < 0x06 >;
phandle = < 0x06 >;
};
dma@10130000 {
compatible = "arm,pl081\0arm,primecell";
reg = < 0x10130000 0x1000 >;
interrupts = < 0x11 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
uart@101f1000 {
compatible = "arm,pl011\0arm,primecell";
reg = < 0x101f1000 0x1000 >;
interrupts = < 0x0c >;
clocks = < 0x02 0x03 >;
clock-names = "uartclk\0apb_pclk";
};
uart@101f2000 {
compatible = "arm,pl011\0arm,primecell";
reg = < 0x101f2000 0x1000 >;
interrupts = < 0x0d >;
clocks = < 0x02 0x03 >;
clock-names = "uartclk\0apb_pclk";
};
uart@101f3000 {
compatible = "arm,pl011\0arm,primecell";
reg = < 0x101f3000 0x1000 >;
interrupts = < 0x0e >;
clocks = < 0x02 0x03 >;
clock-names = "uartclk\0apb_pclk";
};
smc@10100000 {
compatible = "arm,primecell";
reg = < 0x10100000 0x1000 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
mpmc@10110000 {
compatible = "arm,primecell";
reg = < 0x10110000 0x1000 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
display@10120000 {
compatible = "arm,pl110\0arm,primecell";
reg = < 0x10120000 0x1000 >;
interrupts = < 0x10 >;
clocks = < 0x04 0x03 >;
clock-names = "clcdclk\0apb_pclk";
port {
endpoint {
remote-endpoint = < 0x0a >;
arm,pl11x,tft-r0g0b0-pads = < 0x00 0x08 0x10 >;
phandle = < 0x07 >;
};
};
};
sctl@101e0000 {
compatible = "arm,primecell";
reg = < 0x101e0000 0x1000 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
watchdog@101e1000 {
compatible = "arm,primecell";
reg = < 0x101e1000 0x1000 >;
interrupts = < 0x00 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
timer@101e2000 {
compatible = "arm,sp804\0arm,primecell";
reg = < 0x101e2000 0x1000 >;
interrupts = < 0x04 >;
clocks = < 0x05 0x05 0x03 >;
clock-names = "timer0\0timer1\0apb_pclk";
};
timer@101e3000 {
compatible = "arm,sp804\0arm,primecell";
reg = < 0x101e3000 0x1000 >;
interrupts = < 0x05 >;
clocks = < 0x05 0x05 0x03 >;
clock-names = "timer0\0timer1\0apb_pclk";
};
gpio@101e4000 {
compatible = "arm,pl061\0arm,primecell";
reg = < 0x101e4000 0x1000 >;
gpio-controller;
interrupts = < 0x06 >;
#gpio-cells = < 0x02 >;
interrupt-controller;
#interrupt-cells = < 0x02 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
gpio@101e5000 {
compatible = "arm,pl061\0arm,primecell";
reg = < 0x101e5000 0x1000 >;
interrupts = < 0x07 >;
gpio-controller;
#gpio-cells = < 0x02 >;
interrupt-controller;
#interrupt-cells = < 0x02 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
rtc@101e8000 {
compatible = "arm,pl030\0arm,primecell";
reg = < 0x101e8000 0x1000 >;
interrupts = < 0x0a >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
sci@101f0000 {
compatible = "arm,primecell";
reg = < 0x101f0000 0x1000 >;
interrupts = < 0x0f >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
ssp@101f4000 {
compatible = "arm,pl022\0arm,primecell";
reg = < 0x101f4000 0x1000 >;
interrupts = < 0x0b >;
clocks = < 0x02 0x03 >;
clock-names = "SSPCLK\0apb_pclk";
};
fpga {
compatible = "arm,versatile-fpga\0simple-bus";
#address-cells = < 0x01 >;
#size-cells = < 0x01 >;
ranges = < 0x00 0x10000000 0x10000 >;
sysreg@0 {
compatible = "arm,versatile-sysreg\0syscon";
reg = < 0x00 0x1000 >;
};
aaci@4000 {
compatible = "arm,primecell";
reg = < 0x4000 0x1000 >;
interrupts = < 0x18 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
mmc@5000 {
compatible = "arm,pl180\0arm,primecell";
reg = < 0x5000 0x1000 >;
interrupts-extended = < 0x06 0x16 0x06 0x17 >;
clocks = < 0x02 0x03 >;
clock-names = "mclk\0apb_pclk";
};
kmi@6000 {
compatible = "arm,pl050\0arm,primecell";
reg = < 0x6000 0x1000 >;
interrupt-parent = < 0x06 >;
interrupts = < 0x03 >;
clocks = < 0x02 0x03 >;
clock-names = "KMIREFCLK\0apb_pclk";
};
kmi@7000 {
compatible = "arm,pl050\0arm,primecell";
reg = < 0x7000 0x1000 >;
interrupt-parent = < 0x06 >;
interrupts = < 0x04 >;
clocks = < 0x02 0x03 >;
clock-names = "KMIREFCLK\0apb_pclk";
};
uart@9000 {
compatible = "arm,pl011\0arm,primecell";
reg = < 0x9000 0x1000 >;
interrupt-parent = < 0x06 >;
interrupts = < 0x06 >;
clocks = < 0x02 0x03 >;
clock-names = "uartclk\0apb_pclk";
};
sci@a000 {
compatible = "arm,primecell";
reg = < 0xa000 0x1000 >;
interrupt-parent = < 0x06 >;
interrupts = < 0x05 >;
clocks = < 0x02 >;
clock-names = "apb_pclk";
};
mmc@b000 {
compatible = "arm,pl180\0arm,primecell";
reg = < 0xb000 0x1000 >;
interrupt-parent = < 0x06 >;
interrupts = < 0x01 0x02 >;
clocks = < 0x02 0x03 >;
clock-names = "mclk\0apb_pclk";
};
};
gpio@101e6000 {
compatible = "arm,pl061\0arm,primecell";
reg = < 0x101e6000 0x1000 >;
interrupts = < 0x08 >;
gpio-controller;
#gpio-cells = < 0x02 >;
interrupt-controller;
#interrupt-cells = < 0x02 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
gpio@101e7000 {
compatible = "arm,pl061\0arm,primecell";
reg = < 0x101e7000 0x1000 >;
interrupts = < 0x09 >;
gpio-controller;
#gpio-cells = < 0x02 >;
interrupt-controller;
#interrupt-cells = < 0x02 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
pci@10001000 {
compatible = "arm,versatile-pci";
device_type = "pci";
reg = < 0x10001000 0x1000 0x41000000 0x10000 0x42000000 0x100000 >;
bus-range = < 0x00 0xff >;
#address-cells = < 0x03 >;
#size-cells = < 0x02 >;
#interrupt-cells = < 0x01 >;
ranges = < 0x1000000 0x00 0x00 0x43000000 0x00 0x10000 0x2000000 0x00 0x50000000 0x50000000 0x00 0x10000000 0x42000000 0x00 0x60000000 0x60000000 0x00 0x10000000 >;
interrupt-map-mask = < 0x1800 0x00 0x00 0x07 >;
interrupt-map = < 0x1800 0x00 0x00 0x01 0x06 0x1c 0x1800 0x00 0x00 0x02 0x06 0x1d 0x1800 0x00 0x00 0x03 0x06 0x1e 0x1800 0x00 0x00 0x04 0x06 0x1b 0x1000 0x00 0x00 0x01 0x06 0x1b 0x1000 0x00 0x00 0x02 0x06 0x1c 0x1000 0x00 0x00 0x03 0x06 0x1d 0x1000 0x00 0x00 0x04 0x06 0x1e 0x800 0x00 0x00 0x01 0x06 0x1e 0x800 0x00 0x00 0x02 0x06 0x1b 0x800 0x00 0x00 0x03 0x06 0x1c 0x800 0x00 0x00 0x04 0x06 0x1d 0x00 0x00 0x00 0x01 0x06 0x1d 0x00 0x00 0x00 0x02 0x06 0x1e 0x00 0x00 0x00 0x03 0x06 0x1b 0x00 0x00 0x00 0x04 0x06 0x1c >;
};
};
};
/dts-v1/;
/ {
#address-cells = < 0x01 >;
#size-cells = < 0x01 >;
model = "ARM Versatile PB";
compatible = "arm,versatile-pb";
interrupt-parent = < 0x01 >;
chosen {
stdout-path = "/amba/uart@101f1000";
};
aliases {
serial0 = "/amba/uart@101f1000";
serial1 = "/amba/uart@101f2000";
serial2 = "/amba/uart@101f3000";
i2c0 = "/i2c@10002000";
};
memory {
device_type = "memory";
reg = < 0x00 0x8000000 >;
};
xtal24mhz@24M {
#clock-cells = < 0x00 >;
compatible = "fixed-clock";
clock-frequency = < 0x16e3600 >;
linux,phandle = < 0x02 >;
phandle = < 0x02 >;
};
core-module@10000000 {
compatible = "arm,core-module-versatile\0syscon\0simple-mfd";
reg = < 0x10000000 0x200 >;
led@08.0 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x01 >;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x02 >;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x04 >;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x08 >;
label = "versatile:3";
default-state = "off";
};
led@08.4 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x10 >;
label = "versatile:4";
default-state = "off";
};
led@08.5 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x20 >;
label = "versatile:5";
default-state = "off";
};
led@08.6 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x40 >;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
compatible = "register-bit-led";
offset = < 0x08 >;
mask = < 0x80 >;
label = "versatile:7";
default-state = "off";
};
cm_aux_osc@24M {
#clock-cells = < 0x00 >;
compatible = "arm,versatile-cm-auxosc";
clocks = < 0x02 >;
linux,phandle = < 0x04 >;
phandle = < 0x04 >;
};
timclk@1M {
#clock-cells = < 0x00 >;
compatible = "fixed-factor-clock";
clock-div = < 0x18 >;
clock-mult = < 0x01 >;
clocks = < 0x02 >;
linux,phandle = < 0x05 >;
phandle = < 0x05 >;
};
pclk@24M {
#clock-cells = < 0x00 >;
compatible = "fixed-factor-clock";
clock-div = < 0x01 >;
clock-mult = < 0x01 >;
clocks = < 0x02 >;
linux,phandle = < 0x03 >;
phandle = < 0x03 >;
};
};
flash@34000000 {
compatible = "arm,versatile-flash\0cfi-flash";
reg = < 0x34000000 0x4000000 >;
bank-width = < 0x04 >;
};
i2c@10002000 {
#address-cells = < 0x01 >;
#size-cells = < 0x00 >;
compatible = "arm,versatile-i2c";
reg = < 0x10002000 0x1000 >;
rtc@68 {
compatible = "dallas,ds1338";
reg = < 0x68 >;
};
};
net@10010000 {
compatible = "smsc,lan91c111";
reg = < 0x10010000 0x10000 >;
interrupts = < 0x19 >;
};
lcd@10008000 {
compatible = "arm,versatile-lcd";
reg = < 0x10008000 0x1000 >;
};
amba {
compatible = "simple-bus";
#address-cells = < 0x01 >;
#size-cells = < 0x01 >;
ranges;
intc@10140000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = < 0x01 >;
reg = < 0x10140000 0x1000 >;
clear-mask = < 0xffffffff >;
valid-mask = < 0xffffffff >;
linux,phandle = < 0x01 >;
phandle = < 0x01 >;
};
intc@10003000 {
compatible = "arm,versatile-sic";
interrupt-controller;
#interrupt-cells = < 0x01 >;
reg = < 0x10003000 0x1000 >;
interrupt-parent = < 0x01 >;
interrupts = < 0x1f >;
clear-mask = < 0xffffffff >;
valid-mask = < 0x7fe003ff >;
linux,phandle = < 0x06 >;
phandle = < 0x06 >;
};
dma@10130000 {
compatible = "arm,pl081\0arm,primecell";
reg = < 0x10130000 0x1000 >;
interrupts = < 0x11 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
uart@101f1000 {
compatible = "arm,pl011\0arm,primecell";
reg = < 0x101f1000 0x1000 >;
interrupts = < 0x0c >;
clocks = < 0x02 0x03 >;
clock-names = "uartclk\0apb_pclk";
};
uart@101f2000 {
compatible = "arm,pl011\0arm,primecell";
reg = < 0x101f2000 0x1000 >;
interrupts = < 0x0d >;
clocks = < 0x02 0x03 >;
clock-names = "uartclk\0apb_pclk";
};
uart@101f3000 {
compatible = "arm,pl011\0arm,primecell";
reg = < 0x101f3000 0x1000 >;
interrupts = < 0x0e >;
clocks = < 0x02 0x03 >;
clock-names = "uartclk\0apb_pclk";
};
smc@10100000 {
compatible = "arm,primecell";
reg = < 0x10100000 0x1000 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
mpmc@10110000 {
compatible = "arm,primecell";
reg = < 0x10110000 0x1000 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
display@10120000 {
compatible = "arm,pl110\0arm,primecell";
reg = < 0x10120000 0x1000 >;
interrupts = < 0x10 >;
clocks = < 0x04 0x03 >;
clock-names = "clcd\0apb_pclk";
};
sctl@101e0000 {
compatible = "arm,primecell";
reg = < 0x101e0000 0x1000 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
watchdog@101e1000 {
compatible = "arm,primecell";
reg = < 0x101e1000 0x1000 >;
interrupts = < 0x00 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
timer@101e2000 {
compatible = "arm,sp804\0arm,primecell";
reg = < 0x101e2000 0x1000 >;
interrupts = < 0x04 >;
clocks = < 0x05 0x05 0x03 >;
clock-names = "timer0\0timer1\0apb_pclk";
};
timer@101e3000 {
compatible = "arm,sp804\0arm,primecell";
reg = < 0x101e3000 0x1000 >;
interrupts = < 0x05 >;
clocks = < 0x05 0x05 0x03 >;
clock-names = "timer0\0timer1\0apb_pclk";
};
gpio@101e4000 {
compatible = "arm,pl061\0arm,primecell";
reg = < 0x101e4000 0x1000 >;
gpio-controller;
interrupts = < 0x06 >;
#gpio-cells = < 0x02 >;
interrupt-controller;
#interrupt-cells = < 0x02 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
gpio@101e5000 {
compatible = "arm,pl061\0arm,primecell";
reg = < 0x101e5000 0x1000 >;
interrupts = < 0x07 >;
gpio-controller;
#gpio-cells = < 0x02 >;
interrupt-controller;
#interrupt-cells = < 0x02 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
rtc@101e8000 {
compatible = "arm,pl030\0arm,primecell";
reg = < 0x101e8000 0x1000 >;
interrupts = < 0x0a >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
sci@101f0000 {
compatible = "arm,primecell";
reg = < 0x101f0000 0x1000 >;
interrupts = < 0x0f >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
ssp@101f4000 {
compatible = "arm,pl022\0arm,primecell";
reg = < 0x101f4000 0x1000 >;
interrupts = < 0x0b >;
clocks = < 0x02 0x03 >;
clock-names = "SSPCLK\0apb_pclk";
};
fpga {
compatible = "arm,versatile-fpga\0simple-bus";
#address-cells = < 0x01 >;
#size-cells = < 0x01 >;
ranges = < 0x00 0x10000000 0x10000 >;
sysreg@0 {
compatible = "arm,versatile-sysreg\0syscon";
reg = < 0x00 0x1000 >;
};
aaci@4000 {
compatible = "arm,primecell";
reg = < 0x4000 0x1000 >;
interrupts = < 0x18 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
mmc@5000 {
compatible = "arm,pl180\0arm,primecell";
reg = < 0x5000 0x1000 >;
interrupts-extended = < 0x06 0x16 0x06 0x17 >;
clocks = < 0x02 0x03 >;
clock-names = "mclk\0apb_pclk";
};
kmi@6000 {
compatible = "arm,pl050\0arm,primecell";
reg = < 0x6000 0x1000 >;
interrupt-parent = < 0x06 >;
interrupts = < 0x03 >;
clocks = < 0x02 0x03 >;
clock-names = "KMIREFCLK\0apb_pclk";
};
kmi@7000 {
compatible = "arm,pl050\0arm,primecell";
reg = < 0x7000 0x1000 >;
interrupt-parent = < 0x06 >;
interrupts = < 0x04 >;
clocks = < 0x02 0x03 >;
clock-names = "KMIREFCLK\0apb_pclk";
};
uart@9000 {
compatible = "arm,pl011\0arm,primecell";
reg = < 0x9000 0x1000 >;
interrupt-parent = < 0x06 >;
interrupts = < 0x06 >;
clocks = < 0x02 0x03 >;
clock-names = "uartclk\0apb_pclk";
};
sci@a000 {
compatible = "arm,primecell";
reg = < 0xa000 0x1000 >;
interrupt-parent = < 0x06 >;
interrupts = < 0x05 >;
clocks = < 0x02 >;
clock-names = "apb_pclk";
};
mmc@b000 {
compatible = "arm,pl180\0arm,primecell";
reg = < 0xb000 0x1000 >;
interrupt-parent = < 0x06 >;
interrupts = < 0x01 0x02 >;
clocks = < 0x02 0x03 >;
clock-names = "mclk\0apb_pclk";
};
};
gpio@101e6000 {
compatible = "arm,pl061\0arm,primecell";
reg = < 0x101e6000 0x1000 >;
interrupts = < 0x08 >;
gpio-controller;
#gpio-cells = < 0x02 >;
interrupt-controller;
#interrupt-cells = < 0x02 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
gpio@101e7000 {
compatible = "arm,pl061\0arm,primecell";
reg = < 0x101e7000 0x1000 >;
interrupts = < 0x09 >;
gpio-controller;
#gpio-cells = < 0x02 >;
interrupt-controller;
#interrupt-cells = < 0x02 >;
clocks = < 0x03 >;
clock-names = "apb_pclk";
};
pci@10001000 {
compatible = "arm,versatile-pci";
device_type = "pci";
reg = < 0x10001000 0x1000 0x41000000 0x10000 0x42000000 0x100000 >;
bus-range = < 0x00 0xff >;
#address-cells = < 0x03 >;
#size-cells = < 0x02 >;
#interrupt-cells = < 0x01 >;
ranges = < 0x1000000 0x00 0x00 0x43000000 0x00 0x10000 0x2000000 0x00 0x50000000 0x50000000 0x00 0x10000000 0x42000000 0x00 0x60000000 0x60000000 0x00 0x10000000 >;
interrupt-map-mask = < 0x1800 0x00 0x00 0x07 >;
interrupt-map = < 0x1800 0x00 0x00 0x01 0x06 0x1c 0x1800 0x00 0x00 0x02 0x06 0x1d 0x1800 0x00 0x00 0x03 0x06 0x1e 0x1800 0x00 0x00 0x04 0x06 0x1b 0x1000 0x00 0x00 0x01 0x06 0x1b 0x1000 0x00 0x00 0x02 0x06 0x1c 0x1000 0x00 0x00 0x03 0x06 0x1d 0x1000 0x00 0x00 0x04 0x06 0x1e 0x800 0x00 0x00 0x01 0x06 0x1e 0x800 0x00 0x00 0x02 0x06 0x1b 0x800 0x00 0x00 0x03 0x06 0x1c 0x800 0x00 0x00 0x04 0x06 0x1d 0x00 0x00 0x00 0x01 0x06 0x1d 0x00 0x00 0x00 0x02 0x06 0x1e 0x00 0x00 0x00 0x03 0x06 0x1b 0x00 0x00 0x00 0x04 0x06 0x1c >;
};
};
};
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