verifyconvert.py

from myhdl import block, Signal, instance, delay, always, intbv, StopSimulation, modbv
from myhdl.conversion import verify


@block
def top(clk, in1, out1):
    
    index = Signal(modbv(0, min=0, max=8))
    
    @always(clk.posedge)
    def logic():
        out1.next = out1 | (in1 << index)
        index.next = index + 1
        
    return logic

@block
def test_top():
    
    clk = Signal(bool(0))
    in1 = Signal(intbv(0)[1:])  # Workaround
    # in1 = Signal(bool(0))  # Causes Error
    out1 = Signal(intbv(0)[16:])
    dutInst = top(clk, in1, out1)
    
    @instance
    def clkdriver():
        while True:
            clk.next = not clk
            yield delay(5)

    @always(clk.negedge)
    def indriver():
        in1.next = not in1
    
    @instance
    def testlogic():
        yield delay(20)
        print("Converted!")
        raise StopSimulation

    return dutInst, testlogic, clkdriver, indriver

testInst = test_top()
#verify.simulator = 'iverilog'
#assert testInst.verify_convert() == 0
verify.simulator = 'ghdl'
assert testInst.verify_convert() == 0