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saffetblt/RCC_Init.c

Last active Apr 22, 2020
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void RCC_init(void){
/* Configure clocks
* Max SYSCLK: 168 MHz
* Max AHB: 168 Mhz
* Max APB1: 42 Mhz
* Max APB2: 84 Mhz
*/
// Flash settings: 5 CPU cycle wait, enable prefetch, instruction cache enable, data cache enable
FLASH->ACR = FLASH_ACR_LATENCY_5WS | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN;
RCC->CR |= (RCC_CR_HSEON); //Enable HSE
while( !(RCC->CR & RCC_CR_HSERDY) ) {}; //ready to start HSE
//PLL - HSE
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE; //set HSE as PLL source
RCC->CR &= ~(RCC_CR_PLLON); //disable PLL before changes
//PLL M
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLM); //clear all PLLM bits
RCC->PLLCFGR |= RCC_PLLCFGR_PLLM_2; //set PLLM = 4 (100)
//PLL P
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLP); //main PLL division PLLP = 2: 00
//PLL N
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLN); //clear all PLLN bits with mask
RCC->PLLCFGR |= RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_5 | RCC_PLLCFGR_PLLN_7; //set PLLN = 168
//PLL Q 7
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLQ);
RCC->PLLCFGR |= (RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_2);
//AHB Prescaler 1
RCC->CFGR &= ~(RCC_CFGR_HPRE);
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
//APB1 Prescaler 4
RCC->CFGR &= ~(RCC_CFGR_PPRE1);
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
//APB2 Prescaler 2
RCC->CFGR &= ~(RCC_CFGR_PPRE2);
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
//PLL enable
RCC->CR |= RCC_CR_PLLON; //enalbe PLL
while((RCC->CR & RCC_CR_PLLRDY) == 0) {} //wait for PLL is ready
//PLL System
RCC->CFGR |= RCC_CFGR_SW_PLL; //PLL selected as system clock
while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} //wait for PLL is used
SystemCoreClockUpdate();
}
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