`timescale 1ns/1ns

import uvm_pkg::*;
class test extends uvm_test;
   `uvm_component_utils(test)

   function new(string name, uvm_component parent = null);
      super.new(name, parent);
   endfunction : new

  function void start_of_simulation_phase(uvm_phase phase);
    super.start_of_simulation_phase(phase);
    // uvm_top is a constant handle of uvm_root declared in uvm_root.svh file
    uvm_top.set_timeout(100s, 1);  // Override default timeout to 1oo second
    // or you can use below syntax as well
    // uvm_root::get().set_timeout(100s, 1);
  endfunction : start_of_simulation_phase
  
   task pre_main_phase(uvm_phase phase);
      phase.raise_objection(this);
      #100;
      phase.drop_objection(this);
   endtask : pre_main_phase
   
   task main_phase(uvm_phase phase);
      phase.raise_objection(this);
      // Will cause a time-out
      // because we forgot to drop the objection
   endtask : main_phase
   
   task shutdown_phase(uvm_phase phase);
      phase.raise_objection(this);
      #100;
      phase.drop_objection(this);
   endtask : shutdown_phase
endclass : test

module top();
  initial begin
   run_test("test");
  end
endmodule : top

//Output:
// UVM_INFO @ 0: reporter [RNTST] Running test test...
// UVM_FATAL uvm-1.2/src/base/uvm_phase.svh(1508) @ 100000000000: reporter [PH_TIMEOUT] Explicit timeout of 100000000000 hit, indicating a probable testbench issue
// UVM_INFO uvm-1.2/src/base/uvm_report_server.svh(847) @ 100000000000: reporter [UVM/REPORT/SERVER]