module top();
  // Function with Static Lifetime
  // By default lifetime of function/task is Static in Verilog/SV
  function void print_s();
    int a;
    a = a + 1;
    $write("%0d  ", a);
  endfunction : print_s
  
  // Function with Automatic Lifetime
  function automatic void print_a();
    int a;
    a = a + 1;
    $write("%0d  ", a);
  endfunction : print_a  
  
  initial begin
    $display("Static variable");
    for (int i=0; i<4; i++) begin
      print_s();
    end
    $display("\n");
    
    $display("Automatic variable");
    for (int i=0; i<4; i++) begin
      print_a();
    end
    $display();
  end
endmodule : top

//Output:
// Static variable
// 1  2  3  4   
// 
// Automatic variable
// 1  1  1  1