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| <!doctype html> | |
| <html lang="en"> | |
| <meta charset="utf-8"> | |
| <meta name="viewport" content="width=device-width, initial-scale=1"> | |
| <title>Board Pinout Explorer</title> | |
| <meta name="description" content="The connector pinouts of the STM32 NUCLEO boards and Discovery kits with their alternate functions: search pins and functions by regular expression and find the boards that are position compatible."> | |
| <link rel="preconnect" href="https://fonts.googleapis.com"> | |
| <link rel="preconnect" href="https://fonts.gstatic.com" crossorigin> | |
| <link rel="stylesheet" href="https://fonts.googleapis.com/css2?family=IBM+Plex+Mono:wght@400;500;600&family=IBM+Plex+Sans:wght@400;500;600&display=swap"> | |
| <style> | |
| :root { | |
| --ground: #F3F5F4; | |
| --surface: #FFFFFF; | |
| --band: #F8FAF9; | |
| --ink: #16201C; | |
| --muted: #5B6863; | |
| --faint: #85918C; | |
| --rule: #DDE3E0; | |
| --rule-strong: #C3CCC8; | |
| --accent: #1C6B56; | |
| --accent-ink: #FFFFFF; | |
| --accent-soft: #E2EFEA; | |
| --hover: #EEF4F1; | |
| --mark: #FBE3A0; | |
| --mark-line: #C99A1B; | |
| --used: #C2570C; | |
| --error: #B42318; | |
| --kind-s: 55%; | |
| --kind-bg-l: 90%; | |
| --kind-ink-l: 26%; | |
| --nc-ink: #A9B3AF; | |
| --font-sans: "IBM Plex Sans", system-ui, -apple-system, "Segoe UI", Roboto, sans-serif; | |
| --font-mono: "IBM Plex Mono", ui-monospace, "SF Mono", Menlo, Consolas, monospace; | |
| color-scheme: light; | |
| } | |
| @media (prefers-color-scheme: dark) { | |
| :root:not([data-theme="light"]) { | |
| --ground: #0E1311; | |
| --surface: #141A18; | |
| --band: #111715; | |
| --ink: #E2E8E5; | |
| --muted: #9AA8A2; | |
| --faint: #6E7B76; | |
| --rule: #232D29; | |
| --rule-strong: #34403B; | |
| --accent: #5FC0A0; | |
| --accent-ink: #0B1512; | |
| --accent-soft: #16302A; | |
| --hover: #19231F; | |
| --mark: #6A5616; | |
| --mark-line: #D9B13F; | |
| --used: #F08A45; | |
| --error: #F4A39B; | |
| --kind-s: 45%; | |
| --kind-bg-l: 20%; | |
| --kind-ink-l: 78%; | |
| --nc-ink: #4A5853; | |
| color-scheme: dark; | |
| } | |
| } | |
| :root[data-theme="dark"] { | |
| --ground: #0E1311; | |
| --surface: #141A18; | |
| --band: #111715; | |
| --ink: #E2E8E5; | |
| --muted: #9AA8A2; | |
| --faint: #6E7B76; | |
| --rule: #232D29; | |
| --rule-strong: #34403B; | |
| --accent: #5FC0A0; | |
| --accent-ink: #0B1512; | |
| --accent-soft: #16302A; | |
| --hover: #19231F; | |
| --mark: #6A5616; | |
| --mark-line: #D9B13F; | |
| --used: #F08A45; | |
| --error: #F4A39B; | |
| --kind-s: 45%; | |
| --kind-bg-l: 20%; | |
| --kind-ink-l: 78%; | |
| --nc-ink: #4A5853; | |
| color-scheme: dark; | |
| } | |
| * { box-sizing: border-box; } | |
| [hidden] { display: none !important; } | |
| html, body { height: 100%; } | |
| body { | |
| margin: 0; background: var(--ground); color: var(--ink); | |
| font: 14px/1.45 var(--font-sans); | |
| display: flex; flex-direction: column; gap: 10px; | |
| padding-inline: clamp(16px, 3vw, 32px); padding-block: 12px 14px; | |
| height: 100dvh; | |
| } | |
| a { color: inherit; } | |
| /* Top bar */ | |
| .top { display: flex; flex-wrap: wrap; align-items: center; justify-content: space-between; gap: 8px 24px; } | |
| .visually-hidden { | |
| position: absolute; width: 1px; height: 1px; overflow: hidden; | |
| clip: rect(0 0 0 0); white-space: nowrap; | |
| } | |
| .links { display: flex; gap: 14px; font-size: 12px; color: var(--muted); } | |
| .totals { display: flex; gap: 18px; font-variant-numeric: tabular-nums; } | |
| .total { display: grid; gap: 1px; text-align: right; } | |
| .total b { font: 600 17px/1.1 var(--font-mono); } | |
| .total span { color: var(--faint); font-size: 11px; text-transform: uppercase; letter-spacing: 0.06em; } | |
| /* Shell */ | |
| .shell { | |
| flex: 1; min-height: 0; display: grid; gap: 12px; | |
| grid-template-columns: minmax(220px, 270px) minmax(0, 1fr) minmax(230px, 290px); | |
| } | |
| .panel { | |
| background: var(--surface); border: 1px solid var(--rule); border-radius: 10px; | |
| min-height: 0; display: flex; flex-direction: column; overflow: hidden; | |
| } | |
| /* Sidebar */ | |
| .side-head { padding: 10px; border-bottom: 1px solid var(--rule); display: grid; gap: 8px; } | |
| .side-head label { color: var(--faint); font-size: 11px; text-transform: uppercase; letter-spacing: 0.06em; } | |
| .modes { display: grid; grid-auto-flow: column; grid-auto-columns: 1fr; gap: 4px; } | |
| .modes button { | |
| padding: 5px 4px; border: 1px solid var(--rule-strong); border-radius: 7px; cursor: pointer; | |
| background: var(--band); color: var(--muted); font: 600 11px var(--font-sans); display: grid; gap: 1px; | |
| } | |
| .modes button span { font: 400 10px var(--font-mono); color: var(--faint); } | |
| .modes button:hover { background: var(--hover); } | |
| .modes button[aria-pressed="true"] { border-color: var(--accent); background: var(--accent-soft); color: var(--accent); } | |
| .modes button[aria-pressed="true"] span { color: inherit; } | |
| input[type="search"] { | |
| width: 100%; padding: 7px 9px; border: 1px solid var(--rule-strong); border-radius: 7px; | |
| background: var(--band); color: var(--ink); font: 13px var(--font-mono); | |
| } | |
| input:focus-visible, button:focus-visible { outline: 2px solid var(--accent); outline-offset: 1px; } | |
| input.bad { border-color: var(--error); } | |
| .side-list { overflow: auto; padding: 6px; } | |
| .group-row { | |
| display: grid; grid-template-columns: auto 1fr auto; gap: 8px; align-items: baseline; | |
| width: 100%; text-align: left; padding: 5px 8px; border: 0; border-radius: 6px; | |
| background: none; color: inherit; font: 13px var(--font-sans); cursor: pointer; | |
| } | |
| .group-row:hover { background: var(--hover); } | |
| .group-row .count { font: 600 12px var(--font-mono); font-variant-numeric: tabular-nums; min-width: 2ch; text-align: right; } | |
| .group-row .name { font: 12px var(--font-mono); overflow: hidden; text-overflow: ellipsis; white-space: nowrap; } | |
| .group-row .inst { color: var(--faint); font: 11px var(--font-mono); font-variant-numeric: tabular-nums; } | |
| .empty { padding: 14px; color: var(--faint); font-size: 13px; } | |
| /* Main */ | |
| .main-head { padding: 12px 16px; border-bottom: 1px solid var(--rule); background: var(--band); } | |
| .main-head h2 { margin: 0; font: 600 17px var(--font-mono); } | |
| .main-head p { margin: 3px 0 0; color: var(--muted); font-size: 13px; } | |
| .groups { overflow: auto; padding: 12px 16px 16px; display: grid; gap: 12px; align-content: start; } | |
| .group { border: 1px solid var(--rule); border-radius: 9px; background: var(--band); scroll-margin-top: 8px; } | |
| .group > header { padding: 9px 12px; display: grid; gap: 6px; } | |
| .group > header h3 { margin: 0; font: 600 13px var(--font-sans); display: flex; gap: 8px; align-items: baseline; } | |
| .group > header h3 em { font-style: normal; color: var(--faint); font-weight: 400; font-size: 12px; } | |
| .chips { display: flex; flex-wrap: wrap; gap: 4px; } | |
| .chip { | |
| font: 11px var(--font-mono); padding: 2px 6px; border-radius: 5px; cursor: pointer; | |
| background: var(--surface); border: 1px solid var(--rule); color: var(--muted); | |
| } | |
| button.chip:hover, a.chip:hover { background: var(--hover); } | |
| a.chip { text-decoration: none; cursor: pointer; margin-left: auto; } | |
| .chip[aria-pressed="true"] { border-color: var(--accent); background: var(--accent-soft); color: var(--accent); } | |
| .chip.on { background: var(--mark); color: var(--ink); border-color: transparent; } | |
| .chip.static { cursor: default; } | |
| .board { display: flex; flex-wrap: wrap; gap: 10px 22px; padding: 2px 12px 12px; align-items: start; overflow-x: auto; } | |
| /* Physical layout: the ARDUINO and Zio headers sit between the morpho headers */ | |
| .phys { flex: none; display: grid; grid-template-columns: repeat(4, max-content); grid-auto-rows: 18px; column-gap: 10px; justify-content: start; } | |
| .phys > b { grid-row: 1; font: 600 11px var(--font-mono); color: var(--muted); } | |
| .phys > b span, .slot > i span { font-weight: 400; color: var(--faint); } | |
| .slot { display: flex; gap: 4px; } | |
| .slot > i { | |
| writing-mode: vertical-rl; font: 600 10px/1 var(--font-mono); font-style: normal; color: var(--muted); | |
| text-align: center; white-space: nowrap; overflow: hidden; | |
| } | |
| /* Connectors */ | |
| .conn { display: grid; gap: 3px; } | |
| .conn > b { font: 600 11px var(--font-mono); color: var(--muted); } | |
| .conn > b span { font-weight: 400; color: var(--faint); } | |
| .rows { display: grid; gap: 1px; grid-template-columns: minmax(84px, auto) 20px 20px minmax(84px, auto); align-content: start; } | |
| .rows.single { grid-template-columns: 20px minmax(84px, auto); } | |
| .rows.single.mirror { grid-template-columns: minmax(84px, auto) 20px; } | |
| .pin, .num { font: 11px/16px var(--font-mono); height: 17px; white-space: nowrap; padding: 0 5px; border-radius: 3px; } | |
| .num { color: var(--faint); text-align: center; padding: 0; font-variant-numeric: tabular-nums; } | |
| .pin { | |
| border: 1px solid transparent; cursor: default; overflow: hidden; text-overflow: ellipsis; max-width: 230px; | |
| background: var(--surface); border-color: var(--rule); | |
| } | |
| .pin.l { text-align: right; } | |
| .pin small { font-size: 10px; color: var(--muted); } | |
| .pin.power, .pin.ground, .pin.system { | |
| background: hsl(var(--h) var(--kind-s) var(--kind-bg-l)); color: hsl(var(--h) var(--kind-s) var(--kind-ink-l)); | |
| border-color: transparent; | |
| } | |
| .pin.power { --h: 8; } | |
| .pin.ground { --h: 215; } | |
| .pin.system { --h: 275; } | |
| .pin.nc { background: none; border-color: transparent; color: var(--nc-ink); } | |
| .filtered .pin:not(.hit) { opacity: 0.38; } | |
| .pin.hit { background: var(--mark); border-color: var(--mark-line); color: var(--ink); font-weight: 600; } | |
| .pin.hit small { color: inherit; font-weight: 400; } | |
| .inspect .bridge { display: grid; gap: 2px; font-size: 12px; } | |
| .inspect .bridge > b { font: 600 12px var(--font-mono); } | |
| .inspect .bridge > b span { font-weight: 400; color: var(--muted); } | |
| .inspect .bridge p { display: grid; grid-template-columns: auto 1fr; gap: 0 8px; color: var(--muted); } | |
| .inspect .bridge p code { font: 11px var(--font-mono); color: var(--faint); } | |
| .inspect .bridge p.default { color: var(--ink); } | |
| .inspect .bridge p.default code { color: var(--ink); font-weight: 600; } | |
| /* Pins that the board itself already uses */ | |
| .pin.used.r { box-shadow: inset 3px 0 0 var(--used); } | |
| .pin.used.l { box-shadow: inset -3px 0 0 var(--used); } | |
| .pin.used small { color: var(--used); } | |
| /* A solder bridge may free a used pin or change what a pin is connected to */ | |
| .pin.sb:not(.hit) { border-style: dashed; border-color: var(--muted); } | |
| .pin.sb { position: relative; } | |
| .pin.sb::after { | |
| content: ""; position: absolute; top: 0; right: 0; border: 3px solid; | |
| border-color: var(--muted) var(--muted) transparent transparent; | |
| } | |
| .pin.sb.l::after { right: auto; left: 0; border-color: var(--muted) transparent transparent var(--muted); } | |
| .free .pin.used:not(.sb), .free-free .pin.used { opacity: 0.38; } | |
| .pin.same { outline: 2px dashed var(--accent); outline-offset: -1px; opacity: 1 !important; } | |
| .pin:hover, .pin.sel { outline: 2px solid var(--accent); outline-offset: -1px; opacity: 1 !important; } | |
| /* Inspector */ | |
| .inspect { padding: 10px 12px; display: grid; gap: 8px; align-content: start; overflow: auto; } | |
| .inspect h3 { margin: 0; font: 600 14px var(--font-mono); overflow-wrap: anywhere; } | |
| .inspect .sub { color: var(--muted); font: 12px var(--font-mono); } | |
| .inspect p { margin: 0; font-size: 12px; color: var(--muted); } | |
| .inspect dl { margin: 0; display: grid; grid-template-columns: auto 1fr; gap: 2px 10px; font-size: 12px; } | |
| .inspect dt { color: var(--faint); } | |
| .inspect dd { margin: 0; font-family: var(--font-mono); overflow-wrap: anywhere; } | |
| .inspect hr { border: 0; border-top: 1px solid var(--rule); margin: 2px 0; width: 100%; } | |
| .inspect .chip { cursor: default; } | |
| .legend { display: flex; flex-wrap: wrap; gap: 4px; } | |
| .legend .pin { cursor: default; } | |
| @media (max-width: 1100px) { | |
| body { height: auto; } | |
| .shell { grid-template-columns: 1fr; } | |
| .side-list { max-height: 30vh; } | |
| .groups { overflow: visible; } | |
| .inspect { position: sticky; bottom: 0; max-height: 40vh; } | |
| } | |
| </style> | |
| <header class="top"> | |
| <h1 class="visually-hidden">Board Pinout Explorer</h1> | |
| <div class="links"> | |
| <a href="../variants/">Peripheral Variant Explorer</a> | |
| <a href="../svd/">SVD Register Explorer</a> | |
| <a href="https://github.com/modm-io/modm-data">modm-data</a> | |
| </div> | |
| <div class="totals"> | |
| <div class="total"><b id="t-boards">–</b><span>boards</span></div> | |
| <div class="total"><b id="t-groups">–</b><span>compatible sets</span></div> | |
| <div class="total"><b id="t-pins">–</b><span>matching pins</span></div> | |
| </div> | |
| </header> | |
| <div class="shell"> | |
| <nav class="panel" aria-label="Filter and compatible sets"> | |
| <div class="side-head"> | |
| <input id="filter" type="search" placeholder="pin, function, use or bridge, e.g. ^SPI\d_SCK$|PA5|RMII|^SB13$" aria-label="Filter pins and alternate functions by regular expression" autocomplete="off" spellcheck="false"> | |
| <input id="board" type="search" placeholder="boards, e.g. F4|L4|DISCO|-DK" aria-label="Filter boards by regular expression" autocomplete="off" spellcheck="false"> | |
| <label id="l-free">Pins</label> | |
| <div class="modes" id="free" role="group" aria-labelledby="l-free"> | |
| <button type="button" data-free="" aria-pressed="true">all<span>on the headers</span></button> | |
| <button type="button" data-free="bridge" aria-pressed="false">freeable<span>free or bridge</span></button> | |
| <button type="button" data-free="free" aria-pressed="false">free<span>not used</span></button> | |
| </div> | |
| <label id="l-compat">Compatible if matching pins have the same</label> | |
| <div class="modes" id="compat" role="group" aria-labelledby="l-compat"> | |
| <button type="button" data-compat="name" aria-pressed="true">name<span>and position</span></button> | |
| <button type="button" data-compat="function" aria-pressed="false">function<span>any instance</span></button> | |
| <button type="button" data-compat="position" aria-pressed="false">position<span>only</span></button> | |
| </div> | |
| </div> | |
| <div class="side-list" id="list"></div> | |
| </nav> | |
| <main class="panel"> | |
| <div class="main-head"> | |
| <h2 id="m-title">Loading…</h2> | |
| <p id="m-sub"></p> | |
| </div> | |
| <div class="groups" id="groups"></div> | |
| </main> | |
| <aside class="panel inspect" id="inspect" aria-live="polite"></aside> | |
| </div> | |
| <script> | |
| "use strict"; | |
| const state = {boards: [], filter: "", board: "", compat: "name", free: "", shown: new Map(), pinned: null}; | |
| const $ = (id) => document.getElementById(id); | |
| const el = (tag, cls, text) => { | |
| const node = document.createElement(tag); | |
| if (cls) node.className = cls; | |
| if (text !== undefined) node.textContent = text; | |
| return node; | |
| }; | |
| // These connectors count along one row and then along the other, instead of across | |
| const PAIRED = ["stmod", "pmod", "mikrobus"]; | |
| const short = (board) => board.board.replace("NUCLEO-", ""); | |
| function regex(pattern) { | |
| if (!pattern) return null; | |
| try { return new RegExp(pattern, "i"); } catch { return undefined; } | |
| } | |
| /* -------------------------------------------------------------- matching */ | |
| // All connectors of a board with their place on it, which makes them comparable between boards | |
| function connectors(board) { | |
| let nano = 0; | |
| const counts = {}; | |
| return Object.entries(board.connectors).map(([name, connector]) => { | |
| const spot = place(connector, () => nano++); | |
| // STMod+, Pmod and mikroBUS are standards too, but without a common place on the board | |
| const index = (counts[connector.type] = (counts[connector.type] || 0) + 1); | |
| const position = spot ? `${connector.type} ${spot.side} ${spot.row}` : PAIRED.includes(connector.type) ? `${connector.type} ${index}` : name; | |
| return {name, connector, spot, position}; | |
| }); | |
| } | |
| // What the board itself connects to the pin: ST-LINK, Ethernet PHY, crystal, LED, button, ... | |
| const used = (board, pin) => (pin.kind === "gpio" ? (board.uses || {})[pin.signal] : undefined); | |
| // The solder bridges and jumpers whose description mentions the pin | |
| const bridges = (board, pin) => (pin.kind === "gpio" ? (board.bridges || []).filter((b) => b.gpios.includes(pin.signal)) : []); | |
| // The bridges of a group that belong to this pin, if the manual tells them apart | |
| const own = (bridge, pin) => { | |
| const ids = bridge.ids.filter((id) => (bridge.pins[id] || []).includes(pin.signal)); | |
| return ids.length ? ids : bridge.ids; | |
| }; | |
| // A used pin still counts as available if a solder bridge may free it | |
| const taken = (board, pin) => state.free && used(board, pin) && (state.free === "free" || !bridges(board, pin).length); | |
| // The names of a pin that the filter matches: its signal, connector label, net and device functions | |
| function hits(board, pin, pattern) { | |
| const use = used(board, pin) || {}; | |
| const names = [pin.signal, ...(pin.label || "").split(" / "), pin.net, use.label, use.signal, use.use, | |
| ...bridges(board, pin).flatMap((b) => own(b, pin))].filter(Boolean); | |
| const functions = pin.kind === "gpio" ? Object.keys(board.signals[pin.signal] || {}) : []; | |
| return { | |
| names: [...new Set(names)].filter((name) => pattern.test(name)), | |
| functions: functions.filter((name) => pattern.test(name)), | |
| }; | |
| } | |
| // USART2_TX and USART1_TX are the same function on a different instance | |
| const generic = (name) => name.replace(/^([A-Z]+)\d+_/, "$1_"); | |
| // Boards with the same key are position compatible | |
| function analyze(board, pattern) { | |
| const key = []; | |
| let count = 0; | |
| const marks = new Map(); | |
| for (const {name, connector, position} of connectors(board)) { | |
| for (const [number, pin] of Object.entries(connector.pins)) { | |
| const occupied = taken(board, pin); | |
| if (!pattern) { | |
| key.push(`${position}.${number}=${occupied ? "used" : pin.signal}`); | |
| continue; | |
| } | |
| if (occupied) continue; | |
| const hit = hits(board, pin, pattern); | |
| if (!hit.names.length && !hit.functions.length) continue; | |
| count += 1; | |
| marks.set(`${name}.${number}`, hit); | |
| const what = { | |
| name: [...hit.names.filter((n) => n === pin.signal), ...hit.functions].join("+") || pin.signal, | |
| function: [...new Set(hit.functions.map(generic))].join("+") || pin.kind, | |
| position: "", | |
| }[state.compat]; | |
| key.push(`${position}.${number}=${what}`); | |
| } | |
| } | |
| return {key: key.join("|"), count, marks}; | |
| } | |
| /* ------------------------------------------------------------- rendering */ | |
| function renderPin(board, name, number, pin, hit, side) { | |
| const node = el("div", `pin ${pin.kind} ${side}`, pin.signal); | |
| const use = used(board, pin); | |
| if (use) node.classList.add("used"); | |
| const links = bridges(board, pin); | |
| if (links.length) { | |
| node.classList.add("sb"); | |
| node.dataset.bridges = links.flatMap((b) => b.ids).join(" "); | |
| } | |
| // The pin name stays next to the pin number, everything else goes on the outer side | |
| const outside = (text) => (side === "l" ? node.prepend(el("small", "", text), " ") : node.append(" ", el("small", "", text))); | |
| if (hit) { | |
| node.classList.add("hit"); | |
| const extra = [...hit.names.filter((n) => n !== pin.signal), ...hit.functions]; | |
| if (extra.length) outside(extra.join(" ")); | |
| } else if (use) { | |
| outside(use.label || use.signal); | |
| } | |
| node.dataset.pin = `${state.boards.indexOf(board)}|${name}|${number}`; | |
| if (pin.kind === "gpio") node.dataset.signal = pin.signal; | |
| node.title = `${name}-${number}`; | |
| return node; | |
| } | |
| // The rows that the ARDUINO and Zio headers occupy next to the morpho headers. All boards use the | |
| // ARDUINO Uno footprint, where the right headers count from the bottom. Zio extends it downwards. | |
| function place(connector, nano) { | |
| const count = Math.max(...Object.keys(connector.pins).map(Number)); | |
| const gpio = Object.values(connector.pins).some((pin) => pin.kind === "gpio"); | |
| if (connector.type === "arduino") { | |
| if (count === 8 && !gpio) return {side: "left", row: 4}; | |
| if (count === 6) return {side: "left", row: 13}; | |
| if (count === 9 || count === 10) return {side: "right", row: 1, reverse: true, count: 10}; | |
| if (count === 8) return {side: "right", row: 11, reverse: true}; | |
| // The two ARDUINO Nano headers of the Nucleo-32 boards both count from the top | |
| if (count === 15) return {side: nano() ? "right" : "left", row: 0}; | |
| } | |
| if (connector.type === "zio") { | |
| return {16: {side: "left", row: 4}, 30: {side: "left", row: 13}, 20: {side: "right", row: 1}, 34: {side: "right", row: 11}}[count]; | |
| } | |
| return connector.side ? {side: connector.side, row: 0, morpho: true} : undefined; | |
| } | |
| function renderRows(board, name, connector, result, spot = {}) { | |
| // ARDUINO Uno and Nano headers are a single row, morpho and Zio have an odd and an even row | |
| const single = connector.type === "arduino"; | |
| const mirror = single && spot.side === "right"; | |
| const rows = el("div", `rows${single ? " single" : ""}${mirror ? " mirror" : ""}`); | |
| const last = spot.count || Math.max(...Object.keys(connector.pins).map(Number)); | |
| const cell = (number, side) => { | |
| const pin = connector.pins[number]; | |
| const mark = result.marks.get(`${name}.${number}`); | |
| return pin ? renderPin(board, name, number, pin, mark, side) : el("div", "pin nc " + side, "?"); | |
| }; | |
| if (single) { | |
| for (let index = 1; index <= last; index++) { | |
| const number = spot.reverse ? last + 1 - index : index; | |
| const cells = [el("div", "num", String(number)), cell(number, mirror ? "l" : "r")]; | |
| rows.append(...(mirror ? cells.reverse() : cells)); | |
| } | |
| } else { | |
| const half = PAIRED.includes(connector.type) ? Math.ceil(last / 2) : 0; | |
| for (let number = 1; number <= (half || last); number += half ? 1 : 2) { | |
| const other = number + (half || 1); | |
| rows.append(cell(number, "l"), el("div", "num", String(number)), el("div", "num", String(other)), cell(other, "r")); | |
| } | |
| } | |
| return {rows, count: single ? last : Math.ceil(last / 2)}; | |
| } | |
| function renderBoard(board, result) { | |
| const wrap = el("div", "board"); | |
| const phys = el("div", "phys"); | |
| const label = (tag, name, connector) => { | |
| const node = el(tag, "", name); | |
| node.append(" ", el("span", "", [connector.type, connector.side].filter(Boolean).join(" "))); | |
| return node; | |
| }; | |
| for (const {name, connector, spot} of connectors(board)) { | |
| const {rows, count} = renderRows(board, name, connector, result, spot); | |
| if (!spot) { | |
| const block = el("div", "conn"); | |
| block.append(label("b", name, connector), rows); | |
| wrap.append(block); | |
| continue; | |
| } | |
| // Columns: left morpho, left inner, right inner, right morpho | |
| const column = spot.morpho ? (spot.side === "left" ? 1 : 4) : spot.side === "left" ? 2 : 3; | |
| const node = spot.morpho ? rows : el("div", "slot"); | |
| if (spot.morpho) { | |
| const title = label("b", name, connector); | |
| title.style.gridColumn = column; | |
| phys.append(title); | |
| } else { | |
| const tag = label("i", name, connector); | |
| node.append(...(spot.side === "left" ? [rows, tag] : [tag, rows])); | |
| } | |
| node.style.gridColumn = column; | |
| node.style.gridRow = `${spot.row + 2} / span ${count}`; | |
| phys.append(node); | |
| } | |
| if (phys.children.length) wrap.prepend(phys); | |
| return wrap; | |
| } | |
| function render() { | |
| const pattern = regex(state.filter); | |
| const boardPattern = regex(state.board); | |
| $("filter").classList.toggle("bad", pattern === undefined); | |
| $("board").classList.toggle("bad", boardPattern === undefined); | |
| if (pattern === undefined || boardPattern === undefined) return; | |
| const groups = new Map(); | |
| const without = []; | |
| let pins = 0; | |
| for (const board of state.boards) { | |
| if (boardPattern && !boardPattern.test(board.board) && !boardPattern.test(board.device || "")) continue; | |
| const result = analyze(board, pattern); | |
| if (pattern && !result.count) { without.push(board); continue; } | |
| pins += result.count; | |
| if (!groups.has(result.key)) groups.set(result.key, []); | |
| groups.get(result.key).push({board, result}); | |
| } | |
| const sorted = [...groups.values()].sort((a, b) => b.length - a.length || a[0].board.board.localeCompare(b[0].board.board)); | |
| const total = sorted.reduce((sum, group) => sum + group.length, 0); | |
| $("t-boards").textContent = String(total); | |
| $("t-groups").textContent = String(sorted.length); | |
| $("t-pins").textContent = pattern ? String(pins) : "–"; | |
| $("m-title").textContent = pattern ? `/${state.filter}/i` : "All pins"; | |
| $("m-sub").textContent = pattern | |
| ? `${total} boards have matching pins, in ${sorted.length} position compatible sets.` | |
| : `${total} boards in ${sorted.length} sets with identical connectors.`; | |
| const list = $("list"); | |
| const main = $("groups"); | |
| list.textContent = ""; | |
| main.textContent = ""; | |
| sorted.forEach((group, index) => { | |
| const names = group.map(({board}) => short(board)); | |
| const row = el("button", "group-row"); | |
| row.type = "button"; | |
| row.append(el("span", "count", String(group.length)), el("span", "name", names.join(" "))); | |
| if (pattern) row.append(el("span", "inst", `${group[0].result.count} pins`)); | |
| row.title = names.join(", "); | |
| row.addEventListener("click", () => $(`g${index}`).scrollIntoView({behavior: "smooth", block: "start"})); | |
| list.append(row); | |
| const section = el("section", `group${pattern ? " filtered" : ""}${state.free ? ` free free-${state.free}` : ""}`); | |
| section.id = `g${index}`; | |
| const header = el("header"); | |
| const title = el("h3", "", group.length === 1 ? "1 board" : `${group.length} compatible boards`); | |
| if (pattern) title.append(el("em", "", `${group[0].result.count} matching pins`)); | |
| const chips = el("div", "chips"); | |
| // One board stands for the whole set, the chips switch between them | |
| const current = group.find(({board}) => board.board === state.shown.get(group[0].board.board)) || group[0]; | |
| for (const entry of group) { | |
| const chip = el("button", "chip", short(entry.board)); | |
| chip.type = "button"; | |
| chip.title = `${entry.board.device || "unknown device"}, ${entry.board.document}`; | |
| chip.setAttribute("aria-pressed", String(entry === current)); | |
| chip.addEventListener("click", () => { state.shown.set(group[0].board.board, entry.board.board); render(); }); | |
| chips.append(chip); | |
| } | |
| header.append(title, chips); | |
| if (current.board.pinout) { | |
| // The pinout generator starts with what the board already uses its pins for | |
| const link = el("a", "chip", "Pinout generator ↗"); | |
| link.href = `../pinout/${current.board.pinout}`; | |
| link.title = `Configure the ${current.board.device} of the ${current.board.board}`; | |
| chips.append(link); | |
| } | |
| section.append(header, renderBoard(current.board, current.result)); | |
| main.append(section); | |
| }); | |
| const rest = (boards, text) => { | |
| if (!boards.length) return; | |
| const section = el("section", "group"); | |
| const header = el("header"); | |
| header.append(el("h3", "", `${boards.length} boards ${text}`)); | |
| const chips = el("div", "chips"); | |
| for (const board of boards) chips.append(el("span", "chip static", short(board))); | |
| header.append(chips); | |
| section.append(header); | |
| main.append(section); | |
| }; | |
| if (!sorted.length) main.append(el("p", "empty", "No pin matches.")); | |
| rest(without, "without a matching pin"); | |
| const hash = new URLSearchParams(); | |
| if (state.filter) hash.set("q", state.filter); | |
| if (state.board) hash.set("b", state.board); | |
| hash.set("m", state.compat); | |
| if (state.free) hash.set("f", state.free); | |
| history.replaceState(null, "", "#" + hash); | |
| } | |
| /* ------------------------------------------------------------- inspector */ | |
| function inspect(id) { | |
| const panel = $("inspect"); | |
| panel.textContent = ""; | |
| if (!id) { | |
| panel.append(el("h3", "", "Pin details"), el("p", "", "Hover a pin to see its alternate functions, click to keep it.")); | |
| const legend = el("div", "legend"); | |
| for (const kind of ["gpio", "power", "ground", "system", "nc"]) legend.append(el("span", `pin ${kind}`, kind)); | |
| legend.append(el("span", "pin used r", "used on board"), el("span", "pin used sb r", "used, has bridge"), el("span", "pin sb r", "has bridge"), el("span", "pin hit", "match")); | |
| panel.append(legend); | |
| return; | |
| } | |
| const [index, name, number] = id.split("|"); | |
| const board = state.boards[Number(index)]; | |
| const pin = board.connectors[name].pins[number]; | |
| const pattern = regex(state.filter); | |
| panel.append(el("h3", "", `${pin.signal}`), el("div", "sub", `${board.board} ${name}-${number}`)); | |
| const list = el("dl"); | |
| const add = (term, value) => { if (value) list.append(el("dt", "", term), el("dd", "", value)); }; | |
| const use = used(board, pin); | |
| add("kind", pin.kind); | |
| if (use) { | |
| add("used for", [use.use, use.label].filter(Boolean).join(": ")); | |
| add("used as", use.signal); | |
| add("wired to", use.part); | |
| } | |
| add("label", pin.label); | |
| add("net", pin.net); | |
| add("function", pin.function); | |
| add("bridge", pin.bridge); | |
| add("remark", pin.remark); | |
| add("manual", pin.pin); | |
| add("device", board.device); | |
| add("source", board.document); | |
| panel.append(list); | |
| for (const bridge of bridges(board, pin)) { | |
| panel.append(el("hr")); | |
| const block = el("div", "bridge"); | |
| const ids = own(bridge, pin); | |
| const title = el("b", "", ids.join(", ")); | |
| const group = ids.length < bridge.ids.length ? `with ${bridge.ids.filter((id) => !ids.includes(id)).join(", ")}` : ""; | |
| title.append(" ", el("span", "", [bridge.name, group].filter(Boolean).join(" · "))); | |
| title.title = bridge.source || ""; | |
| block.append(title); | |
| for (const option of bridge.states) { | |
| const line = el("p", option.default ? "default" : ""); | |
| line.append(el("code", "", option.state + (option.default ? (bridge.default_from ? ` default in ${bridge.default_from}` : " default") : "")), el("span", "", option.text)); | |
| block.append(line); | |
| } | |
| panel.append(block); | |
| } | |
| const functions = Object.entries(board.signals[pin.signal] || {}); | |
| if (functions.length) { | |
| panel.append(el("hr")); | |
| const chips = el("div", "chips"); | |
| for (const [signal, af] of functions) { | |
| const chip = el("span", "chip", af === null ? signal : `AF${af} ${signal}`); | |
| if (pattern && pattern.test(signal)) chip.classList.add("on"); | |
| chips.append(chip); | |
| } | |
| panel.append(chips); | |
| } else if (pin.kind === "gpio") { | |
| panel.append(el("p", "", "No alternate function data for this device.")); | |
| } | |
| } | |
| /* ----------------------------------------------------------------- start */ | |
| function toggle(container, attribute, apply) { | |
| container.addEventListener("click", (event) => { | |
| const button = event.target.closest("button"); | |
| if (!button) return; | |
| apply(button.dataset[attribute]); | |
| for (const other of container.querySelectorAll("button")) { | |
| other.setAttribute("aria-pressed", String(other === button)); | |
| } | |
| render(); | |
| }); | |
| } | |
| async function start() { | |
| try { | |
| const response = await fetch("nucleo.json"); | |
| if (!response.ok) throw new Error(`${response.status} ${response.statusText}`); | |
| state.boards = (await response.json()).boards; | |
| } catch (error) { | |
| $("m-title").textContent = "Could not load nucleo.json"; | |
| $("m-sub").textContent = `${error.message}. Serve this folder over HTTP, the JSON file sits next to this page.`; | |
| return; | |
| } | |
| const hash = new URLSearchParams(location.hash.slice(1)); | |
| state.filter = hash.get("q") || ""; | |
| state.board = hash.get("b") || ""; | |
| if (["name", "function", "position"].includes(hash.get("m"))) state.compat = hash.get("m"); | |
| state.free = ["bridge", "free"].includes(hash.get("f")) ? hash.get("f") : ""; | |
| for (const button of $("free").querySelectorAll("button")) button.setAttribute("aria-pressed", String(button.dataset.free === state.free)); | |
| $("filter").value = state.filter; | |
| $("board").value = state.board; | |
| for (const button of $("compat").querySelectorAll("button")) button.setAttribute("aria-pressed", String(button.dataset.compat === state.compat)); | |
| let timer; | |
| const later = (key) => (event) => { | |
| state[key] = event.target.value.trim(); | |
| clearTimeout(timer); | |
| timer = setTimeout(render, 150); | |
| }; | |
| $("filter").addEventListener("input", later("filter")); | |
| $("board").addEventListener("input", later("board")); | |
| toggle($("compat"), "compat", (compat) => { state.compat = compat; }); | |
| toggle($("free"), "free", (free) => { state.free = free; }); | |
| const groups = $("groups"); | |
| groups.addEventListener("mouseover", (event) => { | |
| const pin = event.target.closest("[data-pin]"); | |
| // The same GPIO is often routed to several headers | |
| for (const old of groups.querySelectorAll(".pin.same")) old.classList.remove("same"); | |
| if (pin && pin.dataset.signal) { | |
| for (const twin of pin.closest(".board").querySelectorAll(`[data-signal="${pin.dataset.signal}"]`)) { | |
| if (twin !== pin) twin.classList.add("same"); | |
| } | |
| } | |
| // A solder bridge often changes several pins at once | |
| for (const id of pin && pin.dataset.bridges ? pin.dataset.bridges.split(" ") : []) { | |
| for (const twin of pin.closest(".board").querySelectorAll(`[data-bridges~="${id}"]`)) { | |
| if (twin !== pin) twin.classList.add("same"); | |
| } | |
| } | |
| if (pin && !state.pinned) inspect(pin.dataset.pin); | |
| }); | |
| groups.addEventListener("click", (event) => { | |
| const pin = event.target.closest("[data-pin]"); | |
| for (const old of groups.querySelectorAll(".pin.sel")) old.classList.remove("sel"); | |
| state.pinned = pin && pin.dataset.pin !== state.pinned ? pin.dataset.pin : null; | |
| if (state.pinned) pin.classList.add("sel"); | |
| inspect(state.pinned || (pin && pin.dataset.pin)); | |
| }); | |
| inspect(null); | |
| render(); | |
| } | |
| start(); | |
| </script> |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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| { | |
| "001214e7346f1416": "TIM12 to TIM14 debug stop", | |
| "0039846d39059c38": "Security configuration and lock settings", | |
| "00449959ac1e8769": "Write protection pages 8 to 16", | |
| "00647a4b5be97069": "OTGHS support", | |
| "006e9701fcec7941": "Receive enable acknowledgement", | |
| "008e9c22592c2a83": "Group counter value", | |
| "00a1b0968265dc94": "Smartcard and block transfer support", | |
| "00a2b514581b89a3": "ADC3 to ADC5 support", | |
| "00ad31552c84c962": "Additional analog switch selection", | |
| "00af0fddfdc1d2e6": "LSE support", | |
| "00b789663808a08f": "I2C4 debug stop", | |
| "00cf4097b41c19df": "AES support", | |
| "0142838afffc8668": "APB peripheral clock freeze", | |
| "014d557abb991061": "AES support", | |
| "0159aa95f1dc4101": "I/O compensation cell", | |
| "01627a30cbe9009f": "Line 21 trigger configuration", | |
| "016555a8d72b90a7": "Lines 0 to 85 configuration and status", | |
| "017a3bfd4edf56db": "TSC support", | |
| "01832bdb0aa9a729": "TIM3, DFSDM1, and UART4 support", | |
| "019a52ce7dd99df7": "Trace IO configuration", | |
| "01ab7e5ad0267ba1": "Capture/compare channel 1", | |
| "01b49764cdac41b1": "System clock and peripheral configuration", | |
| "01d601d4dc29faa0": "SRAM2A write protection pages 20 to 31", | |
| "01e7a2eca88ce2a2": "Timer 6 and 15 support", | |
| "01f5d4b3bcc59e1c": "Dual flash mode support", | |
| "02053e634596b4ab": "PTP synchronization settings", | |
| "02157a43600289da": "Clock source selection", | |
| "02185d0b8d1363a0": "Peripheral identification", | |
| "021af0a7e1dcaf74": "Display and memory peripherals security", | |
| "024f66585a8b113b": "Data reversal output", | |
| "02857c040fbf9f6e": "I2C fast-mode plus activation", | |
| "02a3a9e881d3c16d": "Security and privilege on line 18", | |
| "02cb02171d374550": "Software reset", | |
| "02e0a2876486804c": "Prescaler configuration", | |
| "03157caf0de749bc": "Wake-up pin and pull-up/down configuration", | |
| "0322947e1e9d4f32": "Data reversal and initialization", | |
| "03410096304b50b8": "Polynomial configuration", | |
| "0354c7bc5a548e48": "DMA2 and USART3 support", | |
| "0355f1ad2cd36a3d": "Backup registers 5 to 15", | |
| "036631df40f4a316": "Wakeup pin 5 configuration", | |
| "03743667aa44b0fb": "SRAM2 write protection pages 0 to 9", | |
| "0384cbcc0c6ae056": "Write protection area 1", | |
| "03c0da3a8b59c209": "Slave mode and trigger selection", | |
| "03d96a81d1ab6ea0": "Line 23 configuration", | |
| "03e2912e52a4b6dc": "Watchdog thresholds and calibration factors", | |
| "03e73d8af8f70b4c": "Cortex-M0 lockup output", | |
| "03f95c1eeed026e3": "Channels 5 to 6 control", | |
| "0412a2dae2e90842": "OTFDEC2 security protection", | |
| "0436338538ebd7e5": "Master voltage regulator status", | |
| "044eacc68785614e": "Interrupt lines 17 to 18", | |
| "045db9cea5333bbc": "Low frequency clock mode", | |
| "04731aaeeadd8326": "Multimode and dual mode support", | |
| "048cd45fb275be84": "SRAM retention", | |
| "0491bba2bebf33b5": "Write protection pages 64 to 107", | |
| "04a6a81b4fca3d59": "Capture/compare channel 6 value", | |
| "04aed24054392ff1": "OCTOSPI security settings", | |
| "04c9f824e01cc5ea": "Event masking", | |
| "04d15ec120431c89": "Master mode selection", | |
| "04d732fcb525dc89": "Tamper inputs 7, 9 and 11 monitoring", | |
| "04e6111e526856c7": "TIM15 and SPI4 security", | |
| "0502115be5acafcc": "Break 2 control", | |
| "0514dcc80912aa7e": "Context swap and digest HR0 to HR4", | |
| "05258d5bbf5c8fdb": "Secure area and write protection", | |
| "0527db9a489a5f70": "DAC and GPIOE peripherals", | |
| "056cf41c194b2483": "Timers 6 and 7 support", | |
| "0571be6f65479d82": "LTDC display controller support", | |
| "0572a28d45ade79b": "LCD interrupt", | |
| "05a7ad6572a12d8e": "Line 26 interrupt masking", | |
| "05c86dd12b1cdd34": "Line 43 interrupt masking", | |
| "05dcf5eaabb5b165": "SHA3 and digest", | |
| "05df5e8e55f54b7a": "Time-stamp sub second tracking", | |
| "05e3cb4a31bf0c10": "Line 16 trigger, software interrupt, and masking", | |
| "05e693a49c676035": "Embedded host and reset detection", | |
| "05ece064b436dbf7": "Line 23 security and privilege", | |
| "05ee6628b458ea24": "Shutdown mode reset generation", | |
| "05fd35248e0e6f25": "Capture/compare channel 1", | |
| "06183fc6d4c3bada": "Capture/compare channels 1 to 6", | |
| "063963bd54a5496e": "Line 23 configuration", | |
| "064fd7248192fbe1": "Analog switch and hysteresis control", | |
| "065562788cbabd8e": "Voltage compensation and FPU interrupts", | |
| "065b3e64529cbff5": "FIFO and interrupt management", | |
| "06816453c0644c8c": "Lines 52 to 86 configuration and status", | |
| "06b9904682b7f5a3": "GPIO retention control and status", | |
| "06be15821c19a532": "MCO1 and MCO2 prescalers", | |
| "06cdbd0256531bad": "Tamper detection pins", | |
| "06cef802f7b0a9ec": "SAES and CCB support", | |
| "06d5ff78b536ce59": "Write protection 12 to 15", | |
| "06de412fbb7dbd74": "Internal high speed clock output", | |
| "06e87f757833d5b1": "Lines 0 to 91 trigger and mask configuration", | |
| "070d2c7e1d55419a": "Flash write protection 1", | |
| "071568dfe63fe400": "GPIO, I2C2, SAI1, SDMMC1 and I3C2 support", | |
| "073b9669d2189729": "Stop 2 flag", | |
| "0772030930bca85e": "USB OTG support", | |
| "078ad7ff3219ab48": "D2 domain and CPU boost options", | |
| "078ce3dfe6d76c3e": "Secondary line mask configuration", | |
| "07b2a69d686502f4": "Multi-bank SRAM ECC and protection", | |
| "07b62ea5869a010e": "Data contact detection and address masking", | |
| "07b73315b80a463e": "ECC enable control", | |
| "07ccaae7e89e0158": "Data transmission and reception", | |
| "07d90d33ce0faefd": "Tamper pin error masking", | |
| "080f6bd923d6a7aa": "Tamper channel selection", | |
| "0814611de33d2ce9": "GFXTIM and SRAM6 protection", | |
| "0838932eba453b97": "Pin PB7 GPIO retention", | |
| "08466491b45ddc79": "Tamper event flag 8", | |
| "087a28fea761a0b3": "AES security settings", | |
| "087c5abbf554fc35": "Line 44 event masking", | |
| "08af8c4355da79ec": "Error correction and protection", | |
| "091da9c9f6220ac8": "JPEG decoder", | |
| "0948577469f31d9a": "LSE clock security system", | |
| "09b84f4c75d341d4": "Lines 10 to 11 input mode configuration", | |
| "09c60b405d16692c": "I/O compensation cell control", | |
| "09cb2e3b20d3be01": "Debug authentication", | |
| "09fb5f2adb3de590": "Line 37 trigger and interrupt", | |
| "09fea1abbe164aa6": "Wakeup pin 5 enable", | |
| "0a10f5a350c817e6": "Write FIFO disable", | |
| "0a432c075fb5ee81": "Line 24 interrupt and event masking", | |
| "0a43cb5281eeeaf4": "External interrupt line configuration", | |
| "0a72dc03f57bf4de": "Complementary output enable for channel 4", | |
| "0a834bc5ed04af8a": "UART5 support", | |
| "0aafa28026a6cc78": "Address offset and bus error handling", | |
| "0abc7595234a732c": "Line 29 event masking", | |
| "0ad0e2f03c5ae4cc": "GPIO analog switch control", | |
| "0ad78309ecf1d38a": "Lines 18 to 19 trigger selection", | |
| "0adf2f3090654fc6": "Receive analog filter", | |
| "0aef6a1b01007e62": "Line trigger and interrupt masking", | |
| "0b50ff873b6f8d81": "Event masking on line 24", | |
| "0b84a01046f7f536": "GPIO retention and supply monitoring", | |
| "0ba0bd5d6e39af03": "USBFS interrupt", | |
| "0bc06bf4b9d0af75": "Bus turnaround phase duration", | |
| "0bc7eb9c15214bcf": "Memory and power configuration", | |
| "0bcbb78ec09305bd": "Regulator voltage scaling", | |
| "0bd91492da28110d": "Remote procedure call configuration settings", | |
| "0be27fc805ba8a1c": "Data sampling delay", | |
| "0be2b1dc07f2fae8": "Access latency control", | |
| "0bea5e8390101eaa": "Channels 27 and 28 sampling time", | |
| "0c1013c17eb66f02": "Message filter bits", | |
| "0c1794077deed09d": "Data", | |
| "0c5b7b4e13691492": "USB OTG and PLL configuration", | |
| "0c5d7600c5ccd52a": "D3 pending request management", | |
| "0c6e2fc1dfcb275d": "I/O compensation cell configuration", | |
| "0c7e398a61bad46e": "I/O analog switch voltage booster", | |
| "0c990ebc4bd57af5": "Debug peripheral clock gating", | |
| "0cab4b4435e66738": "Interrupt and event masking", | |
| "0caefa3986104787": "Regular group channel selection", | |
| "0cb96ed99968e208": "Timers 9 to 11 halting", | |
| "0cd190709962889a": "Tamper input and output management", | |
| "0d0108a707fe581d": "CPU1 APB1 freeze", | |
| "0d2116949eaf362b": "Resistor trim values", | |
| "0d371b6c2fecdbd7": "Read error handling and PCROP", | |
| "0d409c71358d9bfd": "Interrupt enabling for dual core peripherals", | |
| "0d556bc172e4ac51": "Alternate function mapping", | |
| "0d74b1d964ef71de": "Battery voltage sensor", | |
| "0d7a5d5cbd5a4184": "TZSC1 reset", | |
| "0d88d442ae2f1d96": "Port PF pull-up and pull-down", | |
| "0da308a514db4200": "Layer 2 horizontal window stop position", | |
| "0db42bff5419ce3a": "USB device and host support", | |
| "0db869a8a45c34b4": "Computation completion status", | |
| "0df8b9f2703034af": "Bank 1 write protection and PCROP", | |
| "0e09ca763cd08fc9": "CPU2 interrupt and security control", | |
| "0e121a2fbfdf8a81": "Graphics and memory accelerator support", | |
| "0e3b3afc692046c5": "Cache control settings", | |
| "0e5687ed601446a3": "Standby GPIO retention", | |
| "0e587d44b89ec742": "Interrupt masking for line 20", | |
| "0ea03f2c266e88f2": "Bank 1 write protection range", | |
| "0eb19d45a342c40e": "Multi-line capture and data processing", | |
| "0ec019edf9f60b4a": "FM+ I2C drive capability", | |
| "0ed3155ba543d94c": "Oversampling support", | |
| "0efd5a2c28d93189": "Alarm output type selection", | |
| "0f469c2513a14cec": "Domain power down and voltage scaling", | |
| "0f4c95e487360505": "Timer 9 debug stop", | |
| "0f615b60835a9cb4": "Trace IO enable", | |
| "0f77500eebd2da7f": "General peripheral configuration", | |
| "0f944810c44b6e9a": "Memory sub-region watermark configuration", | |
| "0fa04cb8f8b57572": "Analog IO group control", | |
| "0fa5e0e9eba6011f": "TIM8 debug stop", | |
| "0ff99a48ec8ce974": "PKA peripheral support", | |
| "100b2aab31a7c1bc": "Computation and error clearing", | |
| "10331dffc0627a6a": "Ethernet and FMAC clocking", | |
| "104193ca90508bd9": "Channel selection", | |
| "106c053f425fffda": "Repetition counter", | |
| "107a5a9ea0226c1e": "SMPS trimming and status", | |
| "108be0bb6c29ea63": "Low voltage and ECC support", | |
| "10ab540b15061a5d": "Flash and prefetch configuration", | |
| "10b037e7680fd2d5": "PCROP and write protection", | |
| "10c72dd651648ae1": "PTP hardware features", | |
| "1121deb28e6eb40d": "Babble error and sleep rejection", | |
| "112550ec54bce9b8": "Line 30 interrupt masking", | |
| "113ef8dde2548c09": "OTGHS support", | |
| "1142c49279ab63a2": "Monitored channel selection", | |
| "118634ddc103feb7": "USB peripheral", | |
| "11a02f7f2637033b": "Error correction code support", | |
| "11a816aab108d4da": "Line 31 pending interrupt", | |
| "11af8938d32e4d63": "Backup SRAM and comparator control", | |
| "11b04c5d993c7ab2": "Trigger event selection", | |
| "11c1673be21f5449": "System clock and peripheral management", | |
| "11c6841085c02e87": "Security configuration for blocks 12 to 19", | |
| "120598bf50f36528": "Capture/compare 1 DMA request", | |
| "121833972d180725": "Line 32 trigger configuration", | |
| "122ecffb4bcd4bac": "External interrupt and SRAM protection", | |
| "123844fa908f8044": "Error correction code", | |
| "123de16773e0c372": "Dead-time enable", | |
| "124cc5d1044f0847": "Multiplexed mode support", | |
| "125862a16d4feb6e": "Output waveform configuration", | |
| "126b7858abd2d09a": "Early wakeup comparator", | |
| "126c4db100b95d84": "GPIO, DMA, and communication peripheral support", | |
| "126d037fbc04e81e": "Multimode and dual conversion", | |
| "12849ecfcfcc88f9": "Sampling time selection", | |
| "1294f76e1504954f": "Secure block-based bank", | |
| "129b841f0743323d": "GPIO and voltage reference control", | |
| "12a7c8adbe377434": "Analog watchdog and differential mode", | |
| "12b27dc128c2bd08": "Power management and voltage scaling", | |
| "12f6019074947935": "Peripheral request remapping", | |
| "1342050ec8d84b7b": "LCD decoupling capacitance connection", | |
| "137a3ab7e08acb89": "IO manager port configuration", | |
| "137e5440c2fdf033": "TIM3, 6 and 7 clock freeze", | |
| "1389e765012552ac": "Error and secure area extension", | |
| "138e19aab42da6f4": "GPIO retention and USB supply delay", | |
| "1396a12f26762e0b": "Parallel bank mode", | |
| "13ab9f18f8473b21": "Trigger signal selection", | |
| "13b42dad85a059ba": "Internal regulator and interrupt management", | |
| "13c4ab45ca6caf06": "Lines 20 trigger and software interrupts", | |
| "13c8e374548d1b17": "ID division identifier", | |
| "13cfc2b4a2e7cc7b": "USB, SRAM3, SAI, and DFSDM support", | |
| "13e97a07964a8ea2": "Inverting input selection", | |
| "13f9e09bb061d47e": "DMA management", | |
| "140ad84aae341513": "Data and sequence length control", | |
| "141dee44be4b48ce": "TIM4 and 5 clock freeze", | |
| "1449d17b25229677": "AHB1 peripheral clock freeze", | |
| "145f763fd8a2560c": "Line 20 interrupt, event, and trigger configuration", | |
| "1477544669976f48": "Analog IO group management", | |
| "14810c571d34dc5c": "External interrupt lines 0 to 15 configuration", | |
| "148385ecf0eb6d6c": "Wait state and parity error monitoring", | |
| "14854a6984dbe638": "Channel configuration and status", | |
| "148b5ed85dc82bde": "Pin pull-up and pull-down control", | |
| "1493c1b3fbd122d0": "System clock and peripheral management", | |
| "14a69ff4a4897958": "Pin 11 security configuration", | |
| "14ab0953d227fa84": "USART3 clock selection", | |
| "14b668c609967376": "Status monitoring", | |
| "14b993aed2218d01": "TIM5 clock freezing", | |
| "14e25ac8c8bb8cb0": "DAC support", | |
| "14ee2e37ffe0d7f2": "GPIO pin multiplexing", | |
| "14f13403b5805321": "USART1, TIM6, SPI2 and I2C2 peripheral control", | |
| "14f6522716fba663": "Trigger event selection", | |
| "15264ce282ffee06": "External SMPS status monitoring", | |
| "153a04e04e3c5d73": "Event and interrupt masking", | |
| "1546985cba206253": "OPAMP and FDCAN3 security", | |
| "154bb35ddcbda912": "Word-word exchange and flow control", | |
| "155b540610973195": "DSI interface support", | |
| "155ea3d42ba9fd1e": "CORDIC accelerator", | |
| "15629388ad0d6213": "Calibration and watchdog settings", | |
| "159aacf8d6538f61": "Security configuration for line 22", | |
| "15a9fcf733592feb": "SPI4 clocking", | |
| "15b9fb5e039c78a2": "DSI peripheral support", | |
| "15d12b5e26141ae8": "Double data mode and high frequency", | |
| "15e6fdebe8e9ffea": "Line 33 trigger configuration", | |
| "15f6e664ab72508c": "I3C2 freeze", | |
| "1624601c99ea7518": "Flash size configuration", | |
| "1626fe4494a59c64": "SRAM write protection", | |
| "16384d594513088d": "Prefetch and OEM lock features", | |
| "16454862f9730ecd": "DTCM RAM clock enable", | |
| "164b4f17dde24b58": "Wakeup pin 3 enable", | |
| "164cd6c58e558a75": "Pending bit management", | |
| "168b72737c3b1f87": "Multi-domain power management and standby flags", | |
| "16b896e7fba0e48a": "Security and power management", | |
| "16c42e75c8282e2a": "PLL and MCO configuration", | |
| "16c494a52108241f": "Various peripheral privilege configuration", | |
| "16c4e5efb9d7e9de": "Mifare firewall", | |
| "16dd839242a33a22": "Channel acknowledgment", | |
| "16ed4080975b4982": "SRAM2 erase control", | |
| "16f7dbabe42dc519": "Clock division", | |
| "171131988bb56104": "PVD connection lock", | |
| "171d6f711212766a": "Master mode selection", | |
| "1726e68f4a04c7d0": "Secure configuration settings", | |
| "1731ad99da684327": "Wakeup timer and calibration support", | |
| "1732fda01dd37580": "I2C, LPTIM and TIM17 control", | |
| "1759adac8f1c7ea0": "Standby GPIO retention", | |
| "1791bf18ee99f90f": "Secure power configuration", | |
| "17c77dc80dc547a0": "USART3 and I2C2 selection", | |
| "17d58a8aab62f46c": "Lines 24 to 25 security and privilege", | |
| "17e43fa0101a1cec": "Slave mode selection", | |
| "17eb8fe5b791f98c": "Line 16 trigger flags", | |
| "18006413fe30389b": "Hide protection enable", | |
| "181734a4a5a513dc": "CRAM page size configuration", | |
| "1850981e1b853264": "SRAM erase and protection", | |
| "1868a23852c4b6a2": "External debug request", | |
| "186b901f055cae99": "Capture/compare DMA requests", | |
| "187684b5cdf5553a": "Timers 15 to 17 and CEC", | |
| "187b16b5b140a680": "Capture/compare channels 3 and 4", | |
| "18a1bc999c8eb934": "Low frequency trigger", | |
| "18ac2d4a7fb12aeb": "UCPD strobe signal", | |
| "18e2b81d4cc7003e": "Voltage scaling and regulator control", | |
| "18fa24cdaaef6683": "APB1 peripheral clock freezing", | |
| "19051f1f72f71e06": "LCD and SPI2 support", | |
| "190bb5fbdef17913": "Dual bank support", | |
| "192c682353464278": "Data input", | |
| "193a52205d0680aa": "Non-secure erase and protection control", | |
| "1966b4c14d8d743d": "VDDIO compensation and FPU interrupts", | |
| "197aeda65eb94de9": "Time-stamp sub second value", | |
| "19803d5d4e4c1364": "SRAM2 parity protection", | |
| "19a278768adc97aa": "DMA underrun status", | |
| "19dd1526162f2e82": "LPTIM1, RTC, and GPDMA1 stop", | |
| "19e8a9936b55991d": "Burst DMA access", | |
| "19e8e7ac0f11298f": "Line 20 trigger, software, and status", | |
| "19ecd3ee92099dd1": "FIFO and burst settings", | |
| "1a16a6bc3d26926e": "APB1 peripheral freeze", | |
| "1a1b6fd7d6b1dbca": "Power management and voltage scaling", | |
| "1a2a50a25fbef65f": "Line 31 interrupt and event masking", | |
| "1a4b7a1807be3ba5": "Secondary tamper input enable", | |
| "1a4ca067995a909a": "Key protection and selection", | |
| "1a544c15a595cd1f": "Calibration and sample timing", | |
| "1a6dc582cee8849d": "Memory protection and cache control", | |
| "1a753cfcbdfffc68": "TIM13 and TIM14 remapping", | |
| "1a9d2e385ec6c254": "Free-running clock mode", | |
| "1aa9823c3e14e731": "Semaphore interrupt control", | |
| "1b052e62c878d1d2": "Line 45 interrupt masking", | |
| "1b0b733337d96dc3": "Event masking on line 20", | |
| "1b2cd359f638c271": "Data transfer extension and underrun detection", | |
| "1b2e47ab8d651b18": "OEM key CRC check", | |
| "1b3ba11984dc350b": "Digest HR16 to HR39", | |
| "1b6f620a90835d23": "Full DMA subsystem", | |
| "1b8d15849779b683": "High resolution timer debug", | |
| "1bbbc246346932c3": "Channel 1 calibration and sample hold", | |
| "1bc7546a152b4c07": "Secondary detection mode", | |
| "1bcdd1c9a38e1809": "USB interrupt remap", | |
| "1bddd286bc73f65a": "Global interrupt masking", | |
| "1bdfe58f5637e513": "DMA, I2C4 and SPI3 interrupts", | |
| "1be15f5201e10cf4": "PCROP area configuration", | |
| "1beea53832cdc779": "External interrupt line 11 configuration", | |
| "1c42573c9fc1ea86": "Common peripheral settings", | |
| "1c6f6b9899f51749": "Security configuration for peripherals 7 to 12", | |
| "1c779188e1c36eb8": "CPU1 power management", | |
| "1ced46895ffe6ff6": "Analog watchdog configuration", | |
| "1d182d111ceec267": "Transfer size and ID", | |
| "1d1ebff3f4d10834": "Differential mode selection", | |
| "1d365abb6a4da79d": "Device identification and configuration", | |
| "1d5dd7df7a1abecb": "Peripheral security protection", | |
| "1d60f42c0861b229": "DMA burst source selection", | |
| "1d72a24b6e9de085": "Clock source prescaler", | |
| "1d84fe1e35133d1a": "GFXMMU and DCACHE2 security", | |
| "1d88174c44fe9f95": "Sawtooth wave generation", | |
| "1d893569b45543a5": "Peripheral stop in debug", | |
| "1dbc5a83c8689a7d": "Clock prescaler and guard time", | |
| "1de547aa9488c538": "SMPS and secure mode configuration", | |
| "1df0226bd0c416fe": "Advanced power management features", | |
| "1dfc251ae04cdcbf": "Wakeup pin 5 and GPIO retention", | |
| "1dffa261627ad4a7": "SRAM write protection and remapping", | |
| "1e01a6ddfa789ad4": "Standard channel configuration", | |
| "1e53dd3aa12f9833": "Low voltage enable control", | |
| "1e80b6aba012dd33": "DMA buffer size", | |
| "1e868b3fb38775ab": "RNG peripheral", | |
| "1e940b70721fcfc9": "PVD, USBFS, LPTIM1 to LPTIM2 interrupts", | |
| "1ea4cf264e40dd6a": "Memory configuration and security keys", | |
| "1ec3322e42d6a1ab": "I2C3 fast-mode plus", | |
| "1ed4714467522489": "Battery charging mode control", | |
| "1ed883bc667709a1": "Ethernet PHY selection", | |
| "1eda58b58294e567": "CAN2 peripheral support", | |
| "1ee7d778ec57c5f2": "Page empty flag", | |
| "1eeed7e03e56fefe": "Comparator 1 configuration", | |
| "1ef09e3382f31e11": "Channels 5 to 6 DMA requests", | |
| "1f60624eaf647889": "FIFO level monitoring", | |
| "1f6772e5e287dc03": "TIM22 stop in debug", | |
| "1f6efda204dc94ea": "Tamper detection settings", | |
| "1f752c10050a44df": "Privilege mode control", | |
| "1f8d94b17a841128": "I2C fast mode plus enable", | |
| "1fb4a845cc4dc6f4": "USB OTG HS PHY", | |
| "1fd8325e8749af07": "Erase configuration", | |
| "1fe4ef908e5db8ed": "Timer 4 and SMBus stop", | |
| "1ff14df4a18cf421": "Line 38 trigger configuration", | |
| "1ffef487db4fcfd7": "Window vertical start and stop positions", | |
| "20299982accdcba4": "Option byte key access", | |
| "203a5dec7b193213": "Digest HR0 to HR7", | |
| "205423cb9f62aed7": "USB type-C power delivery support", | |
| "20596b7d25d61f0d": "TIM5 clock freezing", | |
| "205eb7163a34976f": "SRAM power down control", | |
| "206139debd3f2d10": "Calibration factors", | |
| "20745ce9bbc1fdac": "Line 28 interrupt masking", | |
| "208d9c0a86ba27dc": "AES and OTFDEC1 support", | |
| "20a0132c3b009799": "Low power mode control", | |
| "20bbcbab02b66744": "Peripheral clock freezing", | |
| "20be41d36312a993": "FDCAN2 privilege configuration", | |
| "20d53dd8d7b15b63": "Memory and voltage boost control", | |
| "20d83590b827ab6a": "SDMMC2 peripheral control", | |
| "20e9ec45a5284488": "I2C3 and LPTIM1 security", | |
| "20ef5c84a1e20a7d": "Address parity check disable", | |
| "20fd4ad2e46dd1c5": "Peripheral clock freeze in debug", | |
| "212154e2a1be09b8": "Command and error handling", | |
| "2140be873cd38ab7": "Interrupt masking for line 18", | |
| "214440ce244a64e8": "Pin PB9 GPIO retention", | |
| "214d0c5036f90236": "SRAM5 power down", | |
| "21647080ed948a43": "I2C1 fast-mode plus support", | |
| "216d73e59219eede": "Channels 30 to 31 sampling time", | |
| "21ad4ff5c9e48701": "Line 24 interrupt masking", | |
| "21dfd4017eeec057": "SRAM write protection pages", | |
| "22020871657dfef2": "Interrupt line 29", | |
| "2210dff49fecd49f": "Capture/compare channels 5 and 6", | |
| "2217e9c5c6278eb4": "LTDCUSB security settings", | |
| "222af6ec13daa1a7": "OTG security configuration", | |
| "22552e807db1fcfc": "SDMMC2 peripheral support", | |
| "2264879680a94b10": "AHB error reporting", | |
| "2267a954d3460a87": "I2C2 freeze", | |
| "228302d5d9ff06e8": "Tamper pins 1 to 2", | |
| "2297260e756d876b": "TIM20 timer support", | |
| "2298657f658b7672": "Extended suspend", | |
| "22a7663677fa4f77": "Lines 43 to 56 interrupt and event masking", | |
| "22af4f7850317903": "Parity check and erase features", | |
| "22bb64eca36bb70d": "Channel 2 configuration", | |
| "22da1f4868c89feb": "Secure masked interrupt status", | |
| "22fbe504d4d37a9b": "Erratic error interrupt masking", | |
| "23110eca627719e1": "Tuning and LDO control", | |
| "2311bb860b52420c": "PVD connection lock", | |
| "231653a16af4d7ed": "Various peripheral clock control", | |
| "233c6ab27908cc8c": "DMA buffer 1 address", | |
| "2357a213df5e442a": "Regulator voltage scaling", | |
| "2361ce0badd52af0": "External interrupt line mapping", | |
| "23ce680b192db640": "Line 58 interrupt and event masking", | |
| "23e8183a8664178a": "Timestamp interrupt flag", | |
| "23e9ba9ef6263901": "Lines 37 to 38 configuration", | |
| "23f58eb54058d701": "Bluetooth radio transmit and receive", | |
| "240094bfe4955ac2": "I3C stop in debug", | |
| "2414694d6926d2c7": "Prescaler configuration", | |
| "242b7d25399a36a6": "Device disconnection detection", | |
| "2434ea12eed35b6c": "Lines 27 interrupt and event masking", | |
| "24398f458dd4ddb7": "ADC 3, 4 and 5 support", | |
| "246a15178a772fa3": "Capture/compare channels 5 and 6", | |
| "247d53ee59e0e2db": "TIM5 and FSMC remapping", | |
| "248a82994163fa31": "Primary analog switch selection", | |
| "24b348e1fcb5e295": "TIM7 debug stop", | |
| "24b89f592ef5a593": "USART2 support", | |
| "254e217c3ba190e7": "Channel configuration and control", | |
| "2553289c7b3edb34": "Regular sequencer and DMA configuration", | |
| "2570283403803349": "Digital calibration enable", | |
| "257adee336d17fc6": "Sub second and calibration", | |
| "25804ed723d1476a": "Peripheral security settings", | |
| "25a855674d76fab8": "Secure channel management", | |
| "25a9ef87be7965cc": "Stop mode wakeup support", | |
| "25aee18768ddbcbe": "Endpoint error and status interrupts", | |
| "25c3880103c71ff4": "Data and error status", | |
| "25f6f31f5e632a0e": "Low frequency trigger mode", | |
| "260b6be8cdc2188c": "System clock and peripheral management", | |
| "26121e4e92c9a4de": "LPTIM3 and LPUART3 interrupts", | |
| "2615ef7b9044cf29": "Clock prescaler", | |
| "261932ba8a656153": "Peripheral clock and reset management", | |
| "2620276cb6cf6047": "HDP area extension", | |
| "26248d3dfdd6dac8": "Security and hardware lock configuration", | |
| "26370d9a242ed977": "I2C4 fast-mode plus", | |
| "264f44c236b9de05": "USB power delivery features", | |
| "2660bd71a4135101": "Peripheral request remapping", | |
| "26688b9ef51e1bc7": "Line 31 software interrupt", | |
| "267138c3e0f43c7d": "Analog watchdog thresholds and sampling time", | |
| "267aab223aeafa48": "Sleep mode debug enable", | |
| "26969a2f2891bbfe": "USB peripheral control", | |
| "26d7a072d57b42a9": "TIM17 debug stop", | |
| "26de0a5f36803909": "PLL Q output configuration", | |
| "26e02c68e0f2d97e": "AHB write protection and debug access", | |
| "26e82830cbb9890f": "AES, SAES and OTFDEC1 support", | |
| "2733f23b8151ca29": "Sub second value", | |
| "274277aaed5a9b4e": "Line 34 interrupt masking", | |
| "274e886863cb71ca": "Flash and wakeup pin control", | |
| "275eb9a0f6a0d032": "Line 46 interrupt masking", | |
| "2772fd214f0fad63": "SRAM and GPIO retention", | |
| "27784e9ddd36cc65": "Timer 7 debug stop", | |
| "278fef60abf7dfb2": "Complementary output control", | |
| "2826a7ecfe6e74a8": "I2C2 security settings", | |
| "28561c7d09f4b8bc": "Single mode and remap selection", | |
| "2859adc00c04246b": "Boot pin selection", | |
| "285e7c9ef6d7e12b": "Hardware request selection", | |
| "28658317b0145438": "I3C2 security", | |
| "2868b3216a9bc3a7": "Global interrupt masking", | |
| "287c44a670c5bcbb": "I2C fast-mode plus support", | |
| "288e9789d0a59fea": "Full cryptographic data processing", | |
| "28c183cc967fd11a": "SDMMC1 security settings", | |
| "28c5b2b9afcc7161": "Block-based privilege control", | |
| "28d02427bbb3293a": "Channel configuration lock", | |
| "28d678b2e25517c4": "Advanced security and write protection", | |
| "28e006d12ff737f3": "ADC3/4 and timer 8 support", | |
| "28fb23cf024a48ba": "Backup registers 16 to 19", | |
| "28ff2e2ee7fcc9e7": "USB OTG_HS power management", | |
| "29416bba8457516a": "VDDIO compensation cell control", | |
| "29489cbae7406f92": "GPIO, FMC, TIM4, TIM8, TIM5, and TIM17 support", | |
| "294dc9c405eea5a2": "DMA channel management", | |
| "2952dc7c08813234": "Timer 2", | |
| "295da1e5d930dc1d": "Key mode and error interrupts", | |
| "299c9799f3c4fe7a": "Line 0 input mode configuration", | |
| "29bba1cb7e3de0b5": "General peripheral configuration", | |
| "29be5c743bdb5f94": "Line 16 interrupt and event masking", | |
| "29c7c33cd7b72b25": "Write protection area boundaries", | |
| "29caf222899a1aa1": "Secure and non-secure programming control", | |
| "29efa3c7fed160ff": "Access port presence", | |
| "29f4c0d390e7cd11": "Common configuration and sensor paths", | |
| "29f650f6b06ff276": "Boot and erase settings", | |
| "2a079e3ddf4059c9": "LPUART and LPTIM support", | |
| "2a0ce573933899a8": "System power and voltage control", | |
| "2a0e4b0c81550b97": "Line 29 interrupt masking", | |
| "2a289951ea27a127": "USART and DMA clock control", | |
| "2a309f7addd84259": "FPU and SRAM security enable", | |
| "2a3f72398487481e": "Privileged access protection", | |
| "2a47bc41d906cdfd": "DMA, SDMMC, DFSDM, SAI, and OSPI clocking", | |
| "2a5865ca56839fa9": "Read, user and write protection", | |
| "2a599b8691c3be26": "Output enable", | |
| "2a89db3b1c5880be": "Early interrupt flag", | |
| "2aaf7a995aa8933c": "Timer 14 debug stop", | |
| "2ab1ef5dc1abb591": "UART5 security settings", | |
| "2accee14bd9a1749": "Channel 4 and 5 configuration", | |
| "2b17d81078b67d84": "FDCAN1 debug stop", | |
| "2b3ec07aa02edb9e": "Secure mode control", | |
| "2b8a135057a99d86": "Active tamper filter control", | |
| "2b995d0dc7ce8921": "SAI1 peripheral support", | |
| "2be92ec0c0c937f0": "Calibration and data conversion", | |
| "2beb3e25ce5dae9d": "Dual bank support", | |
| "2c039b90e1ebc21d": "Secure backup domain protection", | |
| "2c061d35ae004c1c": "Low speed oscillator and trimming", | |
| "2c0a31379318013f": "I3C2 debug stop", | |
| "2c48fe9fd2271da8": "TIM2 to TIM1 protection", | |
| "2c50846c72661e70": "External interrupt line configuration", | |
| "2c72082eee164169": "DMA request identification for channel 7", | |
| "2c98f9026c7a4fac": "Oversampling and watchdog features", | |
| "2cbc46d41e0e8928": "Channel selection", | |
| "2cbc553ed1d0dac1": "Guard time interrupt control", | |
| "2cd596986add6a82": "Backup erase function", | |
| "2ceaf527c65540ec": "Window value management", | |
| "2d2e551a03176154": "Backup domain protection", | |
| "2d392f9d31b34f33": "Input selection for tamper pins", | |
| "2d61b6de6edb95b5": "Synchronization for channels 12 to 13", | |
| "2d681d60ea908771": "Line 40 event masking", | |
| "2d7808391ccbab9c": "TIM4 debug stop", | |
| "2d867e9f4f5343ff": "Analog watchdog and short circuit detection", | |
| "2d9f6fc305f4632d": "Option control settings", | |
| "2e02edb8cb3576a1": "Tamper channel 4", | |
| "2e0a7b62d474e0d5": "Protection area boundaries and keys", | |
| "2e14174456084284": "Autonomous mode control", | |
| "2e15a111a25793ef": "SPI and I2C clocking", | |
| "2e41250cdff03955": "LPUART2 and FDCAN support", | |
| "2e4d77de3fdecb68": "Output idle state 2", | |
| "2e4ff543b04f2bfa": "Debug clock enable", | |
| "2e5f8a5298182d52": "Output and switch control", | |
| "2e65771a9a24b02f": "Line 88 D3 pending and mask configuration", | |
| "2e81673f96357a9e": "Multimode regulator status", | |
| "2e86d127c3c9033a": "UCPD1 to OCTOSPIM2 protection", | |
| "2eb0558e6ab6e9e1": "Tamper channel 1", | |
| "2ebc2d0cb6da2a23": "Memory address channels 1 to 3", | |
| "2ec06968efa409c8": "TIM16 and TIM17 stop", | |
| "2ecfeed9f4e37a52": "Write protection sectors 64 to 95", | |
| "2ed968f049734daf": "Capture/compare channel 2", | |
| "2edd65031c1cb1b1": "Counter reset functionality", | |
| "2ef184765eed5cc0": "TIM8 clock freeze", | |
| "2ef8d97bcd12e6fc": "System clock and peripheral management", | |
| "2efcf29bb42fdd83": "Write protection management", | |
| "2f0e45738bdbf5eb": "Line 38 interrupt masking", | |
| "2f1e384fb42556ba": "Input line 0 configuration", | |
| "2f2afe5fd6300b21": "Configurable device secrets", | |
| "2f612269496e2112": "Security and memory erase status", | |
| "2f6f09f890bfcc80": "DMA controller features", | |
| "2f76d8d1f220dc23": "LPTIM3 interface", | |
| "2f84e31b99173a6b": "Timers 12 and 13 stop", | |
| "2f8b28361bb23743": "Pin remapping and interrupt lines", | |
| "2fad789406ec3d11": "Boot and security configuration", | |
| "2faf48c588600c86": "Lines 28 to 29 event masking", | |
| "2fbc4551299820a1": "Remap selection", | |
| "2fcf98edfccc7b93": "Interrupt line 29", | |
| "2fdf35c4d16bbece": "Analog IO group configuration", | |
| "2fec068f752b1591": "Port PF pull-up and pull-down", | |
| "2ffc66f6ccd52672": "OTFDEC, USB, and XSPI support", | |
| "300f93ebbd993d02": "VDDUSB, CRS and TSC interrupts", | |
| "302a4022c3e68f88": "SRAM2 write protection pages 10 to 15", | |
| "3047c21ca47a5807": "Interrupt masking for line 25", | |
| "3058e653b8ee085f": "Line 17 edge detection flags", | |
| "305b325432b1a2ca": "System clock and peripheral management", | |
| "305ef12a6ebbaf8e": "OPAMP support", | |
| "3075fb2358be6df0": "Line 20 event, interrupt and trigger configuration", | |
| "30b6c306ac9c7a92": "Synchronization overrun flags for channels 12 to 13", | |
| "30c313d8ed206983": "Memory access timing and protection", | |
| "30cbcb5656a8bc3f": "Channel preselection and calibration", | |
| "30cd63af64ba911f": "Encoder interface support", | |
| "30dc90ea1da5c3a0": "Analog signal attenuation", | |
| "30e12f746e84341c": "Hardware identification and version", | |
| "3105bacd2b7ec305": "Device identity information", | |
| "31203b34694840d4": "Suspend state management", | |
| "317af364557a92e6": "SPI4 interface support", | |
| "31b3e80b9b8af09a": "Error handling and status", | |
| "31b5dcfd610dd5b8": "Peripheral clock and reset control", | |
| "31cda18703aae8db": "Privilege configuration for blocks 4 to 11", | |
| "31e00059812ba5a2": "I/O pull-up and pull-down control", | |
| "31e87cfdc0a0abd0": "General configuration", | |
| "31ee757fb73cd236": "Security and privilege modes", | |
| "3202dfb2cf23ea4f": "Line 26 interrupt and event masking", | |
| "32049d2d8173caf6": "Counter value", | |
| "32073211f0650074": "USB power force", | |
| "320a88b83e3e73ee": "CRC, JPEG, and DAC clocking", | |
| "320aefdfd649ba28": "Capture/compare control update selection", | |
| "320afef882574865": "Peripheral channel request remapping", | |
| "32290a82d87abb5d": "Lines 37 to 42 configuration", | |
| "323199602767fbd6": "Differential mode selection", | |
| "32489414bdb21fd5": "Peripheral security protection", | |
| "324cf20f6383348f": "I2C fast mode plus", | |
| "32561de390aa80b0": "TIM3, DFSDM1, and UART4 peripherals", | |
| "325a31aab934be15": "Line trigger and interrupt configuration", | |
| "325b665bfaf7d12c": "Flash ECC error signal", | |
| "325c6bead0b3e5ff": "CAN2 clock freezing", | |
| "325e0df86e9699d4": "TrustZone security configuration", | |
| "325eb2bdc52220b7": "I2C5 debug stop", | |
| "327089a0f7a31aa2": "Channels 27 to 29 sampling time", | |
| "328314819dfc9ab1": "ADC and HSI14 support", | |
| "32999d28e5a51c1c": "Digital calibration support", | |
| "32b5df61bed07105": "Secure memory access control", | |
| "32bd677b926a2787": "Independent data input", | |
| "32c08c164471fd4e": "FIFO threshold setting", | |
| "32ca5f528c7f316b": "Memory type selection", | |
| "32db3faed77139ea": "Update event interrupts", | |
| "32dd762769c87d3d": "Synchronous counter reset", | |
| "32e73df85a91a6f9": "FMC controller enable", | |
| "33242e1d15c86563": "Line 22 pending flags", | |
| "333aee57728432ee": "Secondary ADC operation flags", | |
| "3356cb2de1a2da27": "Oversampling and one bit mode", | |
| "336333cb6c4f4f4d": "PLL and clock source selection", | |
| "3367357ec51ed4e3": "I2C2 fast mode plus enable", | |
| "336f32d07d4b9726": "Port E pull-up/pull-down control", | |
| "3386c5bb0599b698": "Global hardware configuration", | |
| "338aae4d1be4d24c": "UART4 support", | |
| "3392c97a64514ca5": "Multi-channel digital filter configuration", | |
| "339c0420edbfe74f": "Error correction code status", | |
| "33cdaf74ac154982": "Cellular RAM page size", | |
| "33d1361f79d978fd": "DMA channel interrupt line mapping", | |
| "33d341aed62d0c56": "Active tamper and counter features", | |
| "33d72f9f44ffc7dd": "Memory remap and external interrupt configuration", | |
| "33e84d227a8aff28": "HSPI1 and memory sub-region 6 security", | |
| "33eca9e4d6756dee": "Hardware flow control", | |
| "34291b888c213654": "Channel 1 trigger", | |
| "346553179e629ccc": "Window mode enable", | |
| "346dfdb88ca9567c": "Wakeup timer event flags", | |
| "3485073544032532": "Peripheral suspension during debug", | |
| "3491ff67c2506e78": "USART2 and SPI1 control", | |
| "3498fd1156472018": "Output buffer control 2", | |
| "349a2c667b17ba16": "Frame prefetch error handling", | |
| "34b1869747628641": "Wakeup timer and alarm functions", | |
| "34cfc15e444b086c": "Timer 15", | |
| "34d3498d99dac548": "SRAM3 low power clocking", | |
| "34daf4aa238d1777": "Center-aligned mode selection", | |
| "350de36e0b6bf6f4": "SAI2 and GPIO support", | |
| "353b91ccbc5e67d9": "Backup registers 9 to 15", | |
| "354499f0dea5585b": "Host pulldown resistors", | |
| "3560bf48b0286174": "Voltage reference scaling", | |
| "3578cf8b1f7083a4": "Lines 0 to 14 trigger and configuration", | |
| "357cbe6dd539a852": "Port F, G pull-up/pull-down control", | |
| "3585136a23ed6dd5": "ADC3 to 5 and timer 20", | |
| "359f0411838909b4": "Non-secure page selection", | |
| "35d0d5a4e9f5cafc": "Watchdog selection", | |
| "35e4328402a3cd6d": "Event masking for line 21", | |
| "35e517243cde271f": "Window output selection", | |
| "35ea61298f1d76d5": "SRAM and pull configuration", | |
| "35eb6937fcb53782": "AES peripheral", | |
| "3640fb6cb83ec4eb": "Voltage scaling and pin pull-up/down", | |
| "365c1c9a25e2a0e3": "SAI1 interface support", | |
| "365c8570cb5c1d05": "Tamper detection channel 3", | |
| "3661d3e37932ee79": "High density protection level 2 jump", | |
| "368188be150f9058": "Timer 11 debug stop", | |
| "36893850c65b8624": "Bank selection and protection status", | |
| "36a197cc6e0de833": "Calibration and differential mode settings", | |
| "36c042c1c00df953": "Configuration settings", | |
| "36e7a8dd5908e99a": "Secure HDP area access control", | |
| "36e9a86b4f7a051b": "Operation monitoring and aborting", | |
| "36eb04c5eb6267ee": "Memory address channel 7", | |
| "37078ff173259d3b": "Endpoint error and status interrupts", | |
| "3735366c9b2308e5": "Pin remapping", | |
| "3739b53fefd74e1e": "Secure area and protection boundaries", | |
| "374e6b75ce995a2d": "Advanced pin configuration and delay", | |
| "37548ee497ce790e": "Interrupt lines 16 to 17", | |
| "376ab8add1e1802c": "Word count status", | |
| "377990b1ad82088e": "Tamper channel 2", | |
| "379574b333520312": "External wakeup pins and GPIO retention", | |
| "379c911d4f8a178a": "Battery voltage path", | |
| "37bfce5b9a1e37e2": "Early interrupt status", | |
| "37ca33e81dbceb49": "Block-based secure access", | |
| "37d5a1a5144bcc62": "Secure power function protection", | |
| "3809ddb1a01d64fa": "Port pull-up and pull-down control", | |
| "3820c00fec7e3dc5": "Ethernet and DCM peripheral support", | |
| "3828b9a383726b4e": "Core soft reset status", | |
| "385049c2133aa65d": "Secure area and write protection", | |
| "38537b4756d2141f": "APB peripheral debug stops", | |
| "3856d6b1066d4283": "All wakeup pins enable", | |
| "385b6fc0eab6f48d": "LIN and auto baud rate", | |
| "389c5aea7dbae08a": "Input line configuration", | |
| "38a5a987194789ad": "Capture/compare channel 1", | |
| "38b3198d4905ce14": "System clock and peripheral management", | |
| "38c95a9f0f3c34fa": "ADF mode configuration", | |
| "38e6ee21ccef55b4": "Line 36 pending interrupt flag", | |
| "392dff31bb5d01b7": "GPIO, SPI, I2C and DMA management", | |
| "3983dc38846ad653": "Half cycle access and read protection", | |
| "398cd2b4f168fd15": "Cryptographic hardware acceleration", | |
| "39b097047f125b17": "Interrupt management", | |
| "39d1d16d312fe8f3": "Common segment data memory", | |
| "3a01051f6578532c": "Total memory capacity", | |
| "3a0272ad8e2a1605": "UART8 to UART10 and DFSDM", | |
| "3a4af5e50178e1b0": "PATA and SAI1 selection", | |
| "3a7ef2678502a6a5": "Security and privilege configuration", | |
| "3a856d506cece90e": "Data management and calibration features", | |
| "3aaf9eee25d812a6": "TIM17 support", | |
| "3ac00605fb05d934": "Timers 4 and I2C2 debug stop", | |
| "3ade7919c71bd484": "Linked list DMA support", | |
| "3adf8a0fbb9648d5": "Receive FIFO full interrupt", | |
| "3ae80404c7560335": "Independent I/O supply monitoring", | |
| "3af5270f904e9a19": "Read error detection", | |
| "3af7355836cc5cb6": "Lines 18 to 36 trigger configuration", | |
| "3b1e7cd53ae3668a": "Lines 26 to 42 trigger configuration", | |
| "3b2afbe6352c4437": "Analog switch control", | |
| "3b442ce96f66caab": "Operational range setting", | |
| "3b4c6537db7dbc5b": "Non-secure memory operations and error handling", | |
| "3b6645ee8cb97fa9": "Bluetooth error edge detection", | |
| "3b83a907686a784c": "Idle state selection", | |
| "3baca7c31ebcdb18": "USB and CAN support", | |
| "3bb26dd93a883c46": "Stop mode wakeup", | |
| "3bda71507237c7e5": "Linked list DMA management", | |
| "3bfcd1f1a355260b": "Crypto peripheral", | |
| "3c0b69ad1ea4f734": "Channel data and interface settings", | |
| "3c240ee98ec99391": "SRAM2 retention in standby", | |
| "3c7498e35c09f1f6": "Alarm B masking", | |
| "3c758cf73c20c83c": "Non-zero check and BFB2", | |
| "3c8752e2e7219050": "Port PD pull-up and pull-down", | |
| "3ca3c18a40e18501": "JPEG and LTDC support", | |
| "3cad2c38c1e10584": "System peripheral support", | |
| "3cc193bfaeda742e": "Trigger DMA request", | |
| "3cd7dd062f67b4fe": "Block and address offset control", | |
| "3cf962d3683cddb4": "Peripheral and clock freezing", | |
| "3cfc4df726aef76d": "Peripheral and clock debug control", | |
| "3d01b69c419bf662": "Page and area protection", | |
| "3d12a41fdef4bab4": "Lines 32 and all event/interrupt masking", | |
| "3d248ae8f6d5e3ad": "ECC error management", | |
| "3d3975cccbce6d8f": "Bank 1 PCROP areas", | |
| "3d4ab10fda8abf78": "Port pull-up/down configuration", | |
| "3d54aa7d5264b7b5": "Clock output selection", | |
| "3d819339224e0ffa": "Security configuration for blocks 12 to 15", | |
| "3d8c0ae9ad522ae2": "Multimedia peripheral security", | |
| "3d9a18bce8f5bd82": "CAN1 and ADC clocking", | |
| "3df3297728a2748c": "Tamper input and output management", | |
| "3e3aca57dbf34312": "Data and key management", | |
| "3e407f13843fd7b8": "PLL multiplier", | |
| "3e57d6cfb500fbbf": "USART6 security configuration", | |
| "3e898de5c8f4b638": "DMA2 and SPI3 support", | |
| "3eb0fc2837238085": "SDRAM memory geometry and latency", | |
| "3eb45495d829fa80": "Semaphore core ID", | |
| "3eb914aa5d9a1f6d": "Comparator support", | |
| "3ecac6b01284a3c7": "Line 36 interrupt and event masking", | |
| "3ed407e5432a071e": "Memory address and count channel 8", | |
| "3ed5bcddd7644445": "I2C6 debug stop", | |
| "3ef38c7bd20c42b9": "Timer 7 debug stop", | |
| "3f091000c5708207": "Interrupt masking for line 17", | |
| "3f29c04cc58a287c": "Slave mode selection", | |
| "3f4aa38c1f0613eb": "Read protection error reporting", | |
| "3f59687f0529db49": "SDIO interface support", | |
| "3f964612244bf2d2": "I/O voltage booster and parity lock", | |
| "3f9f55223d8d8c91": "Voltage monitoring interrupts", | |
| "3fa8ea97f4b12eae": "Interrupt line 19 configuration", | |
| "3fb9d22021344ae4": "Layer 2 configuration", | |
| "3fc2d62f5d63528e": "External interrupt configuration", | |
| "400fcaf9368a3688": "Bank swapping and I2C3 fast mode plus", | |
| "4034ff1c4979c83d": "Backup registers 5 to 8", | |
| "4046ab76cd562acc": "Window watchdog freeze", | |
| "405372211a79cd3a": "Core operational status and control", | |
| "405ef91433d8e475": "External interrupt line mapping", | |
| "409141f78b8e0769": "Option bit 1", | |
| "40a47daeb02f509a": "CRC, error detection, and option bytes", | |
| "40a7f071a0972fd3": "GPIO port D", | |
| "40d5ae49e35c0ae0": "PKA security configuration", | |
| "40de7ec87c6451a3": "Clock source selection", | |
| "4103f539f8db3650": "3D video support", | |
| "4113f281b69ae4b9": "SAI and DFSDM security", | |
| "411de7f35225012b": "Timer and CEC remapping", | |
| "4149bb4b265dd62d": "Algorithm selection", | |
| "415bc6bdc62a477f": "Interrupt line configuration", | |
| "41a405feb34aa45e": "Wakeup flag management", | |
| "41b26d2cd73a8250": "Byte-level data access", | |
| "41bdb5e8e9c1fa25": "Data reversal and initialization", | |
| "41c70f58b2a38c0b": "Tamper 1 flag", | |
| "41e3b146420f773c": "Timer stop in debug", | |
| "41f15e28d4a974a4": "Memory and FIFO configuration", | |
| "4207a333e7a87ede": "SRAM write protection register 2", | |
| "420a3cb08b24d937": "High speed mode", | |
| "421c6ca17aec56d2": "Sequencer and sampling configuration", | |
| "423a30217fbecbda": "Tamper detection flag", | |
| "423cdd0692e50a12": "Hardware configuration options", | |
| "424cde167af4904f": "Health test and conditioning", | |
| "424da5e45c869ed0": "Memory remapping", | |
| "4262c187c1c69335": "Additional active tamper output", | |
| "426e5bd84e6d5a75": "Input timer selection", | |
| "4270ca61bbcc421d": "LPTIM1 support", | |
| "4272857828f6055f": "Synchronous slave and clock settings", | |
| "428786e274011ee7": "DCMI PSSI security", | |
| "4291b3a05cbdf9b0": "LCD rail capacitor connection", | |
| "42b14d8039ff6fae": "Tamper channel 5", | |
| "42c652c299bdfc79": "Comprehensive security and protection", | |
| "42e1eb33937eda5e": "Line 19 pending flags", | |
| "430cc63ffd8d4670": "Capture/compare preload control", | |
| "432e03916668eff7": "Non-secure boot and ECC features", | |
| "4330889177efd21b": "32-bit data input", | |
| "43402cc3ce821d0a": "Group counter value", | |
| "436f21ea4b29ed0b": "DMA channel 0 freeze", | |
| "4389e6bb1558cceb": "I2C4 and SPI4 support", | |
| "4399eaa468d182a4": "Backup regulator control", | |
| "43b7e773c68bcf69": "Trigger and input remapping", | |
| "43c115d8d4f4187f": "Non-secure channel protection", | |
| "43cd1a1bcfc07529": "Odd/even byte and line selection", | |
| "43d0f4b642956730": "EEPROM deep sleep off", | |
| "43e94d0546694613": "Line 42 event masking", | |
| "43ede88edc77c6e4": "Host and device non-compliant host support", | |
| "4406db8791a975f9": "Low power mode debug control", | |
| "441981f6463bc3d2": "Bank 1 write protection and PCROP", | |
| "442e10beec6e90e7": "Security keys and page access control", | |
| "4437fbbd7fb1f8a9": "PLL3 clock configuration", | |
| "444203bc3c126cff": "Security enable", | |
| "4473ad800ef76932": "Bank swapping configuration", | |
| "449757aec7807a38": "TCM RAM sharing and frequency boost", | |
| "449c19cca1b21fe3": "Digest HR5 to HRA4", | |
| "44a9080a828c3ad6": "Trigger and interrupt for line 20", | |
| "44b77153aad09d93": "HSI trimming", | |
| "451c5c0e7d0fe885": "Low power baud rate", | |
| "4532bfb07fe1e253": "OSPI, SRAM3, and OCTOSPI delay", | |
| "453d382b8e161546": "Chaining mode management", | |
| "4548ebb986d58982": "Multimode operation and common control", | |
| "454b86742f8b970f": "DSI host interface", | |
| "455de35c1d9aab03": "On-the-fly decryption regions", | |
| "457c8a053c1ef16c": "Reverse register read", | |
| "459429f3a6315808": "Memory protection and ECC", | |
| "45a775b34a3ef4ea": "Channel 19 sampling time", | |
| "45c7c6c42f3a8d44": "CPU1 APB1 peripheral freeze", | |
| "45cb94988c20f6ae": "Backup data registers 11 to 34", | |
| "45d374ae406c7ea8": "I2C2 fast mode plus support", | |
| "45d514bc3e70f92c": "SPI 2 and I2C 2", | |
| "45e82d9c51ad0d56": "CRAM page size for bank 1", | |
| "45f9e5d50bd392f1": "TIM1 debug stop", | |
| "45fdf10a36d7e817": "Trace port configuration", | |
| "46034159a2f8b296": "Alarm B sub second tracking", | |
| "461038f826af78a0": "PVDOUT interrupt", | |
| "46196e93898cfd27": "Output type selection", | |
| "462a9fd1e2415419": "Address error correction", | |
| "463a5765b46bcff7": "USB and wake-up pin configuration", | |
| "4645622f4fc99f13": "SAI1 security settings", | |
| "46969fbaf02bde90": "CAN clock freezing", | |
| "46a4d67b63e3db08": "Port pull-up and pull-down control", | |
| "46ae33e6fbdc568c": "External trigger output enable", | |
| "46cfc4828f27b45a": "Peripheral clock configuration", | |
| "46e809832d75c97c": "Multiple ECC error channels", | |
| "46fbd901546a002b": "Peripheral DMA remapping", | |
| "470e24e2258851d2": "I2C3 and LPTIM2 clock freezing", | |
| "4713f26339813762": "Lines 43 to 51 event masking", | |
| "472461eb190a8469": "USART, UART, SPI and SAI security", | |
| "473785346ecafa39": "Lines 39 to 41 configuration", | |
| "475e48604c29c7ae": "Comparator input selection", | |
| "47c45f62749e7545": "Data transfer count", | |
| "4849f7b2a3817b32": "FMAC and GPIO interface control", | |
| "484b415425e2dbc4": "CAN1 debug stop", | |
| "48b824658a0b877b": "CAN2 halting in debug", | |
| "48c324133eec41a4": "Debug authentication and component identification", | |
| "48ca39c9bdc441d8": "Remote procedure call configuration", | |
| "48cf79f3430e1897": "MCO2 output", | |
| "48de8e5e922a7aeb": "Multimode DMA configuration", | |
| "48dfcf9896f17289": "Operation error handling", | |
| "48fe12115f453ff0": "Window mode enable", | |
| "490b48ef15af56d3": "FIFO threshold level 4 bits", | |
| "491e08355bbbe4f7": "MCO2 clock output", | |
| "4942637583dbdfa7": "ECC and write protection banks", | |
| "494b757bab564010": "Interrupt and security access control", | |
| "495a64467708b852": "Voltage scaling selection", | |
| "4967b5dd76b2a7d3": "Digest calculation results", | |
| "498adde834a6c185": "USB voltage monitoring and pull-up/down configuration", | |
| "49a2e8393d239f81": "Lines 49 and 51 pending status", | |
| "49c9f4c06483577d": "Timestamping functionality", | |
| "49d5dabfcdd6dbff": "Wakeup pin configuration and flags", | |
| "49eef06639cf1bae": "SAI2 clock selection", | |
| "4a067cc146dda757": "CAN debug stop", | |
| "4a15a733edb29a1a": "Tamper input and clock selection", | |
| "4a2de7ff0bf7139c": "Hardware request selection", | |
| "4a31628a6246980c": "Non-secure memory protection and ECC", | |
| "4a50d5a597dae89a": "Configuration and conditioning", | |
| "4a580a8aa58e051c": "Peripheral flow control mode", | |
| "4a62fd32426c15ce": "Low-power mode and I/O configuration", | |
| "4a83e4ba3b7cebc9": "Configuration locking", | |
| "4a8d76911aaa88a6": "Fine and coarse calibration", | |
| "4a914ef84d8e6f3c": "Autonomous mode", | |
| "4a9e268d8be35395": "Channel 7 configuration", | |
| "4aa1bf873c553939": "TIM12 debug stop", | |
| "4aac24dea5ab9287": "Master mode selection 3", | |
| "4ac2d014ac439d52": "Peripheral clock freeze in debug", | |
| "4ac5e917f9402954": "Interrupt masking on line 24", | |
| "4adaf791366dc51e": "Smartcard and block features", | |
| "4af7cdd58192b96d": "Secure hide protection extension", | |
| "4b0da74c10c8529e": "Block and address offset control", | |
| "4b26389aa695d131": "Security configuration for blocks 28 to 31", | |
| "4b3b18b5d748f239": "Cryptographic and hash support", | |
| "4b72c819e5a24737": "Lines 21 to 22 security and privilege", | |
| "4b76338e30795359": "Secure boot and operation features", | |
| "4ba90602ced3361a": "Lines 0 to 85 interrupt management", | |
| "4bad39b775b268f5": "SRAM ECC and secure blocks", | |
| "4bbec3e5554c1a8b": "Endpoint 4 and 5 interrupts", | |
| "4bcbbb93ac32dfbb": "Line 32 trigger and interrupt", | |
| "4c21a0c3c4714d80": "DMA remap", | |
| "4c4020cedc80a67d": "UART and SAI clocking", | |
| "4c5f5fda51d5f364": "Voltage booster and strobe signals", | |
| "4c7bcbf7f720e174": "Timer and USART clock control", | |
| "4c7ee58736536ba4": "Channel 6 and 7 configuration", | |
| "4c8c2b873f39c3ac": "Sector erase selection", | |
| "4c92939152a2a9e4": "IN transaction AHB errors", | |
| "4cb6aae3341006d3": "BNA interrupt masking", | |
| "4cd4425c2452943a": "Tamper detection flag", | |
| "4cd9268905a83c45": "SMPS converter support", | |
| "4ce75a1520035d42": "Multiple peripheral and bus clock freezing", | |
| "4d49d862c774c3f1": "USB host interface", | |
| "4d69481bd6174114": "Line 18 trigger selection", | |
| "4d76b6fc1fad4658": "Data hold and byte lane setup", | |
| "4d7a0dd237a6e506": "Data protection and redundancy", | |
| "4d7fe618347a41a7": "Operation error reporting", | |
| "4d8985391cb7b9f4": "Internal trigger remap", | |
| "4d8b90a477838987": "Secure boot and provisioning services", | |
| "4d8c739cfebbfda9": "I2C2 fast-mode plus", | |
| "4d99c55793cbec79": "Non-secure write protection", | |
| "4de670c67811cab2": "Write protection 2 and 3", | |
| "4de74848115ef295": "Power and window mode control", | |
| "4df60bed895b9b01": "USART3 support", | |
| "4dffd2da7321f5fb": "Lines 18 to 20 pending flags", | |
| "4e2110214974156c": "General programming and option management", | |
| "4e32b8ca50fd7f65": "Line 34 interrupt and event masking", | |
| "4e3b0693112be444": "Lines 18 to 22 event masking", | |
| "4e429ed938134162": "OPAMP3 specific features", | |
| "4e5043cb24a0326b": "Trace output control", | |
| "4e51086481b84e96": "RSS command execution", | |
| "4e54a4f9313e48af": "I2C fast mode plus and parity lock", | |
| "4e5e61ba904b4299": "GPIO port E control", | |
| "4e7bd849e5860c03": "Channel delay and sample skipping", | |
| "4e9a12ebfe83f351": "Channel 2 configuration", | |
| "4eb58321f48d1b87": "Additional babble error interrupts", | |
| "4edeb3821d9c8b4e": "Data length and buffer addresses", | |
| "4f354879e807e4b0": "Tamper channel 4 protection", | |
| "4f76d92ad9128ccf": "802.15.4 radio wakeup management", | |
| "4f77020c08d074af": "OTG FS and UART5 support", | |
| "4ff9485942b72526": "Pin pull-up and pull-down control", | |
| "4ffaa84bbf4f0f1e": "Power mode and hysteresis", | |
| "5015910c9f30ad3a": "Channels 12 to 13 DMA requests", | |
| "5018599b17bad4cf": "I2C4 SMBus timeout debug", | |
| "501ad45477a1f05f": "High speed IO configuration", | |
| "5023ff878b73d449": "Synchronization for channels 5 to 6", | |
| "503208f2a553fbea": "TI frame format error detection", | |
| "503e9b4ac6856df0": "Timer 2 debug stop", | |
| "50408731048e0b69": "Data transfer count", | |
| "5046e738af46a966": "High density protection level jumps", | |
| "504c99de92062c99": "ADC channel and SRAM protection", | |
| "50981f4bec83bc9a": "GPIO pull-up and pull-down control", | |
| "50a34298c1710e97": "Clock prescaling", | |
| "50ba2f94f89d687b": "Layer 1 horizontal window stop position", | |
| "5118c3ed74dcbbca": "Analog watchdog 2 and 3", | |
| "513076e8ab62645e": "Extended SRAM2 and external interrupt configuration", | |
| "5134f2f67dc89232": "CAN3, DFSDM and MDIO support", | |
| "5161564be44f8831": "Error correction code address", | |
| "516abf817271e0ed": "Watchdog and timer debug stop", | |
| "5170ebfbbd0eb70e": "VBUS discharge and pulsing", | |
| "517cf8ae7478ec9d": "SDMMC2 security", | |
| "5184f41b52e882d1": "CAN2 peripheral support", | |
| "51936cd583928849": "Internal voltage reference and bandgap", | |
| "51975134151e228a": "Capture/compare channels 5 and 6", | |
| "519c153c28f4750b": "I2C4 freeze", | |
| "519c448cbf9abe7f": "Secure mode interrupt status", | |
| "519fde943beca675": "Waveform and amplitude generation", | |
| "51c4c63e2a3bf767": "Dual bank write protection", | |
| "51c9f7c244a3da73": "Dual mode configuration", | |
| "520fa03c2a9c62a9": "Backup domain and supply control", | |
| "52315ad5fa5ed697": "PCROP area configuration", | |
| "523ba8bc20b87e4c": "Break and dead-time control", | |
| "523ee168ab052f97": "SPI3 and I2C3 support", | |
| "52617c74052cebb8": "FIFO assignment", | |
| "5263075f3e39e5f9": "Memory remapping", | |
| "527db9ada47afdc7": "LPUART1 interrupt routing", | |
| "529746d58e11f0be": "Sleep mode debugging", | |
| "529c664a62fba664": "Line 46 edge detection configuration", | |
| "529f1585fefd8d5c": "Non-secure security features", | |
| "52a30caa77663813": "Sectors 96 to 127 protection", | |
| "52b21e8c77f40b5a": "TSC support", | |
| "52b321aa3a4c5775": "APB0 and APB1 clock freeze", | |
| "52c0eb2f86c32285": "CRC calculation", | |
| "52d69da427d0bfd6": "Special request management", | |
| "532575dc3d7e4754": "Limited mode support", | |
| "534939a2d43217e8": "Component identity and peripheral stop", | |
| "5366a551e2105838": "SRAM2 write protection pages 10 to 15", | |
| "5368070259eb0b90": "Lines 19 to 54 trigger and mask configuration", | |
| "537da52e47db7e1e": "Watchdog channel selection", | |
| "53cd7a41c8f45276": "TIM4 and TIM8 debug stop", | |
| "53dc14ab37f660be": "Pin PB10 to PB14 GPIO retention", | |
| "53dee05b77820e9d": "USB OTG_HS power support", | |
| "542aeb4cc99531e8": "Bank power-down key access", | |
| "5434987883d2574d": "Multiple peripheral clock selection", | |
| "5453b4dbfefd6d0c": "Channels 7 to 13 DMA requests", | |
| "545bb2e05121b543": "Write protection pages 17 to 31", | |
| "546101e583d01142": "Hide protection area management", | |
| "54689c4f852db8bb": "Trigger signal selection", | |
| "546b24021ac51822": "Privilege and security configuration", | |
| "5488b37364232cc9": "Complementary output for channel 2", | |
| "54a5137ace79d8b8": "Voltage monitoring and detection", | |
| "54b1ff8f65bc6d7a": "Component and peripheral identity", | |
| "54b88ce5d67d6516": "Pin pull-up and pull-down control", | |
| "54c1daae20ea89dd": "Tamper protection settings", | |
| "550f894313784595": "Master key management", | |
| "5523b4aeb1e5a8bd": "OTGHS security", | |
| "55300202464c7f8b": "ADC2 and CAN1 support", | |
| "5530f02aeea8ccad": "Port H pull-up/pull-down control", | |
| "5531bd4a2f075ddc": "GPIO, SPI2, USART3, and I2C2 peripherals", | |
| "553cc14febae7067": "Pin PA0 GPIO retention", | |
| "557d5ba465d4b54f": "Trigger signal selection", | |
| "55876a8534676e7a": "Break function configuration", | |
| "5587a718cd6abf72": "Independent I/O supply voltage", | |
| "5587edd21b58b56a": "LCD peripheral support", | |
| "55a1980ff8d6bfca": "UART4 clock selection", | |
| "55a6bd2d4c745182": "Event masking for line 18", | |
| "55ac9571f9be0ea9": "Port PF pull-down control", | |
| "55c57b24ddea93bf": "Block based privilege and security mapping", | |
| "561e4627df620762": "Bank 2 dual bank and PCROP features", | |
| "5620d02c260056c0": "Security and peripheral configuration", | |
| "563adcb24aa554b2": "Clock and power management", | |
| "565384ef4af1e076": "SDRAM initialization and status", | |
| "565e9b23bb04b1a2": "TZSC and SRAM4 protection", | |
| "566a60455eb61297": "System clock and peripheral configuration", | |
| "567ff5c706e0e4fb": "I2C3 fast mode plus", | |
| "56cab91854f19059": "Analog output pin configuration", | |
| "56d7333ace21979d": "Timer 6 and CAN1 debug stop", | |
| "56e8fbdcba820c02": "Sleep and trace control", | |
| "57242e5a90b98d49": "Output color values", | |
| "573704002691f60e": "OTG PHY support", | |
| "574d6afa8e36fee8": "Active tamper output", | |
| "57b2a91933915753": "I2C3 debug stop", | |
| "57c015ca010f6471": "CPU2 peripheral freeze", | |
| "57e9c495184555a2": "Voltage booster and ECC lock", | |
| "5800aa5cae3e235c": "Wake-up line management", | |
| "58268a06cf563c9d": "Line 46 interrupt and event masking", | |
| "5832e8ebf56a95c4": "Channel 6 and 7 status", | |
| "586a1a798751ea87": "TIM16 and HSI48 support", | |
| "5876d838db6c79d9": "IP identification and version", | |
| "58cc0c8f55567e5d": "Lines 29 to 30 trigger configuration", | |
| "58f73b0bfcf7be4a": "Channel interrupt flags", | |
| "5906302b1be5b8cf": "LPUART1, I2C3, LPTIM1 and ADC4 security", | |
| "5906375eafb99114": "Memory remapping", | |
| "591d7e13cbd5a982": "All lines masking", | |
| "592b85cf59bd4fc8": "ADC internal connection and CPU boost", | |
| "5954d221a2194b37": "Counter and auto-reload", | |
| "595e33e0628b82ce": "SRAM parity error control", | |
| "596ae66398e18540": "Analog watchdog and channel selection", | |
| "5979b41c52653127": "Channels 3 to 4 control", | |
| "597f10510a673b19": "Lines 19 to 20 security and privilege", | |
| "5983526c7750571f": "System break interrupt", | |
| "5989fc615ae51ddd": "SDMMC2 interface", | |
| "59b9b6734330afc6": "Lines 28 to 30 interrupt masking", | |
| "59d92c53609b449d": "Lines 19 to 20 pending flags", | |
| "59e802ae0340d412": "High frequency mode", | |
| "5a2eb6f5fcaeeab3": "Memory and core security", | |
| "5a340c4acfafb92e": "Interrupt masking for CPU1 and CPU2", | |
| "5a40f49ee7e1104e": "Master clock generation", | |
| "5a41ab5fd95f0846": "I2C5 and I2C6 security", | |
| "5a46e39ab425e0cb": "USART4 interrupt", | |
| "5a519295b9a00398": "LCD support", | |
| "5a9dac4b3e2c862f": "Parity error detection and protection", | |
| "5ac7127050ee1404": "HRTIM support", | |
| "5ac826c2006f53c3": "Lines 18 to 36 interrupt and event control", | |
| "5acf8b62ec886dc6": "Timer 5 support", | |
| "5ad4f096834ab085": "Multi-channel digital filter configuration", | |
| "5ad7a4404b108d86": "Security attribute assignment", | |
| "5b64cd0f214b48aa": "Privileged state configuration", | |
| "5bda0bd009241a82": "Synchronization for channel 7", | |
| "5bf52181ac276453": "Dual comparator configuration", | |
| "5bf91d92b69b93c9": "APB2 freeze control", | |
| "5c3d95a164ec7395": "Monotonic counter", | |
| "5c4b466de1f944f4": "Update and repetition control", | |
| "5c4c98e033c52f0d": "DMA control", | |
| "5c55b9e319ed27de": "ADC and timer management", | |
| "5caa4d82c8a46143": "Voltage regulator and calibration", | |
| "5cceedb1a0fa7cf1": "PDM interface support", | |
| "5ce4d0f75d00b3eb": "Write protection register 2", | |
| "5cfe0339acae174a": "Dual bank mode", | |
| "5d047dc4a03f69f6": "RAM retention and SMPS trimming", | |
| "5d158407cbfb4197": "Tamper pin 8 support", | |
| "5d1acba170d48f56": "Output compare 2 mode", | |
| "5d2553580ec68917": "Channel delay and sample skipping", | |
| "5d2f2fa980a15bb6": "Tamper and flash ECC interrupts", | |
| "5d3afc30499bc75a": "Lines 21 edge detection flags", | |
| "5d3da5e04d79bf62": "Timers 12 to 14", | |
| "5d41246e980a9247": "Port pull-up/down configuration", | |
| "5d8a6679a1b63c9a": "Security configuration for blocks 4 to 11", | |
| "5d8fb45906b91799": "Boot address configuration", | |
| "5da42a4e63804399": "Trigger selection", | |
| "5db460bb4b9fc705": "HSI48 oscillator smooth trimming", | |
| "5e1b8d9ebf78fbe7": "Read, user and write protection", | |
| "5e5bec44f12d084b": "Dual-core interrupt and event masking", | |
| "5e735e33e2d4a5e0": "Sleep mode control", | |
| "5e88ea755ace72a3": "DMA2, GPIOI, and DCM support", | |
| "5ea1a52bbd6d5665": "Injected sequence and watchdog status", | |
| "5ea52f7ef2991cdb": "Cryptographic hardware acceleration", | |
| "5eb74145272c6abd": "Bitrate prescaler", | |
| "5ecf0644180a6df4": "Alarm A masking", | |
| "5edeebbe8986ed22": "Data transfer interrupts and flags", | |
| "5ef57143ab60f354": "Clock source selection", | |
| "5ef90355b56f2dff": "Line 32 interrupt and event masking", | |
| "5f09cb3d99db8852": "Memory sub-region watermark configuration", | |
| "5f0c8d85e05e0cfd": "Clamping diode enablement", | |
| "5f2f9ba6ac7b1d53": "Input plus selection", | |
| "5f3566380f8a9656": "VBAT support", | |
| "5f6a0eca1c52d2e6": "Peripheral clock freezing", | |
| "5f77b5ca2c321de2": "Security and privilege on line 0", | |
| "5fa3ab8a3e21bba4": "Wakeup pin 2 configuration", | |
| "6004c30f46f26d44": "Protection mode selection", | |
| "6027e6ecae2a235e": "Page number selection", | |
| "605c596a77d3c9dd": "CEC support", | |
| "607666136e829453": "Reference voltage path", | |
| "60827fbd0f4d2af6": "Injected queue overflow monitoring", | |
| "609450e3156c58b9": "GPIO, SPI6 and DMA2 support", | |
| "60a27b9c1fc54d42": "Event and interrupt masking", | |
| "60a3cfd6ad169779": "Maximum transfer size", | |
| "60ada67a4141c2e1": "Line 20 software interrupt", | |
| "60b02fc599148e15": "Multimode status and data", | |
| "60b2b66a33112f7c": "Sector erase selection", | |
| "60ef0cda47d1e3c2": "I2C fast mode plus support", | |
| "60fa6b41b22bafc6": "Master/slave mode selection", | |
| "61309f55bc9fecc6": "Extended parity error monitoring", | |
| "6159e144450bf833": "Privileged block-based bank", | |
| "61968be2cb2f1943": "Cipher context configuration", | |
| "619c2257cccaa3ba": "USART4 peripheral", | |
| "619de6ad1ad393e1": "ADC, DAC, and clock output", | |
| "62086012f61a366e": "Non-secure memory features", | |
| "621e4c2061062c59": "Page number selection", | |
| "6229ca01e0f14bcc": "Block-based privilege management", | |
| "622f3dcc9e594f7c": "USB power supply management", | |
| "623a7e00224d6a18": "Security and lock control", | |
| "62599f24952e0f7b": "Lines 38 to 49 trigger configuration", | |
| "62733c85a2aef1a4": "Line 18 interrupt and event masking", | |
| "62790d555c5fe245": "Line 25 interrupt and event masking", | |
| "627bc5c9c4cbf6b5": "SPDIF, I2C4 and CEC support", | |
| "627ca697cac13af2": "Memory and core lock control", | |
| "6283a68114b15a51": "I3C2 peripheral control", | |
| "62c2b54adf3d7ea0": "AES and SAES security", | |
| "62c510e48fb136b9": "Failing data storage", | |
| "62c8984bcaa72b72": "DSI security protection", | |
| "62f100d1f0092b3a": "VBUS and ID sensing", | |
| "62f18880a4e5fb73": "I2C4 and SPI4 support", | |
| "62f38697b3c0f7ba": "TIM10 and TIM11 debug stop", | |
| "631cdc46b131f72d": "Tamper detection interrupt and erase protection", | |
| "63301b9dabed3d4f": "Input line 16 configuration", | |
| "6343f5e9c72bdcf7": "Lines 60 to 63 mask settings", | |
| "634d01a885b98fa4": "Peripheral clock freeze in debug", | |
| "635f2113b008ce93": "I2C fast mode plus support", | |
| "637225ddecaa142d": "GPDMA1 channels 8 to 11 stop", | |
| "637c86644bb32b14": "Dual core interrupt and security access", | |
| "63a90d4c9cbb9564": "Debug freeze mode", | |
| "63b4278953dc421a": "Health test and noise management", | |
| "63b8b22b473e9b46": "Timers 9 and 11 debug stop", | |
| "63be7446ee66eece": "SDRAM burst and timing configuration", | |
| "63f1e88e0cc3f787": "Chaining and coupling mode", | |
| "63f20d205071a813": "Shutdown and wakeup modes", | |
| "63f46c7933335ff2": "Operational mode and error management", | |
| "63f6bbf99413bb14": "USART5 peripheral", | |
| "641283217b28e9c9": "Line 40 trigger and software interrupt", | |
| "6421a51b223e89e1": "Clock configuration settings", | |
| "645bd0ffc0c7ad38": "FDCAN2 security protection", | |
| "6479b8d08805ae4b": "COMP1 and DAC interrupts", | |
| "64b832f91751bd4b": "Repetition counter", | |
| "64bebd37d58e5711": "SMBus and PEC support", | |
| "64c22bcf5bdba13a": "Security and protection features", | |
| "64cb67dfefa6b646": "Over and under drive control", | |
| "64dd8b2c14c965a0": "Peripheral suspension and access", | |
| "64fbce3692329b47": "Peripheral clock and source configuration", | |
| "65550afd825bd9d8": "Global interrupt masking", | |
| "656e7a51d2008174": "HASH hardware acceleration", | |
| "6575500c35569ee1": "Peripheral and memory security settings", | |
| "658fb1b04cc7c7e3": "AES peripheral", | |
| "65b6f65bdbf65580": "Line 46 trigger and software interrupt configuration", | |
| "65db83c9632c8944": "Timer stop in debug", | |
| "65e463daa72264ff": "Rising and falling edge pending status", | |
| "65e79c94c55871d2": "Lines 46 to 54 event masking", | |
| "65ebe1879f0adb87": "Timer 6 debug stop", | |
| "661a69a427d55fa2": "Capture/compare channels 3 to 6", | |
| "6625e99e557e5a7c": "USB type-C power delivery support", | |
| "6667e7a41e177d91": "Line 34 event masking", | |
| "66bb60f72e638029": "OTFDEC2 peripheral control", | |
| "66c0f5df74c29811": "Peripheral clock and reset control", | |
| "6709ef2fc0bd7517": "Line 36 trigger and interrupt", | |
| "675caad2bc5e85fe": "TIM2 interrupt routing", | |
| "67a35c61c6b69baf": "Lines 10 to 11 interrupt and event control", | |
| "67afaadc348015a1": "Connection detection modes", | |
| "67c97470897600da": "Analog switch control", | |
| "67d4228a002afb00": "Linked list DMA support", | |
| "67e0c5ffd56a4a64": "Multi-bank protection and PCROP", | |
| "67e788b3b88eb597": "External trigger configuration", | |
| "683c59bac4975d97": "LIN, IrDA and smartcard modes", | |
| "6853d000f01c1b41": "Analog watchdog and short circuit detection", | |
| "6869668b325183a9": "Graphics accelerator security", | |
| "68792a5c672d85b1": "Lines 51, 77 trigger and mask configuration", | |
| "68a7847eb65aca24": "Auto reset disable", | |
| "68ba69cea646223f": "Line 35 interrupt masking", | |
| "68bf38dd7315160c": "Chroma sub-sampling selection", | |
| "68e61174204b6c94": "Data reversal support", | |
| "68e743fc4637a46a": "Parallel bank configuration", | |
| "68ec0d67791873f7": "Wakeup pin configuration", | |
| "68fdb58b2ce4a862": "Address cache management", | |
| "692852db60310692": "Layer 1 vertical window start position", | |
| "69441d56e2d41842": "SRAM3 power down", | |
| "6954ee0c5dc83628": "SRAM and JPEG power down", | |
| "6a197dd3e4bed64c": "SDRAM burst and timing configuration", | |
| "6a60fd41915fafc6": "GPIO and SPI2 support", | |
| "6a706d919342532d": "Device configuration 4", | |
| "6a83da1cbee857c5": "Auto baud-rate detection", | |
| "6aa2be42d0f6f413": "Trigger selection and software interrupt generation", | |
| "6ab9c9ae2366f655": "Peripheral security configuration", | |
| "6abe07706a336870": "Line 41 event masking", | |
| "6acaff4d761b0548": "Data alignment and resolution", | |
| "6ad96d8a8783bfb9": "Channels 3 to 4 synchronization", | |
| "6ada05e6542a147c": "Core operation control", | |
| "6ae66c5778169ac4": "Flash abort interrupt masking", | |
| "6b003a7e73a679bd": "32-bit dual mode data", | |
| "6b0c509c717d8822": "Bootloader close and exit extension", | |
| "6b1c598b2409ad47": "Interrupt line 7", | |
| "6b24adb322eb64dd": "Multimode and sensor support", | |
| "6b25ab05c3d32028": "Line 32 event masking", | |
| "6b50eb4d56b59d4e": "LSE configuration", | |
| "6b515dbd016a7564": "Ethernet security", | |
| "6b57862d4800cf54": "Alarm B", | |
| "6ba95aab3864e6d5": "HSI48 clock", | |
| "6bd864b2d60ea8a8": "Write protection pages 64 to 75", | |
| "6be5995fe16cae07": "Semaphore core ID backup", | |
| "6bed367817c16cde": "ECC error detection and correction", | |
| "6beec3eb89d610e9": "Complementary output enable", | |
| "6c23732760c304a6": "I2C driving capability and parity lock", | |
| "6c7dbc5953f576c8": "Security and memory erase control", | |
| "6c8a01dc59311f2d": "Write protection 4 and 5", | |
| "6c920044f06cb117": "CEC and UCPD support", | |
| "6cb2bdaa2cb42d54": "Tamper channel 3", | |
| "6d0e0eb0dca8d266": "Line 34 trigger configuration", | |
| "6d0fbf96776aff20": "Line 23 interrupt masking", | |
| "6d81e4e4710711ae": "Semaphore security status", | |
| "6d9397a3ed39b752": "AES, RNG, and AES/RNG support", | |
| "6d99fd1e3d5c5a1e": "AES and PLLSAI1 support", | |
| "6dd60a7b0eb4222d": "OEM key and operation management", | |
| "6dee426fcb9c8a29": "GCM/GMAC context swapping", | |
| "6df9484923ccc279": "QSPI support", | |
| "6dfdf92cc12cd8e3": "Block based protection settings", | |
| "6e0526b1f3fb69eb": "High-speed low-voltage support", | |
| "6e2b65ca0b9d0a45": "CCB interface", | |
| "6e33cd2e40b2f191": "GPIO ports F and G support", | |
| "6e5c2c4a5f855bca": "I2S audio configuration", | |
| "6e6281dc1e3933b7": "Hardware request selection", | |
| "6e8000db0df7aeee": "GFXTIM security configuration", | |
| "6e9ce5a44088dc86": "General purpose peripheral management", | |
| "6ea06435b84306cf": "Calibration interrupt and flag", | |
| "6ea8de645dee850a": "Output 2 remap", | |
| "6ecba701de6cfdb3": "Line 18 trigger and interrupt control", | |
| "6ed3845ae21570e1": "Line 36 trigger configuration", | |
| "6ed97fee9dfde8c2": "Buffer overflow management", | |
| "6eef93971acdf4bb": "Peripheral remap and encoder mode", | |
| "6f337b7aa11a381b": "Peripheral interrupt line management", | |
| "6f3a62cb3721101c": "Timer, DMA, SPI, and UART clocking", | |
| "6f6b1815194c8016": "ADC digital filter configuration", | |
| "6f7f4b5085d917a6": "Line 29 trigger and interrupt control", | |
| "6f91d85339003170": "Vcore monitoring", | |
| "6fa17c601d707268": "Dedicated suspend register set", | |
| "6faa0f0842ff6606": "Slave mode control", | |
| "6fb719fbe411c274": "Pin pull-up and pull-down control", | |
| "6fbbccaa1ce56a74": "USB clock selection", | |
| "702579bbc4e23ba0": "LIN break detection", | |
| "70622a971c0c50b1": "Low power mode control", | |
| "708f58362900f38b": "FMC and TIM5 support", | |
| "7098c5e9e1f50ed9": "Dual-core interrupt and event management", | |
| "70a1a4fcaad3ce88": "Ethernet PHY interface selection", | |
| "70b845a0aad6f711": "Multimode and common control", | |
| "70ebc5f1fef40a2d": "IRDA modulation and interrupt polarity", | |
| "70f2fad0d584f5c4": "Event mask on line 47", | |
| "70f4e8ca3f26e068": "Timer 2 clock control", | |
| "710596b922970f23": "Backup SRAM and comparator control", | |
| "71175ec91a46f574": "IP identification and version", | |
| "71335e672e634a09": "Channel side and underrun management", | |
| "71384420b1385ed8": "Restart maker configuration", | |
| "713c8f644538cca9": "MCO prescaler configuration", | |
| "7167b0d2fe2d8386": "Line 19 configuration", | |
| "71725627ecb5d4ba": "SAES security configuration", | |
| "7173d48014d4bce2": "Alternate interrupt masking", | |
| "717b104923b78b1a": "Alarm B sub second", | |
| "718ffbf3612d770e": "Endpoint and transaction management", | |
| "71943abbe8f67a42": "Lines 18 to 35 interrupt masking", | |
| "71b5dfcebf595485": "Authentication and DMA control", | |
| "71c833e554a103ad": "CORDIC security access", | |
| "71d2e9fc93671d86": "Line 21 trigger, software, and status", | |
| "71e98cd12996d9cd": "Sub second tracking", | |
| "71f146302df06b52": "Pull-up and pull-down control", | |
| "723b43c8e20f34f7": "DMA request identification for channels 5 to 6", | |
| "7267dcb0a2ba4126": "SRAM power-down and stop 2 flag", | |
| "72759b8021091919": "Trigger and mask configuration", | |
| "728d6781a92bb51a": "Security and protection features", | |
| "72a0eca0f68b4ed3": "Write protection pages 8 to 39", | |
| "72a19ff8cd3f4803": "SRAM power-down and pull control", | |
| "72baa005f000094d": "Subsecond and alarm binary mode", | |
| "72ce2b59f80d210f": "Multimode operation", | |
| "72d26e52c70f35b0": "VBUS input override", | |
| "72d3686ce4a8a854": "Channels 14 to 15 DMA requests", | |
| "72ea8850915af5fb": "System and security configuration", | |
| "72fff5703c4fec58": "Trigger remap", | |
| "730cba0bb0c79e2d": "Monotonic counter", | |
| "73269bdb440f8373": "Output buffer control", | |
| "73399d3b56eb28d6": "Cortex-M7 boot address configuration", | |
| "733e65aa13c61caa": "Oversampling", | |
| "7348de28a7850e3f": "Error and tamper interrupts", | |
| "734f1718431a0f2d": "Wakeup pin polarity", | |
| "7357d8684ddeb06c": "Line 30 trigger and interrupt", | |
| "735dee266eb03752": "Random data output", | |
| "736104fe8241aaf5": "Line trigger and software interrupt configuration", | |
| "738541dea50790d0": "Debug clock enablement", | |
| "738e90e0aa3e2688": "Super block lock control", | |
| "73aa757905da877e": "Battery charging detection", | |
| "73b46f288c0339d5": "SRAM and GPIO retention", | |
| "73bf3694cd01099e": "DAC 2 and 4 support", | |
| "73c3a8f1cd0ee9ca": "Trigger event selection", | |
| "73c4c6595311a859": "Hide protection area configuration", | |
| "73d5bca97f50604e": "I2C fast mode plus and SRAM parity", | |
| "73edd94227ef926d": "Low-power and voltage scaling control", | |
| "740235a998c69e0e": "Output type and bit set/reset", | |
| "7407952e8e5c8c40": "FIFO management", | |
| "744c8681f57e4404": "High-speed IO voltage configuration", | |
| "74548d5f3af1c725": "Security attribute assignment", | |
| "7480d812f4fdabed": "APB2 peripheral freeze", | |
| "74a687a7fc350c3b": "Peripheral debug freeze and trace control", | |
| "74b591f9fea4d4b8": "Boot mode selection", | |
| "74bf201bcc7c3646": "Channel 2 features", | |
| "74d38ce171a46366": "Hardware identification information", | |
| "74d67548eb8d0430": "Peripheral DMA remapping", | |
| "74d9bd6aa20d7eb9": "LTDC support", | |
| "74daffafed78dd11": "GPIO pin multiplexing", | |
| "74ffe1e2dec5d440": "Timer and DAC clocking", | |
| "7508546e6dd60eea": "PVD break input connection", | |
| "75441d254d587572": "Wakeup pin 2 enable", | |
| "7548dba917c4101f": "Context swap", | |
| "754e242c80a135d5": "Calibration and watchdog features", | |
| "756015b4b86d9e03": "Semaphore process ID", | |
| "75aaec035729e392": "D1 and D2 domain power down control", | |
| "75c53ae6b3a92491": "Instruction and polling configuration", | |
| "75d10024f15aedcf": "Proprietary code read protection 1", | |
| "75d12fa003bde398": "Index blanking", | |
| "75ded1087275ce8d": "Option byte and OEM key management", | |
| "75e10e78c48355e9": "Common control and sensor enable", | |
| "75e9807c988d821a": "CRYP hardware acceleration", | |
| "75ffc78b071a8a65": "USART3 and TIM4 remapping", | |
| "7605d0b4e74d6b42": "TIM15 debug stop", | |
| "760dbb89fb86c586": "All channels sampling time", | |
| "764e76ada208e20a": "Serial communication interfaces", | |
| "764e868289c5b2bf": "LDO regulator control", | |
| "767c640c501eda86": "Voltage scaling and SRAM power-down", | |
| "76a11073ca03f760": "SPI2 peripheral", | |
| "76c26ca12f6663b3": "Voltage scaling and SRAM retention", | |
| "76ed31f37b2be314": "Multiple ECC error channels", | |
| "76f559a35540501d": "I2C2 peripheral", | |
| "7709b9e9c84913b9": "Bank 1 security and write protection", | |
| "771d5267c33c9180": "Input lines 10 to 11 configuration", | |
| "7730d8bd436f575c": "Lines 50 and 53 trigger configuration", | |
| "773babbfa3a33989": "Timer 16 and 17 interrupts", | |
| "774d0622e0ce5bdb": "PLLSAI and multiple peripheral support", | |
| "77639ef5145d2e86": "Monotonic counter 1", | |
| "77697a842f88b3dd": "ECC error address reporting", | |
| "776df3233d6d6d08": "LPTIM4 security configuration", | |
| "7774d8765e75ab82": "NPU stop in debug", | |
| "777ddd06b23c524f": "Trigger source selection", | |
| "7783690bdecddb54": "VBUS power down", | |
| "77927cc1213fb6b0": "Line 22 trigger and software interrupts", | |
| "77b7ba8743fc765b": "Peripheral clock freezing", | |
| "7805a17903ebad1e": "Port PF and PG pull-up", | |
| "7813f8df039ca2f2": "LTDC peripheral support", | |
| "7820e43ffc34303e": "SMPS bypass interrupt management", | |
| "783bfcaa452ba9d2": "SDRAM initialization and timing", | |
| "7909d02233984227": "Clock and peripheral configuration", | |
| "79532449a044fc35": "Ethernet support", | |
| "798f05faf965bcac": "Lines 46 to 53 trigger configuration", | |
| "79ad26f0b0deb2b3": "General control and status", | |
| "79e2cdda16a872dd": "GPIO port E", | |
| "79f8837fea6f58af": "Lines 65 to 74 interrupt masking", | |
| "79fa32f3a6d5a22d": "Internal voltage reference path", | |
| "7a0d920d2156aaf7": "Peripheral freeze control", | |
| "7a10197e11c90ed2": "Line 27 interrupt masking", | |
| "7a1fbdb51fe84a2d": "MCO2 output selection", | |
| "7a3445e002b2e3db": "External interrupt configuration", | |
| "7a3da67cbc5e24b5": "Proprietary code read protection 2", | |
| "7a68591275eaa3f0": "Sleep mode configuration", | |
| "7a9efdcd879056da": "Capture/compare channel 1", | |
| "7acee7fb428d960b": "Cortex-M4 lockup output enable", | |
| "7b443d5f74d7d0f2": "Data transfer count", | |
| "7b8ce433e8c4680d": "Enable status monitoring", | |
| "7bd0aaf00e068deb": "MCO, HSI48, CR, and RTC peripherals", | |
| "7bfc332089f1eb91": "Debug mode configuration", | |
| "7c07e0b8433f3526": "I2C fast mode plus", | |
| "7c0b886322aac03c": "NAND flash and PC card support", | |
| "7c7e4ddb3bbf1d83": "Security and privilege on event 16", | |
| "7c818d7f507505d7": "APB1 peripheral clock freeze 1 and 2", | |
| "7cb15f844c0afba1": "USART6 peripheral", | |
| "7cec32d7dad062d8": "Channel sampling time", | |
| "7cf3d164a5981df2": "Port F and G pull-up/pull-down control", | |
| "7d04f3017ac371c4": "Operation and tamper events", | |
| "7d30bdc097ce835e": "Timer 15 debug stop", | |
| "7d315ebf3cf179e2": "JPEG hardware acceleration", | |
| "7d60c7858cfd1349": "FSMC and SDIO support", | |
| "7d612b34754baea7": "Line 26 interrupt masking", | |
| "7d6396ae5d8897a5": "Write protection and boot configuration", | |
| "7d63f11bc2eb1680": "Auto-reload value", | |
| "7d689a8210be68cd": "Stop 2 mode IO retention", | |
| "7d74ae9e9fa8883a": "Multimode slave group control", | |
| "7d7f09f01ac9f2b1": "SAI2 PLL division", | |
| "7d88bcfef076f8ba": "Voltage reference scale selection", | |
| "7de4fd9ef9c68a71": "Flash and memory remapping", | |
| "7df4e8d54b78cc61": "Clock and output configuration", | |
| "7df909d2268ad651": "Transfers per buffer size", | |
| "7e46448d720c7136": "Operation mode selection", | |
| "7e48f13161f2d8d8": "SDRAM mode definition", | |
| "7e59285d63cc8ba1": "Line 58 interrupt and event masking", | |
| "7e96a3972c51a5b2": "Break polarity", | |
| "7eb925c5dc1bd14f": "Debug clock and peripheral freeze", | |
| "7ec6e7a3bd82b490": "ADC3 security", | |
| "7ed3648d9084e6ed": "USART 3 and 4 support", | |
| "7ee500c5f2273e37": "Filter configuration and activation", | |
| "7ef7ebd84cfee24e": "Session request management", | |
| "7efe88f5a783899c": "PPS frequency control", | |
| "7f0b1d577feed853": "Symbol clock control", | |
| "7f4253c57f768124": "Gain compensation", | |
| "7f4c87664c027c2e": "Core power management features", | |
| "7f9cddaf34ac8141": "Line 21 interrupt and event masking", | |
| "7faf2f8686116915": "Capture/compare channels 3 and 4", | |
| "7fb84277da82a3ff": "Line 18 pending bit", | |
| "7fd8797dc6f17ce5": "LSI2 and watchdog support", | |
| "7fe8dc3f78db1fa0": "Alternative interrupt enable", | |
| "800bbfddc8f8716f": "Write protection 2 to 3", | |
| "801b7d851542d3a0": "OTFDEC2 support", | |
| "802626df6817292b": "SAI2, OCTOSPI1_MEM, DFSDM1 and DMA1 to 2", | |
| "8038b5bc8178dc0f": "OUT transaction status interrupts", | |
| "803cdee56f079db7": "Channel 6 configuration", | |
| "80779ec33fd285e0": "Monotonic counter", | |
| "80932faf36f60cda": "UCPD2 strobe signal", | |
| "80952fb7acf68234": "PLL division factor", | |
| "80a56542c1f2db11": "Host LPM L1 transaction request", | |
| "80c16ca647970618": "Timer 2 interrupt", | |
| "80d6b86497e9cc73": "Timer and ADC configuration", | |
| "80e769914b7a0a7f": "Event and interrupt masking", | |
| "80ee6e875b8107bf": "Port PA and PB pull-down/up", | |
| "80f1b92504187356": "Bank 2 control and CRC", | |
| "8116538bbc64fe95": "Prefetch and power management", | |
| "815c565207d614f0": "Voltage regulator mode selection", | |
| "815fb615355b0ac7": "GPDMA2 channels 8 to 11 stop", | |
| "816e63e422e0ec8c": "GPIO port E support", | |
| "817957abf4208c5f": "DSI SRAM power down", | |
| "81990062096a9fcd": "Dual bank mode enable", | |
| "81a394ac89750a74": "Line 37 pending status", | |
| "81a46d9a5453bfa4": "ID pin change detection", | |
| "81ad9be877220ba7": "Peripheral security protection", | |
| "81b60ebfadfade7a": "Access latency configuration", | |
| "81bbcb7ed6ac72e9": "Data hold phase duration", | |
| "81c0e2e54de99cf2": "Timer 14 debug stop", | |
| "81c2fc7fe2ffbfd3": "Data transaction reload count", | |
| "81da4ca7246d482c": "Internal bias control", | |
| "81e2a36c32d6eb38": "Channels 0 to 4 DMA requests", | |
| "81fa32e85c45c480": "Voltage scaling and blanking", | |
| "8208a737ec07e1de": "Clock and peripheral control", | |
| "820cdae5e261f583": "I2C4 peripheral", | |
| "8215e36d9a9d7307": "AXI interconnect 7 QoS", | |
| "821b3cb71a5e4cf4": "Time stamp and overflow flags", | |
| "8231418e93f57bf1": "Global power down control", | |
| "824e0fce115dd570": "Line 32 interrupt masking", | |
| "82958a40c001cd5f": "Memory protection settings", | |
| "82a45e91314b55be": "TIM15 clock freeze", | |
| "82b5cd2562802c27": "Memory and ADC configuration", | |
| "82fd3ea40046d81e": "Non-secure programming and protection", | |
| "8301c6d01e30d552": "I/O pin mode and value", | |
| "8343174922e08ed0": "HSI48, TIM2 and CEC peripherals", | |
| "83488f4828a52e99": "Tamper channel 5 and backup lock", | |
| "83493bcd06141fe8": "TIM1 clock freeze", | |
| "834db87572a0c3a5": "FDCAN block clock", | |
| "836e3ace5f02aa92": "Remote procedure call configuration 0", | |
| "83a8426bc2294d69": "RTC and LPTIM1 freeze", | |
| "84048fcbcc66eb68": "HSI48 and peripheral clock control", | |
| "840874a4e3798c68": "Memory and peripheral security", | |
| "840e30d0c4c6b6dd": "Secure masked interrupt status", | |
| "842da51d9cddd443": "Secure wakeup pin 5", | |
| "8464217b6a4b6766": "OUT status phase received interrupts", | |
| "8464b92c52cd7cc0": "Internal time stamp enable", | |
| "8466935d68119a54": "Tamper input 3, 5 and 6 disabling", | |
| "84812f847c45fbc2": "Tamper channel 2 control", | |
| "84a829be4396a02f": "USB flash abort interrupt", | |
| "84c32d4aff4919a7": "Low power peripheral clocking", | |
| "84c45404fb691fe7": "Cryptographic hardware acceleration", | |
| "84e23732fd2094f1": "Waveform shape", | |
| "84ef7bc6b86add1b": "AXI target 8 functionality", | |
| "84f12dba5318bd27": "SDIO, ADC3 and timer 8", | |
| "84f61da005b5b740": "Privilege configuration for line 22", | |
| "850dcf4dfa9df4aa": "Flash memory sleep control", | |
| "851ed3e38644f946": "Wakeup pins 4, 6 and 7 enable", | |
| "85267e7a66087b93": "Data input not empty flag", | |
| "8528ab38a89fd0eb": "Non-secure high density jump", | |
| "852d0ec59c79fe67": "Core and PVD lock", | |
| "85557e0280b9b395": "Differential mode and pre-channel selection", | |
| "856be7ce0fd21833": "GPIO pin remapping", | |
| "859fe8bab8d33741": "SPI2 and GPIOD support", | |
| "85a7bcdb650aaa18": "Low voltage detection", | |
| "85ae4ce45346d403": "System configuration and I2C mode", | |
| "85b90eaade8382ae": "Dual channel configuration", | |
| "85ccf3defb458e5c": "Pin PB5 to PB6 GPIO retention", | |
| "85daee132ed17b53": "Line 27 event masking", | |
| "8614a89ba08efd92": "Alarm B event flags", | |
| "86247122ab45430a": "SRAM parity check enable", | |
| "86477f7cbaed5e04": "Tamper detection interrupt and erase protection", | |
| "864d1ad29dc56b32": "I/O voltage booster and SRAM parity", | |
| "865f9a95a53a9605": "Privilege configuration for blocks 20 to 27", | |
| "86a0a3b1f908cf3c": "Brownout reset enable", | |
| "86ad87a21a9edb37": "Transmit FIFO empty clear", | |
| "86be286be8e84e24": "I2S configuration", | |
| "86c26f6a6d18dff6": "Channel 19 sampling time", | |
| "86d42e3354215ce0": "Tamper channel 8", | |
| "86e06aa2f3df29d9": "I2C fast mode plus support", | |
| "86e3ddd5aa783ce6": "Transmit FIFO threshold interrupt", | |
| "86eaeac7596e8b00": "Line 28 event masking", | |
| "872807d73a5986a3": "Advanced power management features", | |
| "8766497d52f4d611": "Lines 1 to 12 configuration", | |
| "877c85efaeaa648b": "Write protection and power-down key", | |
| "8783d9be16782e4d": "I2C3 SMBus timeout control", | |
| "878e11ce9d147495": "Line 22 trigger and interrupt control", | |
| "87e19a0867a74cde": "Active tamper generation and monitoring", | |
| "87ed5b2677ff402d": "ADC prescaler", | |
| "87f422af49e91c4c": "Boot and error handling", | |
| "87fba4e1f6072ecb": "Channel 2 enable", | |
| "8800522d41c03fea": "Error and tamper interrupt mapping", | |
| "881c17d4c8d5a742": "Ethernet PHY control", | |
| "883fcad032e4db11": "RNG and DFSDM support", | |
| "8844e9f2a7cbcde6": "Line 35 trigger and interrupt", | |
| "8848f8635180bbd9": "Timestamp data acquisition", | |
| "886a9ae2ffb4a721": "USB support", | |
| "8894f5475358573f": "Multimode operation and dual conversion", | |
| "88a8aad38e7ae08b": "Voltage monitoring and power management", | |
| "88cf7fc7b72a8dd2": "Regulator selection and status", | |
| "88e36c8fc9c6e185": "Tamper and timestamp detection", | |
| "88ed1bf954f974dd": "Security and GPIO retention features", | |
| "892149779b6ee211": "Endpoint transfer management", | |
| "893841d82e729848": "Master mode selection", | |
| "8963d9f3145f6bad": "Channel 2 trigger", | |
| "89e05165bc94165c": "HSI trim adjustment", | |
| "89e4a824243cd6a6": "Trigger and stall configuration", | |
| "89f87080b29a5d22": "I2C fast mode plus and VBAT monitoring", | |
| "8a0d915448ddb6c7": "Line 21 trigger and software interrupts", | |
| "8a2fc0452a17a00a": "Wake-up pin and flag management", | |
| "8a397d9031a067f2": "Line 22 configuration", | |
| "8a56e6aed9876432": "USART 7 and 8 support", | |
| "8a85c736859134d9": "Output compare clear selection", | |
| "8a88d2c7b3c260e0": "OCTOSPI1 security settings", | |
| "8a90bbce632b400b": "Chip select high time", | |
| "8a9207ed510f4a13": "Transmit data flush request", | |
| "8a9ca842ece66617": "Driver enable timing", | |
| "8aa1c0e713deda0c": "SPI5 support", | |
| "8aa974e7a233f6e8": "LPTIM4 and LPTIM5 debug stop", | |
| "8ab4f45f8b245077": "Lines 52 to 56 interrupt and event masking", | |
| "8abb7d3e319d6b85": "Trigger event selection", | |
| "8ac00981fe485cbe": "Write protection and secure areas", | |
| "8ac3409320018c4f": "Sample rate and offset settings", | |
| "8ac7e96bb646e3af": "Voltage scaling management", | |
| "8aeec5b45a88749e": "PVD connection signal", | |
| "8b30cf299d2e48a9": "I2C fast-mode plus driving capability", | |
| "8b3fd0eab19e547b": "Write protection pages 17 to 31", | |
| "8b5442a4cb5f4ab0": "Analog watchdog and calibration", | |
| "8b6235e02b5787e5": "PVD lock feature", | |
| "8b66a5aed116d59c": "Lines 39 to 51 event masking", | |
| "8b719aa34640d5f6": "Write protection pages", | |
| "8b767b05a48c0184": "PLAY1 interface", | |
| "8b804a5e03518865": "Hardware crypto and hash engines", | |
| "8b80a75932cda4ca": "DFSDM and clock delay control", | |
| "8ba539e2fc24c02a": "Line 33 trigger and interrupt", | |
| "8bac2c45bb094161": "Internal voltage reference path", | |
| "8bb7bf025141cd1b": "Channel sampling time selection", | |
| "8bd24a8461ab32a2": "Line 28 interrupt and event masking", | |
| "8c23bb66f53a2eb1": "RTC and EXTI support", | |
| "8c26c1b9aee2d770": "Interrupt and error handling", | |
| "8c609db650c9dd99": "Additional ECC support", | |
| "8c7d1dd5e1f1b3a0": "Channel configuration and control", | |
| "8c931ee3c0bc54e5": "DMA underrun interrupt", | |
| "8cc64a8c2fff24f6": "Debug trace IO connection", | |
| "8cc73dfa1e77106f": "Slave voltage regulator status", | |
| "8cfca7c8094b6aa7": "SRAM power down management", | |
| "8d055755464a5416": "Peripheral clock freezing", | |
| "8d0950481844a301": "Full tamper detection and configuration", | |
| "8d259ba5b1c6c735": "ADC synchronization", | |
| "8d27438614a6f68c": "PVDOUT interrupt", | |
| "8d2abdf98da00eae": "Battery charging detector", | |
| "8d2c96f63c43348b": "Clock calibration", | |
| "8d34311b455d2768": "Bit error interrupt lines", | |
| "8d60867a4c3a4d40": "Context swap storage", | |
| "8d948b6b20fcc835": "Security configuration for blocks 3 to 7", | |
| "8db61b3fce4d1fc4": "Error correction code result", | |
| "8dc1fdec6cb4eb9a": "Clock and smartcard settings", | |
| "8de627c1f1ff6656": "Alternate function and pin configuration", | |
| "8deabf1fd437e47e": "Chip select counter", | |
| "8e12beba1541abce": "MCO1 prescaler", | |
| "8e15304427022c99": "Trace IO and clock enable", | |
| "8e1b7d2e4de1f653": "Line 31 interrupt management", | |
| "8e425e8687ebd45d": "USART4 and RNG interrupts", | |
| "8e83c3de238dd4b2": "SWPMI1 peripheral", | |
| "8e861f89ef21d5b9": "Extended input minus selection", | |
| "8e9562a0ec272fd1": "SRAM2A write protection pages 16 to 19", | |
| "8e9c6a74ca929127": "Dual bank support", | |
| "8ea5056a21f0f6fc": "Secondary tamper configuration", | |
| "8eee90da7d58a503": "I2C fast mode plus enable", | |
| "8f1c1af9361a859a": "Voltage regulator and bias control", | |
| "8f343ac104ef2edb": "Differential mode selection", | |
| "8f40c81995bf4907": "USB and power domain control", | |
| "8f518fc42e98831f": "DSI security configuration", | |
| "8f540c4ea6452eb8": "Tamper channels 12 to 13 status", | |
| "8f740dc2a398298b": "Timers 12 to 14 debug stop", | |
| "8f7d103d474a422f": "Secure mode control", | |
| "8f944552f4cad152": "Channels 12 to 13 DMA requests", | |
| "8fb84abd7d396410": "Event masking for line 19", | |
| "8fbc19ff0cbf827b": "Security and privilege configuration lock", | |
| "8fc39f31ca26e8fc": "External interrupt and SRAM2B protection", | |
| "8fe85a1afcf63044": "Low speed oscillator support", | |
| "90016372097c73bb": "Input minus selection", | |
| "9014e21b23faa15c": "Tamper input 8 disabling", | |
| "9016484c29770335": "NPU RAM and QoS control", | |
| "901814d2bb0a181a": "Event masking on line 25", | |
| "90209d052a69ce83": "Memory remap configuration", | |
| "905037f4d29b4d41": "Single wire master transceiver", | |
| "905390010eb1e99a": "Wake-up pin and pull-up/down configuration", | |
| "905861e5600fd6ff": "Connection and pull-up detection", | |
| "908a2ceefd959a95": "I3C2 security", | |
| "9090ac164857156a": "DMA request identification for channels 8 to 11", | |
| "909fe58535101cdc": "Synchronization for channels 14 to 15", | |
| "90b4dd40eacde776": "ADP module support", | |
| "90b5fa9ef891f17b": "Input selection", | |
| "90c10d9ff3f95967": "Lines 44 to 84 interrupt and event control", | |
| "90d682f1e8b0da1d": "Device security and configuration", | |
| "90dea8542821d59b": "LTDC USB security", | |
| "90e0a1cccd7f4964": "Digital loop delay control", | |
| "90e54e8308167341": "Alarm B wakeup flag", | |
| "90fcbc37f7c5bc58": "Timer and I2C DMA remapping", | |
| "9130b362cdcc1a08": "Timer 6 stop in debug", | |
| "913399cecc5470b7": "APB3 peripheral clock freeze", | |
| "913fd8e769fe843d": "Peripheral interrupt mapping", | |
| "914f1261ed32ba3e": "CPU2 power management", | |
| "9167a696cc67303f": "User data bytes", | |
| "919fbe2f9af088bc": "Channel 1 trigger selection", | |
| "91a2f63f5491bc17": "Comprehensive power management", | |
| "91df7be7bdc2163c": "Low power regulator mode", | |
| "92152b87068fde4b": "Complementary output for channels 3 and 4", | |
| "921d2812c7f29973": "Lines 24 to 25 trigger and pending configuration", | |
| "922d128856dcdb2b": "Lines 10 to 11 trigger flags", | |
| "926fd14eec99c285": "Extended memory support", | |
| "927e9c291cdbfa5e": "SRAM2 parity lock", | |
| "9281a62c7df4dbeb": "SRAM ECC and write protection", | |
| "92a00826eac23446": "I2C and analog switch control", | |
| "93156f9a00d68441": "HSI48 and LSE configuration", | |
| "931b84d4c89c2851": "Error correction address tracking", | |
| "9345e48e75bce538": "Debug authentication and sleep access", | |
| "9369b3c117369ae8": "Transceiver delay configuration", | |
| "936ca3c7931b0eb8": "DAC peripheral", | |
| "93760fc558a14a54": "SDMMC2 and RTC support", | |
| "93a20d2e57a91b11": "DMA linked list and data management", | |
| "93be6b5301f98c76": "HRTIM1 support", | |
| "93c0940afe488978": "Peripheral voltage monitoring output 1", | |
| "93c9918b0663ca71": "GPIO, SPI3, UART5, PKA and VREFBUF support", | |
| "93cc198b4b4585bb": "LPTIM1 debug stop", | |
| "93d61e9e3f4b31e7": "Read protection levels", | |
| "93d84ae318861790": "Multiple ECC error channels", | |
| "93dbc3310ae8582c": "NBOOT0 pin control", | |
| "93f7d6bebf40ffa3": "Line 23 interrupt masking", | |
| "93fea1e02d8e396f": "Line 31 event masking", | |
| "94008a20cd0f005d": "Regular sequencer channel selection", | |
| "9408d72a6a981a24": "Channels 14 to 15 DMA requests", | |
| "9419c62aa3fb3fec": "Chip select selection", | |
| "941c6806ad20d085": "ADC support", | |
| "94310e0fb5b97553": "Prefetch buffer and latency control", | |
| "944730d72f6aefe0": "CEC interface support", | |
| "9447f6e8500c98c7": "Blanking and scaling control", | |
| "94a9f0d3eb959203": "Secure and non-secure memory partitioning", | |
| "94aac01b0a48110a": "Boot mode and write protection", | |
| "94c6fdb279d30d50": "Endpoint address and error configuration", | |
| "94da21c730d87741": "Bank-specific area management", | |
| "94eac40d387cf655": "Dual core power management", | |
| "95692a2108fe19f3": "DMA and MAC configuration", | |
| "957131ea49ebd10e": "System clock and peripheral management", | |
| "9575ed4b76d0520f": "Memory sub-region watermark configuration", | |
| "958d2f3b1a4cc90b": "Line 20 trigger configuration", | |
| "95aad4695e973b9d": "Break management and trigger selection", | |
| "95ac390962fc4c79": "Security attribute configuration", | |
| "95ae59d46d3d6376": "I2C4 fast mode plus support", | |
| "95ca68019f1fd7bd": "Break disarming/re-arming 2", | |
| "95d00d384f0443ca": "Configuration settings", | |
| "95d2d726c58cb66e": "Debug status", | |
| "95de62209db784fc": "Endpoint error and status interrupts", | |
| "95ebe5d182eecac7": "Interrupt masking on line 31", | |
| "95ff59cd41bea4cc": "Flash data options", | |
| "96259e13bb21bc7a": "Memory remap and I2C configuration", | |
| "96424dc13c2b495e": "Bank 1 write protection", | |
| "964285c3467b578c": "Secure masked interrupt status", | |
| "9654467d6e206f2e": "SRAM power-down and pull control", | |
| "9663abdbd53279d0": "Line 33 event masking", | |
| "9676676daf494783": "SRAM control and error handling", | |
| "96883bdb9770ade3": "Capture/compare channels 3 and 4", | |
| "968f8f91cd2eacd4": "System supply and wakeup management", | |
| "96a144871e69a9c4": "Event masking on line 22", | |
| "96bb0b1dbeb7da7b": "Bank 2 security and PCROP", | |
| "96d6c37fe14f594e": "Privilege and security control", | |
| "96da5079d209a2bd": "Ethernet MAC support", | |
| "96e6ddaa2bfd7db8": "Semaphore interrupt status", | |
| "96fdb635158d5570": "Erase and HDP configuration", | |
| "970ac86e03cce023": "Data output buffer", | |
| "970bedf2c559db19": "Channel 7 control", | |
| "97490f426097123c": "I2C fast mode plus support", | |
| "976f1cae98fc1bb1": "Resistor trim values", | |
| "978aeaf97b850f0f": "DAC 1 and TIM15 support", | |
| "97e2a1d193791cb2": "Dual bank configuration", | |
| "980756c54790f849": "ADC, CCB and playback support", | |
| "98342a18ca939f05": "Super block and security configuration", | |
| "9869c139b94d8f03": "Lines 66 trigger configuration and flags", | |
| "98ce9739c86a8e3c": "I3C1 debug stop", | |
| "9903c454d71c4207": "Alarm A and B masking", | |
| "990cb34ae39a99c0": "Interrupt line routing", | |
| "991587655aa7c5f5": "Peripheral interrupt lines", | |
| "99181ce204fbd762": "Voltage output buffer", | |
| "991c7bd5c6ea04a2": "SRAM power-down and pull control", | |
| "993b6855729e37f7": "End of block and guard time", | |
| "9946cd87afcc4b82": "Master mode selection", | |
| "9960547ce061610d": "GPIOE peripheral", | |
| "99686b571f60b7bb": "Resource protection configuration", | |
| "9993ba42fd9c882b": "Line 29 interrupt masking", | |
| "9996ab3be1e10bbb": "Internal wake-up line enable", | |
| "99cb1cffaf5f4c0f": "Flash bank mode selection", | |
| "99d85ff791cdfdff": "Interrupt line configuration", | |
| "99dba9b97bd75cc7": "Link power management support", | |
| "9a00aec78f929c16": "Parity protection and error address", | |
| "9a18f49970483ef1": "Event masking for line 16", | |
| "9a2fe71db161efa3": "Write protection pages 32 to 59", | |
| "9a64452672b22d4d": "CAN, DFSDM and MDIO support", | |
| "9a65e084a0e80c6d": "Hardware flow control", | |
| "9a6975b02f322f00": "Line 37 interrupt masking", | |
| "9a72b3e60e6b56dc": "CPU2 event and interrupt masking", | |
| "9a9b0474a66c5960": "Dual ADC operation", | |
| "9aa7d272d6df4c66": "SRAM2 write protection pages 0 to 9", | |
| "9ab17ee17c1a2f17": "I2C2 clock freezing", | |
| "9ac1b9b7ff551ee5": "Security and privilege control", | |
| "9acbbd7e721c7e75": "Temperature sensor support", | |
| "9af76e3bae72e0b0": "Watchdog thresholds and offset settings", | |
| "9b334a9c8dea378c": "Non-secure control and programming", | |
| "9b3da3c928706235": "OTFDEC1 and OTFDEC2 support", | |
| "9b50e09b9e24fce8": "Sequencer and sampling configuration", | |
| "9baf89b57fc24bda": "Privilege configuration for blocks 12 to 19", | |
| "9bdad74d4f47cc99": "Lines 28 to 31 configuration", | |
| "9c37843001e0af66": "WWDG and TIM1 support", | |
| "9c51a827c8107b65": "Secure masked interrupt status", | |
| "9c5daca7e0111555": "Capture/compare channel 6", | |
| "9c724790bd86ed8d": "Single mode timer start", | |
| "9c9ead25f91f0102": "Timers 9 to 11", | |
| "9cd86180f55c01fc": "Channel 18 selection", | |
| "9cebb176bcf260a9": "Line 19 configuration", | |
| "9d0c4188a6e6bfab": "DMA and digest HR5 to HR7", | |
| "9d3c4bf7207755b1": "Low frequency and VDD core mode", | |
| "9d48d37e5b763c82": "Wakeup line 6 configuration", | |
| "9d4d43d30a3b903c": "LSI2 clock support", | |
| "9d503b8350524fa6": "Mode and configuration settings", | |
| "9d5ef7d385e09578": "Word length bit 1", | |
| "9d6d98180ef4b3f9": "Port H and I pull-up/pull-down control", | |
| "9d7678fde28a66de": "Line 22 trigger, software, and status", | |
| "9d900595aa9428b7": "Frame format enable", | |
| "9da83b7aa4f0c076": "Input plus selection", | |
| "9dcdc841e66f6c1e": "Additional key storage", | |
| "9e136dd6e4444375": "GPIO and communication peripheral clocking", | |
| "9e3b5638e5a87688": "Interrupt line 8", | |
| "9e497d5fbec19c9a": "Product state and RSS management", | |
| "9e5b8867f90ceb12": "SRAM3 retention in stop 2 mode", | |
| "9e6a910d535371af": "Gain compensation mode", | |
| "9e6fe47f33d9a5fa": "Temperature sensor support", | |
| "9e8fe541ddff9fde": "Secondary peripheral freeze control", | |
| "9e8fe5f21c5cadd1": "I2S mode selection", | |
| "9e992c616488b58c": "Fault error code management", | |
| "9eb07f6c59f6b3e7": "SMPS and BOR control", | |
| "9eb4bae45333c783": "Parallel bank mode", | |
| "9ecf26253c51142a": "GPIOD peripheral", | |
| "9ee0ffb846b149ba": "Input plus selection", | |
| "9ef9fa34838a6ae0": "Data management and trigger configuration", | |
| "9f311287aead30c2": "Trigger signal selection", | |
| "9f60e6c68e16f81b": "NAK interrupt masking", | |
| "9f7743e00a75dc15": "SRAM2 write protection pages 20 to 31", | |
| "9f93bd0668db5eb1": "MAC and PTP management", | |
| "9fc30ce3b499c772": "SPI4 and dedicated clock configuration", | |
| "9fc4d66035f28db9": "Data FIFO", | |
| "9fd05f200e485946": "Autonomous mode control", | |
| "9fe0bf00e421328e": "Debug credentials reset type", | |
| "9febae11e1d586da": "TIM19 debug stop", | |
| "a00edd3a38c3685a": "Compensation cell management", | |
| "a00efab96b526e64": "Write protection and power-down", | |
| "a01f6afa678f0cb2": "Chroma sub-sampling selection", | |
| "a08ade40a37534f2": "Endpoint transmission and error management", | |
| "a08f9eaaa90dffe9": "Synchronization overrun flags for channels 7 to 11", | |
| "a096378de0a3bc0a": "USB supply voltage monitoring", | |
| "a0bb27215f6b43e1": "Digital audio and CEC support", | |
| "a0cd0aabf68e61dd": "ECC lock", | |
| "a0d502a22690802c": "Digital filter and detector features", | |
| "a0fa2318d6b02c65": "Advanced control and dead-time generation", | |
| "a107ec045be2f7e9": "HDP area extension", | |
| "a114173beea02fb9": "ECC error monitoring", | |
| "a11a1400e410f6a6": "Page access and security watermarks", | |
| "a11ef36020b9cb24": "I2C2 SMBus timeout debugging", | |
| "a1426d0d4a455272": "Line 17 pending bit", | |
| "a1456862c1570534": "Data input and output", | |
| "a14df7d8ad96635a": "Line offset and mode settings", | |
| "a17becbfee05b787": "VDDIO2 voltage monitoring", | |
| "a1a09540e551aaff": "Capture/compare channels 1 to 4", | |
| "a1add21de5dfca18": "Privilege configuration for blocks 28 to 31", | |
| "a1e9b6544b4f3622": "Line 31 trigger and interrupt", | |
| "a1f3e672001d0bd0": "Peripheral interrupt line management", | |
| "a2008cab82198153": "Common control and VrefInt", | |
| "a20d43666bcac590": "Timer 3 stop in debug", | |
| "a238f3423a86fabd": "Remappable memory regions", | |
| "a27e2137bc9ff3df": "OTG version identification", | |
| "a2a35b891ab0110b": "Sample and hold control", | |
| "a2b7b40ee11aad09": "Over and under drive support", | |
| "a2cf57ed37639655": "Ultra-low power BOR and PVD enable", | |
| "a2d823508d4a557a": "Channel 1 calibration", | |
| "a2f192d896ec2a2a": "LPTIM3 and LPTIM4 stop", | |
| "a3172ceec66a3b9a": "Memory protection area boundaries", | |
| "a3289caa6b621547": "USART2 security settings", | |
| "a33247388ff6f9f3": "Secure memory protection and access control", | |
| "a33ad1a1098b2a18": "Group channel selection", | |
| "a34051d5910f91d7": "Layer 2 vertical window stop position", | |
| "a34127036451cba1": "SRAM2 and I2S23 support", | |
| "a35ead7ce3506332": "SRAM2 erase and parity control", | |
| "a38ae595cd094368": "Boot mode configuration", | |
| "a38d8fc21638ccad": "USB OTG FS prescaler", | |
| "a3934b057d2145a3": "TIM13 and TIM14 security", | |
| "a3dbef4284e60175": "Port PF3 and PF4 pull-up", | |
| "a3ea4aa909747aa1": "Interrupt management", | |
| "a3fa2ba955cc2129": "DMA and USART remapping", | |
| "a407e691293e5604": "Timer 1 debug stop", | |
| "a425bb633b9bc353": "Line 34 event masking", | |
| "a43453994c6c707d": "DMA, offset, and alignment configuration", | |
| "a43dcb5a420d6aa1": "Line 38 pending flag", | |
| "a458e2cbf5ccdd5a": "Color look up table", | |
| "a46fd0226b46454b": "Oscillator frequency trimming", | |
| "a494f42ea58bc73e": "Debug authentication and access control", | |
| "a4baa5e88cc3f204": "Peripheral clock freeze in debug", | |
| "a4c3db2029e17f37": "Peripheral freeze control", | |
| "a4dd31da44e2e3b0": "Security configuration for peripherals 4 to 6", | |
| "a4e20195b5840764": "Line 41 interrupt masking", | |
| "a4ed602dc9fdf3b7": "Pin bit manipulation", | |
| "a4ee8c97dd0a8bd8": "PCROP and erase control", | |
| "a4f47b3c85ffb3eb": "System error correction code", | |
| "a501b6b78b9eb0fb": "Additional active tamper outputs", | |
| "a515107449c8f05a": "Parity error detection", | |
| "a519f9e504b1143b": "Capture/compare channels 1 to 4", | |
| "a533038204d0eba5": "Complementary output idle state 2", | |
| "a544c864bffedac2": "LPTIM and core debug control", | |
| "a549446019adf401": "Low frequency mode", | |
| "a58258c3bcb76fcb": "Noise filtering", | |
| "a5c409e50aaf2ba7": "Channel configuration and status", | |
| "a5c9dd1002748812": "Privilege configuration", | |
| "a5e6c92a3ca76281": "V1.8 power domain reset flag", | |
| "a5ef75f50f01adce": "Lines 48 and 51 interrupt masking", | |
| "a5fec00ea22dc1ad": "Device authentication and clock control", | |
| "a634e23762fcad2d": "Line 35 event masking", | |
| "a651e329113423a5": "Tamper pins 7 to 8", | |
| "a65e79a0300e382c": "FDCAN and LPUART2 support", | |
| "a66a4758c6e72b97": "Option configuration", | |
| "a68e65c4a570c6d3": "Memory and voltage scaling control", | |
| "a69b234ab3fe5d0d": "Line 36 event masking", | |
| "a69bc1f7799c6d5b": "Page-based memory protection", | |
| "a6a504552899b0fd": "Peripheral clock and prescaler control", | |
| "a6ae290af296b4fb": "TIM5 and TIM6 debug stop", | |
| "a6d4cc4619987943": "Line 39 event masking", | |
| "a6ef7656bc5be612": "Low threshold configuration", | |
| "a72954372c893981": "Lines 28 to 69 trigger configuration", | |
| "a72d0ab7dfc44232": "Peripheral clock and reset control", | |
| "a737363dfed6ea75": "External clock source", | |
| "a7582f7b7f59e573": "High-speed low voltage control", | |
| "a7847e7da8066a71": "Capture/compare channels 3 and 4", | |
| "a7882d8c2750240d": "Port PF3 and PF4 pull-down", | |
| "a7a6d8581ec5d70e": "Write protection bits", | |
| "a7ad6980f45ce303": "UART5 clock selection", | |
| "a7f2af0979a66cf7": "LPDMA and GPDMA stop", | |
| "a80a5f8388efbe14": "Line 44 interrupt masking", | |
| "a83a64ca51b4e610": "LCD interrupt line", | |
| "a83e7c2458951ce2": "SPI1 support", | |
| "a843ca47d91536cd": "DMA and MTLQ configuration", | |
| "a85158eb0bef3273": "I/O port pull-up/down control", | |
| "a85a3ec12139dfa1": "Capture/compare channels 5 and 6", | |
| "a8606a2719fb565d": "Channel and sequencer configuration", | |
| "a87ff9d991a9d650": "Secure and privilege blocks", | |
| "a889309b725cdbd2": "SRAM power-down and I/O configuration", | |
| "a898d4f5896d3dab": "RAM size information", | |
| "a8a388f932036c5e": "APB2 clock freeze in debug", | |
| "a8b8161e836e8334": "Wakeup timer and alarm events", | |
| "a8efea76ac19d998": "Configuration settings", | |
| "a8f67f549d809daa": "GPIO pin multiplexing", | |
| "a91f99965c4ccdc1": "Secure memory protection", | |
| "a9378c5747a319f5": "Filter initialization mode", | |
| "a942f0ef16628cbe": "Peripheral and interface remapping", | |
| "a9517500b04be3b9": "TIM6 to TIM15 and I2C2/USART3/4", | |
| "a96af57b543a1fdf": "TIM15 to TIM17 debug stop", | |
| "a97ff20fe34ebd42": "Hide protection area extension", | |
| "a99e524707ea0f79": "Security level configuration", | |
| "a9b0b73fe88656df": "Programmable gain and calibration", | |
| "a9eb22cbd30335c2": "Low power mode configuration", | |
| "a9edeba51f66e6d9": "Low power mode debug", | |
| "a9f2245d147ba935": "Period length constraints", | |
| "aa3cf43c2a1287f3": "Output color values", | |
| "aa4d0174daa56dac": "8-bit data input", | |
| "aa531f5eb87162f9": "Device identification and standby debug", | |
| "aa567fa25f1cc5aa": "Cortex-M4/M7 boot settings", | |
| "aa5cd13d8a2a9c1a": "Port H pin 3 pull-up/pull-down control", | |
| "aa6654db10bf2045": "Wakeup pin configuration", | |
| "aa8c039f397b86bc": "Lines 47 to 53 interrupt and event masking", | |
| "aad5573aa39d1fe5": "Tamper channel 6", | |
| "aae06326b0c84a53": "I2S audio configuration", | |
| "aae1d899636dd972": "SRAM2A write protection pages 10 to 15", | |
| "aaf9644c166467e2": "Digest HR8 to HR15", | |
| "aafeed2d563c6a90": "Peripheral clock and reset management", | |
| "ab072a4629479f31": "SAI1 and SPI3 peripherals", | |
| "ab61684e5ea54160": "Line 40 interrupt masking", | |
| "ab72ba082d94da18": "ECC error detection and correction", | |
| "ab7c0c86e48e2b77": "Double-buffer mode", | |
| "ab7dffea85870070": "Line 59 event and interrupt masking", | |
| "aba2da36de2f94ef": "SRAM2 write protection pages", | |
| "abbb4ec785ceaf3c": "SRAM2 write protection pages 16 to 19", | |
| "abc5a8a87519713f": "Line 42 interrupt masking", | |
| "abd2501eb1d4013a": "Memory remap and I2C3 fast mode plus", | |
| "abe26bf7bde2dc19": "Sub second and calibration support", | |
| "abe9a6b8d25d8cde": "Unprivileged watermark configuration", | |
| "abf3674a185af2a8": "Low power timers debug stop", | |
| "ac0c6434023a3fee": "User flash bank swap", | |
| "ac17e95dd30e5bb8": "Analog watchdog thresholds", | |
| "ac20f3e967edd3d0": "DMA buffer addresses", | |
| "ac2c523236be241d": "Wrapped burst mode support", | |
| "ac31e1f72491bd6e": "Component and peripheral identification", | |
| "ac3cc60743de5819": "I2C4 security settings", | |
| "ac3d116de1119281": "Lines 21 to 22 configuration", | |
| "ac3fb0461d6d5728": "Lines 29 to 30 pending interrupts", | |
| "ac4b4c83d5ae12be": "Synchronous slave mode", | |
| "ac62952e3f1b649f": "SDADC analog part enable", | |
| "ac8585b3bb7e33df": "Auto baud-rate request", | |
| "ac8ad846fff024f9": "Line 23 event masking", | |
| "acabaacd79643f3c": "Multimode DMA and delay", | |
| "acb4dfe897cc77e5": "Device identification and authentication", | |
| "acb5164d269a5090": "GPIO analog switch control voltage selection", | |
| "acb6b59edd4b785e": "USB power voltage monitor", | |
| "acc3f7a2a94960e6": "Line offset configuration", | |
| "acddadb3ecfa0133": "Flash bank mode selection", | |
| "ad24075431f565b5": "Calibration and differential mode", | |
| "ad43a39da32a04cd": "Interrupt masking for line 21", | |
| "ad44924f13b0f5b7": "Lines 37 to 38 event masking", | |
| "ad63305c4201d3d4": "Security and write protection settings", | |
| "ad761e657ec66516": "Interrupt line 14 configuration", | |
| "ad79f8e984a9e156": "FIFO DMA support", | |
| "ad7a9d58b76610d0": "Wakeup pin 8 enable", | |
| "ad877c2265949b66": "Line 34 pending interrupts", | |
| "ad921dbcd45d2c54": "Capture/compare channel 1", | |
| "adab42023d81731c": "USB security", | |
| "adccf627c3392265": "PLL and peripheral clock control", | |
| "ade5d9c430f4865f": "Segment data memory", | |
| "ade8d5dbe7e3e42c": "I2C fast mode plus", | |
| "adf0498c5d374861": "Trace mode configuration", | |
| "adfe7ad208172958": "Low frequency trigger", | |
| "ae015326a217fe2a": "Non-secure wait data write", | |
| "ae07b719d568f186": "ECC error handling", | |
| "ae18dafd28b31aaa": "Memory address channels 4 and 5", | |
| "ae27502064622be9": "I/O compensation cell settings", | |
| "ae2f0c769ab3a36b": "Tamper mask flag", | |
| "ae392eb6b7883a9b": "SMPS and BOR configuration", | |
| "ae60a77234c8c4c9": "Lines 44 to 46 mask settings", | |
| "ae9aad175dc6379b": "TIM2 debug stop", | |
| "aea779dd9f567104": "Write protection pages 80 to 107", | |
| "aefb30e70708b78a": "ADC options", | |
| "af2193780ec181bb": "Line 30 interrupt management", | |
| "af28c2b1d29a7854": "CCB interrupt masking", | |
| "af2a23f5968a5acb": "Key access for security features", | |
| "af4e3aec294308ff": "IrDA low-power mode", | |
| "af6e998f0ca06890": "Secure operation monitoring", | |
| "afc44a7fbbe9e6f8": "Dual comparator mode", | |
| "afdba057d6df69cf": "TIM9 timer support", | |
| "afef875933b93f94": "Tamper detection flag", | |
| "aff888a379ff8256": "TrustZone security configuration", | |
| "b0080c0de59b86ea": "PCROP area configuration", | |
| "b0098cf4a6554501": "Proprietary code readout protection", | |
| "b02fed1c28d201fe": "Double buffer mode", | |
| "b032e58fd0bd4311": "Security configuration", | |
| "b03ae438d58ca09c": "Master injected queue overflow", | |
| "b0893deae611ba78": "Request generator functionality", | |
| "b094c85fe30ccc7b": "FIFO threshold configuration", | |
| "b09dc3fe2a9a9ade": "Color channel inversion and swapping", | |
| "b0b20e179d962995": "Line 40 interrupt and event masking", | |
| "b0b328457a66cf58": "Host authentication", | |
| "b0d24ad38aecf3b1": "External interrupt and memory remapping", | |
| "b0e31372c7620f25": "Word count status", | |
| "b0f2af9869ee1712": "Secure programming and option bytes", | |
| "b11124bd5bd9c7f6": "Trigger event selection", | |
| "b11490f5a963c68a": "Multimode master control", | |
| "b12a88c00a8c6c5c": "PLL dividers", | |
| "b12ea0673cced58f": "TIM7 peripheral", | |
| "b13fc79feceb86fd": "Error configuration", | |
| "b14dad1fff7869b9": "Power management unit configuration", | |
| "b17c7c322ee7b260": "Injected conversion and offset", | |
| "b19054d405852246": "ECC and erase control", | |
| "b1a037b2475678f9": "Digest HR8 to HR15", | |
| "b1b0c64ee18c0023": "Voltage monitoring and port control", | |
| "b2069ba83355c680": "Touch sensor controller support", | |
| "b21d3cdb0ba30add": "I2C1 and LPTIM2 support", | |
| "b23bd86cf6bd373b": "Layer 2 vertical window start position", | |
| "b23fba312f39fd6d": "Lines 1 to 3 pending interrupts", | |
| "b242f563c1ed37fe": "Secure memory size configuration", | |
| "b25372aa95df7af6": "Digital filter and analog watchdog", | |
| "b2563e0463038f83": "Line 24 trigger and interrupt", | |
| "b25ab5fc4c1a313e": "Sample hold for channel 2", | |
| "b25f29defb131831": "Health test settings", | |
| "b26a924553dd78a8": "Peripheral clock freeze in debug", | |
| "b27fd4e04ffb8591": "Timer 22", | |
| "b2a11ec2412f140f": "Non-secure programming and erase control", | |
| "b2a5b61dbf153034": "Low power mode selection", | |
| "b2e8b91d9a6f9730": "PLL clock source", | |
| "b312ca123eaa3a0e": "Linked list address offset", | |
| "b3213a47d5fb1cac": "Line 36 interrupt masking", | |
| "b3467913e1eecb10": "Capture/compare channel 6", | |
| "b34d68dc832d3696": "Backup block protection", | |
| "b35003bbca7bbf4a": "LPTIM4, LPTIM5 and FMAC support", | |
| "b352fcc4d217adde": "User option bytes", | |
| "b3a2ac5d537a8ad5": "LPTIM and PVDOUT interrupts", | |
| "b3a62d1902125e64": "Backup registers 16 to 19", | |
| "b3f4a5cf3832f14f": "Sub-second synchronization", | |
| "b43994f9b532f6b7": "Injected sequencer data", | |
| "b440c9face1b8c40": "Lines 1 to 18 security and privilege", | |
| "b473d27114a31c3c": "UART4 and UART5 support", | |
| "b48d76dced3a7ff3": "GPU2 and LTDC support", | |
| "b4a1dd5766bdd54b": "Voltage scaling and SRAM retention", | |
| "b4ae855075cf41c7": "Channel 2 trigger and selection", | |
| "b4e06987f2ec359f": "I2C PB8 and PB9 fast-mode plus", | |
| "b51f803b57749573": "Line 42 mask configuration", | |
| "b52d13739e472f44": "Update interrupt flag remap", | |
| "b543b1b7b560b13f": "Output compare and input capture filtering", | |
| "b559274fc5e3e840": "Read and user options", | |
| "b56417db08251903": "Additional flash abort interrupts", | |
| "b56bad691a48b55b": "Capture/compare 2 DMA request", | |
| "b5933124f0f60cfb": "VREFBUF secure access", | |
| "b5a00d6ed6baaa85": "Oscillator masking", | |
| "b5b1c140810fbe29": "Memory and calibration settings", | |
| "b5bef6b9f42b0b8f": "Padding length configuration", | |
| "b5c8ee41f4655daf": "WWDG1 debug stop", | |
| "b5cac5c44bed5f80": "Line 39 interrupt masking", | |
| "b5ceffbb55b48fde": "Bank 1 security and PCROP", | |
| "b5e2a08ae9d1d148": "External interrupt line configuration", | |
| "b60dff2cd093da25": "External interrupt line configuration", | |
| "b63010971d763ff7": "Pin speed and pull configuration", | |
| "b6336aa4c3d485ad": "Synchronization and event generation", | |
| "b64368faf63eb7e9": "GPIO retention control and status", | |
| "b643b1c79160c09b": "GFXMMU peripheral support", | |
| "b69aa97a3b76ec9f": "Peripheral clock and reset control", | |
| "b6c9ce95fbda1a31": "Page-based security and ECC configuration", | |
| "b6cacc67579b1eae": "USART3 and LPUART1 interrupts", | |
| "b6cec5a89764b1a8": "Communication DMA request", | |
| "b6f645fa38d70539": "Power voltage detection interrupt", | |
| "b6fbfcb20711aeb7": "USB peripheral management", | |
| "b723023b956a2bef": "Multiple peripheral debug stops", | |
| "b724fe0891ee2141": "Data holding and output", | |
| "b7b4fb5fab5fe490": "Communication and break control", | |
| "b7c1a60b0d0225fd": "Address translation and offsets", | |
| "b7d12f6a98bd9f50": "Dead-time and output control", | |
| "b7d97d287670fb45": "DCMI PSSI interface", | |
| "b80e157ecce8dcf1": "Dual core support", | |
| "b8231a9f83763f93": "Line 30 event masking", | |
| "b84cb8c48edf32f6": "Comprehensive security management", | |
| "b866fa68398c5ce4": "Lines 21 to 22 security and privilege control", | |
| "b88251767a70e061": "Health test configuration", | |
| "b8af8c78b9daf763": "External interrupt line configuration", | |
| "b8b3540627a165b8": "SRAM erase and protection", | |
| "b8d4084c558290c0": "Channel sequencing and sampling time", | |
| "b8ee68529628dd21": "System and memory protection", | |
| "b908afa3780956d1": "USB peripheral", | |
| "b91949e1434b4f4b": "Stop mode enablement", | |
| "b922bbbcd510580e": "Backup registers 0 to 1", | |
| "b93884d6173dba49": "Capture/compare control and break", | |
| "b959cc320990c002": "CAN peripheral", | |
| "b9603aa69ebf8389": "Shift and recalibration flags", | |
| "b965712550b56132": "GPIO port D", | |
| "b97a5357f98b29ce": "Output idle state for channel 4", | |
| "b98cc1041a57cf00": "Lines 37 to 42 event masking", | |
| "b99f7d9d9e5b2da8": "Input and output remapping", | |
| "b9bce2341a29f1d4": "Clock mode selection", | |
| "b9c2f527dff7ac2e": "Radio debug and PKA control", | |
| "b9c541abc24f4566": "Lines 61 to 63 event masking", | |
| "b9d49f68527ab3bb": "Line 22 interrupt and event masking", | |
| "ba0ae602802ff795": "OSPI2, UART9, DTS, IOMNG, and DFSDM support", | |
| "ba2d1ee96b05c0d8": "Frame capture and extended data modes", | |
| "ba307a61885e5b98": "Channel 2 data output", | |
| "ba46dc6f5d6ca4da": "Lines 19 to 20 pending bits", | |
| "ba49c9aae3117d09": "Low power and voltage management", | |
| "ba4c1324bb563a1d": "USB interrupt and PVD connection", | |
| "ba4ee8bb3caf18a5": "Error correction code support", | |
| "ba517239585c9adb": "CRC and option byte management", | |
| "ba5f45804190e490": "Tamper input channel configuration", | |
| "ba6e2edb8f00940d": "DMA support for capture/compare", | |
| "ba6fe1b50c9707b7": "Security settings", | |
| "ba884f6431cba2be": "Analog watchdog threshold", | |
| "baa3d9bcbc591c87": "USB type-C power delivery", | |
| "baaece9599d3766f": "DMA and timer interrupts", | |
| "bab344595634423b": "Wakeup pin and pin control", | |
| "babb1b38c68d63e5": "Security configuration", | |
| "bac5212d77a138eb": "PUF and sector protection", | |
| "baca59313e8dc52e": "SRAM ECC and protection", | |
| "bae77147ce357c1e": "Tamper input channels 1 to 15", | |
| "bb19e24392e7ae0e": "ECC and write protection features", | |
| "bb5881ff71e03d25": "UART7 and UART8 security", | |
| "bbb57c3439da1b0d": "Regulator input supply selection", | |
| "bbddc931dc550357": "PLL and communication peripheral control", | |
| "bbe0e8a23d41e223": "Synchronization inputs and outputs", | |
| "bbf4b6d615a8b547": "Timers 5 to 7 halting", | |
| "bbf8673b279d17e9": "SMPS PWM mode", | |
| "bbfa800a0df24af1": "Line 27 masking", | |
| "bc37d5043e14b6d2": "HSE clock security and GPIO port H", | |
| "bc49375f4f0ec615": "DMA and debug control", | |
| "bc5764aec515011d": "Secure access protection", | |
| "bc98dc4e1b835378": "Timer 8 debug stop", | |
| "bca24c725daf8453": "ADC and MCO support", | |
| "bccc1ff0532490d2": "Security configuration for blocks 8 to 11", | |
| "bce7cba0f56d8afc": "Debug and PCROP support", | |
| "bd1ed6805e8aecba": "Output waveform configuration", | |
| "bd257f1e0a10136c": "Privileged access protection", | |
| "bd61f98ac89a049c": "Security and boot configuration", | |
| "bd73c60e9ee9c975": "COMP2 interrupt", | |
| "bd7e51dc35b81ec9": "Security and debug configuration", | |
| "bd88983b5f172209": "Line 16 event and interrupt masking", | |
| "bd9fca7a08bdf5b9": "Interrupt and status flags", | |
| "bdcd8c1f82ba4c3a": "Data prefetch disable", | |
| "be20125cc1fbf797": "Option byte configuration", | |
| "be2a7bca05163078": "Voltage scaler enable", | |
| "be36c5f5e30b830f": "DSI clock selection", | |
| "be3fe390e1a8b72e": "Capture/compare channel 2", | |
| "be4d18296ba8203f": "Multiplexing and chip select override", | |
| "beb62fcc9a5acebc": "SAI1 and DAC support", | |
| "bee490bbd06e02a5": "Channel 7 synchronization", | |
| "bf240cf7034567f3": "Line 19 trigger, software, and status", | |
| "bf3aa7bf122a3453": "DFSDM mode configuration", | |
| "bf411eff3c680b46": "SMPS voltage and status control", | |
| "bf482ebd76b34ded": "Peripheral clock freezing", | |
| "bf4bdee60c4e7803": "Flash, backup registers and pin control", | |
| "bf4d34b9261b8fdf": "Wakeup timer", | |
| "bf6cf220ad6a04ad": "Data transfer count", | |
| "bf7ac271660cbfb4": "Tamper pin 15", | |
| "bfb57e414315e87b": "Advanced transfer settings", | |
| "bfb7147a20f3e9c4": "GPIO port E support", | |
| "bfb7c0d4600700cc": "Peripheral clock selection", | |
| "bfba8de8fc9804ee": "Tamper channel 4", | |
| "bfd1d4e0b85e9ac7": "Start bit error handling", | |
| "bff02a191b06ba9d": "Voltage regulator status", | |
| "bff1f309ecae606c": "Write protection 8 to 11", | |
| "bffe9e817fb37bbd": "Line 32 pending interrupt flag", | |
| "c0348cd2a0665928": "Timer 7", | |
| "c03e56e9f53e43c3": "PLL and LSE control", | |
| "c044485be8f3579b": "Sector 32 to 63 protection", | |
| "c072cd0df003d10f": "Timer base bits 2 to 3", | |
| "c0794fdfd8fa6f4c": "Multi-ADC mode and status", | |
| "c07be8b749a62645": "USART6 to MPCBB5 protection", | |
| "c07f25800be3fe80": "Color mode and interrupt management", | |
| "c08ca951d596d937": "Voltage regulator and calibration interrupts", | |
| "c08e008f4534263d": "Injected data channels", | |
| "c0c94bf04fed5194": "Write protection sectors 96 to 111", | |
| "c0e9676a3bacce2a": "CAN3 debug stop", | |
| "c11de4bdb247a6a1": "DMA2, GPIOI, and DCM peripherals", | |
| "c135591a56d3a189": "DMA and MTLQ status", | |
| "c13ed894423fe714": "Tamper channels 7 to 11", | |
| "c1498bf124333fe4": "Analog watchdog and sequencer configuration", | |
| "c17c6919c18ee7f4": "Line 46 trigger and software interrupt", | |
| "c18c09b5c3ae9ba2": "USART2 security protection", | |
| "c197fe60d2297b04": "Peripheral clock control", | |
| "c1b8a6f29a1570e7": "Dead-time preload enable", | |
| "c1c66f6c6ff412d2": "DAC and TSC support", | |
| "c1dd935b4add3a96": "Fast role swap detection", | |
| "c1ec38dff2167eb7": "Maximum transfer size", | |
| "c1f955e3bda12ffe": "General power management features", | |
| "c21cecfe230a7b12": "TIM7 and USART3 support", | |
| "c2381bb99328c499": "Line 18 trigger, software, and status", | |
| "c23d81f889d1500e": "Privileged access control", | |
| "c2472d36235eea5c": "Master clock division", | |
| "c253e27b0f149edd": "AES, PKA and OTFDEC support", | |
| "c27ba46129f988a2": "Byte select mode", | |
| "c2a67a8136c60071": "Interrupted operation address tracking", | |
| "c2edad7e106d8d04": "DMA, ADC, and RTC clocking", | |
| "c313fd23a38c380c": "Frame prefetch error monitoring", | |
| "c3320946c666eb6f": "Channel 2 trigger selection", | |
| "c39792f99a9b53a1": "GPIO, SPI6, and DMA2 clocking", | |
| "c39c2189772a49fa": "SPI2 and I2C2 support", | |
| "c3ae0de7c105c06e": "SRAM parity error handling", | |
| "c4068877b6a75d74": "Write protection pages 17 to 43", | |
| "c41de22671d9c7c5": "Padding and alignment mode", | |
| "c42471f4127ebb2d": "Data transfer count", | |
| "c44bacdf5614e894": "Touch sensing controller interrupt", | |
| "c48bc939af690620": "Break 2 control", | |
| "c4a9b093e4228325": "TIM15 to TIM17 support", | |
| "c4ced388528a145e": "Peripheral security", | |
| "c4d0b51379dd025a": "Write protection and non-secure settings", | |
| "c4ec0b7367f90808": "Tamper channels 12 to 13", | |
| "c516be7bb26172e6": "Access latency and write protection", | |
| "c518127e79aac2d6": "Security configuration for peripherals 1 to 3", | |
| "c530f804a3a10ede": "Single instruction mode", | |
| "c53973987d2bdb40": "Peripheral remapping and modes", | |
| "c53b941c9ac0e524": "Hardware version and mode selection", | |
| "c53f16295ccf080d": "ECC error lock", | |
| "c5609300d3b8aae0": "Line 22 pending flag", | |
| "c560c78b5360b1ae": "Health test configuration", | |
| "c57f53d6242ec7da": "Firewall access enable", | |
| "c59b919d38f6cb4c": "Analog switch control", | |
| "c5bf59fb656ecc47": "Wakeup pin 2 configuration", | |
| "c5f1b7be08220fec": "SRAM erase and parity features", | |
| "c610458e0c3801b1": "Alarm A and B masking", | |
| "c65171f84aa4d3a2": "Slave injected queue overflow", | |
| "c6547b49036f655e": "GPIO, FMC, and PLL configuration", | |
| "c666fe4418257821": "Capture/compare channels 1 to 4", | |
| "c684fb5aa02711db": "External interrupt lines 21 and 28", | |
| "c69340548f1bd01e": "Smartcard and block transfer support", | |
| "c694420505eacaf6": "CRC, error detection, and option bytes", | |
| "c6a23bebfd465b4c": "Hardware request selection", | |
| "c6c57896a910e2fc": "TIM16 clock freeze", | |
| "c6e55535e6c8862b": "Channels 0 to 11 DMA requests", | |
| "c708ab1d2010a65c": "TIM12 and miscellaneous remapping", | |
| "c72b0727d3fd263f": "Timer stop in debug", | |
| "c72cc619859e8e79": "I/O analog switch voltage selection", | |
| "c73bce73206e6467": "Super block configuration and locking", | |
| "c768b90e0619496a": "Channel request remapping", | |
| "c808070a20fe169c": "Lines 61 to 66 interrupt and event control", | |
| "c8361c9bb2c3c62b": "USB host interface extension", | |
| "c847b5feded965d0": "Slave transmitter and signal management", | |
| "c88164a0810e50cc": "Peripheral clock and reset management", | |
| "c88cbcedd3c9c686": "Synchronization for channels 8 to 11", | |
| "c89e2c934d7ac24c": "SDRAM memory geometry and latency", | |
| "c8d07a6153be36ff": "SRAM, USB power and GPIO pull control", | |
| "c8e9f785bbd51a6d": "Clock phase and polarity", | |
| "c8ff71b86bf3aa7e": "Secure channel configuration", | |
| "c93312b14c58e87a": "SRAM parity error storage", | |
| "c937241f800aa4f7": "Compare values", | |
| "c943f130f9f1812a": "Line 33 pending interrupt", | |
| "c969f61ec2f9cecf": "Boot selection", | |
| "c96c534f45a57402": "Option settings", | |
| "c9718bad4895fac2": "Security configuration for blocks 0 to 2", | |
| "c97b306ccdde40e6": "I2C1 source selection", | |
| "c993b338af180158": "Timer, SPI, USART, and I2C clocking", | |
| "c9c1b47c88b9b6c8": "Digest HR8 to HR15", | |
| "c9e356a4146bccac": "Pin reset commands", | |
| "c9eaa234a8d7d091": "Analog watchdog and calibration", | |
| "c9ef8017cd370f4c": "Interrupt edge selection", | |
| "ca16f64cb424f376": "GFXMMU security settings", | |
| "ca2ef21602572c13": "Secure area and write protection boundaries", | |
| "ca3db15b8bba264c": "Multimode status and clock control", | |
| "ca4720fe408bf2ac": "Access port configuration", | |
| "ca4fa78e1a3f9530": "System clock division", | |
| "ca70673bbdd6c223": "System and I/O configuration", | |
| "ca941a334da04f2b": "Write protection page 21", | |
| "caa2911a8a1ebe2e": "SAI1 clock selection", | |
| "cac32ff8b514c39d": "MPCBB control and security state", | |
| "cb122c6365e21093": "DMA request identification for channels 3 to 4", | |
| "cb134d90dac04da4": "Data and error status", | |
| "cb21a1d63816e691": "Watchdog channel selection", | |
| "cb40f9b540300ea9": "FDCAN2, HSP1 and SPI4 security", | |
| "cb4e18dd51333312": "Sector write protection", | |
| "cb8a8de362ad5e81": "VREFBUF privilege configuration", | |
| "cb9adb31f6fa1c95": "Break disarming/re-arming 1", | |
| "cbe57fcb5cce151c": "I2C2 and LPTIM3 stop", | |
| "cc47192aba9458ba": "Low voltage enable and ECC", | |
| "cc6929306085f901": "Lines 1 to 16 configuration", | |
| "cc79dfe5a5f7f02d": "I3C pin pull-up", | |
| "ccaae9a2d1fad6a7": "Digest HR8 to HR15", | |
| "ccb09733acc5e006": "MDIO register status flags", | |
| "ccc291e4fc89fb73": "Analog switch and interrupt control", | |
| "cccc0a906baf5298": "Pin pull-up and pull-down control", | |
| "ccdb2eab84d61d4c": "Error correction code", | |
| "cced45cf721df73e": "TIM3, TIM7 and I2C3 stop", | |
| "ccf049988228e4a2": "Line 45 interrupt management", | |
| "ccf266ea3fb7b9a9": "Audio prescaler", | |
| "ccfb057b8f0a33ed": "Asynchronous start enable", | |
| "cd1267a98b1e799b": "Boot acknowledgment timeout", | |
| "cd1d356171e8742b": "Wakeup pin configuration", | |
| "cd21c7292a315f5b": "Pin pull-up and pull-down control", | |
| "cd22a8afa779b46b": "Extended channel management", | |
| "cd29a39ca3a83a54": "Multi-ADC mode support", | |
| "cd4d8f6eb6034e88": "Peripheral clock and reset control", | |
| "cda8b32094f36f57": "Algorithm and context swap", | |
| "cde0f129aad9018c": "Voltage monitoring and wake-up pins", | |
| "cde8c9c385fbdaa7": "Channel selection", | |
| "ce07acbb79da6069": "Peripheral freeze in low power modes", | |
| "ce102a31a799a1ec": "DMA request identification for channels 1 to 2", | |
| "ce3718b349ff9221": "FDCAN1 security settings", | |
| "ce403ed320cb81f5": "TIM6 to TIM7 interrupts", | |
| "ce727e517defb5bd": "Tamper input configuration", | |
| "ce82cd13f1695d85": "CPU2 peripheral freeze control", | |
| "ce86917a4423f30c": "SRAM2 erase and lock control", | |
| "ce8746f4df6d7274": "Line 33 interrupt and event masking", | |
| "ce883a5902c72564": "Babble error interrupts", | |
| "ce94ab67c1fa2613": "I2S2 and I2S3 support", | |
| "ceb83cf28145aa9c": "SDRAM burst and timing configuration", | |
| "cec2dadedf325dcf": "DFSDM1 clock selection", | |
| "ced033d7bdbbc244": "Early wakeup configuration", | |
| "cee8ca44e6078156": "Hardware identification and versioning", | |
| "ceeb2df8828ce049": "CAN alternate function remapping", | |
| "cefcd2d602da9a7e": "Key and suspend storage", | |
| "cf23335f9a68c1f1": "JPEG and SRAM6 support", | |
| "cf46ce605314d477": "Synchronization for channels 3 to 4", | |
| "cf4c3e47b50ba57a": "ECC error monitoring", | |
| "cf516f7cc1d01290": "Inter-processor communication and buffering", | |
| "cf6672d2c8519250": "Bank 2 programming and erase control", | |
| "cf66cd8327db11ea": "Line 37 event masking", | |
| "cf963730cb4a0b51": "ADC, TIM16/17, and HSI48", | |
| "cf9e3eef6ad53b0a": "Software trigger B", | |
| "cfce8dfd7557a8ea": "Secure configuration settings", | |
| "cfd6f8b30eb5c463": "APB1 peripheral freeze", | |
| "cff1272933ebfaa3": "Write protection pages 08 to 16", | |
| "d00276d26e1cf8bb": "Advanced timer functions", | |
| "d015d6dd11a7030d": "Word length bit 1", | |
| "d01eb2ae7eedf17c": "Memory latency and error handling", | |
| "d01ef8c30a45bb20": "Bank mapping", | |
| "d022e33fc6c969af": "Line 17 trigger and software interrupts", | |
| "d02e93af5bb13a47": "Clock source and status management", | |
| "d05057bb0f3ba8f3": "Backup regulator management", | |
| "d06a5c4fae5ec626": "LSE mode selection", | |
| "d06d30591d63145f": "Channel configuration and control", | |
| "d0a14c4ae93852b6": "Parallel bank and sector protection", | |
| "d0a29a0e96dc4d5a": "Timers 2 and 3 debug stop", | |
| "d0a7d99bb71f3d8e": "Watchdog, offset, and gain compensation", | |
| "d0eba2237297dd19": "Differential mode and watchdog", | |
| "d1130a1e5b5fcc5c": "BNA continuation control", | |
| "d118d2f0fe68d2b7": "Configuration settings 2", | |
| "d14e12e0e315b39a": "Analog watchdog and short circuit detection", | |
| "d15b0bb539339f06": "Analog watchdog thresholds and sequencer", | |
| "d160717aed94b620": "Wakeup and GPIO control", | |
| "d184d4c6f3e3a797": "Line 41 trigger configuration", | |
| "d18ee291ba1f5ca8": "Peripheral and component identification", | |
| "d18f50ad6c9889fb": "Analog watchdog interrupts", | |
| "d1a6059216b4eb5d": "FIFO request clearing", | |
| "d1ae7e746e84cc81": "Timers 6 and 7 debug stop", | |
| "d1b5628e9a64b667": "DSI interface support", | |
| "d1c3e113fa517c2e": "Bit reset functionality", | |
| "d1c58db8ff10d2f0": "SRAM2 write protection pages 16 to 19", | |
| "d1f46860120699fd": "VDDIO compensation cell", | |
| "d23dff8f32a213f9": "Timer 4 debug stop", | |
| "d2505600692ccbf6": "Trigger event selection", | |
| "d274647982db33f9": "Peripheral interrupt line mapping", | |
| "d28e146ea4aca185": "Primary tamper configuration", | |
| "d2a984d1fe98b322": "SRAM2B write protection pages 0 to 3", | |
| "d2f68d6a5400be05": "TrustZone and privilege protection", | |
| "d2f8c49035a58f3d": "Port pull-up and pull-down", | |
| "d333208c76758ff1": "Capture/compare channels 5 and 6", | |
| "d349c80f76690570": "Line 38 event masking", | |
| "d3644fcd7dc1751d": "Advanced security and error management", | |
| "d36e16ed6fcc8c38": "Line offset and mode settings", | |
| "d38adcf56a85a34d": "TIM17 clock freeze", | |
| "d3b1c440715a2c79": "Port PH2 pull-up/down", | |
| "d3b8ad0e67b753b1": "Channel 1 trigger selection", | |
| "d3c0f321df8cc47c": "ADC DMA remap", | |
| "d3cfe8575acb430e": "Secure muxing enable", | |
| "d3d00914a41d4082": "Transmit FIFO clear flag", | |
| "d3dc99a4cd759c8b": "Regular sequencer rank 28", | |
| "d411dc4b0b9f0010": "Sample rate configuration", | |
| "d42708ea512e5d35": "Capture/compare channel 5 value", | |
| "d4432e58e3f420c0": "Event masking for line 17", | |
| "d4544b1ad2524b29": "I2C fast mode plus", | |
| "d45497a3c2acc53e": "IN transaction AHB error interrupts", | |
| "d485160c5be58405": "Internal timestamp flag", | |
| "d4ba81e7e6764abb": "Comparator 1 input selection", | |
| "d4c33bf0f6251356": "Non-inverting input selection", | |
| "d4f092ac27b47f9e": "GPU2D and GFXMMU protection", | |
| "d4f0a3943ea5ef6f": "Interrupt line mapping", | |
| "d5084757186c828b": "Initialization and status monitoring", | |
| "d524a5098b9d4d35": "MCO clock output configuration", | |
| "d56544ff9122e0ee": "Capture/compare 2 value", | |
| "d56c75215c580636": "Write protection area boundaries", | |
| "d5943a43ee96a172": "I2C4 interrupt", | |
| "d5bc4623302ecdcd": "APB1 peripheral debug stop", | |
| "d5cb1d9e994aef5b": "Boot timeout and transfer size", | |
| "d5e05e800c278cec": "Timers and communication peripherals security", | |
| "d5ee3f869bbdf519": "Peripheral remapping and protection", | |
| "d6590e90263af301": "Option byte configuration", | |
| "d68222fc7d794134": "Wakeup status and clear", | |
| "d6ba25c4a65e5f25": "Secondary input selection", | |
| "d6e43baefc3ed047": "Lines 39 to 53 interrupt and event masking", | |
| "d7046fa64553fcc8": "FMAC, CPU, TIM23, I2C5, and CORDIC support", | |
| "d7109a58d1b9e720": "Data length and count", | |
| "d713cd8838bd47b1": "Channel 1 data output", | |
| "d726d90b36ebf8c4": "Complementary output polarity for channel 4", | |
| "d7401697f1289587": "AES and OTFDEC1 security protection", | |
| "d74fcaf4f0ed4ef3": "Clock source selection", | |
| "d764d84e240bf2ee": "Security configuration for blocks 20 to 27", | |
| "d79172ecb76dae17": "Memory and I2C configuration", | |
| "d79724363b001d9f": "Hardware feature management", | |
| "d7b2dd635ea7ea63": "Watchdog channel selection", | |
| "d7c550fd8c077305": "Vector protection", | |
| "d7de4d3fcf0af5d5": "CORDIC and ethernet support", | |
| "d7e57dd6302cb062": "Timer 4 freeze", | |
| "d8200a2b3cb189fa": "CacheAXI and NPU support", | |
| "d8347dc2e02ed4f0": "Line trigger, software interrupt, and security configuration", | |
| "d847e480dad9e291": "Wakeup flag clearing", | |
| "d88331e42449eb6c": "ECC error monitoring", | |
| "d8972a24dcb4cfca": "Security and protection features", | |
| "d8b2d14536e3986c": "PKA32 SRAM power down", | |
| "d8eb76055f8ccd95": "Advanced cryptographic operations", | |
| "d904a7e75ed4424d": "SDMMC1 peripheral", | |
| "d9466f983c5bbe8d": "Output selection and blanking", | |
| "d9500148bf7c602b": "Configuration and offset control", | |
| "d957b39e87be3ec1": "AES key bits", | |
| "d97070a10a1985b6": "Line 0 trigger flags", | |
| "d97df1389665ff59": "User hardware configuration", | |
| "d9a7aa700705a642": "Internal RAM", | |
| "d9c70f257bb5d9e4": "USB and MCO output selection", | |
| "d9c8553b6683c206": "Memory mapping swap", | |
| "d9e916501bc8ba6c": "TIM3 clock freezing", | |
| "d9ee1d0e36cb428e": "Dual mode operation", | |
| "d9f57b2edb936ff7": "Peripheral DMA remapping", | |
| "da26f66b541f11d0": "Algorithm selection", | |
| "da2f444f1a985fd4": "TIM8 support", | |
| "da35330f43a499da": "Trigger and interrupt for line 18", | |
| "da74dea118ede7e8": "Bank 2 error correction and write protection", | |
| "da90c405ad93b207": "I2C2 fast-mode plus activation", | |
| "daa1a4a22aedf70f": "ECC error monitoring", | |
| "daa3855c024adf32": "CAN and ADC trigger remapping", | |
| "daba60f0438dae50": "Temperature sensor path", | |
| "dae33d73bd7a65a6": "I2C4 clock selection", | |
| "daf0d5f818b57ebc": "Wakeup interrupt control", | |
| "daf5043915c2cfd2": "Lines 0 to 41 interrupt and event configuration", | |
| "daf632a70c69eb5b": "Test mode functionality", | |
| "db08c55cfcbed051": "AXI targets 9 to 10 functionality", | |
| "db4562c56681b31e": "GPU2D security settings", | |
| "db69912d96c2da3e": "UART, SAI and CAN peripherals", | |
| "db69efd4a19d2a9f": "Channel interrupt flags", | |
| "dbc068cbb3039405": "Output compare 1 mode", | |
| "dbc2170b39f78303": "Write protection pages 32 to 57", | |
| "dbe08972b5c02d27": "Backup registers 16 to 31", | |
| "dc0b65ea09e752b6": "Input/output data lines", | |
| "dc13949ecdc84c43": "Comparator peripheral control", | |
| "dc438971c5f4f527": "Cortex M4 lockup output enable", | |
| "dc4e18ad20f8f8e4": "LCD, SPI, I2C, DAC and COMP management", | |
| "dc5c28f065fc8b3a": "HSPI I/O compensation cell", | |
| "dc61655398ecc93e": "Clock prescaler configuration", | |
| "dc7c31e3a8e543d8": "I/O compensation and memory protection", | |
| "dc8b80d2861ec238": "Various peripheral interrupt masking", | |
| "dca3a3dc8129b6dd": "Ethernet PHY interface selection", | |
| "dd28007e855eff37": "ECC error monitoring", | |
| "dd399f7fed51aaab": "Bank 2 write protection", | |
| "dd3b9ef1626f8566": "Security and debug configuration", | |
| "dd51e20bab2589c8": "Security and privilege on line 17", | |
| "dd67fecb4688cb38": "Secure memory size configuration", | |
| "dd8137f116177764": "Privilege configuration for line 21", | |
| "dd991af6ddf31784": "PC card and I/O bank 4 support", | |
| "ddaba947c860ddb3": "AHB1 and AHB3 peripherals", | |
| "ddabfdc6eba81438": "AES hardware acceleration", | |
| "ddbc90880b436e5a": "MAC and DMA error monitoring", | |
| "ddf6af7cbdaed50b": "ECC error detection and correction", | |
| "de002ffe14f38ce5": "FIFO and clock configuration", | |
| "de2999cb31516bcd": "DMA underrun monitoring", | |
| "de3d618760d46110": "PLLI2 configuration", | |
| "de485a7643d644ee": "USB clock source selection", | |
| "de5263fbd3847d8d": "Channel bank and sequencer selection", | |
| "de869b87c81ea805": "Tamper and sub second", | |
| "dec66c07d14d7c74": "Noise source control", | |
| "df023c65c991b50c": "Peripheral freeze in debug", | |
| "df07dd9fd3d84f6a": "LTDCUSB security protection", | |
| "df12fa985245a056": "DSI pad pull-down control", | |
| "df338423d3fc701f": "Input selection", | |
| "df3f3986e9d28a19": "Memory protection unit settings", | |
| "df8f783513df49fb": "Tamper channel 4 selection", | |
| "dfb13bf0f9312525": "Automatic frequency and gain control", | |
| "dfb916fa9e8be169": "Flash write protection 1", | |
| "dff813abd770f760": "Peripheral supply and wakeup control", | |
| "e000c1a8b4e9e2f3": "Clock tree and PLL configuration", | |
| "e0279d776bfd217a": "TIM9 to TIM11 remapping", | |
| "e093124f2daa7d56": "High speed PHY configuration", | |
| "e09b54c9e86277c4": "Tamper detection output enable", | |
| "e0a6329de7d77aab": "Tamper pin 3 configuration", | |
| "e0db443bceaa4157": "Line 28 interrupt masking", | |
| "e0ee2770e83eee4b": "Differential pair trimming", | |
| "e108281cb6d51e8e": "LPTIM2 debug stop", | |
| "e11d5801bd07ae17": "TIM4, TIM8 and TIM17 clock freezing", | |
| "e1288bc43b985680": "Component and peripheral identity", | |
| "e1340475e9a2f23c": "OTG and communication peripherals", | |
| "e13b0b4c6fd2e198": "Break bidirectional mode", | |
| "e13e0a528f586724": "Operation control and status", | |
| "e1455b576e22dfeb": "Trace port clock enable", | |
| "e148037aaf76150c": "Lines 44 to 57 interrupt and event masking", | |
| "e15b78fe29a6b919": "CAN clock freezing", | |
| "e175192534907a6c": "Wakeup pin configuration", | |
| "e18b87f5bbdd7901": "Backup registers 2 to 4", | |
| "e20b1a779716d011": "RF analog PLL input selection", | |
| "e21f91f9731ca39a": "Secondary bank start", | |
| "e22084ec1f5b1158": "AES interrupt routing", | |
| "e254a61379590610": "Internal event timestamping", | |
| "e264feb06399c8fd": "Channel delay and sample skipping", | |
| "e28f428909c1f6e6": "Internal voltage reference ready flag", | |
| "e2ae1d265e1e0544": "Clock source and PLL configuration", | |
| "e2b1cfd7eefeb472": "I2C3 stop in debug", | |
| "e2e4c329ba4205db": "I2C3 and TIM1 clock freezing", | |
| "e2f10f8cfd6ae056": "OUT status phase received interrupt", | |
| "e306a20745edbffc": "Power voltage detector", | |
| "e330b7be72a7646d": "Word count and digest HR16 to HR38", | |
| "e3370bf3bee19ebd": "Line 37 trigger and software interrupt", | |
| "e33c595f95b90043": "Time stamp and tamper", | |
| "e34aeaabecd09781": "Write protection pages 0 to 7", | |
| "e354ffbc2651531a": "I2C3 clock freeze", | |
| "e362b0f00de5ba82": "Line 39 mask configuration", | |
| "e37aa78d90807bee": "SRAM6 power down", | |
| "e381e458524e1722": "Context swap storage", | |
| "e38e484c863a6dad": "Line 0 trigger, software interrupt, and masking", | |
| "e3a7b49636a03e7e": "Clock security and synchronization", | |
| "e3ce424af783b3d2": "Bank selection and erase control", | |
| "e3d97c63e1867966": "Timer stop in debug", | |
| "e3e7f491fcbd5db4": "Non-secure operation and erase control", | |
| "e3f7fda21d8b9be4": "Alternate interrupt masking 2", | |
| "e40dd4629ba9885a": "Line 25 event and interrupt masking", | |
| "e43a1c04761974c9": "Channels 1 to 7 DMA requests", | |
| "e444f48f5aa41549": "PTA converter and SAI1 support", | |
| "e46d5873d92031f8": "Secure programming and control", | |
| "e470aa5a10301617": "Bank power-down and protection", | |
| "e4776d49a0924236": "External interrupt line mapping", | |
| "e47c90b45da76748": "ECC error status", | |
| "e4bb2db27ace6df2": "COMP and ADC3 support", | |
| "e4d4508c85a2e2a1": "Peripheral and clock freezing", | |
| "e4f1318e3626c3a3": "I/O port F and G", | |
| "e4f8a8a3185a821e": "Interrupt acknowledgment", | |
| "e50cd7e037c28700": "Lines 57 to 59 mask settings", | |
| "e51ea69937483a2c": "Backup write protection", | |
| "e54bb124bfe27479": "SMPS security enable", | |
| "e568e5c82a60a2fc": "I2C3 clock selection", | |
| "e57640810bbfcfb6": "Interrupt masking for various peripherals", | |
| "e578da060484855d": "SRAM ECC and write protection", | |
| "e5880cf4bb763941": "Baud rate division", | |
| "e58c935edc001270": "HSI48 DIV6 output", | |
| "e59470f3d758de46": "Trigger input selection", | |
| "e5d64623a5f7c403": "IR mode configuration", | |
| "e5f632c8ed9184a1": "Line 45 event masking", | |
| "e622f7103a8a0145": "TIM6 and I2C2 stop", | |
| "e64013573474821b": "Hardware request selection", | |
| "e692bc538c373bf4": "UART4 clock selection", | |
| "e6a8b337a6d02d98": "TIM6 debug stop", | |
| "e6aa194b639ab479": "IPCC and peripheral clock control", | |
| "e6dd7bc627fe8003": "Debug and trace control", | |
| "e6eadada38d3f823": "Suspend functionality", | |
| "e6fbfac74b2e8681": "HRTIM1 debug stop", | |
| "e7293a66ee127d05": "Capture/compare channel 2", | |
| "e7374bb8d5c3033e": "Dual mode configuration", | |
| "e74eb9925cec1646": "Multimode operation", | |
| "e7666b53df33f429": "RTC clock freezing", | |
| "e77dff04e12f0ede": "Wakeup line management", | |
| "e79866cccdf6d3fd": "Option validity and sector protection", | |
| "e7a2cc7fd0bd1bc3": "CAN stop in debug", | |
| "e7c23add9710fd9b": "Tamper channels 3, 5 and 6", | |
| "e7c8d8b64310a5bb": "Timer 2 stop in debug", | |
| "e7e6a53a56d7893e": "Guard time transmission completion", | |
| "e8186760623f0b34": "External clock enable", | |
| "e81d796e5bd0efa3": "Lines 40 to 41 pending interrupt flags", | |
| "e837e604eb181a98": "Comprehensive health and noise control", | |
| "e858b9c835be09ee": "IN transaction AHB error interrupt", | |
| "e874e591af5e11d8": "DMA remapping", | |
| "e879be1046dfcbf4": "Secure channel management", | |
| "e89382efe279f9a7": "Peripheral and clock freezing", | |
| "e899926f3c5079e5": "Watchdog timer", | |
| "e8a2de93bed40fcc": "Page selection and HDP extension", | |
| "e8a7148e969e4798": "CAN2 debug stop", | |
| "e8c24950641e4c19": "Random value output", | |
| "e8c2e6d60fb769ce": "LCD peripheral", | |
| "e8c3ce2055a80496": "Pin 11 voltage control", | |
| "e8eebdfe59cd468f": "High speed mode and offset trimming", | |
| "e8f7f18b43db8400": "Tamper channel 3", | |
| "e9189b052343600b": "Backup registers 20 to 31", | |
| "e91e4dd3b0165f3d": "Line 17 trigger, software, and status", | |
| "e94fb053c268fce7": "GPIOE and USART2 support", | |
| "e98d8b32226ff9c6": "Window mode configuration", | |
| "e9b469f928ca2ef6": "Channel 18 sampling time", | |
| "e9cf6b487aa996d2": "Library segment configuration", | |
| "e9d20ab32d8c6df8": "Tamper event flag 4", | |
| "e9e8fa9ff586c1c9": "Bank access control and protection", | |
| "e9e9e481967bcf64": "Update and repetition control", | |
| "ea0b7771b0c564b6": "DMA2 channel interrupt masking", | |
| "ea170121d196648c": "Command memory range", | |
| "ea1f91f4e54d4b29": "Secure boot and programming", | |
| "ea572e6040edcb46": "SRAM2B write protection pages 4 to 31", | |
| "ea73f7f46742e09b": "I2C fast mode plus and I/O compensation", | |
| "ea76f2807275d225": "Additional PDM clocks", | |
| "ea7b19c5ff0ba12a": "Power rail compensation and security", | |
| "ea9f9606230fa4a0": "Clock output selection", | |
| "eab08c568b1b588a": "UCPD2 interrupt routing", | |
| "eada675c24ef1ba9": "DFSDM multi-channel delay control", | |
| "eae1a9fe4a2d5ea7": "Comprehensive power and I/O control", | |
| "eae9fe403b171b5e": "UCPD configuration and behavior", | |
| "eaf5c117ba90aea8": "Advanced signal processing functions", | |
| "eafd6c050d094cf1": "Line 26 event masking", | |
| "eb3428ebd7ad737e": "Timer 6 and 15 stop", | |
| "eb401ac619169fdc": "I2C fast mode plus enable", | |
| "eb5bebf748d408ff": "FIFO threshold interrupt", | |
| "eb7909a1c0fe4cb1": "Peripheral security configuration", | |
| "eb865e16272dc970": "Option register configuration", | |
| "eb9c3ad90e059ab6": "CRAM page size configuration", | |
| "eb9f352ee2f4ac11": "I2C2 fast mode plus support", | |
| "eba7ed8f2f275891": "Write protection pages 64 to 79", | |
| "ebb484214a21164c": "CCB security", | |
| "ebcddd69c865635e": "Privileged access protection", | |
| "ebdf2d29e7de738f": "Standby GPIO retention", | |
| "ebfd246190219b73": "Lines 1 to 15 input mode configuration", | |
| "ec0b97869e6c9cc2": "Line 54 software interrupt", | |
| "ec13aa82d8076da4": "Touch sensor comparator mode", | |
| "ec15774bcf872fa2": "Secure memory protection", | |
| "ec470c3161be4cab": "Event mask on line 12", | |
| "ec85ceb3a30c9558": "Channels 5 to 6 synchronization", | |
| "ecc10f9f63a8d010": "Pin mode and speed settings", | |
| "ecc509b7df7bc143": "Multiple peripheral clock management", | |
| "ecd86f317ccc045f": "Line 35 interrupt and event masking", | |
| "ecf3f4a82abae4f7": "LIN and low power modes", | |
| "ed05c8d5f729eba2": "Line 35 trigger and software interrupt", | |
| "ed1ea0b4482db75a": "TSC comparator mode", | |
| "ed22430ba3860a10": "I2C3 fast mode plus", | |
| "ed396f31041df1a8": "Memory protection and ECC", | |
| "ed3ab668b5d8989b": "TrustZone and security management", | |
| "ed479f8a3618c175": "Flash power control and wake-up pins", | |
| "edba5929f37cecec": "SRAM and GPIO retention", | |
| "eddb318e6917aad2": "Write protection 6 and 7", | |
| "eddbe076bb0c2150": "Hardware compensation cell control", | |
| "eddda3b391dbc91d": "Layer 1 vertical window stop position", | |
| "ede50e578ddbc2de": "Configuration control", | |
| "edfc0811cfdf0d10": "Timer and DAC remaps", | |
| "edfd30c384216834": "RTC, FDCAN1 and LPTIM1 stop", | |
| "ee27b8c3ed0d6825": "Wrap and communication modes", | |
| "ee4b1eeda92a3540": "Lines 1 to 5 trigger and mask configuration", | |
| "ee6b6f105c7e7255": "Advanced calibration and watchdog settings", | |
| "ee6e34166c2d0024": "Interrupt management", | |
| "ee824f9b96bc726a": "Input remap selection", | |
| "ee9fcb6f5658270e": "Memory remapping and peripheral mode", | |
| "eebbf544ad16ff04": "Write protection 2 to 5", | |
| "eec9c24ffe13df8f": "High speed mode and range", | |
| "ef23d3bc40a7f0e4": "Interrupt masking and security access", | |
| "ef383e4636a0aa93": "Multiple peripheral clock and source management", | |
| "ef3ae71dfe54794b": "Interrupt status and clear", | |
| "ef57e8bdb28e0942": "Synchronization overrun flags for channels 5 to 6", | |
| "ef620b517def3f18": "Lines 26 to 40 security and privilege", | |
| "ef7653a8e2acc9cf": "Peripheral clock and reset control", | |
| "ef7efb7049991724": "Interrupt line 28 configuration", | |
| "eff5b4c470ef0d58": "Voltage scaling and pin configuration", | |
| "effcf81fc3f36700": "Multiple peripheral secure access", | |
| "f008ee3e3bee89b4": "External interrupt line 11 configuration", | |
| "f07a62d95a5b1e48": "ADC, HSI14 and MCO support", | |
| "f07d809f9c9f89bd": "ASCOM support", | |
| "f092783bf90548ac": "Ethernet interface", | |
| "f0bb8e165700443c": "Smartcard and block features", | |
| "f0be5c1d1b7a139a": "Timestamp edge detection", | |
| "f0c12b9a71607c17": "TIM7 clock freezing", | |
| "f0d7d1b7c15c7b1b": "Error correction and security configuration", | |
| "f10e2f90c02274c2": "Capture/compare channel 2", | |
| "f11702c695a79960": "USART 2 clock selection", | |
| "f121eb39bf9d17b4": "Timer 10 stop in debug", | |
| "f1222e3ecaf5aa25": "Timer 12 debug stop", | |
| "f12f6a359141222a": "Peripheral flow control", | |
| "f16d24ee5570ab69": "Active tamper output selection", | |
| "f175d7e32e66393a": "I/O voltage monitoring and pull control", | |
| "f188ece12b58dc2f": "HSI48, TSC, USB, RNG, CRS and DAC", | |
| "f1a11ab21a09a9d0": "Channel sequencing and data management", | |
| "f1a65be54e0aa94c": "Voltage monitoring enable", | |
| "f1b8eb91c63cd51b": "USART5 and USART6 peripherals", | |
| "f1fbe87f33be8699": "Line 46 event masking", | |
| "f2070845a3736fca": "Bank protection and dual bank support", | |
| "f2105a57c204ce24": "Interrupt line 30", | |
| "f214ac662e918b6a": "Peripheral and clock freezing", | |
| "f2153713e765b72b": "COMP security configuration", | |
| "f2153af657ff3ed7": "USART3, UCPD1 and SAI1 support", | |
| "f230e1fec0a88c4d": "Interrupt line 0", | |
| "f2336a7d95051409": "Line 21 interrupt masking", | |
| "f25f574f34eaf51b": "Voltage monitoring interrupts", | |
| "f268fb1c0ffbb2d1": "Timer controlled mux selection", | |
| "f2b90e181daa1eea": "Auto baud rate detection", | |
| "f2e4b9d7f719e767": "DAC 2 and timer support", | |
| "f2ef3f84c6f6bfdb": "Alternate output configuration", | |
| "f3165e49b252362d": "Backup registers 20 to 31", | |
| "f32f686cc329f816": "Line 18 event masking", | |
| "f342953b45a591d0": "Comparator 2 interrupt", | |
| "f36d7bbcb1b0329c": "HASH peripheral support", | |
| "f37dcda44d48b4b9": "Lines 49 to 64 trigger configuration", | |
| "f3867ed8a964d70f": "Low voltage and power control", | |
| "f3870f3b51f20608": "Hardware identification and version", | |
| "f39c766afd4bcb92": "Power and hysteresis settings", | |
| "f3c0164a7b4fa33e": "Channel and watchdog configuration", | |
| "f3c08d18bd4eab5d": "External interrupt line configuration", | |
| "f3c2931d9d630dc6": "USB device support", | |
| "f3ca0fa56bf792de": "Wakeup timer functionality", | |
| "f40d91fe78985fbd": "Option byte configuration", | |
| "f42b9603a955231c": "QSPI clocking", | |
| "f4344d5a31c1da7f": "Secure page configuration", | |
| "f4427d3dff804897": "Break and repetition control", | |
| "f4645d7f629333ac": "I2C3 stop in debug", | |
| "f4668e599945e31d": "Capture/compare channels 1 and 2", | |
| "f46ea5471f606416": "Peripheral clock control and freeze", | |
| "f475cfb54a870b3e": "Interrupt masking for line 19", | |
| "f476966fc43837ce": "GPIO, SPI2, USART3, and I2C2 support", | |
| "f47723947aa55176": "FMPI2C1 SDA drive capability", | |
| "f47ff2dcc6830dec": "TIM8 and TIM20 clock freezing", | |
| "f49940ac389d42da": "Burst write programming mode", | |
| "f4a2346ef43afeea": "Internal sensor access", | |
| "f4b1e076b39c2ed8": "TIM1, TIM5, TIM8, and TIM15 stop", | |
| "f4d933c802429abb": "General configuration", | |
| "f4e63ba863cfb265": "GPIO and VREF support", | |
| "f4ecbbed378df3b1": "Tamper detection parameters", | |
| "f4f3d4d9d4de7ad2": "Line offset and mode settings", | |
| "f4fd93102875d289": "PKA and OTFDEC support", | |
| "f4fe646625766804": "Line 34 trigger and interrupt configuration", | |
| "f50d915d99568da9": "Digest registers 0 to 4", | |
| "f5227405b08f2453": "Peripheral SRAM and USB supply", | |
| "f5423b2587e6774c": "DSI security", | |
| "f547c99580084487": "Tamper pin 3 functionality", | |
| "f554443ce4a10a5c": "Attack clock selection", | |
| "f55907c1138a1909": "Early wakeup functionality", | |
| "f56468cf0a082637": "Memory mapping and ADC configuration", | |
| "f56c9d9aca458463": "D2 domain stop mode reset options", | |
| "f5902402295c4036": "Output compare modes for channels 3 and 4", | |
| "f599d996b396d67b": "Full peripheral feature set", | |
| "f59c7fb48025b809": "Multiple suspend control bits", | |
| "f5ad17f382f67c17": "Peripheral configuration", | |
| "f5bd376bdb4ef969": "RNG interrupt", | |
| "f63fc5c70540d070": "Break filter", | |
| "f648b953862fe972": "Security attribute configuration", | |
| "f68fa3ceeabf919b": "Voltage scaling status monitoring", | |
| "f691a1d55cff4f75": "Voltage and error handling configuration", | |
| "f6af41a7b483e30a": "Non-secure watermark management", | |
| "f6c0cabd95d0381f": "Clock error detection", | |
| "f6c9855d14d92957": "Backup registers 5 to 9", | |
| "f6ccc6193bcf288f": "Power voltage detection interrupt", | |
| "f6d412386c02cc96": "CID filtering and request selection", | |
| "f705a3cf65e531bb": "VDD compensation and secure configuration", | |
| "f75f33e83af5ef7f": "Hardware identification and versioning", | |
| "f76b2fc64d5a7fa6": "Synchronization overrun flags for channels 14 to 15", | |
| "f78a2bfaeca35546": "Channel 8 configuration", | |
| "f7975b2708af6c22": "TSC support", | |
| "f7c164e247ac6041": "Wakeup pin 5 control", | |
| "f7cb3f7e449f7c45": "COMP1, COMP2 and DAC interrupts", | |
| "f7d35892f85c8c91": "Boot, CRC, and error detection", | |
| "f7ec0f5d92dfd145": "PLL, ADC and OTGHS peripherals", | |
| "f7ed62f68a4388ce": "Window horizontal stop positions", | |
| "f807814c58cb6223": "TIM15 to TIM17 debug stop", | |
| "f8231bd43b9f1c8d": "Channel configuration and control", | |
| "f86b76fb2e8a5a91": "FIFO threshold level 5 bits", | |
| "f88607bd46c341c8": "Non-secure programming and control", | |
| "f89e4f447c9038f7": "Data transfer count", | |
| "f8b3e4eb2fdde5d6": "Watchdog and channel selection", | |
| "f8e77f066b7c95f2": "Channel 2 calibration and timing", | |
| "f8f20b662e7c7fc6": "Gain compensation coefficients", | |
| "f92380cdb733e10c": "Tamper event flags", | |
| "f94fd2e7d79d0043": "Port PD7 pull-up/down", | |
| "f95d6fb6ea364fb2": "Line 29 trigger and interrupt", | |
| "f96bfca1db413f19": "Semaphore core ID storage", | |
| "f975c4e69821b9cc": "Alarm A wakeup flag", | |
| "f9837c867ca004f9": "Buffer not available interrupts", | |
| "f98dd43309dbcee8": "Line 33 interrupt masking", | |
| "f99c4a7dfffc14a9": "FDCAN debug stop", | |
| "f9bbfc5d13712696": "Lines 88 to 91 interrupt and event masking", | |
| "f9cb3e0083389201": "Timer prescaler selection", | |
| "f9dac1af311efcd7": "Channel bank selection", | |
| "f9dbd7eb6f54b055": "SAI2 security configuration", | |
| "f9dc3ddd57ba9527": "Capture/compare 1 value", | |
| "fa0fccd112ef99a1": "PHY interface selection", | |
| "fa2197499b301d19": "Break and dead-time control", | |
| "fa5e5450f1d94739": "Super-block lock control", | |
| "fa944289b91ca06a": "Interrupt masking for lines 1 to 5", | |
| "fa95a94ed26ee0a9": "ADF1 and FDCAN support", | |
| "fa993603818502dd": "I2C stop in debug", | |
| "faa120ae94a4c4a5": "Analog IO group settings", | |
| "faa34917197dcb09": "Capture/compare values", | |
| "fabb723a5ce13177": "TIM15 and SPI4 protection", | |
| "fac9108f6218d437": "Line trigger and pending status", | |
| "fad50e42464d8793": "Additional sampling time setting", | |
| "fadae1d1aa4e5bbc": "SDA hold duration", | |
| "fae690b7a6cde8d9": "Line 57 event and interrupt masking", | |
| "faf5c22233a24e6d": "Multiple comparator configuration", | |
| "fb114a7952f4a5d5": "Memory address channel 6", | |
| "fb18cfa9ed9d2bac": "Lines 61 to 66 configuration", | |
| "fb2106795ea034b4": "Serial communication peripheral clocking", | |
| "fb22dbef546bf05a": "Peripheral and trace control", | |
| "fb2c42153551b6e8": "Interrupt masking for line 22", | |
| "fb4acfdb67880bff": "Lines 39 trigger configuration", | |
| "fb819b47ebb524d0": "UART7 and UART8 protection", | |
| "fb82398bf9d49c40": "LCD support", | |
| "fb920c93c620baba": "SDRAM mode definition", | |
| "fb9858b3879bfae9": "SRAM parity error signal", | |
| "fb9d431ef6b51709": "Parity error address tracking", | |
| "fb9e21f6ef89e29b": "ECC error detection and correction", | |
| "fba6354c49478c08": "Wake-up pin and pull-up/down configuration", | |
| "fbadf0741afd721e": "Trigger and interrupt for line 17", | |
| "fbc1bcd832053ffb": "Sector 96 to 111 protection", | |
| "fbca157070dd95e7": "USB security", | |
| "fbd2723e327c1785": "Secondary detection mode", | |
| "fbe8f3dd92a4ba40": "System PLL configuration", | |
| "fc0db0b83e2338d5": "Wakeup flag 2", | |
| "fc179e70bd7f5115": "PCROP area 2 support", | |
| "fc1ed02de784b47b": "Dual-SIM interface support", | |
| "fc2f34944b6ec42f": "UCPD strobe signals", | |
| "fc3010b84cbbabb7": "Cryptographic and MCE support", | |
| "fc399428d56c07bf": "Clock division and data latency", | |
| "fc3e488fe8abf85b": "Digest registers 5 to 7", | |
| "fc6705e573fa2153": "PA10 fast-mode plus enable", | |
| "fc6b8bbfeb638e43": "Capture/compare 4 output enable", | |
| "fc6d5cde434d2fee": "Timer base bits 0 to 1", | |
| "fc7b40fa28894eb8": "Address selection for operations", | |
| "fc8a9a0687717c72": "Alarm A and B configuration", | |
| "fc991ea1b03f68d9": "Voltage scaling status", | |
| "fca21c57154ad73e": "Capture enable", | |
| "fcacddaa47d54678": "Advanced peripheral security protection", | |
| "fcbdb9630c13cded": "Power control register 2", | |
| "fcbf8b563dc22614": "Line 23 event masking", | |
| "fcc6c01cea516c85": "Lines 0 to 38 trigger configuration", | |
| "fcc9e1d27f538917": "I3C2 interface", | |
| "fccd935f33d651d7": "Lines 32 to 33 interrupt and event masking", | |
| "fccde78647d7dcf5": "Tamper channel 4", | |
| "fcf297e85580c7c2": "SRAM, USB type-C and GPIO pull control", | |
| "fd38670da0bc0681": "Lines 47 to 53 interrupt masking", | |
| "fd3bd20bf2ab3fec": "Comparator security access", | |
| "fd550e05cdcb0e72": "Timers 16 and 17 stop", | |
| "fd74932b48fcddc5": "SRAM error correction code", | |
| "fd8e153adfec963d": "Continuous clock and FIFO control", | |
| "fdca7848997d9231": "DMA and MAC configuration", | |
| "fdcc6455b9fe7a7a": "SRAM2 write protection pages 20 to 31", | |
| "fdf003830b275887": "OTG HS PHY tuning", | |
| "fe0af59ebc9af4c8": "ECC error address", | |
| "fe3b16652ecb7ebb": "Lines 0 to 21 pending flags", | |
| "fe3f27d5608352c2": "TIM16 interrupt line mapping", | |
| "fe49d920bd06bcb2": "SRAM reset and ECC", | |
| "fe514750a3e3e713": "GPIO port F and G control", | |
| "fe5ea7d2ba8dc6c3": "Multimode status and data", | |
| "fe6c1a963987bb35": "Data transfer", | |
| "fe7b5e97f6d43753": "Analog watchdog configuration", | |
| "fe803c892f687876": "PVD lock", | |
| "fe88a6e312dc46a5": "DMA burst and selection", | |
| "fe8ec67b4f1e6f7f": "VDDIO power rail compensation", | |
| "fe9247e0b186d482": "DMA2, I2C3, and AES1 support", | |
| "fe929c1a3f904993": "Peripheral clock and source selection", | |
| "fea5fbbb1c4ae63b": "Autonomous mode control", | |
| "febac888d542e369": "Comparator configuration settings", | |
| "fec8156e966d1e1c": "Tamper input configuration and monitoring", | |
| "ff04626db87b5651": "Internal event timestamping", | |
| "ff1c6cda4ee973ce": "Cryptographic hardware security", | |
| "ff269f8ac447c402": "FIFO and data size management", | |
| "ff449e2abe919bdb": "Peripheral interrupt masking for CPU2", | |
| "ff4574d475380465": "Timer 5 debug stop", | |
| "ff60556fedbe535b": "Line 35 pending interrupt flag", | |
| "ff7610a528b25406": "RTC clock freeze", | |
| "ff962299ab20075a": "HSI48 clock support", | |
| "ffa0d0d09002385d": "HSI48 reference selection", | |
| "ffca6788981cd735": "Oversampling and calibration", | |
| "ffd465ee31420b7d": "PVDOUT interrupt", | |
| "ffd4721c60611853": "CRC to FLASH protection", | |
| "ffeeae3a2dc20550": "Port clock and DQS configuration" | |
| } |
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| { | |
| "001214e7346f1416": "TIM12/13/14 freeze", | |
| "0024ce36a89a4c50": "Port G pull and SRAM power", | |
| "0032ec76f26e814c": "I2C Fast-mode Plus on PB6", | |
| "00449959ac1e8769": "Write Protection Pages 8-16", | |
| "00647a4b5be97069": "OTG High Speed", | |
| "006e9701fcec7941": "Receive enable acknowledgment", | |
| "00741f4d1c04cc6a": "Value ready and source control", | |
| "008e9c22592c2a83": "Group 7 counter", | |
| "00ad31552c84c962": "Alternate channel selection", | |
| "00b789663808a08f": "I2C4 halt", | |
| "00bb1b17590521ec": "Hysteresis and bias control", | |
| "00c7b3c77e24e6a5": "Slave Mode Control", | |
| "00cf4097b41c19df": "AES Cryptographic Engine", | |
| "0124b1532d3adc40": "Debug in low power modes", | |
| "0142838afffc8668": "APB peripheral freeze", | |
| "014d557abb991061": "AES encryption", | |
| "0159aa95f1dc4101": "I/O compensation cell", | |
| "01627a30cbe9009f": "Line 21 trigger configuration", | |
| "016555a8d72b90a7": "Pending request clear selection", | |
| "019a52ce7dd99df7": "Trace mode and I/O enable", | |
| "01b49764cdac41b1": "Extended memory bus and interfaces", | |
| "01ca4045ed40c733": "External trigger selection", | |
| "01d601d4dc29faa0": "SRAM2A write protection pages", | |
| "01d9742bb642b18e": "Boot and bank configuration", | |
| "01f5d4b3bcc59e1c": "Dual Flash Mode", | |
| "02053e634596b4ab": "Timestamp event status", | |
| "02185d0b8d1363a0": "Peripheral ID registers 5–7", | |
| "021af0a7e1dcaf74": "Graphics and multimedia interfaces", | |
| "024f66585a8b113b": "Output Reversal", | |
| "02668ddfb0531237": "TIM15 stop in debug", | |
| "0266bf0a8a00552c": "BCH error correction", | |
| "0275e5e3ebd03d32": "Line 44 interrupt and event mask", | |
| "0284b23c45a5e1cd": "COMP2 enable", | |
| "02857c040fbf9f6e": "I2C Fast Mode Plus", | |
| "02a3a9e881d3c16d": "Line 18 security and privilege", | |
| "02cb02171d374550": "Software reset", | |
| "02e0a2876486804c": "Seconds predivider", | |
| "02f21db92f0ab75c": "FDCAN2 interrupt line", | |
| "03157caf0de749bc": "USB supply and Wake-Up Pin 3", | |
| "0322947e1e9d4f32": "Data Reversal and Initialization", | |
| "03410096304b50b8": "Configurable Polynomial", | |
| "0354c7bc5a548e48": "DMA2 and USART3 routing", | |
| "0355f1ad2cd36a3d": "Backup registers 5-15", | |
| "035805598f53d1a6": "Extended wakeup and power detection", | |
| "03743667aa44b0fb": "SRAM2 write protection", | |
| "03777c1d7ab3d771": "Alternate function options", | |
| "038388bbbb8ef66f": "Device configuration and security", | |
| "0384cbcc0c6ae056": "Write protection zone configuration", | |
| "0389e2ea971293d7": "CAN remapping", | |
| "039025a636678f0b": "Inverting input and blanking", | |
| "0396bcc6f006b159": "DMA and core peripheral configuration", | |
| "03bda903a97ea10f": "ADC prescaler", | |
| "03c0da3a8b59c209": "Channel 2 Complementary", | |
| "03d96a81d1ab6ea0": "Line 23 trigger and interrupt", | |
| "03e2912e52a4b6dc": "Calibration factors and thresholds", | |
| "03e73d8af8f70b4c": "Cortex-M0 LOCKUP Break lock", | |
| "03f95c1eeed026e3": "Channels 5-6", | |
| "0412a2dae2e90842": "Second decryption engine", | |
| "042d0404a45899bc": "PVD rising threshold", | |
| "0436338538ebd7e5": "Master voltage regulator ready", | |
| "044eacc68785614e": "Interrupt lines 17 and 18", | |
| "045db9cea5333bbc": "Low frequency clock modulation", | |
| "048cd45fb275be84": "RAM retention", | |
| "0491bba2bebf33b5": "Write Protection Pages 64-127", | |
| "049cefe882541dd7": "SPI 2 and I2C 2", | |
| "04a6a81b4fca3d59": "Capture/Compare 6 register", | |
| "04a964a13758008d": "ADC external trigger remapping", | |
| "04aed24054392ff1": "OctoSPI manager interface", | |
| "04c9f824e01cc5ea": "Event masking support", | |
| "04d15ec120431c89": "Master Mode Selection 2", | |
| "04e6111e526856c7": "Timer 15 and SPI4 access control", | |
| "0502115be5acafcc": "Break2 generation and interrupt", | |
| "0514dcc80912aa7e": "Extended context and digest", | |
| "0527db9a489a5f70": "DAC and GPIO port E", | |
| "056cf41c194b2483": "Timer 6 and Timer 7 clock", | |
| "0571be6f65479d82": "Display controller", | |
| "057246f9feb54655": "LPTIM4 and LPTIM5 freeze", | |
| "05727e64d9de308b": "Master/Slave Synchronization", | |
| "0572a28d45ade79b": "LCD interrupt masking", | |
| "0575123b8500c2b7": "Capture/compare channels 3 and 4", | |
| "0592c836e59abd39": "PA2 Interrupt Status and Clear", | |
| "059f3929b7c6775f": "SRAM4 power-down and port C pull", | |
| "05a7ad6572a12d8e": "Line 26 interrupt and event mask", | |
| "05bff755d9797266": "COMP1 enable and configuration", | |
| "05c5268472addc1b": "Line 24 trigger configuration", | |
| "05c86dd12b1cdd34": "Line 43 interrupt mask", | |
| "05dcf5eaabb5b165": "SHA-3 algorithm and configuration", | |
| "05df5e8e55f54b7a": "Timestamp subseconds", | |
| "05e3cb4a31bf0c10": "Line 16 interrupt configuration", | |
| "05e693a49c676035": "Embedded host with reset detection", | |
| "05ece064b436dbf7": "Line 23 privilege and security", | |
| "05fd35248e0e6f25": "Capture/Compare Channel 1", | |
| "06183fc6d4c3bada": "Capture/Compare Channel 2", | |
| "06233d5610a4e06c": "Break 2 and system break", | |
| "063963bd54a5496e": "Line 23 trigger control", | |
| "064fd7248192fbe1": "Analog switch routing", | |
| "065b3e64529cbff5": "Masked Interrupt Status", | |
| "06696c4a981914e7": "Channel 1", | |
| "0671210d41caa3c6": "SRAM3 page 4 power-down", | |
| "06816453c0644c8c": "Extended lines with D3", | |
| "06b9904682b7f5a3": "PA9-11, PB2, PC13 retention", | |
| "06be15821c19a532": "MCO output prescaling", | |
| "06cdbd0256531bad": "Secure interrupt masking with VCORE", | |
| "06cef802f7b0a9ec": "Secure AES and CCB", | |
| "06d5ff78b536ce59": "Write protection regions 12-15", | |
| "06de412fbb7dbd74": "HSI Clock Output", | |
| "06e87f757833d5b1": "Interrupt trigger selection", | |
| "06fdd9feaa82c90b": "Line 21 interrupt trigger control", | |
| "070014a86c608b95": "I2C4 fast mode plus", | |
| "07071e8640af7e2e": "Port F and Port G pull-up and pull-down", | |
| "070d2c7e1d55419a": "Write protection region 1", | |
| "071568dfe63fe400": "Port G, SD/MMC, and audio", | |
| "073b9669d2189729": "Stop 2 flag", | |
| "0772030930bca85e": "USB OTG high-speed", | |
| "078673a9c080c01a": "USB", | |
| "078ad7ff3219ab48": "Domain reset and TCM configuration", | |
| "078ce3dfe6d76c3e": "Alternate interrupt and event masking", | |
| "079e384ef693f81e": "SMPS supply ready", | |
| "07b004da1c444037": "SRAM1 page 4 and GPIO retention", | |
| "07b2a69d686502f4": "Backup SRAM ECC Configuration", | |
| "07b62ea5869a010e": "Device address and charger detection", | |
| "07b73315b80a463e": "ECC enable", | |
| "07b76c82184f3143": "RTC and watchdog freeze", | |
| "07d90d33ce0faefd": "Internal tampering no-erase control", | |
| "080c96a8d40d2171": "ICache and PKA erase monitoring", | |
| "080f6bd923d6a7aa": "Active tamper 3 output selection", | |
| "0814611de33d2ce9": "Graphics timer support", | |
| "0838932eba453b97": "PB7 GPIO retention", | |
| "08466491b45ddc79": "Input 8 secure detection", | |
| "087247d2af8d35e6": "Voltage detection and radio support", | |
| "087a28fea761a0b3": "AES encryption engine", | |
| "087c5abbf554fc35": "Line 44 event mask", | |
| "093596ec6be7355b": "DCACHE1 SRAM power-down in Stop", | |
| "0948577469f31d9a": "Low Speed External CSS", | |
| "0954b91d2996789e": "Authentication mailbox", | |
| "099da4b2e78cab11": "Timers 16 and 17", | |
| "09a4fb8f36ce6532": "SPI and USART interfaces", | |
| "09b8273fab9f0c6d": "DCMI interface", | |
| "09b84f4c75d341d4": "GPIO source selection, EXTI lines 10-11", | |
| "09c60b405d16692c": "I/O compensation cell", | |
| "09fb5f2adb3de590": "Line 37 edge trigger", | |
| "09fea1abbe164aa6": "External wakeup pin", | |
| "0a10f5a350c817e6": "Write FIFO disable", | |
| "0a129bb0641e81b4": "FPU interrupts and SRAM2 control", | |
| "0a251d16166b711a": "Line 25 software interrupt", | |
| "0a432c075fb5ee81": "Input line 24", | |
| "0a43cb5281eeeaf4": "EXTI line configuration", | |
| "0a49e2bcbb2d6eaa": "Line 16 software interrupt", | |
| "0a72dc03f57bf4de": "Channel 4 complementary output", | |
| "0a7955b526d2249f": "Access port status", | |
| "0a834bc5ed04af8a": "UART5 interface", | |
| "0a98da74754abcce": "Secure configuration and status", | |
| "0aafa28026a6cc78": "Bus Error and Address Offset", | |
| "0abc7595234a732c": "Line 29 event masking", | |
| "0ad0e2f03c5ae4cc": "GPIO deglitch and input buffer control", | |
| "0ad78309ecf1d38a": "Line 19 trigger and interrupt", | |
| "0adf2f3090654fc6": "Rx analog filter", | |
| "0aef6a1b01007e62": "Lines 79, 84 trigger and interrupt", | |
| "0b50ff873b6f8d81": "Event mask for line 24", | |
| "0b84a01046f7f536": "GPIO retention in Standby", | |
| "0b876c6c2ec5a0dd": "SRAM power control", | |
| "0ba0bd5d6e39af03": "USB interrupt", | |
| "0bacbad818579f0d": "Break 2 COMP2 input", | |
| "0bc06bf4b9d0af75": "Bus turnaround phase", | |
| "0bc7eb9c15214bcf": "Power management and flash bank security", | |
| "0bcbb78ec09305bd": "Voltage scaling and under-drive", | |
| "0bd5bf25ca5b3acc": "Rising and falling edge trigger", | |
| "0bd91492da28110d": "Resource protection groups 1-5, 31", | |
| "0be1993da4ef8303": "Lines 46, 50, 53 trigger and pending", | |
| "0be27fc805ba8a1c": "Delayed read data sampling", | |
| "0bea5e8390101eaa": "High channel sampling configuration", | |
| "0c1013c17eb66f02": "Message filters", | |
| "0c1794077deed09d": "Receive transmit data", | |
| "0c32b982c9bb5da7": "Comparator 8 break input", | |
| "0c58c26fbb219bd6": "Break polarity", | |
| "0c5b7b4e13691492": "CAN interface and USB support", | |
| "0c5d7600c5ccd52a": "Domain 3 pending control", | |
| "0c62b76b82c28e8a": "Stop mode SRAM power-down", | |
| "0c7e398a61bad46e": "I/O Analog Booster", | |
| "0c8cd59f0216945c": "Internal asynchronous interrupt polarity", | |
| "0c8df43b4d65df4b": "GPIO pull-up and pull-down", | |
| "0c990ebc4bd57af5": "I2C3 and TIM10 freeze", | |
| "0ca13827a2140625": "C2 LPTIM3 freeze", | |
| "0cab4b4435e66738": "Register 2 interrupt event mask", | |
| "0caefa3986104787": "Channel selection", | |
| "0cc8a95d3427e686": "System boot addresses", | |
| "0cd190709962889a": "Tamper 7 with internal tamper outputs", | |
| "0d2116949eaf362b": "Pull-up resistor trim values", | |
| "0d371b6c2fecdbd7": "PCROP and read error protection", | |
| "0d543b59ba197834": "Injected group conversions", | |
| "0d556bc172e4ac51": "Alternate function", | |
| "0d687844e136bb87": "Differential channel selection", | |
| "0d6e05ed4e2908b6": "Write protection for pages 8-16", | |
| "0d74b1d964ef71de": "VBAT sensor", | |
| "0d7a5d5cbd5a4184": "TrustZone Security Controller", | |
| "0d88d442ae2f1d96": "Port F5-F13 pull-up with F9-F10 pull-down", | |
| "0da308a514db4200": "Layer 2 window horizontal stop", | |
| "0dacc9d57512089d": "Output polarity", | |
| "0db42bff5419ce3a": "Receive status", | |
| "0db67f4694b235ec": "Interrupt routing and configuration", | |
| "0db869a8a45c34b4": "Completion status flag", | |
| "0dc902f76750d31f": "Regular group conversions", | |
| "0df8426b2ef9e76e": "Channels 1-5 selection", | |
| "0df8b9f2703034af": "Bank 1 write and read protection", | |
| "0e121a2fbfdf8a81": "Graphics accelerator and LCD-TFT display", | |
| "0e3b3afc692046c5": "Cache control", | |
| "0e5687ed601446a3": "PA3, PB0-1 retention", | |
| "0e587d44b89ec742": "Line 20 interrupt masking", | |
| "0e7ca86683ba03b6": "Break 2 Comparator 3", | |
| "0e8012a38c204a10": "SRAM3 pages and USB Power Delivery", | |
| "0e9ae2527ed1a28e": "SRAM2 page 1 power-down", | |
| "0ea03f2c266e88f2": "Bank 1 write protection", | |
| "0eb19d45a342c40e": "Multiple Input Channels", | |
| "0ebb534f12857e08": "Interrupt and event lines 47-53", | |
| "0ec019edf9f60b4a": "FM+ I2C configuration", | |
| "0ec37028d4ed27fb": "CID filtering", | |
| "0ed3155ba543d94c": "Oversampling configuration", | |
| "0eecd9364f48e159": "Extended data output", | |
| "0efd5a2c28d93189": "Alarm output type", | |
| "0f469c2513a14cec": "Domain standby and voltage scaling", | |
| "0f615b60835a9cb4": "Trace I/O enable", | |
| "0f84564cb652cf1a": "GPIO pin multiplexer", | |
| "0f944810c44b6e9a": "Extended security configuration and memory protection", | |
| "0fa04cb8f8b57572": "Groups 6-7 I/O configuration", | |
| "0fa5e0e9eba6011f": "TIM8 counter halt", | |
| "0fb0355209bb7790": "Extended second interrupt bank", | |
| "0fe1f690e1da5a79": "Break input with COMP1", | |
| "0ff4434ae7cf6986": "I2C fast mode plus and interrupts", | |
| "0ff99a48ec8ce974": "Public key accelerator", | |
| "100b2aab31a7c1bc": "Status control in core register", | |
| "10195db5d5fe9825": "Break 2", | |
| "10331dffc0627a6a": "Ethernet and math accelerators", | |
| "104193ca90508bd9": "Stream-to-channel mapping", | |
| "104450b89ce44230": "SRAM2 retention and voltage output scaling", | |
| "105e454c3bfbf33f": "Extended peripheral domain support", | |
| "107a5a9ea0226c1e": "SMPS configuration", | |
| "10ab540b15061a5d": "Flash Selection and Prefetch", | |
| "10b037e7680fd2d5": "Code and write protection offset", | |
| "10c72dd651648ae1": "Timestamp packet filtering", | |
| "10ecd6deb2001c30": "Read completion interrupt", | |
| "10fda4ab1286e1ac": "Backup SRAM hardware erase", | |
| "1121deb28e6eb40d": "Babble error and deep sleep", | |
| "112550ec54bce9b8": "Line 30 interrupt", | |
| "113ef8dde2548c09": "USB OTG HS", | |
| "1142c49279ab63a2": "Watchdogs 2-3 channel selection", | |
| "114d459d21af892d": "USB supply and port D configuration", | |
| "118634ddc103feb7": "USB interface", | |
| "11a02f7f2637033b": "ECC error correction", | |
| "11a816aab108d4da": "Pending line 31", | |
| "11af8938d32e4d63": "Backup SRAM and touch sensing", | |
| "11b04c5d993c7ab2": "Trigger event selection", | |
| "11c1673be21f5449": "USB device support", | |
| "11c6841085c02e87": "Extended security configuration", | |
| "11d4cdb289f88b2a": "Break 2 Comparator 4", | |
| "120598bf50f36528": "Channel 1 DMA request", | |
| "1208266e8b48f9b7": "Double error address and ECC", | |
| "121833972d180725": "Line 32 trigger configuration", | |
| "122ecffb4bcd4bac": "EXTI routing and SRAM2 write protection", | |
| "124cc5d1044f0847": "Multiplexed mode with timing control", | |
| "125554cf828878ae": "Extended Output Compare Modes", | |
| "125862a16d4feb6e": "Output remapping", | |
| "1263cab3328a1b79": "NAND interrupt and ECC", | |
| "126b7858abd2d09a": "Early interrupt threshold", | |
| "126c4db100b95d84": "GPIO E and peripheral expansion", | |
| "126d037fbc04e81e": "Multimode conversion data", | |
| "12849ecfcfcc88f9": "Channel 29 sampling time", | |
| "1294f76e1504954f": "Secure block-based protection", | |
| "129b841f0743323d": "Extended GPIO ports", | |
| "129c9534edc78167": "USART 2", | |
| "12a7c8adbe377434": "Watchdog and differential configuration", | |
| "12afe62f8a491d9c": "Lines 27, 32 interrupt masks", | |
| "12b27dc128c2bd08": "Backup domain and power management", | |
| "12b69737f6e35e1c": "UART5 support", | |
| "12f6019074947935": "Channel request remapping", | |
| "1303ee52a57aa2c6": "Secure programming and status", | |
| "1341f9c6eeaec699": "Analog test bus control", | |
| "1342050ec8d84b7b": "LCD decoupling capacitance", | |
| "137a3ab7e08acb89": "Multi-port signal routing", | |
| "137e5440c2fdf033": "TIM3 TIM6 TIM7 stop in debug", | |
| "138e19aab42da6f4": "PD GPIO retention and USB VDD11", | |
| "1396a12f26762e0b": "Parallel bank mode", | |
| "13ab9f18f8473b21": "Injected conversion trigger selection", | |
| "13c4ab45ca6caf06": "Line 20 edge and software trigger", | |
| "13c8e374548d1b17": "Revision ID", | |
| "13e97a07964a8ea2": "Inverting input selection", | |
| "140ad84aae341513": "Secondary ADC output", | |
| "141dee44be4b48ce": "TIM4 and TIM5 stop in debug", | |
| "1449d17b25229677": "Freeze GPDMA1 channels", | |
| "1477544669976f48": "Group 8 I/O control", | |
| "14810c571d34dc5c": "External interrupt line selection", | |
| "148385ecf0eb6d6c": "Wait state and parity error", | |
| "14854a6984dbe638": "Interrupt flags and control", | |
| "148b5ed85dc82bde": "Port C GPIO pull control", | |
| "1493c1b3fbd122d0": "Secure privilege configuration", | |
| "14a69ff4a4897958": "Pin 11 security", | |
| "14a95462536d92c9": "Output level", | |
| "14ab0953d227fa84": "USART 3 clock source selection", | |
| "14b993aed2218d01": "TIM5 counter stop", | |
| "14c7e9b6b4268d9a": "Line 0 falling interrupt flag", | |
| "14e25ac8c8bb8cb0": "Digital-to-analog converter", | |
| "14eba846de3a5eb1": "Speed and input configuration", | |
| "14ee2e37ffe0d7f2": "GPIO pin multiplexer", | |
| "14f13403b5805321": "USART1, Timer 6, SPI2, I2C2", | |
| "14f6522716fba663": "Trigger event selection", | |
| "1506cd8e486ec739": "DAC 1, GPIO E, USART 2", | |
| "15264ce282ffee06": "External SMPS switch readiness", | |
| "1546985cba206253": "Analog and CAN access control", | |
| "154bb35ddcbda912": "Word exchange and flow control", | |
| "155b540610973195": "DSI display serial interface", | |
| "155ea3d42ba9fd1e": "CORDIC math accelerator", | |
| "15629388ad0d6213": "Calibration and voltage regulation", | |
| "15a9fcf733592feb": "SPI4 interface", | |
| "15aa4910700265f8": "Key management and context", | |
| "15b9fb5e039c78a2": "Display serial interface", | |
| "15d12b5e26141ae8": "Dual-buffered data output", | |
| "15d78555a08037d6": "Port H pull-up and pull-down", | |
| "15e6fdebe8e9ffea": "Line 33 trigger configuration", | |
| "15f6e664ab72508c": "I3C2 freeze", | |
| "1605e50c0dc7a726": "Line 53 pending mask", | |
| "1624601c99ea7518": "Device status and identification", | |
| "1626fe4494a59c64": "SRAM write protection", | |
| "16384d594513088d": "OEM key storage", | |
| "16454862f9730ecd": "DTCM RAM", | |
| "164b4f17dde24b58": "Wakeup pin 3", | |
| "164cd6c58e558a75": "Extended interrupt pending", | |
| "166abc6c66ec02a6": "Power mode selection", | |
| "168b72737c3b1f87": "Dual-CPU power management", | |
| "16b896e7fba0e48a": "Prefetch and power management", | |
| "16c42e75c8282e2a": "Alternate PLL multiplication ratios", | |
| "16c494a52108241f": "Core privilege configuration", | |
| "16c4e5efb9d7e9de": "Firewall reset flag", | |
| "16dd839242a33a22": "Stream interrupt acknowledge", | |
| "16f7dbabe42dc519": "Clock division", | |
| "171131988bb56104": "PVD Timer1 Break lock", | |
| "171d6f711212766a": "Master Mode", | |
| "1726e68f4a04c7d0": "Secure locks", | |
| "1731ad99da684327": "Wakeup output and calibration", | |
| "1732fda01dd37580": "I2C1, Timer 17, LPTIM2", | |
| "174bf6bea8270041": "HSE/32 Clock", | |
| "1759adac8f1c7ea0": "GPIO standby retention", | |
| "17808b68b4b81a03": "Extended wakeup with Ethernet and USB", | |
| "1785596f62dde73c": "Bank 2 secure block protection", | |
| "1791bf18ee99f90f": "Secure access and SMPS control", | |
| "179638d4c0afaf59": "Wakeup Pin Flags", | |
| "17a00282efa7148c": "Line 45 interrupt and event mask", | |
| "17d58a8aab62f46c": "Lines 24–25 privilege and security", | |
| "17d7fa0a53c77360": "Trigger input selection", | |
| "17eb8fe5b791f98c": "Line 16 interrupt pending status", | |
| "1806b7580e09a650": "Lines 10-11 falling interrupt flags", | |
| "181734a4a5a513dc": "CRAM page size", | |
| "1850981e1b853264": "ECC and extended protection", | |
| "185788d1e56eec39": "Secure channel 15 interrupts", | |
| "1868a23852c4b6a2": "External debug request", | |
| "186af312dfd63fd4": "Brownout Reset Interrupt Enable", | |
| "186b901f055cae99": "Channels 3 and 4 DMA", | |
| "187684b5cdf5553a": "Advanced timers 15-17 and CEC interface", | |
| "18a1bc999c8eb934": "Low frequency trigger", | |
| "18ac2d4a7fb12aeb": "UCPD1 strobe signal", | |
| "18c7595f5325e2a2": "High-speed oscillator, ADC, and wireless", | |
| "18fa24cdaaef6683": "TIM3 and TIM4 stop", | |
| "1912828dea75842b": "Capture/Compare 2 with trigger selection", | |
| "192bf367cbac921e": "Data offset correction", | |
| "192c682353464278": "Data input", | |
| "193a52205d0680aa": "Non-secure write protection", | |
| "1949490c62a973ac": "Dual-core serial and analog interfaces", | |
| "195f85db449fb6ca": "Multiple PLL and USB OTG FS", | |
| "196928cb7550f928": "GPIO Status with Power Enable", | |
| "1978c9d8311443ca": "Voltage detector level selection", | |
| "197aeda65eb94de9": "Timestamp subsecond", | |
| "19803d5d4e4c1364": "SRAM2 parity lock", | |
| "19916a2d01e44e88": "RF regulator and debug retention", | |
| "19a278768adc97aa": "Channel 2 DMA underrun flag", | |
| "19d1d8cea9349f80": "SRAM3 page 2 power-down", | |
| "19dd1526162f2e82": "Low-power timer and DMA freeze", | |
| "19e4b7bd905869f9": "Sub-group wakeup interrupt", | |
| "19e8a9936b55991d": "DMA burst access", | |
| "19e8e7ac0f11298f": "Line 20 interrupt configuration", | |
| "19ecd3ee92099dd1": "Advanced transfer parameters", | |
| "19f30b4e8c132e20": "Wireless RF control", | |
| "19fdab0ae559558b": "Secure power and SMPS control", | |
| "1a2a50a25fbef65f": "Line 31 interrupt masking", | |
| "1a341995450aace7": "D3 standby freeze", | |
| "1a4b7a1807be3ba5": "Tamper 2 control", | |
| "1a4ca067995a909a": "Key source selection", | |
| "1a544c15a595cd1f": "Sample and hold", | |
| "1a576deaf7699bb9": "Input Capture 1 remap", | |
| "1a6dc582cee8849d": "Flash programming control", | |
| "1a753cfcbdfffc68": "TIM13-14 remapping", | |
| "1a9d2e385ec6c254": "Free-running clock mode", | |
| "1aa9823c3e14e731": "Core 2 interrupt control", | |
| "1b03a12dd9c7932e": "Odd-channel positive input selection", | |
| "1b052e62c878d1d2": "Line 45 interrupt mask", | |
| "1b0b733337d96dc3": "Line 20 event mask", | |
| "1b0d2c7b7ab6aef6": "Privilege configuration and lock", | |
| "1b131c5153ff50ca": "802.15.4 Activity Flag", | |
| "1b2cd359f638c271": "Transfer extension and underrun", | |
| "1b2e47ab8d651b18": "Extended OEM keys", | |
| "1b3ba11984dc350b": "Large digest output", | |
| "1b56b3fc8724cfa0": "Alternate function 1", | |
| "1b8d15849779b683": "High-resolution timer debug", | |
| "1b949761586684c0": "Port I pins 8-11 pull configuration", | |
| "1bc7546a152b4c07": "Secondary detection mode", | |
| "1bcdd1c9a38e1809": "USB interrupt remapping", | |
| "1bddd286bc73f65a": "Interrupt mask all", | |
| "1bdfe58f5637e513": "DMA and peripheral interrupts", | |
| "1beea53832cdc779": "External Interrupt Line 11", | |
| "1bf59ded16dbb925": "Bank 1 block protection", | |
| "1c19afb9ea969379": "Internal asynchronous interrupt edges", | |
| "1c3d78af13495745": "Write protection for pages 32-63", | |
| "1c42573c9fc1ea86": "Common clock and internal routing", | |
| "1c6f6b9899f51749": "Extended peripheral access", | |
| "1c779188e1c36eb8": "Low-power modes and wake-up control", | |
| "1cdc224841c86d58": "Interrupt masking for dual cores", | |
| "1ced46895ffe6ff6": "Watchdog channel configuration", | |
| "1d0444e579384ffd": "OEM key storage", | |
| "1d182d111ceec267": "Buffer size configuration", | |
| "1d1ebff3f4d10834": "Differential channel selection", | |
| "1d2792ce6c33d8d2": "SRAM2 security", | |
| "1d365abb6a4da79d": "Device identification", | |
| "1d5dd7df7a1abecb": "Core peripherals", | |
| "1d60f42c0861b229": "DMA burst source selection", | |
| "1d72a24b6e9de085": "Clock source and prescaler", | |
| "1d84fe1e35133d1a": "Graphics memory management protection", | |
| "1d88174c44fe9f95": "Sawtooth waveform generator", | |
| "1d893569b45543a5": "Mixed peripheral freeze", | |
| "1dbc5a83c8689a7d": "Guard time and prescaler", | |
| "1df0226bd0c416fe": "RF and power supply tuning", | |
| "1dfc251ae04cdcbf": "Programmable wake-up pin and GPIO retention", | |
| "1dffa261627ad4a7": "DMA remap and SRAM protection", | |
| "1dffaf6c052889e1": "Port F pull-up and pull-down", | |
| "1e01a6ddfa789ad4": "Linked-list DMA operation", | |
| "1e53dd3aa12f9833": "Low voltage support", | |
| "1e7139291aab4d6a": "802.15.4 end-of-activity interrupts", | |
| "1e7f55bc8d8e7bfb": "AES accelerator", | |
| "1e868b3fb38775ab": "Random Number Generator and MCO1", | |
| "1e940b70721fcfc9": "PVD and interrupt monitoring", | |
| "1ec3322e42d6a1ab": "I2C3 Fast-mode Plus", | |
| "1ec5e6f9fab2fe9c": "Break 2 and Commutation", | |
| "1ec91d304da296bd": "Sequencer rank 6", | |
| "1ed4714467522489": "Battery charging mode", | |
| "1ed883bc667709a1": "Ethernet PHY selection", | |
| "1eda58b58294e567": "CAN2 interface", | |
| "1edb89c28d1b7133": "Dual-bank mode", | |
| "1ee7d778ec57c5f2": "Memory empty status flag", | |
| "1eeed7e03e56fefe": "Full control configuration", | |
| "1ef09e3382f31e11": "Request source selection", | |
| "1f1437f5fb87118d": "COMP2 inverting input selection", | |
| "1f1467c1c5637188": "Channels 3 and 4 capture/compare", | |
| "1f22395a716c1bcd": "Configurable device secrets", | |
| "1f60624eaf647889": "FIFO Threshold Level", | |
| "1f6772e5e287dc03": "TIM22 freeze", | |
| "1f67c7dfb9263164": "SPI2 for secondary core", | |
| "1f6efda204dc94ea": "Tamper frequency filtering", | |
| "1f752c10050a44df": "Privilege mode control", | |
| "1f8d94b17a841128": "I2C1 Fast Mode Plus", | |
| "1f9b078576d0a455": "Deep sleep pin control", | |
| "1fafc75a6486a4c7": "Advanced Output and Break Features", | |
| "1fb4a845cc4dc6f4": "USB OTG HS PHY configuration", | |
| "1fb56c57e500e8ed": "Break and dead-time control", | |
| "1fb80ca1398d324e": "Clock security interrupt", | |
| "1fd8325e8749af07": "Erase configuration", | |
| "1fe4ef908e5db8ed": "Timer and I2C SMBUS debug", | |
| "1fefad8d340fa3fc": "FSMC NADV remapping", | |
| "1ff14df4a18cf421": "Line 38 trigger control", | |
| "1ff6f05849aa7b5d": "Backup Domain Features", | |
| "1ffef487db4fcfd7": "Vertical window position", | |
| "1fff7f3ec2a00593": "Memory erase status", | |
| "2014506876d99d66": "SRAM1 power-down in Run", | |
| "20299982accdcba4": "Option byte key", | |
| "203a5dec7b193213": "Base digest output", | |
| "204b44dbfbcb1bda": "Data cache control", | |
| "20596b7d25d61f0d": "TIM5 freeze", | |
| "205eb7163a34976f": "JPEG and SRAM6 power-down", | |
| "20745ce9bbc1fdac": "Line 28 interrupt mask", | |
| "207eb2e366a16486": "DMA1 request line selection", | |
| "208d9c0a86ba27dc": "Cryptographic Accelerators", | |
| "20a0132c3b009799": "APB7 debug control", | |
| "20a2a3f7901da38d": "SRAM power-down control", | |
| "20be41d36312a993": "FDCAN2 access control", | |
| "20d53dd8d7b15b63": "Memory and analog power management", | |
| "20d83590b827ab6a": "SD Memory Card Controller", | |
| "20e9ec45a5284488": "I2C3 and low-power timer configuration", | |
| "20f85d7370b1d9b7": "External Interrupts 12-15, Voltage Booster, SRAM Protection", | |
| "20fd4ad2e46dd1c5": "Freeze APB1 and APB2 peripherals", | |
| "212154e2a1be09b8": "CE-ATA command support", | |
| "21231ea8561e83d4": "Write protection for pages 17-31", | |
| "2123c3fbe4656043": "Ethernet CAN2 SPI3 timer remapping", | |
| "2140be873cd38ab7": "Line 18 interrupt masking", | |
| "214440ce244a64e8": "PB9 standby retention", | |
| "214d0c5036f90236": "SRAM5 power-down", | |
| "21647080ed948a43": "I2C1 Fast-mode Plus", | |
| "216d73e59219eede": "Extended channel sampling time", | |
| "21ad4ff5c9e48701": "Line 24 masking", | |
| "22020871657dfef2": "Interrupt line 29", | |
| "2210dff49fecd49f": "Capture/Compare channels 5-6", | |
| "2217e9c5c6278eb4": "LCD and USB interface", | |
| "222af6ec13daa1a7": "USB OTG access control", | |
| "2250f4847ed2b18d": "Switched-mode power supply", | |
| "22552e807db1fcfc": "SD/MMC card support", | |
| "2264879680a94b10": "IN endpoints 4-5 AHB error interrupt", | |
| "22679f1909ef131d": "Master Mode and Trigger Selection", | |
| "2267a954d3460a87": "I2C2 freeze", | |
| "2273228a28390f22": "Core interrupt trigger and masking", | |
| "228302d5d9ff06e8": "Internal tampering detection 1-2", | |
| "22880f91eb7dd5f8": "Line 31 trigger and interrupt", | |
| "2298657f658b7672": "Context suspension", | |
| "22a7663677fa4f77": "Interrupt and event lines 43-56", | |
| "22af4f7850317903": "SRAM Parity Error Detection Bank 3", | |
| "22bb64eca36bb70d": "Channel 2 control", | |
| "22da1f4868c89feb": "Secure masked interrupt status", | |
| "22fbe504d4d37a9b": "Erratic error interrupt", | |
| "23110eca627719e1": "Tuning and regulator", | |
| "2311bb860b52420c": "PVD timer break lock", | |
| "231653a16af4d7ed": "Graphics and multimedia peripherals", | |
| "2320bc1bd1b15b5a": "Extended line trigger and control", | |
| "233c6ab27908cc8c": "DMA buffer 1", | |
| "233e5d0dc4cfcc3d": "Alternative register interface", | |
| "23505cf28a54c3d9": "Advanced timer stop in debug", | |
| "23523e16c6a9e551": "Secure block protection", | |
| "2357a213df5e442a": "Voltage scaling output", | |
| "2361ce0badd52af0": "Interrupt line status", | |
| "23a1a346c2c30f3e": "Injected queue and voltage regulator", | |
| "23b571df2b4a5e55": "External trigger ADC3 remap", | |
| "23ce680b192db640": "Line 58 interrupt and event", | |
| "23e8183a8664178a": "Internal timestamp flag", | |
| "23e9ba9ef6263901": "Lines 37 and 38 edge triggers", | |
| "23f58eb54058d701": "BLE transceiver interrupt and deglitch control", | |
| "23f7c1ca97c09845": "DMA Burst", | |
| "240094bfe4955ac2": "I3C debug freeze", | |
| "2414694d6926d2c7": "Prescaler divider", | |
| "242b7d25399a36a6": "Device disconnect detection", | |
| "2434ea12eed35b6c": "Input line 27", | |
| "24398f458dd4ddb7": "ADC 3, 4, 5 clock selection", | |
| "246a15178a772fa3": "Break 2 and Channels 5-6", | |
| "247d53ee59e0e2db": "FSMC and TIM5 channel remapping", | |
| "248a82994163fa31": "Channel selection", | |
| "24b348e1fcb5e295": "Timer 7 freeze", | |
| "24b609097ab69a45": "I/O compensation cell control", | |
| "24bb01741325d0b5": "Peripheral voltage monitoring 2 output", | |
| "24c99af8dbb40d91": "LPTIM timer input routing", | |
| "24cbd8f93417a9f8": "Dead-time and break control", | |
| "24e04d755d4acc58": "Wakeup flags", | |
| "254e217c3ba190e7": "Extended DMA channel support", | |
| "25515fcea1ad8aba": "GPDMA channels 8-11 stop in debug", | |
| "2570283403803349": "Digital calibration", | |
| "257adee336d17fc6": "Calibration and sub-second adjustment", | |
| "25804ed723d1476a": "Multimedia and storage interface protection", | |
| "258e360cb7f2ccb2": "Control and Status Monitoring", | |
| "25a24ead9a61b8f7": "External trigger source selection", | |
| "25a855674d76fab8": "Channels 0-7 secure state", | |
| "25a9ef87be7965cc": "Wake up interrupt", | |
| "25aee18768ddbcbe": "Extended endpoint interrupts", | |
| "25b6c1b3022e7924": "Paired comparator control", | |
| "25d93ae973968aa0": "SRAM1 power-down", | |
| "26121e4e92c9a4de": "Low-power timer and UART interrupt status", | |
| "2615ef7b9044cf29": "Clock prescaler", | |
| "261932ba8a656153": "Dual-core support", | |
| "2620276cb6cf6047": "Hide protection area extension", | |
| "26248d3dfdd6dac8": "Security configuration and FPU controls", | |
| "26370d9a242ed977": "I2C4 fast mode plus", | |
| "264a8e7396e4cd95": "Break input disarming", | |
| "264f44c236b9de05": "USB Power Delivery controls", | |
| "2660bd71a4135101": "Extended request remapping", | |
| "26688b9ef51e1bc7": "Line 31 trigger configuration", | |
| "267138c3e0f43c7d": "Multiple watchdogs with extended channels", | |
| "267aab223aeafa48": "Sleep mode debugging", | |
| "2693f104bd386f95": "Dead-time and break control", | |
| "26969a2f2891bbfe": "USB with Sleep Support", | |
| "26a241ec5e9cc877": "CPU2 interrupt masking", | |
| "26ab2b730e631055": "Break 2 and system break", | |
| "26d7a072d57b42a9": "Timer 17 freeze", | |
| "26de0a5f36803909": "PLL Q output", | |
| "26e02c68e0f2d97e": "Debug and Lock Support", | |
| "26e82830cbb9890f": "Cryptographic accelerators", | |
| "2733f23b8151ca29": "Sub-second precision", | |
| "274277aaed5a9b4e": "Line 34 interrupt mask", | |
| "274e886863cb71ca": "Wake-up pin 6 with flash power", | |
| "275eb9a0f6a0d032": "Line 46 interrupt mask", | |
| "2772fd214f0fad63": "SRAM1 and GPIO retention control", | |
| "27784e9ddd36cc65": "TIM7 freeze", | |
| "278fef60abf7dfb2": "Complementary outputs", | |
| "27ebf0c4b600776a": "Audio processing mode", | |
| "2826a7ecfe6e74a8": "I2C bus interface", | |
| "282e1a9b61ff6a5f": "GPDMA 12–15 stop in debug", | |
| "28561c7d09f4b8bc": "Single mode with input remapping", | |
| "2859adc00c04246b": "Boot option configuration bits", | |
| "285e7c9ef6d7e12b": "Extended hardware request selection", | |
| "285ed461dfc06bce": "Fast mode plus and SRAM parity", | |
| "28658317b0145438": "I3C2 security control", | |
| "2868b3216a9bc3a7": "Alternate interrupt masks", | |
| "2868dc4ef3999c59": "Input 4 remap", | |
| "287af750b46d49ca": "Alternate function option 1", | |
| "288060e9da509b78": "Update and repetition events", | |
| "288e9789d0a59fea": "Advanced encryption with suspend", | |
| "28966791b85fdeb3": "Channel selection and interrupt", | |
| "28c183cc967fd11a": "Memory card interface", | |
| "28d02427bbb3293a": "Configuration lock", | |
| "28d292b737f6cc6e": "Comparator 3 break input", | |
| "28d678b2e25517c4": "Flash memory protection configuration", | |
| "28ff2e2ee7fcc9e7": "USB OTG power and GPIO retention", | |
| "292b95ab3f3c2a63": "Option register", | |
| "29416bba8457516a": "VDDIO compensation control", | |
| "294d923d0808a10d": "Voltage detection and GPIO pull", | |
| "294dc9c405eea5a2": "Advanced DMA channel operations", | |
| "2952dc7c08813234": "Timer 2 clock", | |
| "295da1e5d930dc1d": "RNG error interrupt", | |
| "295e9f21cab62357": "Port H3 pull-up and pull-down", | |
| "29959ace8a022f94": "Alternate peripheral routing", | |
| "299c9799f3c4fe7a": "GPIO source selection, EXTI line 0", | |
| "29bba1cb7e3de0b5": "Single group conversion", | |
| "29bdaf21bc1f757f": "CPU2 interrupt masking", | |
| "29be5c743bdb5f94": "Line 16 interrupt masking", | |
| "29caf222899a1aa1": "Programming and erase", | |
| "29e92e3af750f6b8": "Extended power control", | |
| "29efa3c7fed160ff": "Access port status", | |
| "29f4c0d390e7cd11": "Clock and reference configuration", | |
| "29f650f6b06ff276": "Multi-bank and protection options", | |
| "2a079e3ddf4059c9": "Low-power UART and timers", | |
| "2a0ce573933899a8": "Power mode and domain control", | |
| "2a0e4b0c81550b97": "Line 29 masking", | |
| "2a1bd7e7024fe638": "CEC interface", | |
| "2a289951ea27a127": "Extended USART and DMA", | |
| "2a3ed0cda20ba60b": "ADC3 and SDIO interface", | |
| "2a3f72398487481e": "Non-secure privilege protection", | |
| "2a599b8691c3be26": "Output enable", | |
| "2aaf7a995aa8933c": "TIM14 freeze", | |
| "2ab1ef5dc1abb591": "UART communication interface", | |
| "2abd0cf48587520d": "Break input sources", | |
| "2accee14bd9a1749": "Channel 4-5 control", | |
| "2b17d81078b67d84": "FDCAN freeze", | |
| "2b3ec07aa02edb9e": "Secure mode configuration", | |
| "2b4f4b31a365348e": "External interrupt routing and memory remap", | |
| "2b50aaee08bb5fa8": "USB and VDDIO2 voltage monitoring", | |
| "2b8a135057a99d86": "Active tampering filter and output", | |
| "2b92ea0a2dd31e4b": "I/O configuration with RAM retention", | |
| "2bded52c48478fec": "SRAM3 and port F GPIO", | |
| "2beb3e25ce5dae9d": "64-bit access", | |
| "2bf59c03f2713c9f": "External interrupt configuration", | |
| "2bf659b924e42a5f": "PA11 pin remap", | |
| "2c061d35ae004c1c": "Oscillator gating and trimming", | |
| "2c0a31379318013f": "I3C2 stop in debug", | |
| "2c39254eb4557730": "Deepsleep and standby control", | |
| "2c48fe9fd2271da8": "Extended peripherals", | |
| "2c72082eee164169": "Request identification for channel 7", | |
| "2c89c869ca567264": "Extended security (high range)", | |
| "2cbc553ed1d0dac1": "Transmission complete before guard time interrupt", | |
| "2cd596986add6a82": "Backup erase control", | |
| "2ceaf527c65540ec": "Programmable watchdog window", | |
| "2cf3ad9b9651c2e6": "Line 22 edge trigger", | |
| "2cfe0adf371fa428": "I/O selection", | |
| "2d154a33ddc739e3": "Input Capture Remap", | |
| "2d3717b321878b81": "Core 1 interrupt control", | |
| "2d3778e2d6645861": "Low-power mode selection", | |
| "2d392f9d31b34f33": "Tamper input selection", | |
| "2d61b6de6edb95b5": "External event synchronization", | |
| "2d681d60ea908771": "Line 40 event mask", | |
| "2d7808391ccbab9c": "TIM4 freeze", | |
| "2d867e9f4f5343ff": "Watchdog and detector monitoring", | |
| "2d9f6fc305f4632d": "Option Configuration", | |
| "2dcb4ce9c5f8fec1": "Timer 6", | |
| "2dee1be93cfca55e": "Timer 7 and DAC1 DMA remapping", | |
| "2df8b0f231d617ca": "Injected group conversion and extended calibration", | |
| "2e02edb8cb3576a1": "Active tamper input 4", | |
| "2e0a7b62d474e0d5": "Page privilege with power-down", | |
| "2e14174456084284": "Autonomous mode", | |
| "2e15a111a25793ef": "Serial communication interfaces", | |
| "2e1636b76c30ebb2": "Non-secure flash operations", | |
| "2e2605b7c3cda086": "IR modulation and FPU exceptions", | |
| "2e41250cdff03955": "LPUART2 and FDCAN clock", | |
| "2e4d77de3fdecb68": "Complementary output 2", | |
| "2e4ff543b04f2bfa": "Debug clock enable", | |
| "2e541cc7e14ea3ce": "Wake-up flag", | |
| "2e65771a9a24b02f": "D3 domain line 88 interrupt control", | |
| "2e86d127c3c9033a": "Advanced peripherals", | |
| "2e9cf38113ef786b": "GPIO pull configuration for ports C-D", | |
| "2eb0558e6ab6e9e1": "Tamper 1 detection", | |
| "2ebc2d0cb6da2a23": "Channel 1-3 memory address", | |
| "2ec06968efa409c8": "Advanced timer halt", | |
| "2ecfeed9f4e37a52": "Extended write protection", | |
| "2ed97c1128517cbc": "HSI14 clock and Debug MCU", | |
| "2edd65031c1cb1b1": "Counter reset", | |
| "2ef184765eed5cc0": "TIM8 counter halt", | |
| "2ef3a17aa149c694": "Interrupt and event masking", | |
| "2ef8d97bcd12e6fc": "Cryptographic engines and core", | |
| "2efcf29bb42fdd83": "Error interrupts and protection", | |
| "2f0e45738bdbf5eb": "Line 38 interrupt mask", | |
| "2f1e384fb42556ba": "Line 0 interrupt control", | |
| "2f2afe5fd6300b21": "Configurable device secrets", | |
| "2f3f4d0de19388bb": "Output Compare Clear Source", | |
| "2f612269496e2112": "Security and FPU", | |
| "2f6f09f890bfcc80": "DMA channel operations", | |
| "2f76d8d1f220dc23": "Low-power timer interface", | |
| "2f85b54e70ec32e2": "SAI2 interface with clock selection", | |
| "2f8b28361bb23743": "Interrupt status and pin remapping", | |
| "2faf48c588600c86": "Lines 28–29 event masking", | |
| "2fbc4551299820a1": "Input remapping", | |
| "2fcf98edfccc7b93": "Interrupt line 29 status", | |
| "2fd888968b68f2ed": "Wake-up flag bits B", | |
| "2fdf35c4d16bbece": "Groups 5-6 I/O configuration", | |
| "2fec068f752b1591": "Port F GPIO pull control", | |
| "2ff4dae5b25d05cc": "Line 19 falling pending interrupt", | |
| "2ffc66f6ccd52672": "Encrypted flash and XSPI1", | |
| "300f93ebbd993d02": "Power monitor and interrupts", | |
| "302a4022c3e68f88": "SRAM2 write protection pages 10-15", | |
| "3047c21ca47a5807": "Line 25 interrupt masking", | |
| "3058e653b8ee085f": "Line 17 pending interrupt flags", | |
| "305ef12a6ebbaf8e": "Operational Amplifier", | |
| "3075fb2358be6df0": "Line 20 interrupt and event control", | |
| "30b6c306ac9c7a92": "Synchronization overrun status for channels 12-13", | |
| "30c313d8ed206983": "Extended latency control", | |
| "30cd63af64ba911f": "Encoder interface with dithering", | |
| "30dc90ea1da5c3a0": "Automatic gain control", | |
| "30e12f746e84341c": "Device Information and Control", | |
| "3105bacd2b7ec305": "Component identity", | |
| "31203b34694840d4": "Context suspension", | |
| "312cd9d1462fa3c1": "2.4 GHz RADIO control", | |
| "31b3e80b9b8af09a": "Error recovery configuration", | |
| "31b5dcfd610dd5b8": "Additional serial interfaces", | |
| "31cda18703aae8db": "Extended privilege attributes", | |
| "31ce5c96723f6574": "Single flash bank mode", | |
| "31e87cfdc0a0abd0": "Configuration register", | |
| "31ee757fb73cd236": "Security and privilege configuration", | |
| "31f07cd0e95360ee": "External wakeup pin 7", | |
| "3202dfb2cf23ea4f": "Line 26 interrupt masking", | |
| "32049d2d8173caf6": "Counter value", | |
| "32073211f0650074": "Force USB power", | |
| "320a88b83e3e73ee": "Multimedia processing accelerators", | |
| "320aefdfd649ba28": "Update source selection", | |
| "320afef882574865": "DMA1 channels 6-7 remapping", | |
| "321987b6f2f016ff": "Channel control and status", | |
| "32290a82d87abb5d": "Lines 37–42 interrupt and security", | |
| "323199602767fbd6": "Differential mode selection", | |
| "323aa4318202c953": "Extended read protection control", | |
| "32489414bdb21fd5": "General peripheral security", | |
| "324cf20f6383348f": "I2C2 and I2C3 Fast mode", | |
| "324dc4fc0f48934a": "Booster and compensation", | |
| "32561de390aa80b0": "Timer 3 with UART4 and audio", | |
| "325a31aab934be15": "Extended trigger configuration", | |
| "325b665bfaf7d12c": "ECC error break locking", | |
| "325c6bead0b3e5ff": "CAN2 freeze", | |
| "325dd537f16164b0": "Port B pull-up/down", | |
| "325e0df86e9699d4": "TrustZone security", | |
| "325eb2bdc52220b7": "I2C5 stop in debug", | |
| "327089a0f7a31aa2": "High-channel sampling time", | |
| "328314819dfc9ab1": "HSI14 internal oscillator and ADC", | |
| "328e7bf7e0636072": "GPIO D and LCD controller", | |
| "3294f7c198e77dac": "Break and dead-time control", | |
| "32999d28e5a51c1c": "Digital calibration", | |
| "32c08c164471fd4e": "FIFO Threshold", | |
| "32ca5f528c7f316b": "Memory type selection", | |
| "32d2d3f072915bf6": "Interrupt line source selection", | |
| "32d3cd771e83ce00": "Timer 2", | |
| "32db3faed77139ea": "Repetition counter", | |
| "32dd762769c87d3d": "Counter reset modes", | |
| "32e73df85a91a6f9": "Controller enable", | |
| "33242e1d15c86563": "Line 22 pending interrupt flags", | |
| "333aee57728432ee": "ADC2 start and overrun", | |
| "3356cb2de1a2da27": "Configurable oversampling", | |
| "336333cb6c4f4f4d": "QSPI and DSI clock selection", | |
| "3367357ec51ed4e3": "I2C2 fast mode plus", | |
| "336f32d07d4b9726": "Port E pull-up and pull-down", | |
| "33860ce2adf6b464": "Port G pull-up and pull-down", | |
| "3386c5bb0599b698": "Hardware configuration and ADP", | |
| "338aae4d1be4d24c": "UART4 interface", | |
| "3392c97a64514ca5": "Filter 2 data and control", | |
| "3399426067821d3a": "Extended SRAM protection and dual-core routing", | |
| "33cdaf74ac154982": "Cellular RAM page size", | |
| "33d1361f79d978fd": "DMA1 Extended Interrupts", | |
| "33d341aed62d0c56": "Active tamper PRNG and seed", | |
| "33e84d227a8aff28": "HSPI1 and memory 6 protection", | |
| "33eac67ecaf0ca88": "Port F low pins pull", | |
| "33eca9e4d6756dee": "Hardware flow control with interrupts", | |
| "3421f042b9e72dcc": "Event input 16 privilege enable", | |
| "342747fc1eac64f3": "Peripheral debug freeze registers", | |
| "346dfdb88ca9567c": "Wakeup timer", | |
| "3485073544032532": "DMA channel debug suspend", | |
| "3491ff67c2506e78": "SPI1 and USART2", | |
| "3498fd1156472018": "Channel 2 buffer control", | |
| "349a2c667b17ba16": "Flexible payload error checking", | |
| "34b1869747628641": "Wakeup timer and Alarm B", | |
| "34cfc15e444b086c": "Timer 15 clock", | |
| "34d3498d99dac548": "SRAM 3", | |
| "34daf4aa238d1777": "Center-aligned mode", | |
| "34e7a510589ec146": "Extended interrupt trigger and pending", | |
| "353b91ccbc5e67d9": "Backup registers 9-15", | |
| "354499f0dea5585b": "Host pulldown resistors", | |
| "35558739a5e48c75": "Write protection status", | |
| "3560bf48b0286174": "Voltage reference scale", | |
| "3574bbd3ccd7e1ba": "Comparator 4 break input", | |
| "3578cf8b1f7083a4": "External interrupt source selection", | |
| "357cbe6dd539a852": "Port F pull and voltage monitor", | |
| "3585136a23ed6dd5": "ADC345 and TIM20 peripherals", | |
| "35b021b8cc6862e9": "TCM size and cache margin", | |
| "35c153a84068ee6a": "Option register", | |
| "35c5582855173c52": "Complementary PWM with break", | |
| "35d0d5a4e9f5cafc": "Watchdog control", | |
| "35d745c5d7538a38": "Port mode and drive configuration", | |
| "35e4328402a3cd6d": "Line 21 event masking", | |
| "35e517243cde271f": "Window output selection", | |
| "35ea61298f1d76d5": "ICACHE power-down and pull control", | |
| "35eb6937fcb53782": "AES encryption", | |
| "3640fb6cb83ec4eb": "Voltage regulation and USB monitoring", | |
| "365c8570cb5c1d05": "Tamper 3 input", | |
| "3661d3e37932ee79": "Jump HDP level 2", | |
| "36893850c65b8624": "Flash memory bank control", | |
| "3694e073a22ccf62": "FIFO full status", | |
| "36a197cc6e0de833": "Linearity calibration and boost", | |
| "36bbcf8e2247741e": "Configuration lock", | |
| "36c042c1c00df953": "Extended configuration", | |
| "36eb04c5eb6267ee": "Channel 7 memory address", | |
| "37078ff173259d3b": "Mid-range endpoint interrupts", | |
| "372eae933a6e5bcd": "CPU1 extended line masking", | |
| "3735366c9b2308e5": "PA11 and PA12 remapping", | |
| "3739b53fefd74e1e": "Flash protection region addresses", | |
| "3748461398e4c800": "SRAM Power-down and I3C", | |
| "374e6b75ce995a2d": "Privilege and lock", | |
| "37548ee497ce790e": "Interrupt lines 16-17", | |
| "376ab8add1e1802c": "Data word counter", | |
| "377990b1ad82088e": "Tamper 2 control", | |
| "379574b333520312": "Port D GPIO and CPU2 wake-up", | |
| "379c911d4f8a178a": "Internal battery voltage", | |
| "37ca33e81dbceb49": "Bank 1 block security", | |
| "37d5134bdc914e74": "Low-power timer and DAC", | |
| "37d5a1a5144bcc62": "Security and privilege control", | |
| "37e65582ce10210d": "Timer 4", | |
| "3809ddb1a01d64fa": "Port H pull-up and pull-down", | |
| "380d22e80cc3f04f": "CPU2 event masking", | |
| "38152bf175f008ca": "ECC error and power-down key", | |
| "3820c00fec7e3dc5": "Ethernet MAC and DCMI", | |
| "3828b9a383726b4e": "Core soft reset completion", | |
| "38537b4756d2141f": "Peripheral stop in debug", | |
| "38553355c5e3ede0": "SRAM4 error correction and write protection", | |
| "3856d6b1066d4283": "Global wakeup pin control", | |
| "385b6fc0eab6f48d": "LIN break and auto baud rate", | |
| "3870621c740993f9": "Complementary PWM outputs", | |
| "388a41b36567f574": "Wakeup pin 4 and regulator control", | |
| "389c5aea7dbae08a": "GPIO source selection", | |
| "38a5a987194789ad": "Capture/Compare Channel 1", | |
| "38b228e8741063ce": "I2C3 freeze", | |
| "38b3198d4905ce14": "I2S PLL and communication peripherals", | |
| "38c95a9f0f3c34fa": "ADF mode configuration", | |
| "38e6ee21ccef55b4": "Pending line 36", | |
| "392dff31bb5d01b7": "DMA2D and multimedia interfaces", | |
| "395d4f7a60dcdf36": "Option bit 0", | |
| "3972f61bd7873db6": "Port B pins 5-6 pull configuration", | |
| "3983dc38846ad653": "Readout protection", | |
| "398cd2b4f168fd15": "Cryptography and hash engine", | |
| "39af85f64a2b99e9": "Break input remapping", | |
| "39bcc22acdf5281b": "Break and deadtime control", | |
| "39d1d16d312fe8f3": "Common line memory", | |
| "39e1eddcfbbb50e8": "Lines 21-22 security configuration", | |
| "39ede8921de677b8": "Regulator low-power mode", | |
| "3a01051f6578532c": "Memory size", | |
| "3a0272ad8e2a1605": "Extended UART and Delta-Sigma filter", | |
| "3a4575a4f2c6b1e6": "Extended ADC, SPI, and timer support", | |
| "3a7ef2678502a6a5": "Security and privilege configuration lock", | |
| "3a856d506cece90e": "Data resolution and conversion modes", | |
| "3a866687907608bb": "SPI 3 with DMA2", | |
| "3ac00605fb05d934": "Timer 4 and SMBus freeze", | |
| "3ac7ab148ee36c05": "Debug clock enable", | |
| "3adf8a0fbb9648d5": "Receive FIFO full interrupt", | |
| "3ae80404c7560335": "I/O supply monitor", | |
| "3af5270f904e9a19": "Read error detection", | |
| "3af7355836cc5cb6": "Edge-triggered interrupt masking", | |
| "3b1e7cd53ae3668a": "Mid-range interrupt lines", | |
| "3b2afbe6352c4437": "Switch control", | |
| "3b442ce96f66caab": "Range selection", | |
| "3b6645ee8cb97fa9": "BLE transceiver edge detection", | |
| "3b77e0e84ff9208f": "Seed error interrupt", | |
| "3b83a907686a784c": "Output idle state", | |
| "3b893859e22ba8c3": "Line 0 pending mask", | |
| "3b8b85782ff10b8c": "I2C2 SMBUS timeout stop in debug", | |
| "3b988b57580bf81e": "External break input", | |
| "3baca7c31ebcdb18": "USB and CAN support", | |
| "3bb26dd93a883c46": "Wakeup from stop mode", | |
| "3bccff3c6bfebcee": "Wakeup and retention", | |
| "3bd274da76a3c52c": "TIM17 stop in debug", | |
| "3bd5aa1d9d098831": "SPI2 interface", | |
| "3bdb277c1ab6e5e7": "Line 23 rising edge trigger", | |
| "3bfcd1f1a355260b": "Crypto accelerator clock", | |
| "3c0b69ad1ea4f734": "Channel 4-5 configuration", | |
| "3c18cc07a46ed982": "Comparator hysteresis", | |
| "3c240ee98ec99391": "SRAM2 standby retention", | |
| "3c7498e35c09f1f6": "Alarm B sub-second mask", | |
| "3c758cf73c20c83c": "Dual-bank boot mode", | |
| "3c8752e2e7219050": "Port D GPIO pull control", | |
| "3c9d886b3c84d938": "Motor encoder interface", | |
| "3ca3c18a40e18501": "JPEG and LTDC display", | |
| "3cc193bfaeda742e": "Trigger DMA request", | |
| "3cd7dd062f67b4fe": "Block repeat mode", | |
| "3cfc4df726aef76d": "Freeze APB3 and APB4", | |
| "3d248ae8f6d5e3ad": "Single error address", | |
| "3d395e556d3499c5": "Privilege-based page protection", | |
| "3d3975cccbce6d8f": "PCROP area address registers", | |
| "3d54aa7d5264b7b5": "Microcontroller clock output", | |
| "3d686aca35f4f8a1": "Input 1 remap", | |
| "3d6f7f86ab45eb54": "USB supply timing", | |
| "3d819339224e0ffa": "Block security configuration", | |
| "3d8c0ae9ad522ae2": "Graphics timer and JPEG codec", | |
| "3da076cc2e252cec": "Hysteresis and bias generator", | |
| "3dd7132c4560292f": "I2S and peripheral routing", | |
| "3df3297728a2748c": "Tamper 8 and internal tamper 15", | |
| "3e3aca57dbf34312": "Initialization vector support", | |
| "3e407f13843fd7b8": "PLL input divider", | |
| "3e57d6cfb500fbbf": "USART6 access control", | |
| "3e898de5c8f4b638": "DMA2 and SPI3", | |
| "3eb0fc2837238085": "SDRAM bank 2 configuration", | |
| "3eb45495d829fa80": "Semaphore core ID", | |
| "3eb914aa5d9a1f6d": "Analog comparator", | |
| "3ecac6b01284a3c7": "Line 36 interrupt and event masks", | |
| "3ed407e5432a071e": "Channel 8 transfer parameters", | |
| "3ed5bcddd7644445": "I2C6 stop in debug", | |
| "3ed72edc2b742f91": "I2C2 freeze", | |
| "3ee8f05c9ca983e3": "General-purpose timers and communication", | |
| "3ef38c7bd20c42b9": "Timer 7 freeze", | |
| "3f06cc35346c0c28": "AES Debug and Lock Control", | |
| "3f091000c5708207": "Line 17 interrupt masking", | |
| "3f0ed5cf9d229c65": "Port A and B selective pulls", | |
| "3f18376d6e0108a6": "External trigger source selection", | |
| "3f29ac121b858e4b": "Interrupt line status", | |
| "3f29c04cc58a287c": "Extended slave mode selection", | |
| "3f4aa38c1f0613eb": "Read protection error flag", | |
| "3f8229c39ecfc7ab": "Output and break control", | |
| "3f9806d62993674f": "Output compare remapping selection", | |
| "3f9f55223d8d8c91": "Power supply and clock recovery interrupts", | |
| "3fa8ea97f4b12eae": "Interrupt line 19", | |
| "3fb9d22021344ae4": "Layer 2 control", | |
| "3fc2d62f5d63528e": "External interrupt configuration", | |
| "3fdf77d0fd78671a": "Alternate function", | |
| "400fcaf9368a3688": "User bank swap and I2C acceleration", | |
| "40120397324c530a": "Extended Mode Selection", | |
| "4020561385d90a4b": "Linearity calibration with LDO", | |
| "402e5dd2eee5266d": "Line 48 interrupt mask", | |
| "4034ff1c4979c83d": "Backup registers 5-8", | |
| "40398ce646102a4f": "IQ Sample and Antenna Status", | |
| "4046ab76cd562acc": "Watchdog freeze", | |
| "405372211a79cd3a": "Initialization and status", | |
| "405ef91433d8e475": "DMA and Peripheral Interrupts", | |
| "409141f78b8e0769": "Option bit 1", | |
| "40a47daeb02f509a": "Sector erase and programming", | |
| "40a7f071a0972fd3": "GPIO port D clock", | |
| "40d5ae49e35c0ae0": "Public Key Accelerator protection", | |
| "40de7ec87c6451a3": "Clock source selection", | |
| "4103f539f8db3650": "3D Stereo Control", | |
| "4113f281b69ae4b9": "Audio and external memory access", | |
| "411de7f35225012b": "Advanced timer and DMA remapping", | |
| "415bc6bdc62a477f": "Interrupt line status", | |
| "41674d0ae3466827": "Interrupt Line Status", | |
| "416e4e97ec7827f1": "Privileged state configuration", | |
| "41a2200c497b114c": "Pin and signal remapping with interrupt status", | |
| "41a405feb34aa45e": "Wakeup flag", | |
| "41ad814d5b601bec": "Encoder mode and break input", | |
| "41b26d2cd73a8250": "Data byte access", | |
| "41c70f58b2a38c0b": "Tamper 1 detection", | |
| "41e02713ba0d2772": "Lines 49, 58, 59, 64 trigger and pending", | |
| "41e3b146420f773c": "CPU2 timer freeze", | |
| "41f15e28d4a974a4": "Flash Selection and Delay", | |
| "4207a333e7a87ede": "Write Protection Register 2", | |
| "420a3cb08b24d937": "High speed mode", | |
| "421c6ca17aec56d2": "Alternative sequencer mode", | |
| "42325a7f4e53894c": "LPUART1 clock support", | |
| "423a30217fbecbda": "Tamper 2 flag", | |
| "423cdd0692e50a12": "System option bits", | |
| "424cde167af4904f": "Advanced configuration and health testing", | |
| "424da5e45c869ed0": "System memory remapping", | |
| "4262c187c1c69335": "Analog output selection 4", | |
| "426e5bd84e6d5a75": "TI1 selection", | |
| "4270ca61bbcc421d": "Low-power timer 1", | |
| "4272857828f6055f": "Synchronous slave mode", | |
| "42765e17c03e75a8": "Port E pull control", | |
| "428786e274011ee7": "DCMI and PSSI access control", | |
| "4291b3a05cbdf9b0": "Vlcd external capacitor connection", | |
| "42b14d8039ff6fae": "External tamper 5", | |
| "42ba74d24bb71bbb": "Bank 2 mass erase", | |
| "42c652c299bdfc79": "Dual-bank secure regions", | |
| "42e1eb33937eda5e": "Line 19 pending interrupt flags", | |
| "42e8e9654b57c85e": "UART 4 and 5", | |
| "42f3004117b51854": "Extended write protection register", | |
| "430cc63ffd8d4670": "Preload control", | |
| "432106a0292538fe": "Extended option registers", | |
| "432e03916668eff7": "Flash operation control", | |
| "43402cc3ce821d0a": "Group 8 counter", | |
| "4348a8be3eff5203": "Power domain sleep mode control", | |
| "436f21ea4b29ed0b": "GPDMA2 channel 0 freeze", | |
| "4399eaa468d182a4": "Backup regulator control", | |
| "43b7e773c68bcf69": "Trigger and input remapping", | |
| "43bc8d4de11a0b7b": "Variant device freeze registers", | |
| "43c115d8d4f4187f": "Channel privilege and lock", | |
| "43cd1a1bcfc07529": "Odd/even byte and line selection", | |
| "43d0f4b642956730": "Deep sleep EEPROM", | |
| "43e94d0546694613": "Line 42 event mask", | |
| "43ede88edc77c6e4": "Host Negotiation Protocol", | |
| "4406db8791a975f9": "D3 domain stop and standby", | |
| "441981f6463bc3d2": "Page read and write protection", | |
| "442e10beec6e90e7": "Security keys and block protection", | |
| "4437fbbd7fb1f8a9": "PLL3 and Camera Interface", | |
| "443d627e250f1bac": "Wake-up flag register A", | |
| "444203bc3c126cff": "Security Enable", | |
| "4452aeae9ca0a00c": "Regulator status", | |
| "4473ad800ef76932": "Flash bank swap", | |
| "449757aec7807a38": "Extended option status", | |
| "449c19cca1b21fe3": "Extended digest variant", | |
| "44a9080a828c3ad6": "Line 20 trigger and pending", | |
| "44acc76a052f35d8": "External wakeup pin selection", | |
| "44af9145a084db38": "Watchdog reset flag", | |
| "44b77153aad09d93": "HSI oscillator trimming", | |
| "451c5c0e7d0fe885": "LPUART baud rate", | |
| "454b86742f8b970f": "DSI Host Interface", | |
| "455de35c1d9aab03": "Decryption regions", | |
| "457c8a053c1ef16c": "Retention range selection", | |
| "459429f3a6315808": "Page and address configuration", | |
| "45a775b34a3ef4ea": "Channel 19 sampling time", | |
| "45cb94988c20f6ae": "Extended backup data", | |
| "45d374ae406c7ea8": "I2C2 Fast Mode Plus", | |
| "45d514bc3e70f92c": "SPI2 and I2C2 clock", | |
| "45e82d9c51ad0d56": "CRAM page size", | |
| "45f9e5d50bd392f1": "TIM1 freeze", | |
| "45fdab027d8303f5": "Falling pending interrupt flags", | |
| "45fdf10a36d7e817": "Trace port configuration", | |
| "46034159a2f8b296": "Alarm B subseconds", | |
| "461038f826af78a0": "Power voltage detection", | |
| "46174a9d6413ce48": "Rising trigger selection", | |
| "46196e93898cfd27": "Output type per pin", | |
| "462a9fd1e2415419": "ECC error address", | |
| "463a5765b46bcff7": "Security configuration and power management", | |
| "4645622f4fc99f13": "Audio interface protection", | |
| "46969fbaf02bde90": "CAN freeze", | |
| "46a4d67b63e3db08": "Port C and D GPIO pull control", | |
| "46a50fa0aca59cee": "SRAM3 page power-down", | |
| "46a9f20a054cd4f8": "Touch Sensing Controller", | |
| "46ae33e6fbdc568c": "External trigger output", | |
| "46e809832d75c97c": "ECC monitors 4 and 5", | |
| "46e8943a4a2b1897": "Core ID for clear operations", | |
| "46fbd901546a002b": "SPI and I2C DMA remapping", | |
| "470e24e2258851d2": "I2C low-power freeze", | |
| "472461eb190a8469": "Advanced peripheral interface access control", | |
| "4724b500ba721e1f": "SRAM1 page 2 power-down in Stop", | |
| "473785346ecafa39": "Extended interrupt line control", | |
| "475e48604c29c7ae": "Input selection", | |
| "477559201cd7dc68": "SRAM3 and SRAM4 power-down", | |
| "47c45f62749e7545": "Channel transfer count", | |
| "47e3b44ce5cf3739": "Line 34 falling interrupt", | |
| "480d6e249fc1d57e": "Wake-up line control", | |
| "483f404f111c207c": "Extended channel monitoring", | |
| "4849f7b2a3817b32": "Math Acceleration with Extended Peripherals", | |
| "484b415425e2dbc4": "CAN1 freeze", | |
| "4851305d4ca1d432": "Dual break and comparators", | |
| "487560b4a705432a": "Health flags reset", | |
| "48c80a21ee491e98": "CPU2 interrupt control", | |
| "48ca39c9bdc441d8": "Readout protection configuration", | |
| "48cf79f3430e1897": "MCO2 clock output", | |
| "48de8e5e922a7aeb": "Multimode DMA configuration", | |
| "48dfcf9896f17289": "Operation Error Handling", | |
| "48fe12115f453ff0": "Window mode", | |
| "490b48ef15af56d3": "FIFO threshold", | |
| "491e08355bbbe4f7": "MCO2 prescaler", | |
| "493e55e8dbf69b98": "Data hold and byte lane setup", | |
| "4942637583dbdfa7": "Dual-bank write protection", | |
| "494b757bab564010": "CPU2 interrupt masking", | |
| "494e7249f9b135cb": "Time, date, and alarm A", | |
| "495a64467708b852": "Voltage output selection", | |
| "4967b5dd76b2a7d3": "SHA3 extended digest", | |
| "498adde834a6c185": "USB supply monitoring and GPIO control", | |
| "499dbe59c8510424": "Amplifier routing and offset calibration", | |
| "49a2e8393d239f81": "Pending request lines 49, 51", | |
| "49a975492ac82c67": "Shutdown wakeup and SMPS trim", | |
| "49bc930aec93cea2": "Break Disarming and Re-arming", | |
| "49c9f4c06483577d": "Internal timestamp", | |
| "49d5dabfcdd6dbff": "Wakeup pins 3 and 5", | |
| "49da68b40d8552c1": "Break Input Control", | |
| "49eef06639cf1bae": "SAI2 clock source", | |
| "4a067cc146dda757": "CAN debug freeze", | |
| "4a15a733edb29a1a": "Internal tamper 4 with active clock", | |
| "4a2de7ff0bf7139c": "Hardware request selection", | |
| "4a31628a6246980c": "Non-secure control registers", | |
| "4a3dcbcdf29d9d4f": "DMA and GPIO clock enables", | |
| "4a50d5a597dae89a": "Noise source configuration", | |
| "4a580a8aa58e051c": "Peripheral flow control mode", | |
| "4a83e4ba3b7cebc9": "Configuration lock", | |
| "4a8d76911aaa88a6": "Delay Line Calibration", | |
| "4a914ef84d8e6f3c": "Autonomous mode", | |
| "4a9e268d8be35395": "Channel 7 configuration", | |
| "4aa1bf873c553939": "Timer 12 freeze", | |
| "4aac24dea5ab9287": "Master mode selection", | |
| "4ac2d014ac439d52": "Watchdog and timer 1 freeze", | |
| "4ac5e917f9402954": "Line 24 interrupt masking", | |
| "4adaf791366dc51e": "SmartCard mode with End of Block", | |
| "4b0da74c10c8529e": "Block repeat configuration", | |
| "4b26389aa695d131": "Extended security bits (high)", | |
| "4b369ec152700673": "DMA channel freeze", | |
| "4b3b18b5d748f239": "Decryption and hash engines", | |
| "4b72c819e5a24737": "Secure interrupt line configuration", | |
| "4ba90602ced3361a": "D2 event masking", | |
| "4bad39b775b268f5": "SRAM ECC and block protection", | |
| "4bbec3e5554c1a8b": "Endpoints 4 and 5", | |
| "4bc880e6eb833944": "DMA2 and audio interface", | |
| "4bcbbb93ac32dfbb": "Line 32 edge trigger", | |
| "4c059ccb2997ae09": "SRAM3 page 12 power-down", | |
| "4c141e57b65c8ce5": "Port E GPIO pull control", | |
| "4c1c450ef73c79b9": "SRAM1 single error correction", | |
| "4c21a0c3c4714d80": "DMA remapping", | |
| "4c3cd263e56c036d": "VDDIO2 voltage monitoring", | |
| "4c5f5fda51d5f364": "Analog switch booster and UCPD", | |
| "4c7bcbf7f720e174": "Timer and USART support", | |
| "4c7ee58736536ba4": "Channels 6-7 control", | |
| "4c8c2b873f39c3ac": "Sector erase selection", | |
| "4c92939152a2a9e4": "IN endpoint AHB error interrupt", | |
| "4cb6aae3341006d3": "IN endpoint bulk NAK interrupt", | |
| "4cd4425c2452943a": "Tamper 3 mask flag", | |
| "4cd9268905a83c45": "Step-down converter and LPUART", | |
| "4ce75a1520035d42": "CPU1 freeze control", | |
| "4d0b5037b3dbee19": "Port F pin 3 pull-down", | |
| "4d3f4b145b1c6870": "Multimode operation", | |
| "4d49d862c774c3f1": "Host channel 8", | |
| "4d69481bd6174114": "Line 18 interrupt triggers", | |
| "4d76b6fc1fad4658": "Data hold and byte lane setup", | |
| "4d7a0dd237a6e506": "DPA protection", | |
| "4d7fe618347a41a7": "Operation error detection", | |
| "4d8985391cb7b9f4": "Timer trigger remapping", | |
| "4d8b90a477838987": "Secure provisioning and product state", | |
| "4d8c739cfebbfda9": "I2C2 Fast mode plus", | |
| "4d99c55793cbec79": "Write protection", | |
| "4da4c316a80acdbc": "CPU1 extended interrupt masking", | |
| "4db5bb8b4019d70c": "Line 24 security configuration", | |
| "4de670c67811cab2": "Write protection regions 2-3", | |
| "4de6cf7ac80dbf9b": "Backup SRAM and TSC comparator", | |
| "4dffd2da7321f5fb": "Line 18 pending interrupt flags", | |
| "4e00968326fbf12f": "CPU2 Power Management", | |
| "4e2643afe96b3e50": "SRAM2 erase and write protection", | |
| "4e2cf7cbef0d6fc7": "LPTIM3 freeze", | |
| "4e32b8ca50fd7f65": "Line 34 interrupt and event masks", | |
| "4e3b0693112be444": "Line 22 interrupt and event masking", | |
| "4e429ed938134162": "Amplifier 3", | |
| "4e5043cb24a0326b": "Trace pin control", | |
| "4e51086481b84e96": "RSS command", | |
| "4e5e61ba904b4299": "GPIO port E", | |
| "4e79a77af57ef3fa": "Extended peripheral interfaces", | |
| "4e7bd849e5860c03": "Channel 4-7 input delay", | |
| "4e907fa69a48c72b": "Wake-up flag bits A", | |
| "4e9a12ebfe83f351": "Dual output", | |
| "4eb58321f48d1b87": "Babble error detection", | |
| "4ed837912b99f678": "Timer 6/15, USART 3/4, I2C 2", | |
| "4edeb3821d9c8b4e": "Dual DMA buffers", | |
| "4eee38e10395e3cc": "Digit calibration", | |
| "4efe6903ae7906f8": "Identification and version", | |
| "4f15503fc0f13aea": "Miscellaneous remapping", | |
| "4f1cb977083d9c59": "Core ID for read-lock operations", | |
| "4f354879e807e4b0": "Internal tamper 4 erase control", | |
| "4f6b61d6abbf49ce": "Advanced timer 8", | |
| "4f76d92ad9128ccf": "802.15.4 radio wakeup control", | |
| "4f83c71c612103d6": "DAC interface", | |
| "4faf0be57effe3ef": "External clock security system", | |
| "4ff9485942b72526": "Upper B-C pull resistors", | |
| "4ffaa84bbf4f0f1e": "Power and hysteresis control", | |
| "5008b004c6c74890": "Phase-locked loop 3", | |
| "5015910c9f30ad3a": "Request source selection", | |
| "5018599b17bad4cf": "I2C4 SMBUS timeout", | |
| "501ad45477a1f05f": "VDDIO2 high speed IO", | |
| "5023ff878b73d449": "Synchronization interrupt and event", | |
| "502796e0cc2c0260": "RF and SMPS advanced features", | |
| "503208f2a553fbea": "TI frame error flag", | |
| "503e9b4ac6856df0": "Timer 2 freeze", | |
| "50408731048e0b69": "Channel 8 transfer count", | |
| "5046e738af46a966": "HDP level 2 and 3 jumps", | |
| "504c99de92062c99": "ADC external trigger remap", | |
| "508dcb1ea1a13876": "Break comparator 1", | |
| "50981f4bec83bc9a": "SRAM3 DMA2D stop power-down", | |
| "50a34298c1710e97": "Clock prescaler", | |
| "50ba2f94f89d687b": "Layer 1 window horizontal stop", | |
| "50c5725a6addc0c0": "Port B15 input enable", | |
| "50ce94af19a4a9a1": "Voltage reference", | |
| "5132945424f5a284": "FDCAN and USB SRAM power-down", | |
| "5134f2f67dc89232": "CAN3, DFSDM1, and PLL output divider", | |
| "515dd7c5a0e3e14b": "Extended interrupt and event masking", | |
| "51622888fb4fe490": "Extended control features", | |
| "516abf817271e0ed": "Watchdog and timer freeze", | |
| "5170ebfbbd0eb70e": "Device VBUS discharge and pulse timing", | |
| "517cf8ae7478ec9d": "SDMMC2 access control", | |
| "5184f41b52e882d1": "CAN2 interface", | |
| "51975134151e228a": "Six-channel output compare", | |
| "519905e40e9ecdb8": "Port F3 pull-up", | |
| "519c153c28f4750b": "I2C4 freeze", | |
| "519c448cbf9abe7f": "Secure mode", | |
| "519fde943beca675": "Channel 1 waveform generation", | |
| "51a3e4a5c741cdd4": "Extended GPIO and backup", | |
| "51a9ceabb930bea9": "External wake pin configuration", | |
| "51c4c63e2a3bf767": "Bank 2 write protection ranges", | |
| "51c9f7c244a3da73": "Dual ADC mode", | |
| "51da688b95ae0b13": "Regular conversion and sequencing", | |
| "520fa03c2a9c62a9": "Power supply monitoring", | |
| "52128e9a947f2126": "D3 pending interrupt mask and clear", | |
| "52315ad5fa5ed697": "Proprietary code read-out protection", | |
| "523ba8bc20b87e4c": "Break and dead-time", | |
| "523ee168ab052f97": "SPI3 and I2C3 interfaces", | |
| "52617c74052cebb8": "Extended filter FIFO assignment", | |
| "5263075f3e39e5f9": "Memory remapping", | |
| "527db9ada47afdc7": "LPUART1 global interrupt", | |
| "527f74ddac0196e6": "Wake-up flag register B", | |
| "5282b2f0fba8504c": "Access control", | |
| "529b11459b480e53": "Line 24 software interrupt", | |
| "529d33d51e51ccb0": "Event 16 security configuration", | |
| "52a30caa77663813": "High-range write protection", | |
| "52b21e8c77f40b5a": "Touch Sense Controller", | |
| "52b321aa3a4c5775": "Alternate APB freeze", | |
| "52b90ea57891f6f1": "Extended wakeup pin 20", | |
| "52b9c651337a1c12": "I2C Fast mode plus", | |
| "52c0eb2f86c32285": "Hardware CRC", | |
| "52d69da427d0bfd6": "Break send and flush", | |
| "52fc9353509ecc99": "Extended security bits", | |
| "5300e33184342202": "Commutation and Break events", | |
| "532575dc3d7e4754": "Limited Mode", | |
| "534939a2d43217e8": "Freeze DMA channels", | |
| "5366a551e2105838": "SRAM2 write protection extension", | |
| "5368070259eb0b90": "Extended interrupt trigger and event", | |
| "537da52e47db7e1e": "Watchdog channel selection", | |
| "53af3d67a84116c0": "SMPS and regulator tuning", | |
| "53cd7a41c8f45276": "Timer 4 and 8 freeze", | |
| "53dc14ab37f660be": "PB10-14 standby retention", | |
| "53dee05b77820e9d": "USB OTG SRAM power-down", | |
| "53ffe3cf04912f17": "Error correction key", | |
| "542aeb4cc99531e8": "Power-down key", | |
| "5453b4dbfefd6d0c": "Request source selection", | |
| "545bb2e05121b543": "Write Protection Pages 17-31", | |
| "545d3e3c74256e46": "Break 2 BKIN2 input", | |
| "54689c4f852db8bb": "Injected conversion trigger selection", | |
| "546b24021ac51822": "Privilege and security register 2", | |
| "5488b37364232cc9": "Complementary Output Channel 2", | |
| "54a5137ace79d8b8": "Voltage detector and monitoring", | |
| "54b1ff8f65bc6d7a": "Device identification and freeze", | |
| "54b88ce5d67d6516": "Port A-B pull resistors", | |
| "54c1daae20ea89dd": "No-erase on tamper", | |
| "54ee2217fec957ea": "Line 21 edge trigger", | |
| "550510aa9bb148be": "Secure flash operations", | |
| "550f894313784595": "Master key and cipher mode", | |
| "5523b4aeb1e5a8bd": "OTGHS access control", | |
| "55300202464c7f8b": "CAN1 and ADC2 interfaces", | |
| "5530f02aeea8ccad": "Port H pull-up and pull-down", | |
| "5531bd4a2f075ddc": "GPIO Port D with communication interfaces", | |
| "553cc14febae7067": "PA0 standby retention", | |
| "55509bd47a677d3d": "External trigger remap", | |
| "557d5ba465d4b54f": "Injected conversion trigger selection", | |
| "55876a8534676e7a": "Bidirectional Break", | |
| "5587a718cd6abf72": "Port G pull-down and IO2 supply", | |
| "5587edd21b58b56a": "Segmented display", | |
| "55a1980ff8d6bfca": "UART 4 clock source selection", | |
| "55a6bd2d4c745182": "Line 18 event masking", | |
| "55a833aca0304337": "Seconds and alarm events", | |
| "55ac9571f9be0ea9": "Port F5-F8 and F11-F13 pull-down", | |
| "55af6e3b5e3dcaca": "AHB peripheral clock control", | |
| "55f347628091514d": "Lines 28, 30 event mask", | |
| "55ff61de4abc292b": "GPIO pin multiplexer", | |
| "561e4627df620762": "Dual bank configuration", | |
| "563adcb24aa554b2": "Prescaler and frequency control", | |
| "5642c557523981c7": "Timer 1", | |
| "565384ef4af1e076": "SDRAM device initialization and status", | |
| "565448066fae2a09": "Programmable voltage detector control", | |
| "565e9b23bb04b1a2": "SRAM4 security", | |
| "567ff5c706e0e4fb": "I2C3 Fast Mode Plus", | |
| "568cc9b59599baf1": "Voltage regulator", | |
| "56a0db2a214f791a": "D3 pending clear selection", | |
| "56bdd32439ae8822": "Control register variant 3", | |
| "56c095fe447d0faa": "Peripheral identification and GPDMA2", | |
| "56cab91854f19059": "Alternate output routing", | |
| "56d7333ace21979d": "TIM6 and CAN1 freeze", | |
| "57242e5a90b98d49": "Extended output color formats", | |
| "573704002691f60e": "USB OTG physical layer", | |
| "574d6afa8e36fee8": "Active tamper input", | |
| "57759406fbc5f864": "SRAM3 Single Error Address", | |
| "579b6ad4882d0204": "Port B pin 7 pull configuration", | |
| "57b2a91933915753": "I2C3 halt", | |
| "57dcad2726d9be53": "Synchronization for channels 0-2", | |
| "5800aa5cae3e235c": "Individual wakeup line control", | |
| "58268a06cf563c9d": "Line 46 interrupt and event mask", | |
| "5832e8ebf56a95c4": "Channels 6-7 interrupts", | |
| "5876d838db6c79d9": "DMA with variant support", | |
| "58cc0c8f55567e5d": "Lines 29-30 trigger configuration", | |
| "58f73b0bfcf7be4a": "Channel 7 interrupt flags", | |
| "5906302b1be5b8cf": "Low-power and analog device protection", | |
| "5906375eafb99114": "Memory Remap Configuration", | |
| "5907934f389cc835": "Bank 2 write protection configuration", | |
| "591d65a0929a6434": "Voltage scaling", | |
| "591d7e13cbd5a982": "Interrupt and event mask all", | |
| "592b85cf59bd4fc8": "Extended system configuration", | |
| "5954d221a2194b37": "Counter and auto-reload", | |
| "595e33e0628b82ce": "SRAM Parity Error Lock", | |
| "5979b41c52653127": "Channels 3-4", | |
| "597af561f085d619": "Processor core and memory configuration", | |
| "597f10510a673b19": "Lines 19-20 security and privilege", | |
| "5980065e5a93b761": "SRAM1 page 12 power-down", | |
| "5983526c7750571f": "System break", | |
| "5989fc615ae51ddd": "Memory card interface", | |
| "599ea56a1eb44269": "Complementary outputs channels 2-3", | |
| "59b9b6734330afc6": "Lines 28-30 interrupt masking", | |
| "59cd0c2e5f526176": "SRAM5 error correction support", | |
| "59d1268e0990727a": "Non-secure flash operation control", | |
| "59d92c53609b449d": "Line 20 pending interrupt flags", | |
| "59e802ae0340d412": "High frequency mode", | |
| "5a21ec993900e4c7": "Complementary Output", | |
| "5a2eb6f5fcaeeab3": "Extended privilege configuration and memory watermarks", | |
| "5a40f49ee7e1104e": "Master clock generation", | |
| "5a41ab5fd95f0846": "I2C5 and I2C6 access control", | |
| "5a46e39ab425e0cb": "USART4 interrupt", | |
| "5a519295b9a00398": "LCD controller", | |
| "5a81a46d810c05c9": "Master mode selection", | |
| "5a9dac4b3e2c862f": "Parity protection", | |
| "5ac7127050ee1404": "High-resolution timer 1", | |
| "5ac826c2006f53c3": "Dual-edge interrupt detection", | |
| "5acf8b62ec886dc6": "General-purpose Timer 5", | |
| "5ad4f096834ab085": "Channel 2-3 configuration", | |
| "5ad7a4404b108d86": "Security attributes", | |
| "5b3ed363793f6793": "DMA and peripheral halt", | |
| "5b64cd0f214b48aa": "Channel privilege configuration", | |
| "5b6a88aaa0dc4ca4": "Port F-G pull resistors and PVM 2", | |
| "5bda0bd009241a82": "Synchronization interrupt and event", | |
| "5bdfb79edfd8d300": "DES cipher modes", | |
| "5bf52181ac276453": "Dual comparator support", | |
| "5c021becd23c4668": "Line 18 trigger configuration", | |
| "5c36015cf896542b": "Bank 1 page protection", | |
| "5c4b466de1f944f4": "Repetition counter", | |
| "5c4c98e033c52f0d": "DMA control", | |
| "5c55b9e319ed27de": "Timer 7, 8 and dual ADC", | |
| "5c5e12a4fedb7115": "Power status register 2", | |
| "5c629946e331a759": "Range 1 normal mode", | |
| "5c96a3f6a7497993": "Watchdog and timer freeze", | |
| "5caa4d82c8a46143": "Calibration and voltage regulation", | |
| "5cceedb1a0fa7cf1": "PDM interface", | |
| "5ce4d0f75d00b3eb": "Write protection", | |
| "5cf972a4eab58699": "SRAM1 page 1 power-down", | |
| "5cfe0339acae174a": "Dual-bank mode", | |
| "5d047dc4a03f69f6": "Shutdown wakeup and SMPS", | |
| "5d0ace269e7e064f": "Dead-time and repetition control", | |
| "5d158407cbfb4197": "Input 8 detection and control", | |
| "5d1acba170d48f56": "Output compare mode extension", | |
| "5d2553580ec68917": "Channel 2-3 input delay", | |
| "5d2f2fa980a15bb6": "Tamper and ECC interrupt status", | |
| "5d3afc30499bc75a": "Line 21 pending interrupt flags", | |
| "5d3c481037911380": "Line 20 falling pending interrupt", | |
| "5d3da5e04d79bf62": "General purpose timers 12-14", | |
| "5d41246e980a9247": "Port B and C GPIO pull control", | |
| "5d8a6679a1b63c9a": "Extended security attributes", | |
| "5d8fb45906b91799": "Dual-core boot addresses", | |
| "5da42a4e63804399": "Trigger input selection", | |
| "5da9a500ea28ef85": "Memory remap and interrupt status", | |
| "5db460bb4b9fc705": "HSI48 oscillator smooth trimming", | |
| "5e5bec44f12d084b": "Extended domain pending control", | |
| "5e5cebba12cf1dbc": "I2C1 and PB7 Fast-mode Plus", | |
| "5e735e33e2d4a5e0": "Sleep mode freeze", | |
| "5e856b2dbca4601e": "GPIO and SRAM power", | |
| "5ea1a52bbd6d5665": "Dual mode status flags", | |
| "5ea52f7ef2991cdb": "Cryptographic accelerators", | |
| "5eb74145272c6abd": "Basic bitrate prescaler", | |
| "5ecf0644180a6df4": "Alarm A sub-second mask", | |
| "5ed30c98ce7d9784": "Trace clock enable", | |
| "5edeebbe8986ed22": "Basic transmit receive interrupts", | |
| "5ef57143ab60f354": "Clock source selection", | |
| "5ef90355b56f2dff": "Input line 32", | |
| "5f09cb3d99db8852": "High-speed parallel interface and memory", | |
| "5f0c8d85e05e0cfd": "GPIO clamping diode enable", | |
| "5f2f9ba6ac7b1d53": "Positive input selection", | |
| "5f3566380f8a9656": "VBAT input", | |
| "5f45af2725088a4c": "HSEM, timer, and LSI2 control", | |
| "5f609859b7e57405": "Multi-UART and audio support", | |
| "5f6a0eca1c52d2e6": "Low-power peripheral freeze", | |
| "5f77b5ca2c321de2": "Line 0 security and privilege", | |
| "5f95794cfe12cc37": "Port D pins 6-9 pull configuration", | |
| "5fe19196fe995f87": "Advanced break control", | |
| "6004c30f46f26d44": "Write protection mode selection", | |
| "6027e6ecae2a235e": "Page number selection", | |
| "605c596a77d3c9dd": "CEC interface", | |
| "606382c2c65661b2": "DMA remap", | |
| "607666136e829453": "Common configuration", | |
| "60827fbd0f4d2af6": "Dual injected queue", | |
| "609450e3156c58b9": "Extended GPIO and 2D DMA", | |
| "60a27b9c1fc54d42": "Extended interrupt and event masks", | |
| "60a3cfd6ad169779": "Maximum Transfer Size", | |
| "60b02fc599148e15": "Dual mode status and data", | |
| "60b2b66a33112f7c": "Sector selection", | |
| "60d36a7c77cbcb24": "Channel 2 with Trigger", | |
| "60ef0cda47d1e3c2": "FM+ I2C SDA", | |
| "60fa6b41b22bafc6": "Master/slave synchronization", | |
| "61309f55bc9fecc6": "Parity error protection", | |
| "6131c5ee8f53a983": "Channels 6-7 selection", | |
| "6159e144450bf833": "Privilege block-based protection", | |
| "618c35a5e893a7af": "D3 domain line 25 pending mask", | |
| "619530ebf74f8c57": "External Trigger Filtering", | |
| "61968be2cb2f1943": "Cipher context configuration", | |
| "61c8b8a9c0276c44": "M4 DMA and audio support", | |
| "61d949d078a90495": "Lines 24-25 access control", | |
| "62086012f61a366e": "Latency and ECC detection", | |
| "621e4c2061062c59": "Flash page number", | |
| "6229ca01e0f14bcc": "Memory privilege control", | |
| "622f3dcc9e594f7c": "USB power management", | |
| "623a7e00224d6a18": "Security and lock configuration", | |
| "6244617082f33006": "Option Control Bits", | |
| "62599f24952e0f7b": "Line 49 trigger configuration", | |
| "625ffa3eec7c98a7": "Antenna switching and debug", | |
| "62733c85a2aef1a4": "Input line 18", | |
| "62790d555c5fe245": "Line 25 interrupt masking", | |
| "627bc5c9c4cbf6b5": "Digital audio and I2C", | |
| "627ca697cac13af2": "Core lockup and memory swap", | |
| "6283a68114b15a51": "I3C Serial Interface", | |
| "62bf25b895a26661": "Protocol Configuration and Interrupts", | |
| "62c2b54adf3d7ea0": "AES and SAES encryption", | |
| "62c510e48fb136b9": "Monitor 1 failing data", | |
| "62c8984bcaa72b72": "Display serial interface", | |
| "62d06c79f080d5d8": "Port F pull control", | |
| "62e4901affd36b01": "Single Error Correction", | |
| "62f100d1f0092b3a": "VBUS session detection", | |
| "62f18880a4e5fb73": "I2C 4 and SPI 4 control", | |
| "62f38697b3c0f7ba": "TIM10/11 freeze", | |
| "62fc49267ab5e66e": "Commutation and Complementary", | |
| "631cdc46b131f72d": "Tamper 3 interrupts", | |
| "632a3c88f2ce1e81": "Power domain control", | |
| "63301b9dabed3d4f": "Line 16 interrupt control", | |
| "6343f5e9c72bdcf7": "Lines 60, 62-63 interrupt and event mask", | |
| "63475b412fa32712": "Dual mode and VBAT", | |
| "634d01a885b98fa4": "Timer 4, I2C2, I2C4 freeze", | |
| "637225ddecaa142d": "Extended DMA channel halt", | |
| "638d4442f9aa0387": "Interrupt mask control", | |
| "63a3de2acaac2e76": "Memory bank control", | |
| "63a90d4c9cbb9564": "Debug freeze", | |
| "63b1782271322a05": "Secure mode control", | |
| "63b4278953dc421a": "Health test configuration", | |
| "63b8b22b473e9b46": "Timers 9 and 11 stop in debug", | |
| "63be7446ee66eece": "SDRAM bank 1 timing", | |
| "63f1e88e0cc3f787": "Chaining Mode with RNG", | |
| "63f20d205071a813": "Shutdown wake and SMPS trim", | |
| "63f46c7933335ff2": "Core operation control", | |
| "640a3401810f34e8": "Option byte and prefetch", | |
| "641283217b28e9c9": "Line 40 trigger control", | |
| "6421a51b223e89e1": "Calibration output", | |
| "644114216f0b0c5b": "Pin I/O mode", | |
| "6443b9c66adb277d": "Wakeup pin 5 enable and configuration", | |
| "644bf4871e0e3811": "Wake-up pin 6", | |
| "645bd0ffc0c7ad38": "FDCAN2 interrupts", | |
| "6479b8d08805ae4b": "Comparator 1 and DAC interrupts", | |
| "648f8c317bbe90ec": "Linked list DMA with buffer base", | |
| "649327418c19cfd7": "Trigger edge detection", | |
| "64b832f91751bd4b": "Repetition counter", | |
| "64b9cfdcc16b74b3": "Reset and option byte control", | |
| "64bebd37d58e5711": "SMBus and timeout support", | |
| "64cb67dfefa6b646": "Overdrive control", | |
| "6530ea7bc656004f": "SRAM3 page 3 power-down", | |
| "6534cb8871eaeffe": "Regulator selection", | |
| "65550afd825bd9d8": "Global interrupt mask", | |
| "656e7a51d2008174": "Hash processor", | |
| "6575500c35569ee1": "Extended memory and peripheral configuration", | |
| "658fb1b04cc7c7e3": "AES crypto accelerator", | |
| "65978ac3f018d862": "ETR source selection", | |
| "65b6f65bdbf65580": "Line 46 trigger configuration", | |
| "65db83c9632c8944": "Timer 3 freeze", | |
| "65e0edfc0de81e0c": "Random number generator", | |
| "65e463daa72264ff": "Pending request registers", | |
| "65e79c94c55871d2": "Interrupt pending flags", | |
| "65e9a26e335d237b": "Timer Input 1 Remap", | |
| "661a69a427d55fa2": "Channels 3 and 4 capture/compare", | |
| "6625e99e557e5a7c": "UCPD standby control", | |
| "6637d496b29bcdf0": "Trigger input routing", | |
| "6667e7a41e177d91": "Line 34 event mask", | |
| "668723f07b54de4e": "External trigger source selection", | |
| "6693081071073dae": "Line 16 trigger configuration", | |
| "66998b19e407d784": "Capture/Compare channel 1", | |
| "66b87169c6a06ed4": "Extended wakeup lines", | |
| "66bb60f72e638029": "Cipher Decryption Engine", | |
| "66c0f5df74c29811": "AES encryption with SPI and UART", | |
| "66fc9b3a433758de": "USART DMA remapping", | |
| "6704d08418da0f20": "Voltage detection and monitoring", | |
| "6709ef2fc0bd7517": "Line 36 edge trigger", | |
| "671c167417fad3d9": "Input capture 4 remap", | |
| "672f06cae6047f78": "Secure state and interrupt status", | |
| "675caad2bc5e85fe": "TIM2 Interrupt", | |
| "6760042de64a0a12": "Internal wakeup features", | |
| "676c2b2c7de41248": "Timer and interface control", | |
| "6798bb15536e270d": "Port selection", | |
| "67a35c61c6b69baf": "Lines 10-11 interrupt configuration", | |
| "67afaadc348015a1": "Battery charger detection modes", | |
| "67c97470897600da": "Analog switch control", | |
| "67d4228a002afb00": "Linked list DMA", | |
| "67e0c5ffd56a4a64": "Write and read protection ranges", | |
| "67e788b3b88eb597": "External trigger filtering", | |
| "67f63fc86838ff64": "Port A pin 4 pull configuration", | |
| "683c59bac4975d97": "LIN, IrDA, and SmartCard modes", | |
| "6844a8514f00b4f5": "Channel selection register", | |
| "6853d000f01c1b41": "Watchdog and detector monitoring", | |
| "6869668b325183a9": "Graphics accelerator and cache", | |
| "68792a5c672d85b1": "Lines 51, 77 trigger and mask", | |
| "689b4329d5db868a": "Port A and B GPIO pulls", | |
| "68a7847eb65aca24": "Auto reset disable", | |
| "68ba69cea646223f": "Line 35 interrupt", | |
| "68bc1e9d8d4da104": "Health test system", | |
| "68bf38dd7315160c": "Chroma subsampling", | |
| "68e61174204b6c94": "Reverse Type Control", | |
| "68e743fc4637a46a": "Parallel bank mode", | |
| "68ec0d67791873f7": "Wakeup pin polarity and pull", | |
| "68fdb58b2ce4a862": "Address cache control", | |
| "691d1f75c3017cd6": "General-purpose timer 19", | |
| "692852db60310692": "Layer 1 window vertical start", | |
| "692a2a7f0774c3a2": "Port F4 pull-down", | |
| "69386a4bd9bf1c49": "Port A external wakeup", | |
| "69441d56e2d41842": "SRAM3 power-down in Run", | |
| "6954ee0c5dc83628": "SRAM6 power-down control", | |
| "6a197dd3e4bed64c": "SDRAM bank 0 timing", | |
| "6a445e63cae6a23b": "Port B external wakeup", | |
| "6a592fd91452886e": "Input capture 1 remap", | |
| "6a60fd41915fafc6": "LCD, Port D, and SPI2", | |
| "6a69ebde00a305c6": "Extended dual control", | |
| "6a706d919342532d": "Refresh Configuration", | |
| "6a83da1cbee857c5": "Automatic baud rate detection", | |
| "6a9f156c00afeb95": "AES post-processing and diagnostics", | |
| "6aa2be42d0f6f413": "Extended edge trigger and software interrupt", | |
| "6ab9c9ae2366f655": "Serial communication and timers", | |
| "6abe07706a336870": "Line 41 event mask", | |
| "6acaff4d761b0548": "Dual channel output data", | |
| "6ad96d8a8783bfb9": "Synchronization for channels 3-4", | |
| "6addb2bd61e84ee3": "SRAM2 and I2C Fast Mode Plus", | |
| "6ae66c5778169ac4": "External PA bypass and Flash abort", | |
| "6b003a7e73a679bd": "32-bit dual data", | |
| "6b0c509c717d8822": "Close and exit HDP extension", | |
| "6b1c598b2409ad47": "Interrupt line 7 status", | |
| "6b24adb322eb64dd": "Multimode status and DMA", | |
| "6b25ab05c3d32028": "Line 32 event mask", | |
| "6b50eb4d56b59d4e": "Low-speed oscillator configuration", | |
| "6b515dbd016a7564": "Ethernet access control", | |
| "6b57862d4800cf54": "Alarm B", | |
| "6b9a5f78df0c0e4f": "Hide protection extension", | |
| "6b9d680ec7d3ae40": "Counter and Reload", | |
| "6bd864b2d60ea8a8": "Write protection pages 64-95", | |
| "6be5995fe16cae07": "Core ID for semaphore access extended", | |
| "6bed367817c16cde": "SRAM5 ECC and Protection", | |
| "6beec3eb89d610e9": "Complementary output 3", | |
| "6c261ac8b1ccf87a": "Backup memory with extended wake-up", | |
| "6c8a01dc59311f2d": "Write protection regions 4-5", | |
| "6c91149270978a98": "OCREF clear input selection", | |
| "6c920044f06cb117": "CEC and USB Power Delivery", | |
| "6c98c4c113d5516d": "Secure boot reset vector", | |
| "6cabd5444e29f1e9": "PA0 Interrupt Status and Clear", | |
| "6cb2bdaa2cb42d54": "External tamper 3", | |
| "6cb619a9fc373aac": "Break COMP2 input", | |
| "6cb6a80dc28abbdb": "Privilege and backup domain control", | |
| "6cc71f3899f92007": "Comparator 2 break source", | |
| "6d0e0eb0dca8d266": "Line 34 trigger configuration", | |
| "6d0fbf96776aff20": "Line 23 interrupt masking", | |
| "6d15848a5921844f": "I2C Fast-mode Plus driving", | |
| "6d24fbb9103e6723": "General-purpose timer routing", | |
| "6d5b3caacdb7b509": "Security and trustzone configuration", | |
| "6d7e0beac17d56df": "D3 pending mask register", | |
| "6d81e4e4710711ae": "Semaphore security and privilege bits", | |
| "6d9397a3ed39b752": "AES and random number generator", | |
| "6ddda6fd9ab463ac": "Extended wakeup modes", | |
| "6df84b912d5f1e31": "OEM keys and HDP protection", | |
| "6df9484923ccc279": "Quad SPI interface", | |
| "6e0526b1f3fb69eb": "High-speed low-voltage mode", | |
| "6e2b65ca0b9d0a45": "Core control block interrupts", | |
| "6e33cd2e40b2f191": "GPIO Ports F and G", | |
| "6e53358e81e18885": "Analog switch voltage selection", | |
| "6e5c2c4a5f855bca": "Extended I2S audio interface", | |
| "6e6281dc1e3933b7": "Hardware request selection", | |
| "6e8000db0df7aeee": "Graphics timer access control", | |
| "6e9747ece4c196d1": "External trigger control", | |
| "6e9ce5a44088dc86": "Core Peripheral Set", | |
| "6ea06435b84306cf": "End of calibration detection", | |
| "6ea8de645dee850a": "Output 2 remapping", | |
| "6ecba701de6cfdb3": "Line 18 edge trigger", | |
| "6ed3845ae21570e1": "Line 36 trigger configuration", | |
| "6ed97fee9dfde8c2": "Buffer overflow clearing", | |
| "6eef93971acdf4bb": "Peripheral remapping and protection", | |
| "6f3a62cb3721101c": "Timer 5 with SPI 3 and UART 4-5", | |
| "6f48fdcf2dda4030": "Clock gating with I2S and PLLSAI", | |
| "6f54a6bafc7c2393": "Single buffer DMA", | |
| "6f6b1815194c8016": "ADC1 decoupling", | |
| "6f7f4b5085d917a6": "Line 29 interrupt trigger", | |
| "6f91d85339003170": "Core voltage monitoring", | |
| "6f9be49d35401ffc": "Comparator and CAN interrupt status", | |
| "6fa17c601d707268": "Context suspension", | |
| "6faa0f0842ff6606": "Slave mode", | |
| "6fb0735bba27f5e7": "Timer 5", | |
| "6fb28f673b941261": "Input capture 4 remap", | |
| "6fb719fbe411c274": "Port F Pin 3 pull control", | |
| "6fbbccaa1ce56a74": "USB clock selection", | |
| "6fc49c20c8a3fa8c": "Extended high-numbered interrupt lines", | |
| "6fdf117d06feb814": "Command execution", | |
| "700e642b5d6027e7": "I2S audio interface", | |
| "702579bbc4e23ba0": "LIN break detection", | |
| "702e53da54ea13ce": "SAI1 audio routing with PLLI2S", | |
| "70622a971c0c50b1": "Link Power Management", | |
| "706f8ddafaa500c4": "Timer 15", | |
| "708f58362900f38b": "FMC and Timer 5 control", | |
| "7098c5e9e1f50ed9": "D2 domain interrupt masking", | |
| "70a1a4fcaad3ce88": "Ethernet PHY interface selection", | |
| "70b770f7eb7e48f1": "Extended readout protection", | |
| "70b845a0aad6f711": "Multimode status flags", | |
| "70ebc5f1fef40a2d": "Infrared output configuration", | |
| "70f4e8ca3f26e068": "Timer 2", | |
| "710596b922970f23": "Backup SRAM and TSC support", | |
| "71175ec91a46f574": "DMA buffer and IP version", | |
| "71335e672e634a09": "I2S channel and underrun", | |
| "71384420b1385ed8": "Restart marker configuration", | |
| "71499d599e879f8e": "Extended external interrupt control", | |
| "7155d33ee9a5d032": "SRAM2 page 1 standby retention", | |
| "7167b0d2fe2d8386": "Line 19 trigger and pending", | |
| "71725627ecb5d4ba": "Secure AES protection", | |
| "7173d48014d4bce2": "Alternate interrupt mask", | |
| "717b104923b78b1a": "Alarm B sub-second", | |
| "7180f69d7495747d": "Ethernet MAC", | |
| "718fac87928ee06d": "Capture/Compare channel 2", | |
| "718ffbf3612d770e": "Endpoint Control and Status", | |
| "71943abbe8f67a42": "Separate edge-triggered interrupt status", | |
| "71b5dfcebf595485": "GPDMA2 channel and authentication", | |
| "71c833e554a103ad": "CORDIC coprocessor access control", | |
| "71d2e9fc93671d86": "Line 21 edge selection", | |
| "71d42ca104c82ef6": "Capture/Compare 3 and 4", | |
| "71d524ce892cf65e": "SRAM1 page 3 power-down", | |
| "71e98cd12996d9cd": "Subsecond counter", | |
| "71f146302df06b52": "Extended power and pull configuration", | |
| "72372300bbf0e19d": "ETR source selection", | |
| "723b43c8e20f34f7": "Request identification for channels 5-6", | |
| "7267dcb0a2ba4126": "PKA SRAM control in Stop mode", | |
| "72759b8021091919": "Core trigger and interrupt control", | |
| "7290ce57800eb5f9": "Flash option byte configuration", | |
| "72a0eca0f68b4ed3": "Write Protection Pages 8-31", | |
| "72a19ff8cd3f4803": "SRAM3 and SRAM4 power control", | |
| "72baa005f000094d": "Binary subsecond support", | |
| "72ce2b59f80d210f": "Dual ADC multimode operation", | |
| "72d26e52c70f35b0": "External VBUS valid override", | |
| "72d3686ce4a8a854": "Request source selection", | |
| "72ea8850915af5fb": "Cortex-M55 system configuration", | |
| "72f900a2d2bcb52b": "General-purpose timers 12 and 13", | |
| "72fff5703c4fec58": "External trigger remapping", | |
| "730cba0bb0c79e2d": "Monotonic counter", | |
| "73269bdb440f8373": "Channel 1 buffer control", | |
| "73399d3b56eb28d6": "Cortex-M7 boot address", | |
| "733e65aa13c61caa": "Oversampling configuration", | |
| "7345598e25588388": "MCO and PLL2 ready interrupt", | |
| "7348de28a7850e3f": "FLASH ECC and Tamper", | |
| "734f1718431a0f2d": "Wake-up line 10 polarity", | |
| "7357d8684ddeb06c": "Line 30 edge selection", | |
| "7358ae8823f2a22e": "Multiplexed segment display", | |
| "735dee266eb03752": "Random data output", | |
| "735e4c964a1ce21c": "Window watchdog stop in debug", | |
| "736104fe8241aaf5": "Extended interrupt and trigger", | |
| "73664ad044912d3f": "CPU2 programming interface", | |
| "7368ecc440810705": "D3 pending mask select", | |
| "738e90e0aa3e2688": "Extended lock bits", | |
| "73a3f51fc7d0a35a": "SRAM3 page 5 power-down", | |
| "73a69702bc8c2a39": "Channel 2 capture/compare", | |
| "73aa757905da877e": "Battery Charging Detection", | |
| "73b46f288c0339d5": "Graphics memory and port I/J", | |
| "73bf3694cd01099e": "DAC 2 and 4 control", | |
| "73c3a8f1cd0ee9ca": "Trigger event selection", | |
| "73d5bca97f50604e": "I2C Fast mode and parity lock", | |
| "73d86e438e05ffe6": "Line 22 software interrupt", | |
| "740235a998c69e0e": "Output type and bit set/reset", | |
| "7407952e8e5c8c40": "FIFO Threshold and Delay", | |
| "744c8681f57e4404": "Vddio2 high-speed I/O", | |
| "74548d5f3af1c725": "Extended transfer security", | |
| "747e2a4f5a7d409f": "DFSDM Break 0 input", | |
| "74a687a7fc350c3b": "D1 domain freeze", | |
| "74d0c8517c649a06": "Regular and injected conversions", | |
| "74d38ce171a46366": "Hardware Identification Registers", | |
| "74d67548eb8d0430": "Timer and USART3 DMA remap", | |
| "74daffafed78dd11": "GPIO pin multiplexer", | |
| "74ffe1e2dec5d440": "Basic timers and DAC interface", | |
| "7508546e6dd60eea": "PVD timer break locking", | |
| "7534a9fe219c3a31": "Break 2 Input", | |
| "75441d254d587572": "Wakeup pin 2", | |
| "7548dba917c4101f": "Complete algorithm support with context", | |
| "754e242c80a135d5": "Variant register mapping", | |
| "755fa4381ca6cbb7": "Comparator break input", | |
| "756015b4b86d9e03": "Process ID and lock indication", | |
| "758a720e2f287d0d": "Extended interrupt and event masking", | |
| "75aaec035729e392": "Domain power state control", | |
| "75c53ae6b3a92491": "Write Command Configuration", | |
| "75c6bc133fc2a39f": "PWM with Repetition", | |
| "75d09254541f7334": "Break input and comparator selection", | |
| "75d10024f15aedcf": "PCROP area boundaries", | |
| "75d12fa003bde398": "Index Blanking", | |
| "75ded1087275ce8d": "Option byte programming", | |
| "75e9807c988d821a": "Cryptography accelerator", | |
| "75f3e2ab112aa084": "Common line segment data", | |
| "75ffc78b071a8a65": "USART3 and TIM4 remapping", | |
| "7605d0b4e74d6b42": "TIM15 stop in debug", | |
| "760dbb89fb86c586": "All channels sampling time", | |
| "761a409166a73c74": "Input remapping", | |
| "762317ad6a7ed29b": "Enable and interrupt control", | |
| "764e868289c5b2bf": "Low-dropout regulator and timing", | |
| "767c640c501eda86": "Cache SRAM and core voltage control", | |
| "76982b3fdcd65e9a": "Capture/Compare channel 1", | |
| "76a11073ca03f760": "SPI 2 reset and clock", | |
| "76bd62da27f0cb8a": "Configurable window mode", | |
| "76c26ca12f6663b3": "SRAM2 retention and voltage scaling", | |
| "76e8b2d65967eace": "COMP2 output status", | |
| "76ebee8a33e6dc00": "Dual-core peripheral freeze", | |
| "76ed31f37b2be314": "ECC monitors 0, 2, and 3", | |
| "7709b9e9c84913b9": "Bank 1 page operations", | |
| "771d5267c33c9180": "Lines 10–11 interrupt control", | |
| "77238396bf63c0cd": "Break Comparators 5-7", | |
| "7730d8bd436f575c": "Lines 50 and 53 trigger and pending", | |
| "773babbfa3a33989": "Advanced timer interrupts", | |
| "774d0622e0ce5bdb": "Audio PLL and extended serial clocking", | |
| "77639ef5145d2e86": "Monotonic counter 1", | |
| "77697a842f88b3dd": "ECC failure address", | |
| "776df3233d6d6d08": "LPTIM4 access control", | |
| "7774d8765e75ab82": "NPU stop in debug mode", | |
| "777adb1ac914898c": "Double error detection and write protection", | |
| "7783690bdecddb54": "VBUS power down", | |
| "77927cc1213fb6b0": "Line 22 interrupt control", | |
| "77b7ba8743fc765b": "CPU2 APB freeze", | |
| "77eb6f9f6a13e417": "TIM15 encoder mode", | |
| "7805a17903ebad1e": "Port F14-F15 pull-down and G pull-up", | |
| "7813f8df039ca2f2": "Display controller", | |
| "7820e43ffc34303e": "SMPS bypass mode control", | |
| "78248e2346cc19d8": "Lines 17 and 30 edge triggers", | |
| "783bfcaa452ba9d2": "SDRAM device initialization and timing", | |
| "78448629b24c4a12": "Capture/Compare channels 3 and 4", | |
| "785d6403c9f4f579": "Lines 10-11 trigger configuration", | |
| "786d0068a9271c2e": "RTC and SDMMC2", | |
| "78f6442d847c6eca": "Internal asynchronous interrupt detection", | |
| "7909d02233984227": "Extended memory and audio support", | |
| "79532449a044fc35": "Ethernet domain", | |
| "798f05faf965bcac": "Rising and falling edge triggers", | |
| "79e2cdda16a872dd": "GPIO port E clock", | |
| "79f8837fea6f58af": "Extended EXTI lines 65-74", | |
| "79fa32f3a6d5a22d": "Internal reference voltage", | |
| "7a0d920d2156aaf7": "I2C2 and LPTIM3 freeze", | |
| "7a10197e11c90ed2": "Line 27 interrupt mask", | |
| "7a15cb8522167a71": "PB9 pull-up and pull-down", | |
| "7a1fbdb51fe84a2d": "MCO2 source selection", | |
| "7a3445e002b2e3db": "EXTI port configuration", | |
| "7a3da67cbc5e24b5": "Bank 2 code protection areas", | |
| "7a68591275eaa3f0": "Sleep mode", | |
| "7a977ed800824974": "Peripheral freeze control", | |
| "7a9efdcd879056da": "Channel 1", | |
| "7ac6afbbfc2e0a63": "Conversion result", | |
| "7acee7fb428d960b": "Cortex-M4 LOCKUP output", | |
| "7aea748bedae134d": "Break input disable", | |
| "7b443d5f74d7d0f2": "Channel 7 transfer count", | |
| "7b8ce433e8c4680d": "Enable status", | |
| "7bb8cb0d144fe8fd": "AES encryption data path", | |
| "7bc276b4091cc073": "Low-power modes and wakeup control", | |
| "7bd0aaf00e068deb": "HSI48 oscillator and clock recovery", | |
| "7be9d0fb8b89d579": "Component identity", | |
| "7bf4b924d115274e": "Complementary output control", | |
| "7bf6f4e23edeed32": "PLLSAI R divider", | |
| "7bfc332089f1eb91": "Stop and standby modes", | |
| "7bfc673cdc83878d": "Comprehensive peripheral freeze", | |
| "7c07e0b8433f3526": "I2C fast mode plus configuration", | |
| "7c0b886322aac03c": "Bank 3 NAND and PC Card interface", | |
| "7c2463b32fbaf62e": "GPIO Enable with Power Status", | |
| "7c3873e342d8f6d2": "Peripheral signal remapping", | |
| "7c7e4ddb3bbf1d83": "Event input 16 security and privilege", | |
| "7c818d7f507505d7": "APB1 peripheral stop in debug", | |
| "7c97ee4c1434382e": "Complementary Capture/Compare 3 and 4", | |
| "7ca71760b8c446eb": "LCD and analog peripheral clocks", | |
| "7cae9b36adad1bda": "Power mode", | |
| "7cb15f844c0afba1": "USART6 support", | |
| "7cc144430dcf11c1": "Parity Write Protection", | |
| "7cec32d7dad062d8": "Extended channel sampling time", | |
| "7cf3d164a5981df2": "Port F-G pull resistors", | |
| "7d04f3017ac371c4": "Tamper event detection", | |
| "7d30bdc097ce835e": "Timer 15 freeze", | |
| "7d315ebf3cf179e2": "JPEG codec", | |
| "7d60c7858cfd1349": "FSMC and SDIO", | |
| "7d612b34754baea7": "Line 26 interrupt mask", | |
| "7d6396ae5d8897a5": "Sector write protection", | |
| "7d63f11bc2eb1680": "Auto-reload value", | |
| "7d689a8210be68cd": "Stop 2 PTA retention", | |
| "7d80d8c65e6d309b": "I2C Fast mode plus", | |
| "7d84acf1d389e11d": "Line 19 pending mask", | |
| "7d88bcfef076f8ba": "Voltage reference scale", | |
| "7de4fd9ef9c68a71": "Flash memory configuration", | |
| "7df4e8d54b78cc61": "Output configuration", | |
| "7e083bc363a09637": "DFSDM break inputs", | |
| "7e085059dbb86cae": "Interrupt flag status", | |
| "7e0d0294e2565de7": "Semaphore interrupt control", | |
| "7e46448d720c7136": "Mode of operation", | |
| "7e48f13161f2d8d8": "Mode register", | |
| "7e5735fe29d3f8df": "Extended SRAM2 write protection", | |
| "7e59285d63cc8ba1": "Extended line masking and control", | |
| "7eb925c5dc1bd14f": "Debug clock and peripheral freeze", | |
| "7ec6e7a3bd82b490": "ADC3 access control", | |
| "7ecd6592952e2e60": "DFSDM Break Input", | |
| "7ed3648d9084e6ed": "USART3 and USART4", | |
| "7ee500c5f2273e37": "Extended filter blocks", | |
| "7ee6c8fffb8f2dd9": "Watchdog 2 and 3 configuration", | |
| "7ef7ebd84cfee24e": "Session request and bulk NAK", | |
| "7efe88f5a783899c": "Pulse per second output", | |
| "7f0b1d577feed853": "Symbol Clock and Input Threshold", | |
| "7f1043abb4ae93eb": "Line 17 security configuration", | |
| "7f11a6db3a5a5074": "Complementary outputs 3 and 4", | |
| "7f4626c7ae251d1c": "Device identification", | |
| "7f4f471e0027b012": "Backup domain and supply monitoring", | |
| "7f9cddaf34ac8141": "Line 21 interrupt masking", | |
| "7fad91490b5db463": "Frequency measurement", | |
| "7faf2f8686116915": "Channels 3 and 4 capture/compare", | |
| "7fb84277da82a3ff": "Line 18 pending bit", | |
| "7fd8797dc6f17ce5": "LSI2 and touch sensing", | |
| "7fe55397bff7d895": "Selective GPIO pull resistors", | |
| "7fe5b0a06e77bb1f": "Capture/Compare 5 and 6", | |
| "7fe8dc3f78db1fa0": "Interrupt enable", | |
| "8006ff6eddf62dd1": "High speed analog configuration", | |
| "800bbfddc8f8716f": "Write protection regions 2-3", | |
| "801b7d851542d3a0": "OTP Flash Decoder 2", | |
| "802626df6817292b": "Audio and DMA interrupts", | |
| "8038b5bc8178dc0f": "OUT endpoint status phase and AHB error", | |
| "803cdee56f079db7": "Channel 6 configuration", | |
| "80779ec33fd285e0": "Monotonic counter", | |
| "80932faf36f60cda": "UCPD2 strobe signal", | |
| "80952fb7acf68234": "PLL output divider", | |
| "80a56542c1f2db11": "Host LPM L1 transaction", | |
| "80b06033b95eda70": "Port F pin 1 pull-down", | |
| "80c16ca647970618": "Timer 2 interrupt status", | |
| "80c1ff6c1ae80a17": "Timer and UART interrupt status", | |
| "80cf65ea8bb62302": "Port B pull-down control", | |
| "80d6b86497e9cc73": "Timer 7, 8, 20 and ADC", | |
| "80e769914b7a0a7f": "Cortex-M4 masking", | |
| "80ee55d228d99a9d": "Line 20 security enable", | |
| "80ee6e875b8107bf": "Selective port A and B pull", | |
| "80f1b92504187356": "Secondary flash control", | |
| "80fc0d0ef5a19729": "GPIO edge detection and events", | |
| "810b1061557deaa7": "Port F3 pull-down", | |
| "8116538bbc64fe95": "Flash basic configuration", | |
| "815c565207d614f0": "Range 1 normal mode", | |
| "815fb615355b0ac7": "GPDMA2 channels 8–11 stop", | |
| "81664aed2d4de3fd": "Flash memory fast wakeup", | |
| "816e63e422e0ec8c": "GPIO Port E", | |
| "817957abf4208c5f": "DSI SRAM power-down", | |
| "81a394ac89750a74": "Line 37 pending request", | |
| "81a46d9a5453bfa4": "ID pin change detection", | |
| "81ad9be877220ba7": "Graphics and wireless interfaces", | |
| "81b60ebfadfade7a": "Memory latency", | |
| "81bbcb7ed6ac72e9": "Data hold phase", | |
| "81c2fc7fe2ffbfd3": "Transfer extension flag", | |
| "81da4ca7246d482c": "Automatic bias in Run mode", | |
| "81dd9da29d2a4f00": "Alternate function options", | |
| "81e2a36c32d6eb38": "Request source selection", | |
| "8208a737ec07e1de": "PLLSAI and extended peripherals", | |
| "820cdae5e261f583": "I2C4 with clock selection", | |
| "8215e36d9a9d7307": "INI 7 QoS support", | |
| "821b3cb71a5e4cf4": "Timestamp", | |
| "8231418e93f57bf1": "Synopsys ID and power down", | |
| "82323eef032abff2": "Capture/Compare 3–4", | |
| "824e0fce115dd570": "Line 32 interrupt mask", | |
| "82531a834363f70d": "Input and operating configuration", | |
| "825e39feafddb010": "Programming control and status", | |
| "82880182baa77fea": "M4 ADC support", | |
| "82958a40c001cd5f": "Segment protection", | |
| "82a45e91314b55be": "Freeze TIM15", | |
| "82b5cd2562802c27": "Memory remap and flash swap", | |
| "82fd3ea40046d81e": "Non-secure Flash operations", | |
| "8301c6d01e30d552": "Tamper GPIO configuration", | |
| "8343174922e08ed0": "HSI48 internal oscillator", | |
| "83488f4828a52e99": "Hardware key lock and TAMP5 monitoring", | |
| "83493bcd06141fe8": "TIM1 stop in debug", | |
| "834db87572a0c3a5": "FDCAN bootloader clock", | |
| "836e3ace5f02aa92": "Resource protection group 0", | |
| "838bc7e636ccd6e6": "CPU2 interrupt and event masking", | |
| "83a8426bc2294d69": "RTC and low-power timer", | |
| "83d286f2c43591b3": "Falling pending interrupt flags", | |
| "84048fcbcc66eb68": "HSI48 and wireless interface", | |
| "840874a4e3798c68": "Core system peripherals", | |
| "840a67ddc301a3c5": "Port E pull control", | |
| "840e30d0c4c6b6dd": "Secure interrupt status", | |
| "84364ec1d68dd9c4": "CPU1 low-power modes", | |
| "8438237d49f64f14": "Input remap control", | |
| "8464217b6a4b6766": "OUT status phase received interrupt", | |
| "8464b92c52cd7cc0": "Internal timestamp", | |
| "84792aaec25d4bf4": "Line 27 trigger configuration", | |
| "84812f847c45fbc2": "Tamper 2 interrupts", | |
| "849d9dc8f6997c9e": "Break input", | |
| "84a829be4396a02f": "USB Flash abort interrupt", | |
| "84c32d4aff4919a7": "SPI2, USART6, and fast I2C", | |
| "84c45404fb691fe7": "Cryptographic Accelerators", | |
| "84e23732fd2094f1": "Waveform polarity", | |
| "84e97da1bb298a6f": "Debug authorization registers", | |
| "84ef7bc6b86add1b": "TARG 8 issuing functionality", | |
| "84f12dba5318bd27": "Advanced timer, ADC3, and SDIO interface", | |
| "84f61da005b5b740": "Extended privilege register", | |
| "84fa43352b19a9b5": "Low voltage enable", | |
| "850dcf4dfa9df4aa": "Flash memory low-power control", | |
| "851ed3e38644f946": "External wakeup pins", | |
| "8528ab38a89fd0eb": "Jump HDP level 3 non-secure", | |
| "852d0ec59c79fe67": "Core lockup and PVD locks", | |
| "85557e0280b9b395": "Differential channel configuration", | |
| "85669592829378cc": "Debug Status", | |
| "856be7ce0fd21833": "PA12 Remap", | |
| "85a7bcdb650aaa18": "Flash configuration options", | |
| "85ae4ce45346d403": "Peripheral configuration and protection", | |
| "85b90eaade8382ae": "Channel 2 extended features", | |
| "85ccf3defb458e5c": "PA5-6 standby retention", | |
| "85daee132ed17b53": "Line 27 event masking", | |
| "8606891bded63abd": "Port D extended pull-down control", | |
| "860dd321c3d2d79b": "Break 2 and Update Interrupt", | |
| "8614a89ba08efd92": "Alarm B", | |
| "86247122ab45430a": "SRAM3 parity protection", | |
| "86477f7cbaed5e04": "Tamper 1 interrupts", | |
| "8648d8331dd21641": "Alternate function option 2", | |
| "865f9a95a53a9605": "Extended privilege (high range)", | |
| "866024291b70b629": "ADC1 external trigger input", | |
| "86a0a3b1f908cf3c": "Brown-out reset", | |
| "86ad87a21a9edb37": "Transmit FIFO empty clear", | |
| "86b587ea01a4c2d0": "Option register 1", | |
| "86be286be8e84e24": "I2S configuration", | |
| "86c26f6a6d18dff6": "Channel 19 sampling time", | |
| "86d42e3354215ce0": "Internal tamper 8 input", | |
| "86e06aa2f3df29d9": "I2C Fast Mode Plus pins", | |
| "86e3ddd5aa783ce6": "Transmit FIFO threshold interrupt", | |
| "86eaeac7596e8b00": "Line 28 event mask", | |
| "86f225c1e4bfb8ad": "Extended lock register", | |
| "87613005c0916631": "Strobe error flag clear", | |
| "8765fcf52115fe45": "Calibration factors", | |
| "8766497d52f4d611": "Interrupt pending flags", | |
| "8783d9be16782e4d": "I2C3 SMBUS timeout freeze", | |
| "878e11ce9d147495": "Line 22 interrupt configuration", | |
| "879754190a6164ed": "Line 23 software interrupt and pending", | |
| "87e19a0867a74cde": "Tamper 6 with active tamper seed", | |
| "87ed5b2677ff402d": "ADC prescaler", | |
| "87f422af49e91c4c": "Low-power and reset options", | |
| "87fba4e1f6072ecb": "Channel 2 enable", | |
| "8800522d41c03fea": "Voltage booster and error lock", | |
| "880cfe5ea3679bbe": "Port D pull-down", | |
| "881c17d4c8d5a742": "Ethernet external PHY control", | |
| "8826b467748bcc02": "D3 stop freeze", | |
| "882b76d52f5b7ef3": "Extended options", | |
| "883fcad032e4db11": "Random number and audio converter", | |
| "8844e9f2a7cbcde6": "Line 35 edge trigger", | |
| "8848f8635180bbd9": "Time stamp", | |
| "886a9ae2ffb4a721": "USB interface", | |
| "88730b0161ab58a0": "Line 18 privilege enable", | |
| "887ed31684bf566f": "SMPS and internal wake-up", | |
| "888b83db89a6265d": "CPU2 wake pin control", | |
| "88a8aad38e7ae08b": "Voltage monitoring and SMPS", | |
| "88b62d96d90b2666": "Port D pull-down configuration", | |
| "88ba0ace909e166f": "M4 timer support", | |
| "88cf7fc7b72a8dd2": "Regulator selection and status", | |
| "88e36c8fc9c6e185": "Timestamp on tamper", | |
| "88e9d43c9d2b610d": "CPU2 event and interrupt masking", | |
| "88ed1bf954f974dd": "Power domain security and GPIO retention", | |
| "88fdcda9334c327e": "SRAM4 stop mode power-down", | |
| "891c2cad12c4f95f": "Injected queue and calibration", | |
| "892149779b6ee211": "Extended endpoint control", | |
| "893841d82e729848": "Master mode selection", | |
| "897b94b10c70b419": "802.15.4 Wakeup and Activity", | |
| "89982890a3a97005": "Extended retention and bias control", | |
| "89e05165bc94165c": "HSI oscillator calibration", | |
| "89e4a824243cd6a6": "Trigger and Stall Control", | |
| "89f87080b29a5d22": "I2C2 and VBAT monitoring", | |
| "8a0d915448ddb6c7": "Line 21 interrupt control", | |
| "8a1d6d0924bf4c80": "External wakeup pin 6", | |
| "8a23f671c2692504": "Repetition counter and filter", | |
| "8a2514fbef284482": "Analog-to-digital converter", | |
| "8a2fc0452a17a00a": "Wake-up pin 5", | |
| "8a397d9031a067f2": "Line 22 trigger and pending", | |
| "8a56e6aed9876432": "USART7 and USART8 support", | |
| "8a7a72cbe4e1ee34": "Oversampling", | |
| "8a85c736859134d9": "Output compare clear", | |
| "8a88d2c7b3c260e0": "OctoSPI memory protection", | |
| "8a8b1f07d3df8830": "D3 pending clear register", | |
| "8a90bbce632b400b": "Chip Select Timing", | |
| "8a9207ed510f4a13": "Transmit data flush request", | |
| "8a9ca842ece66617": "RS-485 driver enable", | |
| "8aa1c0e713deda0c": "SPI5 interface", | |
| "8aa2fd640ec0470f": "Remap selection bits", | |
| "8aa974e7a233f6e8": "Low-power timer stop in debug", | |
| "8aaf1e78e57e70b7": "Peripheral debug freeze", | |
| "8abb7d3e319d6b85": "Trigger event selection", | |
| "8ac00981fe485cbe": "Secure and protection area boundaries", | |
| "8ac3409320018c4f": "Offset compensation", | |
| "8ac7e96bb646e3af": "Voltage scaling", | |
| "8acff79898e50856": "Transmit interrupt enable", | |
| "8ad310ca8ffcaa1f": "External interrupt wakeup line 4", | |
| "8aebe0af942524f1": "Input capture 4 remap", | |
| "8aeec5b45a88749e": "PVD Break Input Lock", | |
| "8b17e13cb8a27ed4": "Alternate channel configuration mode", | |
| "8b30cf299d2e48a9": "Fast Mode Plus", | |
| "8b3b0b69e5044151": "Active tamper generation", | |
| "8b3fd0eab19e547b": "Write protection pages 17-31", | |
| "8b6235e02b5787e5": "PVD lock", | |
| "8b66a5aed116d59c": "Extended event masking", | |
| "8b719aa34640d5f6": "Write protection page range", | |
| "8b767b05a48c0184": "Audio playback interface", | |
| "8b804a5e03518865": "Cryptography and hash engine", | |
| "8b80a75932cda4ca": "DFSDM configuration and locks", | |
| "8b9f9ce3e7a6f106": "Wake-up flags 10 through 15", | |
| "8ba539e2fc24c02a": "Line 33 trigger and pending", | |
| "8bac2c45bb094161": "Internal reference and temperature", | |
| "8bc5b50a8325c3fa": "Overdrive and underdrive modes", | |
| "8bd24a8461ab32a2": "Line 28 interrupt masking", | |
| "8bd53bbc9a7618a1": "Sleep modes with external wake-up", | |
| "8be163ed3416dee0": "SRAM2A Page 8 Write Protection", | |
| "8c1e4fdfe31108c5": "Break Control and Trigger Extension", | |
| "8c23bb66f53a2eb1": "RTC and external interrupts", | |
| "8c26c1b9aee2d770": "Interrupt and error control", | |
| "8c43aec7b9eb2847": "Channels 8–11 secure state", | |
| "8c609db650c9dd99": "Single error detection", | |
| "8c6d70b5a8ea9ef3": "Version identification", | |
| "8c7d1dd5e1f1b3a0": "Channel 6 configuration and addressing", | |
| "8c931ee3c0bc54e5": "Channel 2 DMA underrun interrupt", | |
| "8cc64a8c2fff24f6": "Debug trace I/O connection", | |
| "8cc73dfa1e77106f": "Slave voltage regulator ready", | |
| "8cd8d3bf7c9b1128": "Symmetric cipher algorithm modes", | |
| "8cdbd505710f58bb": "Offset and watchdog thresholds", | |
| "8cf5abb31aee210c": "Trace and peripheral halt", | |
| "8cfca7c8094b6aa7": "SRAM1 SRAM4 stop power-down", | |
| "8d068b0fe445e7f4": "Core system peripherals", | |
| "8d0950481844a301": "Tamper detection and backup protection", | |
| "8d259ba5b1c6c735": "ADC Synchronization", | |
| "8d27438614a6f68c": "Power voltage detection", | |
| "8d2abdf98da00eae": "Battery charger detector", | |
| "8d2c96f63c43348b": "Digital calibration", | |
| "8d34311b455d2768": "Bit Error Interrupts", | |
| "8d948b6b20fcc835": "Extended per-block security", | |
| "8db208591df3002e": "FDCAN and HRTIM freeze", | |
| "8db61b3fce4d1fc4": "ECC result", | |
| "8dc11f61264724c5": "Alarm B", | |
| "8dc1fdec6cb4eb9a": "Synchronous SmartCard mode", | |
| "8de627c1f1ff6656": "Pin alternate function selection", | |
| "8deabf1fd437e47e": "Chip select counter", | |
| "8e12beba1541abce": "MCO prescaler", | |
| "8e15304427022c99": "Trace I/O and clock enable", | |
| "8e1b7d2e4de1f653": "Line 31 interrupt control", | |
| "8e2c4e12bb8915b0": "Internal trigger 1 remap", | |
| "8e425e8687ebd45d": "USART4 and RNG Interrupts", | |
| "8e83c3de238dd4b2": "SWPMI with clock selection", | |
| "8e861f89ef21d5b9": "Extended input selection", | |
| "8e9562a0ec272fd1": "SRAM2A write protection pages", | |
| "8e984972b97780ef": "Lines 21-22 privilege control", | |
| "8e9c6a74ca929127": "Bank 2 mass erase control", | |
| "8ea5056a21f0f6fc": "Tamper 2 input", | |
| "8eee90da7d58a503": "I2C4 Fast Mode Plus and Ethernet", | |
| "8f1c1af9361a859a": "SMPS and debug features", | |
| "8f40c81995bf4907": "USB clock control", | |
| "8f4e28411e81d55a": "Master ADC control", | |
| "8f518fc42e98831f": "Display interface access control", | |
| "8f540c4ea6452eb8": "Internal inputs 1-2 secure detection", | |
| "8f5e8f7ef666c338": "Comparators 5-7 break inputs", | |
| "8f740dc2a398298b": "Timers 12, 13, 14 stop in debug", | |
| "8f7d103d474a422f": "Secure backup register control", | |
| "8f944552f4cad152": "Request source selection", | |
| "8fb84abd7d396410": "Line 19 event masking", | |
| "8fc39f31ca26e8fc": "EXTI11 and SRAM2B write protection", | |
| "8fe0d4f4473da47f": "External input selection", | |
| "8fe85a1afcf63044": "Touch sensing and semaphore", | |
| "90016372097c73bb": "Input minus selection", | |
| "9016484c29770335": "NPU interface QoS and clock control", | |
| "901814d2bb0a181a": "Line 25 event mask", | |
| "90209d052a69ce83": "Memory remap configuration", | |
| "905037f4d29b4d41": "Complete protocol transceiver", | |
| "905390010eb1e99a": "Wake-Up Pin 5 and GPIO", | |
| "905861e5600fd6ff": "Charger detection", | |
| "908a2ceefd959a95": "I3C2 privilege control", | |
| "9090ac164857156a": "Request source selection", | |
| "909e7f362052d31f": "Port G pull-down", | |
| "909fe58535101cdc": "External event synchronization", | |
| "90b4dd40eacde776": "Accessory detection protocol", | |
| "90b5fa9ef891f17b": "Extended input selection", | |
| "90b6ec536bb5c49c": "Break Comparator 8", | |
| "90c10d9ff3f95967": "Domain 2 selective lines", | |
| "90c41ec5739c6740": "VDDIO2 voltage monitor", | |
| "90d682f1e8b0da1d": "Device protection and configuration", | |
| "90dea8542821d59b": "Display and USB host interface", | |
| "90e0a1cccd7f4964": "Master Compare and Calibration", | |
| "90e54e8308167341": "Alarm B ready flag", | |
| "90fcbc37f7c5bc58": "Timer and I2C DMA remapping", | |
| "90fd0f900f5bbce3": "CM55 DC-AI Core Lock", | |
| "9112df906ecf34ea": "Engine priority and control", | |
| "9130b362cdcc1a08": "Timer 6 freeze", | |
| "913399cecc5470b7": "LPTIM1 stop in debug", | |
| "913fd8e769fe843d": "DMA2 and SPI3 interrupts", | |
| "914f1261ed32ba3e": "CPU2 control and status", | |
| "91561e992f270adf": "Line 18 software interrupt", | |
| "9167a696cc67303f": "User data bytes", | |
| "918cf6d4b5578a85": "PVD threshold and LPMU sampling", | |
| "91a2f63f5491bc17": "Low power and wakeup control", | |
| "91deca86abcae568": "Configuration with voltage scaling", | |
| "91df7be7bdc2163c": "Low power deep sleep", | |
| "92152b87068fde4b": "Complementary Output Channels 3-4", | |
| "921d2812c7f29973": "Lines 24–25 trigger control", | |
| "921e9ffd86e5f3da": "Dual-processor line 31 mask", | |
| "922d128856dcdb2b": "Interrupt pending for lines 10-11", | |
| "9266e3e8b6a443f3": "Analog circuit configuration", | |
| "926fd14eec99c285": "Extended Memory Support", | |
| "927e9c291cdbfa5e": "SRAM2 parity lock", | |
| "9281a62c7df4dbeb": "Comprehensive error protection", | |
| "9287d1976630bf6b": "GPIO Pull Configuration", | |
| "92a00826eac23446": "RF and analog interface", | |
| "930d85983db001a8": "Device and I/O features", | |
| "93156f9a00d68441": "HSI kernel and LSE drive", | |
| "931b84d4c89c2851": "Error and operation addresses", | |
| "9322abdea94fcc91": "SDMMC receive delay control", | |
| "9345e48e75bce538": "Device authentication and sleep debug", | |
| "935e1b6b28ecf542": "Boot and I2C Fast Mode Plus", | |
| "9369b3c117369ae8": "Transceiver delay", | |
| "93760fc558a14a54": "SDMMC2 and real-time clock", | |
| "939f6de19ae2cf8d": "Lock violation trap", | |
| "93a20d2e57a91b11": "Linked list DMA", | |
| "93be6b5301f98c76": "High-Resolution Timer 1", | |
| "93c0940afe488978": "Peripheral voltage monitoring 1 output", | |
| "93c9918b0663ca71": "Dual ADC, PKA, and serial", | |
| "93cc198b4b4585bb": "LPTIM1 freeze", | |
| "93d61e9e3f4b31e7": "Read protection levels", | |
| "93d84ae318861790": "ECC monitor 0 with shared data", | |
| "93dbc3310ae8582c": "Boot pin option", | |
| "93dd4fc41eaecfe5": "SMPS bypass mode interrupt", | |
| "93f7d6bebf40ffa3": "Line 23 interrupt mask", | |
| "93fea1e02d8e396f": "Line 31 event masking", | |
| "94008a20cd0f005d": "Extended channels 19-22", | |
| "9408d72a6a981a24": "Request source selection", | |
| "941779fb84a17cb2": "SRAM2 power-down in run mode", | |
| "9419c62aa3fb3fec": "Chip Select Control", | |
| "941c6806ad20d085": "ADC clock control", | |
| "94310e0fb5b97553": "Access performance control", | |
| "9447f6e8500c98c7": "Blanking and scaling", | |
| "946eb38fcef5bca6": "Line 29 trigger edge select", | |
| "94a9f0d3eb959203": "Hardware data protection", | |
| "94aac01b0a48110a": "Sector and multi-bank configuration", | |
| "94b61c237d8b10fa": "NAND command sequencer", | |
| "94c6fdb279d30d50": "Channel endpoint operation", | |
| "94da21c730d87741": "Dual-bank page-based flash protection", | |
| "94eac40d387cf655": "Dual-core CPU2 power control", | |
| "9521a529a4b13cd4": "Oscillator and PLL ready status", | |
| "9573b5240dbcab9f": "Output data ready", | |
| "9575ed4b76d0520f": "Memory 1 watermark configuration", | |
| "95ac390962fc4c79": "Transfer security attributes", | |
| "95ae59d46d3d6376": "I2C4 Fast Mode Plus", | |
| "95ca68019f1fd7bd": "Break2 disarming and re-arming", | |
| "95d00d384f0443ca": "General configuration", | |
| "95d30fdf46450f5c": "Secure interrupt line configuration", | |
| "95de62209db784fc": "Device OTG and endpoint interrupts", | |
| "95ebe5d182eecac7": "Line 31 interrupt masking", | |
| "95ff59cd41bea4cc": "User data option bytes", | |
| "96424dc13c2b495e": "Bank 1 write protection", | |
| "964285c3467b578c": "Secure interrupt status", | |
| "9649a3f0e5fd0b0f": "Debug in stop mode", | |
| "9654467d6e206f2e": "SRAM1 and PKA32 power-down", | |
| "965dcee44ea9bc5a": "Line 49 pending mask", | |
| "9676676daf494783": "ECC error correction", | |
| "967db528de4f1c59": "Timestamp and counter sub-second", | |
| "96a144871e69a9c4": "Line 22 event mask", | |
| "96a149a0459a1bb5": "Channel 3-4 Idle Output State", | |
| "96bb0b1dbeb7da7b": "Bank 2 security register", | |
| "96d6c37fe14f594e": "Privilege and protection", | |
| "96da5079d209a2bd": "Ethernet MAC controller", | |
| "96e6ddaa2bfd7db8": "Core 2 interrupt control extended", | |
| "96fdb635158d5570": "Sector and HDP area configuration", | |
| "970ac86e03cce023": "Voltage-controlled mode", | |
| "970bedf2c559db19": "Channel 7", | |
| "973b6a0321c18f72": "Full health test monitoring", | |
| "97490f426097123c": "I2C1 Fast Mode Plus", | |
| "976f1cae98fc1bb1": "RP1A5 resistor trim values", | |
| "978aeaf97b850f0f": "DAC1 and TIM15 clock", | |
| "97c3d5db702c89b1": "Standard interrupt masks", | |
| "97db466ae28fdc56": "Flash ready", | |
| "97e2a1d193791cb2": "Dual-bank Flash", | |
| "980756c54790f849": "Audio Playback and Analog Conversion", | |
| "98342a18ca939f05": "Privilege and lock configuration", | |
| "9869c139b94d8f03": "EXTI with security configuration", | |
| "986caefd563e8594": "USART3 DMA remap", | |
| "98be5f4aabd35854": "Output Compare Clear Source", | |
| "98ce9739c86a8e3c": "I3C1 halt", | |
| "98cf7a3228e51409": "Line 23 security enable", | |
| "98ea53ad61779cad": "SRAM1 Page 7 Power-down", | |
| "9903c454d71c4207": "Alarm sub-second mask", | |
| "990ab49543eb51f4": "Output switching", | |
| "990cb34ae39a99c0": "Pin remapping and interrupt status", | |
| "991587655aa7c5f5": "DMA and I2C interrupt status", | |
| "99181ce204fbd762": "Voltage output buffer", | |
| "991c7bd5c6ea04a2": "Port G GPIO and SRAM1 power-down", | |
| "993b6855729e37f7": "End of Block interrupt", | |
| "9946cd87afcc4b82": "Master mode", | |
| "9960547ce061610d": "GPIO Port E", | |
| "9964c902ec0374c0": "SMPS Bypass Control", | |
| "99686b571f60b7bb": "Resource protection configuration", | |
| "9993ba42fd9c882b": "Line 29 interrupt", | |
| "9996ab3be1e10bbb": "Internal wake-up line", | |
| "99cb1cffaf5f4c0f": "Flash bank mode selection", | |
| "99dba9b97bd75cc7": "LPM support and session override", | |
| "99f466be0a460cb0": "USART3 TIM4 remapping", | |
| "9a00aec78f929c16": "Parity key and address", | |
| "9a18f49970483ef1": "Line 16 event masking", | |
| "9a2fe71db161efa3": "Write protection pages 32-62", | |
| "9a64452672b22d4d": "CAN3, DFSDM1, MDIO", | |
| "9a65e084a0e80c6d": "Hardware flow control", | |
| "9a6975b02f322f00": "Line 37 interrupt mask", | |
| "9a72b3e60e6b56dc": "Dual-core interrupt and event masking", | |
| "9a9b0474a66c5960": "Master-slave ADC mode", | |
| "9ab17ee17c1a2f17": "I2C2 freeze", | |
| "9ac1b9b7ff551ee5": "Extended security and trigger", | |
| "9acbbd7e721c7e75": "Temperature sensor support", | |
| "9ad217c1fc85a64c": "Complete encryption control", | |
| "9b220754b6925a8d": "SAI with encryption and memory", | |
| "9b371af4ed788698": "Line 0 privilege enable", | |
| "9b4ed2b633506f34": "HDP area protection", | |
| "9b50e09b9e24fce8": "Power management and extended sequencer", | |
| "9ba42c70b8411dc0": "PA15 and PB4 pull-down", | |
| "9baf89b57fc24bda": "Extended privilege configuration", | |
| "9bafe6b7f5ee0c66": "Channels 3 and 4", | |
| "9bc557a5b1a89ad9": "Power voltage detector", | |
| "9bdad74d4f47cc99": "Secondary interrupt bank", | |
| "9c37843001e0af66": "Watchdog and Timer 1", | |
| "9c51a827c8107b65": "Secure masked interrupt status", | |
| "9c5daca7e0111555": "Capture/compare channel 6", | |
| "9c724790bd86ed8d": "Single mode start", | |
| "9c7bc1b0b7f92f76": "VDDIO2 supply voltage monitoring", | |
| "9c9d2ef0d1ae06b1": "ECC error locking and I/O compensation", | |
| "9c9ead25f91f0102": "General purpose timers 9-11", | |
| "9ca99b3f8a499822": "Port F4 pull-up", | |
| "9cd86180f55c01fc": "Extended channel 18", | |
| "9cebb176bcf260a9": "Line 19 interrupt configuration", | |
| "9d0c4188a6e6bfab": "Algorithm variant mode", | |
| "9d142d8b78ce3310": "Full control and status", | |
| "9d3c4bf7207755b1": "Low frequency mode", | |
| "9d415ebb0f770dc2": "Channel 1 capture/compare", | |
| "9d48d37e5b763c82": "Wake-up pin 6 control", | |
| "9d503b8350524fa6": "Port configuration bits", | |
| "9d6d98180ef4b3f9": "Port H pull resistors", | |
| "9d7678fde28a66de": "Line 22 edge selection", | |
| "9d8eae4154a96612": "CEC", | |
| "9d900595aa9428b7": "TI frame format", | |
| "9da520484ebc8c7d": "SAI audio interface", | |
| "9da83b7aa4f0c076": "Positive input selection", | |
| "9dcdc841e66f6c1e": "Extended key registers", | |
| "9dd958c30e1e0675": "Wakeup Pin 5", | |
| "9dedf658161f2b43": "Multi-comparator operation", | |
| "9e136dd6e4444375": "Timer with USB support", | |
| "9e3b5638e5a87688": "Interrupt line 8", | |
| "9e497d5fbec19c9a": "Product state and security status", | |
| "9e5b8867f90ceb12": "SRAM3 retention in Stop mode", | |
| "9e6a910d535371af": "Gain compensation mode", | |
| "9e6fe47f33d9a5fa": "Temperature sensor enable", | |
| "9e80049a474c9d78": "Low-power mode debugging", | |
| "9e8fe541ddff9fde": "D2 domain freeze", | |
| "9e8fe5f21c5cadd1": "I2S mode", | |
| "9eb07f6c59f6b3e7": "Brownout reset and SMPS", | |
| "9eb4bae45333c783": "Page selection field", | |
| "9ecf26253c51142a": "GPIO D", | |
| "9ee0ffb846b149ba": "Dual-channel positive input selection", | |
| "9ef6db5990c13151": "Voltage scaling and Port H pins", | |
| "9f0ccf563e5b9df0": "SRAM1 page 3 power-down in Stop", | |
| "9f1051991bf8c73f": "Line 34 pending mask", | |
| "9f311287aead30c2": "Injected conversion trigger selection", | |
| "9f60e6c68e16f81b": "NAK interrupt masking", | |
| "9f610f82fea8a80e": "Standby wakeup enable", | |
| "9f6766e83970267f": "GPIO pin multiplexer", | |
| "9f7743e00a75dc15": "SRAM2 write protection pages 20-31", | |
| "9f8ffe14951132c5": "Port A wakeup and pull-up/down", | |
| "9f93bd0668db5eb1": "Debug and status monitoring", | |
| "9fbd51fe7cc07adf": "Capture/compare channels 3 and 4", | |
| "9fc30ce3b499c772": "SPI4 interface", | |
| "9fc4d66035f28db9": "Data FIFO", | |
| "9fd05f200e485946": "Autonomous mode triggering", | |
| "9fe0bf00e421328e": "Debug credentials reset type", | |
| "9febae11e1d586da": "Timer 19 freeze", | |
| "a00edd3a38c3685a": "I/O compensation cell", | |
| "a01f6afa678f0cb2": "Chroma subsampling", | |
| "a034a1aa55ac6465": "Capture/Compare 2", | |
| "a03f50fe6b83d6ba": "Port H0-H1 pull-up and pull-down", | |
| "a04c7ed883b01cee": "Multi-timer halt control", | |
| "a08ade40a37534f2": "Buffer descriptor and error tracking", | |
| "a08f9eaaa90dffe9": "Synchronization overrun status for channels 7-11", | |
| "a096378de0a3bc0a": "USB supply valid", | |
| "a0cd0aabf68e61dd": "ECC lock", | |
| "a0d502a22690802c": "Outlier and Short Circuit Detection", | |
| "a0da1fc251399fcc": "External interrupt wakeup line 2", | |
| "a0fa2318d6b02c65": "Dead-Time and Break Control", | |
| "a107ec045be2f7e9": "Bank 1 HDP extension", | |
| "a114173beea02fb9": "ECC monitor 2", | |
| "a11ef36020b9cb24": "I2C2 SMBUS timeout freeze", | |
| "a12c5332c007e8cc": "TIM8 and TIM20 timers", | |
| "a140ab0e9f998307": "Repetition counter", | |
| "a1426d0d4a455272": "Line 17 pending bit", | |
| "a14df7d8ad96635a": "Basic operation modes", | |
| "a16c9797f964c616": "VDDADC power monitoring", | |
| "a17becbfee05b787": "VDDIO2 voltage monitoring", | |
| "a1a09540e551aaff": "Capture/Compare Channels 3-4", | |
| "a1add21de5dfca18": "Extended privilege bits", | |
| "a1b53e415cac72df": "SMPS startup current selection", | |
| "a1e9b6544b4f3622": "Line 31 edge selection", | |
| "a1f3e672001d0bd0": "Interrupt routing status", | |
| "a20d43666bcac590": "Timer 3 freeze", | |
| "a238f3423a86fabd": "Memory region remapping", | |
| "a24257b2ad64b1ea": "Break Comparator 3 Polarity", | |
| "a2546652ffdaf164": "ICACHE SRAM power-down in Stop", | |
| "a255bad7c04bd232": "Channel 2 capture/compare", | |
| "a27e2137bc9ff3df": "OTG version", | |
| "a2a35b891ab0110b": "Channel 1 sample and hold", | |
| "a2b7b40ee11aad09": "Over Drive and Under Drive", | |
| "a2cf57ed37639655": "Ultra-low power monitoring", | |
| "a2d823508d4a557a": "Channel 1 calibration", | |
| "a2f192d896ec2a2a": "Low-power timer halt", | |
| "a3289caa6b621547": "USART communication interface", | |
| "a33247388ff6f9f3": "Page privilege protection", | |
| "a33259f3ec592ada": "Capture/Compare 1", | |
| "a33ad1a1098b2a18": "Channel 5 grouping", | |
| "a33e79b5773d70ae": "Peripheral voltage monitoring 3", | |
| "a34051d5910f91d7": "Layer 2 window vertical stop", | |
| "a34127036451cba1": "SRAM2 and I2S audio", | |
| "a35483384f2c703f": "Pin I/O mode", | |
| "a38ae595cd094368": "Boot and USB configuration", | |
| "a38d8fc21638ccad": "USB OTG FS prescaler", | |
| "a3934b057d2145a3": "Timer 13 and 14 access control", | |
| "a3b08cdc795d6c2d": "Capture/Compare channel 2", | |
| "a3dbef4284e60175": "Port F3-F4 pull-up", | |
| "a3ea4aa909747aa1": "Interrupt enable register", | |
| "a3fa2ba955cc2129": "USART1 RX DMA remap", | |
| "a407e691293e5604": "Timer 1 freeze", | |
| "a425bb633b9bc353": "Line 34 event masking", | |
| "a43dcb5a420d6aa1": "Line 38 pending request", | |
| "a458e2cbf5ccdd5a": "Background color palette", | |
| "a46fd0226b46454b": "Oscillator trimming", | |
| "a48e0b89f832c719": "Dual PLL and USB OTG", | |
| "a494f42ea58bc73e": "Debug access port and authentication", | |
| "a4baa5e88cc3f204": "Timers 8, 12, I2C4, HSP1 freeze", | |
| "a4c3db2029e17f37": "Extended debug freeze control", | |
| "a4dd31da44e2e3b0": "Secondary timer and serial", | |
| "a4e20195b5840764": "Line 41 interrupt mask", | |
| "a4ed602dc9fdf3b7": "Output bit set/reset", | |
| "a4f47b3c85ffb3eb": "ECC detection and correction", | |
| "a4fb8f599c915259": "Master ADC status flags", | |
| "a501b6b78b9eb0fb": "TAMP3/4 output selection", | |
| "a511af425d543110": "General-purpose timers 10 and 11", | |
| "a515107449c8f05a": "Dual SRAM Parity Error Tracking", | |
| "a519f9e504b1143b": "Center-Aligned Mode", | |
| "a51d00b08962b7fe": "Voltage common mode", | |
| "a524866d4fa6f262": "UART7 and UART8", | |
| "a52fd6bfc58cdb9e": "Low power analog configuration", | |
| "a533038204d0eba5": "Complementary output 2N idle state", | |
| "a53579e3bf8a3c36": "Comparator enable and output", | |
| "a544c864bffedac2": "Core debug mode", | |
| "a549446019adf401": "Low frequency mode", | |
| "a5566cba8d620b54": "Dual-core M4 processor", | |
| "a55f55232dfa1c80": "Memory configuration", | |
| "a58258c3bcb76fcb": "Programmable noise filters", | |
| "a5c33432db937490": "SRAM1 pages 3-4 power management", | |
| "a5c409e50aaf2ba7": "Channel 8 configuration and addressing", | |
| "a5c9dd1002748812": "Privilege attributes", | |
| "a5df95acaba498ad": "M4 low-power UART support", | |
| "a5e6c92a3ca76281": "V1.8 power domain reset flag", | |
| "a5fec00ea22dc1ad": "Extended APB1 freeze", | |
| "a5ffb5b91723630c": "Alternate function options", | |
| "a617464cd0e75bdf": "Input selection", | |
| "a62400814cd2ddbc": "APB2 peripheral clock control", | |
| "a62d13425e504fa6": "ICODE SRAM write protection", | |
| "a62f92c6a070445c": "AHB reset", | |
| "a634e23762fcad2d": "Line 35 event", | |
| "a635368e1fb0bbe0": "Shutdown wakeup control", | |
| "a651e329113423a5": "Input 7 detection and control", | |
| "a65a2cc7bf4af19f": "Extended mode selection", | |
| "a65e79a0300e382c": "FDCAN and LPUART2 clock", | |
| "a66a4758c6e72b97": "Option control", | |
| "a68e65c4a570c6d3": "Memory shutdown and analog power", | |
| "a69b234ab3fe5d0d": "Line 36 event mask", | |
| "a69bc1f7799c6d5b": "Memory region configuration", | |
| "a6a504552899b0fd": "CAN controller with dual ADC", | |
| "a6ae290af296b4fb": "TIM5/6 freeze", | |
| "a6d4cc4619987943": "Line 39 event mask", | |
| "a6ef7656bc5be612": "Threshold Configuration", | |
| "a72954372c893981": "High-number interrupt lines", | |
| "a72a851c59d6e4b4": "Power control register 5", | |
| "a72d0ab7dfc44232": "Audio, USB, and memory interfaces", | |
| "a737363dfed6ea75": "Reference clock output", | |
| "a7465408a70d8342": "External and comparator break", | |
| "a7582f7b7f59e573": "Pin high-speed low voltage", | |
| "a7847e7da8066a71": "Channels 3-6 Output Control", | |
| "a7882d8c2750240d": "Port F3-F4 pull-down", | |
| "a790c89a0e527bfb": "Page privilege protection", | |
| "a7a6d8581ec5d70e": "Write protection bits", | |
| "a7ad6980f45ce303": "UART 5 clock source selection", | |
| "a7ea91842d49a617": "Wakeup Pin Configuration", | |
| "a7f2af0979a66cf7": "Extended DMA freeze", | |
| "a80a5f8388efbe14": "Line 44 interrupt mask", | |
| "a821d8b2be51abe6": "Complementary channels 3 and 4", | |
| "a832a92a6cac05bb": "CAN 1", | |
| "a83a64ca51b4e610": "LCD interrupt status", | |
| "a843ca47d91536cd": "Transmit queue and burst control", | |
| "a85158eb0bef3273": "Port B-C pull resistors", | |
| "a85a3ec12139dfa1": "Channels 5 and 6", | |
| "a8606a2719fb565d": "Differential input conversion", | |
| "a87ff9d991a9d650": "Block protection additional registers", | |
| "a898d4f5896d3dab": "RAM size", | |
| "a8a388f932036c5e": "APB2 freeze register", | |
| "a8b8161e836e8334": "Timestamp on tamper detection", | |
| "a8c57b74ce00ac57": "Low-power RF wakeup", | |
| "a8d0d7f04799cc2d": "Port B-D pull control", | |
| "a8da03e1047cb3b9": "Multiple peripheral DMA remapping", | |
| "a8efea76ac19d998": "Configuration 1", | |
| "a8f67f549d809daa": "GPIO pin multiplexers", | |
| "a90dace87adf2bed": "Analog switch voltage booster", | |
| "a91f99965c4ccdc1": "SRAM3 parity and block security", | |
| "a93031cb63083a48": "Boot mode selection", | |
| "a9378c5747a319f5": "Filter initialization", | |
| "a942f0ef16628cbe": "Extended peripheral remapping", | |
| "a9517500b04be3b9": "Extended timer and serial support", | |
| "a9565a308aabcaa8": "Flash error correction", | |
| "a96af57b543a1fdf": "Advanced timer freeze", | |
| "a98e013120701bbb": "Monitoring control", | |
| "a99e524707ea0f79": "Security Level", | |
| "a9a7063148d2dc5a": "APB1HFZ1 freeze register", | |
| "a9ea3efa0ba05e9b": "Line 21 software interrupt", | |
| "a9eb22cbd30335c2": "Low power mode", | |
| "a9f2245d147ba935": "Period length bounds", | |
| "aa3cf43c2a1287f3": "Output color register", | |
| "aa3d6dd2d267e0b4": "Cortex-M0 lockup output locking", | |
| "aa3f6733f51ee204": "Camera interface and PLL3", | |
| "aa4d0174daa56dac": "Auxiliary Data Register", | |
| "aa531f5eb87162f9": "Device ID and standby debug", | |
| "aa567fa25f1cc5aa": "Dual-core boot configuration", | |
| "aa5cd13d8a2a9c1a": "Port H3 pull control", | |
| "aa6654db10bf2045": "External wakeup pins 2-3", | |
| "aa675892548e063a": "Port D pull control", | |
| "aa6c1b582e82d403": "Port B wakeup and pull-up/down", | |
| "aa70cedd89a005db": "Channels 3 and 4 capture/compare", | |
| "aa8c039f397b86bc": "Extended line interrupt masking", | |
| "aa9137594ec0c21f": "Interrupt pending flags", | |
| "aab93a0519fd61ac": "Power management and wakeup", | |
| "aabbc09cf16456d6": "Wake-up and standby control", | |
| "aad5573aa39d1fe5": "Input 6 detection and control", | |
| "aae06326b0c84a53": "I2S audio interface", | |
| "aae1d899636dd972": "SRAM2A Pages 10-15 Write Protection", | |
| "aae29e3f7738ac7f": "Lines 1-15 security configuration", | |
| "aaf9644c166467e2": "Algorithm with extended output", | |
| "aafeed2d563c6a90": "GPIO and integrated peripherals", | |
| "ab072a4629479f31": "SAI1 with audio PLL", | |
| "ab528ab0076fdeed": "Analog switch control", | |
| "ab61684e5ea54160": "Line 40 interrupt mask", | |
| "ab72ba082d94da18": "SRAM6 ECC and Protection", | |
| "ab7c0c86e48e2b77": "Double-buffer mode and security", | |
| "ab7dffea85870070": "Line 59 interrupt and event mask", | |
| "ab81661d4507baa6": "Low-power timer and SAI", | |
| "abba4c0ee402c04f": "Calibration factors", | |
| "abbb4ec785ceaf3c": "SRAM2 write protection pages 16-19", | |
| "abc54cc6e1122842": "Option byte status", | |
| "abc5a8a87519713f": "Line 42 interrupt mask", | |
| "abd2501eb1d4013a": "Memory remap configuration", | |
| "abdcf58cdbdc7874": "Extended line interrupt trigger and masking", | |
| "abe26bf7bde2dc19": "Sub-second adjustment", | |
| "abe9a6b8d25d8cde": "Unprivileged memory access", | |
| "abf3674a185af2a8": "Low-power timers freeze", | |
| "abf6171c541a95b8": "GPIO and peripheral clock enables", | |
| "ac032fd726ab8191": "Channels 1 and 7 privileged state", | |
| "ac0c6434023a3fee": "User Flash Bank swap", | |
| "ac17e95dd30e5bb8": "Watchdog threshold configuration", | |
| "ac20f3e967edd3d0": "Dual buffer DMA", | |
| "ac2c523236be241d": "Wrapped burst mode", | |
| "ac2f8c806b1b19b8": "DMA transfer control", | |
| "ac31e1f72491bd6e": "Component and Peripheral ID", | |
| "ac3cc60743de5819": "Advanced I2C interface", | |
| "ac3d116de1119281": "Lines 21–22 interrupt and security", | |
| "ac3fb0461d6d5728": "Extended pending support", | |
| "ac4b4c83d5ae12be": "SPI slave mode", | |
| "ac62952e3f1b649f": "SDADC analog power", | |
| "ac8585b3bb7e33df": "Auto-Baud Rate detection", | |
| "ac8ad846fff024f9": "Line 23 event mask", | |
| "acabaacd79643f3c": "Multimode and DMA configuration", | |
| "acad293e76b66627": "Line 28 trigger edge select", | |
| "acb4dfe897cc77e5": "GPDMA2 and access control", | |
| "acb5164d269a5090": "Analog switch control", | |
| "acb6b59edd4b785e": "VDDUSB voltage monitor", | |
| "acc3b9abbf456a18": "DCACHE2 stop mode power-down", | |
| "ace0d746f0be1308": "Fast soft start", | |
| "aceebc17575adadc": "GPIO pull control", | |
| "ad3ddc36d5da99ef": "Capture/Compare 2", | |
| "ad43a39da32a04cd": "Line 21 interrupt masking", | |
| "ad44924f13b0f5b7": "Event masking for specific lines", | |
| "ad63305c4201d3d4": "Memory protection area configuration", | |
| "ad761e657ec66516": "Interrupt line 14", | |
| "ad79f8e984a9e156": "DMA request generation", | |
| "ad7a9d58b76610d0": "External wake-up pin 8", | |
| "ad877c2265949b66": "Line 34 pending flags", | |
| "ad8dba155c00cac5": "Timer 14", | |
| "ad921dbcd45d2c54": "Channel 1 capture/compare", | |
| "ad9b49987af4485a": "Capture/Compare Channel 2", | |
| "ada58274c6c065b0": "GPDMA2 mid channels freeze", | |
| "adab42023d81731c": "USB privilege control", | |
| "adccf627c3392265": "Audio interface PLL with encryption", | |
| "ade5d9c430f4865f": "Multiplexed segment display", | |
| "ade8d5dbe7e3e42c": "I2C Fast Mode Plus on PA", | |
| "adf0498c5d374861": "Trace mode", | |
| "adf5691ba082e677": "Non-secure operations", | |
| "adfe7ad208172958": "Low frequency trigger", | |
| "ae07b719d568f186": "ECC Error Address Reporting", | |
| "ae18dafd28b31aaa": "Channel 4-5 memory address", | |
| "ae27502064622be9": "I/O compensation cell control", | |
| "ae2f0c769ab3a36b": "Input 6 secure detection", | |
| "ae392eb6b7883a9b": "SMPS and BORH Configuration", | |
| "ae60a77234c8c4c9": "Lines 44 and 46 masking", | |
| "ae938d33d905e5e9": "Extended interrupt lines", | |
| "ae9aad175dc6379b": "Timer 2 freeze", | |
| "aea0bca86a3dc27a": "Dual-processor interrupt masks", | |
| "aea779dd9f567104": "Extended write protection", | |
| "aeefaddb1d24f3fa": "Edge trigger configuration", | |
| "aefb30e70708b78a": "Configuration options", | |
| "af1a39f5c3dda162": "Capture/compare channels 3 and 4", | |
| "af2193780ec181bb": "Line 30 interrupt control", | |
| "af28c2b1d29a7854": "Event status clear", | |
| "af45857871933c6c": "Line 26 trigger edge select", | |
| "af4e3aec294308ff": "IrDA low-power mode", | |
| "af7a56e9bd73108f": "Channel 1 complementary output", | |
| "af7f4f3b60bf4ced": "External SMPS ready flag", | |
| "af8d266296121073": "GPIO and DMA controller", | |
| "afc44a7fbbe9e6f8": "Even comparator control", | |
| "afef875933b93f94": "Tamper 3 detection", | |
| "aff888a379ff8256": "TrustZone and privilege", | |
| "b02fed1c28d201fe": "Double-buffer mode", | |
| "b032e58fd0bd4311": "Security configuration", | |
| "b03ae438d58ca09c": "Injected queue overflow", | |
| "b044994f6c89b2de": "Input Capture 1 remap", | |
| "b06b838adcc91b40": "Compensation cell power", | |
| "b0893deae611ba78": "DMA request generator", | |
| "b09dc3fe2a9a9ade": "Color format transformation", | |
| "b0b20e179d962995": "Line 40 interrupt and event", | |
| "b0b328457a66cf58": "Host debug authentication", | |
| "b0d24ad38aecf3b1": "External interrupt configuration", | |
| "b0e31372c7620f25": "Data word counter", | |
| "b0eff6c1d238fbf0": "Line 0 security configuration", | |
| "b0f2af9869ee1712": "Programming and erase operations", | |
| "b0fbb32111d7d66b": "Power monitoring and domain management", | |
| "b11124bd5bd9c7f6": "Trigger event selection", | |
| "b11490f5a963c68a": "Temperature sensor and reference voltage", | |
| "b12a88c00a8c6c5c": "PLL output dividers", | |
| "b12ea0673cced58f": "Timer 7", | |
| "b13fc79feceb86fd": "Error configuration", | |
| "b144f61482aaea21": "Dual comparator output control", | |
| "b14dad1fff7869b9": "Extended wakeup control", | |
| "b14e0bdbb504afef": "Break Comparator 4", | |
| "b17c7c322ee7b260": "Injected conversion", | |
| "b18f80721913b2a8": "Single comparator configuration", | |
| "b19054d405852246": "ECC Error Detection and Correction", | |
| "b192d1d587b0abd5": "External interrupt configuration", | |
| "b1a037b2475678f9": "Extended hash digest", | |
| "b1b0c64ee18c0023": "Peripheral voltage monitor 2", | |
| "b1bab2405c9fb033": "Break Disarming", | |
| "b1c1d839b843c8a4": "GPIO pull-up and pull-down", | |
| "b22fadbd45a37e91": "Line 31 security configuration", | |
| "b23bd86cf6bd373b": "Layer 2 window vertical start", | |
| "b23fba312f39fd6d": "CPU2 interrupt control", | |
| "b25372aa95df7af6": "Sigma-delta digital filter", | |
| "b2563e0463038f83": "Line 24 interrupt trigger", | |
| "b25f29defb131831": "Health test mode", | |
| "b26a924553dd78a8": "I2C2 and I3C2 freeze", | |
| "b27391c91d805562": "Channel 4 complementary output", | |
| "b27fd4e04ffb8591": "Low-power Timer 22", | |
| "b28c261d17e77af9": "Extended Output Compare 1", | |
| "b2a5b61dbf153034": "Low-power mode and pull control", | |
| "b3213a47d5fb1cac": "Line 36 interrupt mask", | |
| "b3467913e1eecb10": "Channel 6 capture/compare", | |
| "b35003bbca7bbf4a": "Timers and DSP accelerator", | |
| "b352fcc4d217adde": "User option bits", | |
| "b375553f9164b67c": "Wake-up pin 1", | |
| "b3797b8f4e804d57": "Timer 6 and DAC1 DMA remapping", | |
| "b3a2ac5d537a8ad5": "Interrupt line status", | |
| "b3a62d1902125e64": "Backup registers 16-19", | |
| "b3cb5a8bada2867f": "OEM keys and SRAM reset", | |
| "b3d6b652b339c24e": "Line 18 security enable", | |
| "b3f4a5cf3832f14f": "Binary mode with sub-second", | |
| "b41a46150062fb22": "Write protection option", | |
| "b43994f9b532f6b7": "Four-rank injected group", | |
| "b43b6ede1c942ec2": "Secure memory watermarks", | |
| "b440c9face1b8c40": "Security and privilege configuration", | |
| "b44a713b0bda0177": "I2C1 Fast Mode Plus", | |
| "b473d27114a31c3c": "UART 4 and UART 5", | |
| "b48d76dced3a7ff3": "Graphics and display", | |
| "b4a1dd5766bdd54b": "SRAM and RTC retention", | |
| "b4b921d0925e09af": "Regular oversampling", | |
| "b4d347ad61b0fcf5": "External trigger remapping", | |
| "b4e06987f2ec359f": "PB8-PB9 I2C Fast-mode Plus", | |
| "b4e24189dac37ab5": "Programmable gain amplifier configuration", | |
| "b51f803b57749573": "Line 42 interrupt and event masking", | |
| "b5262c0e04d42dff": "Flash operation control", | |
| "b52d13739e472f44": "Update interrupt flag remap", | |
| "b559274fc5e3e840": "Read and write protection options", | |
| "b55e3c598ff83d3b": "Internal tampers 4 and 6", | |
| "b56397e0d7b98bf3": "M4 boot address", | |
| "b56417db08251903": "Flash abort interrupt enable", | |
| "b571e3a535c243e9": "Brown-out reset status", | |
| "b5933124f0f60cfb": "Voltage reference buffer configuration", | |
| "b5a00d6ed6baaa85": "Oscillator 4-6 control", | |
| "b5abde7597509442": "Watchdog and I2C4 freeze", | |
| "b5b1c140810fbe29": "Memory Selection and Calibration", | |
| "b5bef6b9f42b0b8f": "Partial block support", | |
| "b5c8ee41f4655daf": "Watchdog stop in debug", | |
| "b5cac5c44bed5f80": "Line 39 interrupt mask", | |
| "b5ceffbb55b48fde": "Bank 1 protection status", | |
| "b5d4b4051a98c2ab": "Extended control bits", | |
| "b5e2a08ae9d1d148": "External Interrupts 0-10", | |
| "b6069b85a12af8e3": "Line 19 security configuration", | |
| "b60dff2cd093da25": "External interrupt routing", | |
| "b63010971d763ff7": "Output speed and pull resistors", | |
| "b6336aa4c3d485ad": "External event synchronization", | |
| "b639ffdde594df7b": "Encoder mode", | |
| "b64368faf63eb7e9": "Standby GPIO retention", | |
| "b643b1c79160c09b": "Graphics memory management", | |
| "b67da6873c4d4664": "Dual flash bank support", | |
| "b69aa97a3b76ec9f": "Timer 3, 7, USART 4, 5, I2C3", | |
| "b6cacc67579b1eae": "USART3 and LPUART1 interrupts", | |
| "b6cec5a89764b1a8": "Commutation DMA request", | |
| "b6f645fa38d70539": "Power voltage detection", | |
| "b6f6e15408c95bcf": "SRAM ECC Configuration", | |
| "b6fbfcb20711aeb7": "USB with Low-Power Support", | |
| "b723023b956a2bef": "Extended timer and I2C stop", | |
| "b74e5a9acf6c30ff": "SRAM power-down in Stop modes", | |
| "b7966b1e94909546": "DFSDM Break 1 input", | |
| "b7bb593d9986ffcf": "Privilege gating for main lines", | |
| "b7d97d287670fb45": "Camera interface", | |
| "b7e0bb07e77b6003": "Extended Interrupt Sources", | |
| "b7f1b279c9fb3105": "Wake-up pin 3 with Port E GPIO", | |
| "b80e157ecce8dcf1": "CPU2 flash control", | |
| "b8231a9f83763f93": "Line 30 event", | |
| "b82978d87dec8a2a": "Break 2 COMP1 input", | |
| "b84cb8c48edf32f6": "Secure flash operation control", | |
| "b866fa68398c5ce4": "Lines 21-22 security and privilege", | |
| "b88251767a70e061": "Health test configuration", | |
| "b8b3540627a165b8": "Double Error and Erase", | |
| "b8b693e318204728": "FPU interrupt enable", | |
| "b8d4084c558290c0": "Multiple watchdog and sampling", | |
| "b8e687e5ed279c52": "Standard peripheral set", | |
| "b8ee68529628dd21": "Software compensation control", | |
| "b9014d7df92071e1": "ADC1 and ADC2", | |
| "b908afa3780956d1": "USB support", | |
| "b91949e1434b4f4b": "STOP mode operation", | |
| "b922bbbcd510580e": "Backup registers 0-1", | |
| "b92c9f2b4a5f7b00": "Port D pull-down configuration", | |
| "b93884d6173dba49": "Commutation and break control", | |
| "b959cc320990c002": "CAN reset and clock", | |
| "b9603aa69ebf8389": "Shift and recalibration", | |
| "b965712550b56132": "GPIO port D clock", | |
| "b97a5357f98b29ce": "Channel 4 output idle state", | |
| "b982cd240f2c34f3": "Interrupt edge detection", | |
| "b98cc1041a57cf00": "Lines 37–42 event masking", | |
| "b99f7d9d9e5b2da8": "Tamper pin remapping", | |
| "b9bce2341a29f1d4": "Clock mode", | |
| "b9c2f527dff7ac2e": "Radio and PKA debug control", | |
| "b9c541abc24f4566": "Lines 61-63 event mask", | |
| "b9d49f68527ab3bb": "Line 22 interrupt masking", | |
| "b9e4c47e9cd31ae8": "Power control", | |
| "b9fe469e08d2ac00": "Port B pins 10-11, 13-14 pull configuration", | |
| "ba058f9c6c55a839": "Power supply and voltage management", | |
| "ba2d1ee96b05c0d8": "Frame capture rate and data mode", | |
| "ba307a61885e5b98": "Channel 2 output data", | |
| "ba46dc6f5d6ca4da": "Interrupt pending for lines 19-20", | |
| "ba49c9aae3117d09": "Power and wake control", | |
| "ba4c1324bb563a1d": "Interrupt remap and PVD lock", | |
| "ba4ee8bb3caf18a5": "SRAM error correction and control", | |
| "ba565767961d4d60": "Dual-bank control and protection", | |
| "ba5f45804190e490": "Internal tamper 12 and 13", | |
| "ba6fe1b50c9707b7": "Transfer security and privilege", | |
| "ba884f6431cba2be": "Single watchdog support", | |
| "ba933aef7eceecdc": "ADC 2", | |
| "ba9f7bc89017a41e": "Line 0 interrupt and event masking", | |
| "baa3d9bcbc591c87": "USB Power Delivery control", | |
| "baaece9599d3766f": "DMA and TIM16 interrupt status", | |
| "bab344595634423b": "Wake-up Pin 5 with Port D GPIO", | |
| "babb1b38c68d63e5": "Security configuration", | |
| "babd2380fa2624da": "Line 16 interrupt masking", | |
| "bac5212d77a138eb": "Physical unclonable function support", | |
| "bac56b6f7bf1c2d7": "SRAM1 page 9 power-down", | |
| "baca59313e8dc52e": "SRAM Bank 3 ECC Protection", | |
| "bae5baa185dde77a": "Port D pin 7 pull", | |
| "bae77147ce357c1e": "Internal tamper 1, 2, and 15", | |
| "bb19e24392e7ae0e": "Write Protection Pages 17 Onward", | |
| "bb462de64750040c": "Ultra-low power mode sampling", | |
| "bb5881ff71e03d25": "High-speed UART access control", | |
| "bb981534931be78a": "Extended transfer registers", | |
| "bba98a1c794b0761": "Wake-up pin 5", | |
| "bbb57c3439da1b0d": "VDDHPA regulator selection", | |
| "bbc90a9382af8339": "Lines 31 and 33 interrupt and event", | |
| "bbe0e8a23d41e223": "Synchronization routing", | |
| "bbf804aee2dc7057": "Comprehensive freeze support", | |
| "bbf8673b279d17e9": "SMPS and VDDHPA ready", | |
| "bbfa800a0df24af1": "Line 27 masking", | |
| "bc37d5043e14b6d2": "HSE Clock Security and GPIO H", | |
| "bc98dc4e1b835378": "TIM8 stop in debug", | |
| "bc9e1264ef9e19ae": "AHB1 peripheral clock control", | |
| "bcad8b7efa436ccb": "Pending interrupt status", | |
| "bccc1ff0532490d2": "Block security configuration", | |
| "bce178aaf1de7253": "Voltage scaling and battery charging", | |
| "bce7cba0f56d8afc": "Readout protection status", | |
| "bce9fbc1086daca0": "Bank 1 security and debug", | |
| "bd1ed6805e8aecba": "Output remapping", | |
| "bd257f1e0a10136c": "Privileged access protection", | |
| "bd4c7941bedd3e6b": "Delay line configuration", | |
| "bd61f98ac89a049c": "Read protection and reset configuration", | |
| "bd67e58997473046": "Calibration and channel sequencer", | |
| "bd73c60e9ee9c975": "Comparator 2 global interrupt", | |
| "bd7e51dc35b81ec9": "Secure system configuration", | |
| "bd88983b5f172209": "Line 16 event and interrupt mask", | |
| "bd9fca7a08bdf5b9": "Capture and trigger interrupt", | |
| "bdcd8c1f82ba4c3a": "Prefetch Control", | |
| "be29c5aa0d537806": "DMA2D SRAM power-down in Stop", | |
| "be2a7bca05163078": "Voltage scaler", | |
| "be33872e9bd48db4": "Microcontroller clock output", | |
| "be36c5f5e30b830f": "DSI clock source", | |
| "be4d18296ba8203f": "Chip select selector override", | |
| "be4f75ef20071add": "Timer input connection", | |
| "be6fee8a9068e66b": "Wakeup Pin 1", | |
| "bee490bbd06e02a5": "Synchronization for channel 7", | |
| "bf11fe9424cb6b8c": "Enable control", | |
| "bf2239a5a0c99cf0": "System memory and ADC configuration", | |
| "bf240cf7034567f3": "Line 19 interrupt configuration", | |
| "bf335edb96d0a0fd": "Memory shut-off and voltage control", | |
| "bf3aa7bf122a3453": "DFSDM mode configuration", | |
| "bf411eff3c680b46": "External SMPS control", | |
| "bf482ebd76b34ded": "Peripheral freeze in debug", | |
| "bf4bdee60c4e7803": "Flash power-down and backup domain", | |
| "bf4d34b9261b8fdf": "Wakeup timer", | |
| "bf6cf220ad6a04ad": "Channel 6 transfer count", | |
| "bf7ac271660cbfb4": "Internal tamper 15 input", | |
| "bf850fbec39059f0": "Capture/Compare 1–4", | |
| "bfa5ede39d8a89df": "I2C fast mode plus", | |
| "bfb57e414315e87b": "Advanced transfer configuration", | |
| "bfb7147a20f3e9c4": "I/O port E", | |
| "bfb7c0d4600700cc": "Peripheral clock selection", | |
| "bfba8de8fc9804ee": "Internal input 4 detection and control", | |
| "bfd1d4e0b85e9ac7": "Start bit error detection", | |
| "bfe953fee0c87d53": "SRAM1 page 8 power-down", | |
| "bff02a191b06ba9d": "Voltage regulator status", | |
| "bff1f309ecae606c": "Write protection regions 8-11", | |
| "bff8d2617fe6211f": "OPAMP2 calibration output", | |
| "bffe9e817fb37bbd": "Line 32 pending flag", | |
| "c005c6e80d915eab": "Wake-up pin retention control", | |
| "c0110580c6e2229b": "External wake-up enable", | |
| "c023aca777a3fb54": "I2C5 fast mode plus", | |
| "c0348cd2a0665928": "Timer 7", | |
| "c03ab20ce0f56c7f": "Low-power regulator status", | |
| "c03e56e9f53e43c3": "Backup domain and low-speed oscillator", | |
| "c043337414759322": "APB2 prescaler", | |
| "c044485be8f3579b": "Mid-range write protection", | |
| "c068f1d9930ae768": "Health error monitoring", | |
| "c06b4e2452dad1ed": "Capture/compare channel 2", | |
| "c0760d1e38264bfa": "PA13-14 GPIO and bias control", | |
| "c0794fdfd8fa6f4c": "Dual and triple ADC mode", | |
| "c07be8b749a62645": "High-speed interfaces", | |
| "c07f25800be3fe80": "Color lookup table support", | |
| "c08e008f4534263d": "Injected conversion data", | |
| "c0961b39a423729c": "Debug CKD3 clock enable", | |
| "c099769f8118a6f5": "Extended freeze registers", | |
| "c0acfb00f17fc263": "Supply scaling and battery domain", | |
| "c0c94bf04fed5194": "Expanded write protection", | |
| "c0e621ff77fbcb93": "Flash readiness state", | |
| "c0e9676a3bacce2a": "CAN3 freeze", | |
| "c0fa31ce3d1e3cd6": "Non-secure configuration and status", | |
| "c11de4bdb247a6a1": "2D graphics and camera support", | |
| "c132331214ef7e4e": "Secure channel interrupt", | |
| "c13ed894423fe714": "Internal tamper inputs 7 through 11", | |
| "c1498bf124333fe4": "Single ADC conversion", | |
| "c1598e0c34d828d8": "Extended comparator configuration", | |
| "c17c6919c18ee7f4": "Line 46 trigger configuration", | |
| "c18981b64c913138": "HSI48 and clock recovery", | |
| "c18c09b5c3ae9ba2": "USART2 interrupts", | |
| "c197fe60d2297b04": "LPTIM2 and I2C1 freeze", | |
| "c1b8a6f29a1570e7": "Deadtime preload", | |
| "c1c66f6c6ff412d2": "DAC and touchscreen controller", | |
| "c1dd935b4add3a96": "Fast Role Swap events", | |
| "c1ec38dff2167eb7": "Maximum Transfer Length", | |
| "c2381bb99328c499": "Line 18 edge selection", | |
| "c23d81f889d1500e": "Privilege mode control", | |
| "c2427473e4304c63": "Core power and low-power modes", | |
| "c2472d36235eea5c": "Master clock divider", | |
| "c253e27b0f149edd": "Encryption and key accelerators", | |
| "c27ba46129f988a2": "Byte select mode", | |
| "c2a67a8136c60071": "Interrupted operation address", | |
| "c2a95b6f881e26ca": "Dual-core boot address", | |
| "c2be71e102dedab1": "Break comparator 2", | |
| "c2e248d1c4cfef4f": "SRAM3 page 1 power-down", | |
| "c2edad7e106d8d04": "Security accelerators and high-speed DMA", | |
| "c313fd23a38c380c": "Flexible payload error status", | |
| "c34dc7376eed5b03": "USART 3", | |
| "c38ac389d7f144e6": "DMA requests", | |
| "c39792f99a9b53a1": "GPIO J/K with SPI6 and DMA2D", | |
| "c39c2189772a49fa": "SPI 2 and I2C 2", | |
| "c4068877b6a75d74": "Write Protection Pages 17-63", | |
| "c41de22671d9c7c5": "Padding and alignment mode", | |
| "c42471f4127ebb2d": "Transfer count", | |
| "c44bacdf5614e894": "Touch sense controller interrupt", | |
| "c48bc939af690620": "Break 2 input", | |
| "c4ced388528a145e": "Communication and timer functions", | |
| "c4d0b51379dd025a": "Single-bank page configuration", | |
| "c4ec0b7367f90808": "Internal tampers 12, 13", | |
| "c516be7bb26172e6": "Latency and write protect", | |
| "c518127e79aac2d6": "Core peripheral security", | |
| "c530f804a3a10ede": "Send Instruction Once Mode", | |
| "c53973987d2bdb40": "Peripheral routing and error protection", | |
| "c53b941c9ac0e524": "Offset modes and sleep control", | |
| "c53f16295ccf080d": "ECC lock", | |
| "c54e16a51d17c2be": "High-performance DMA halt", | |
| "c5609300d3b8aae0": "Line 22 pending request", | |
| "c560c78b5360b1ae": "Health test configuration", | |
| "c57f53d6242ec7da": "Firewall access enable", | |
| "c59b919d38f6cb4c": "Analog switch enable", | |
| "c5bf59fb656ecc47": "Wakeup pin 2 configuration and status", | |
| "c5e6cc39ba6b4e59": "Dead-time generation and break control", | |
| "c5f1b7be08220fec": "Write Protection Pages 32 Onward", | |
| "c5f2354dc62bc58d": "Input 1 routing interface", | |
| "c5f44521f05fa722": "SRAM2 page 2 power-down in Stop", | |
| "c610458e0c3801b1": "Alarm flag clear", | |
| "c63806833a459cca": "Non-secure locks", | |
| "c65171f84aa4d3a2": "Injected queue overflow", | |
| "c6547b49036f655e": "Ethernet and high-speed USB", | |
| "c660b8352b89e5be": "Line 25 edge detection", | |
| "c666fe4418257821": "Capture/Compare channels 1-4", | |
| "c66d6f98528585a0": "Secure channel configuration", | |
| "c6804365d31d2e51": "SRAM1 error correction enable", | |
| "c684fb5aa02711db": "TSC and LPUART2 interrupts", | |
| "c68fc7e457d665aa": "GPIO pull-up and pull-down control", | |
| "c6926524eeedeecc": "Bank 2 ECC and PCROP", | |
| "c69340548f1bd01e": "SmartCard Protocol Support", | |
| "c694420505eacaf6": "Flash status and control", | |
| "c6a23bebfd465b4c": "Hardware request selection", | |
| "c6b9ecbf51ac0e56": "Debug disable", | |
| "c6c57896a910e2fc": "Freeze TIM16", | |
| "c6cf40cfe61f8a20": "Dual-bank configuration", | |
| "c6d8e4127b50beea": "SRAM3 double error NMI and protection", | |
| "c6e55535e6c8862b": "Request source selection", | |
| "c6ecff5055a716ed": "Lines 19-20 privilege control", | |
| "c708ab1d2010a65c": "TIM12 and miscellaneous remapping", | |
| "c72b0727d3fd263f": "Timer 20 freeze", | |
| "c72cc619859e8e79": "Analog switch voltage selection", | |
| "c73bce73206e6467": "Core control and locking", | |
| "c768b90e0619496a": "Channel request selection", | |
| "c77a114abbfad40c": "Parallel ADC 3 and 4", | |
| "c7be0c17f87d9ac4": "Bank 1 PCROP and security", | |
| "c7e65bcb32411511": "Infrared output polarity", | |
| "c8046ae5bde3ac19": "Low-power mode and GPIO", | |
| "c808070a20fe169c": "Register 3 interrupt configuration", | |
| "c82a72eb8be30adc": "Advanced-control timers 16 and 17", | |
| "c8361c9bb2c3c62b": "Host channel 12", | |
| "c83700993f2635fb": "Slave mode trigger selection", | |
| "c847b5feded965d0": "Underrun and RDY control", | |
| "c85d2950c28d7051": "Version and Error Status", | |
| "c88cbcedd3c9c686": "Synchronization for channels 8-13", | |
| "c89e2c934d7ac24c": "SDRAM bank 0 configuration", | |
| "c8c7fa6947ea3baa": "Reset mode configuration", | |
| "c8cc144566fd96c9": "Additional device secrets configuration", | |
| "c8d07a6153be36ff": "SRAM5 and USB power control", | |
| "c8d1759d72bdadbb": "Backup register lock", | |
| "c8e9f785bbd51a6d": "Clock phase and polarity", | |
| "c8f31261f73cf1fa": "USART3 remapping", | |
| "c8ff71b86bf3aa7e": "Channels 12-15 secure state", | |
| "c907cad99a0056df": "Interrupt flag", | |
| "c93312b14c58e87a": "Parity error detection", | |
| "c937241f800aa4f7": "Compare 1 Channel Values", | |
| "c943f130f9f1812a": "Pending line 33", | |
| "c969f61ec2f9cecf": "Boot selection", | |
| "c96c534f45a57402": "Optional features", | |
| "c9718bad4895fac2": "Per-block security bits", | |
| "c976a2ed596c84ce": "Option register", | |
| "c97b306ccdde40e6": "I2C1 source selection", | |
| "c982e93cf832c152": "Line 17 interrupt trigger", | |
| "c98db131e132eb71": "I/O edge detection", | |
| "c993b338af180158": "Timer 4 with SPI 2 and USART 3", | |
| "c9c1b47c88b9b6c8": "Extended digest output", | |
| "c9e356a4146bccac": "Pin bit reset", | |
| "c9eaa234a8d7d091": "Analog watchdog and oversampling", | |
| "c9ef8017cd370f4c": "Transmit/receive edge status", | |
| "ca0d5e50401760ff": "Gain compensation coefficient", | |
| "ca10fcaff5743251": "Input selection", | |
| "ca16f64cb424f376": "Graphics memory management", | |
| "ca3db15b8bba264c": "Clock prescaling", | |
| "ca4fa78e1a3f9530": "System clock divider", | |
| "ca53019863590c9f": "Flexible memory controller", | |
| "ca70673bbdd6c223": "Break lock and EXTI configuration", | |
| "ca7e1fcafcb3a2c2": "Low power mode selection", | |
| "ca8cf80afea24d26": "Freeze register set", | |
| "ca941a334da04f2b": "Write protection register 2", | |
| "caa2911a8a1ebe2e": "SAI1 clock selection", | |
| "cac32ff8b514c39d": "Peripheral control", | |
| "cad34034c2c8c77c": "Sub-GHz RF support", | |
| "cb01876632b56947": "Extended line trigger with pending support", | |
| "cb122c6365e21093": "Request identification for channels 3-4", | |
| "cb134d90dac04da4": "Error detection and output", | |
| "cb21a1d63816e691": "Watchdog 2 and 3 channel selection", | |
| "cb40f9b540300ea9": "High-speed peripheral protection", | |
| "cb4e18dd51333312": "Extended write protection areas", | |
| "cb8a8de362ad5e81": "Voltage reference security and privilege modes", | |
| "cb9adb31f6fa1c95": "Break disarming and re-arming", | |
| "cbe57fcb5cce151c": "CPU2 I2C2 and LPTIM3 freeze", | |
| "cc0a2774bd6377ac": "I2C Port B fast mode plus", | |
| "cc47192aba9458ba": "Low voltage erase", | |
| "cc6929306085f901": "Register 2 trigger and pending", | |
| "cc79dfe5a5f7f02d": "I3C pull-up", | |
| "cc8a8729d163560e": "Counter reload and trigger remap", | |
| "cca2965a07feeb10": "Individual line trigger and pending configuration", | |
| "ccaae9a2d1fad6a7": "Algorithm with extended digest", | |
| "ccb09733acc5e006": "Status and error flags", | |
| "ccb8ea7d80004f7e": "Core debug capabilities", | |
| "ccc291e4fc89fb73": "Intelligent transmission audio interface control", | |
| "cccc0a906baf5298": "Extended GPIO pull control", | |
| "ccdb2eab84d61d4c": "Dual bank and ECC configuration", | |
| "cced45cf721df73e": "TIM3, TIM7, and I2C3 freeze", | |
| "cced8a1ca42ea42f": "Bank 1 privilege bits", | |
| "ccf049988228e4a2": "Line 45 trigger configuration", | |
| "ccf266ea3fb7b9a9": "I2S prescaler", | |
| "ccfb057b8f0a33ed": "Asynchronous I2S start", | |
| "cd1267a98b1e799b": "Boot acknowledgment timeout", | |
| "cd184d163b6ea427": "Linked list DMA with FIFO", | |
| "cd1d356171e8742b": "External wakeup pins", | |
| "cd21c7292a315f5b": "Port D pull resistors", | |
| "cd22a8afa779b46b": "Channels 8–11 privileged configuration", | |
| "cd29a39ca3a83a54": "Dual and triple mode conversion", | |
| "cd331e69bd0ca57a": "Internal Trigger 1 remap", | |
| "cd3861e2786938ca": "Wake-up line polarity and status", | |
| "cd54413896b3a02e": "SRAM3 double error correction", | |
| "cd82033bc7168ac5": "Dual comparator core", | |
| "cd8bef1d12d9daf5": "Line 21 falling pending interrupt", | |
| "cd98947367d98c35": "Line 23 falling edge trigger", | |
| "cda8b32094f36f57": "Algorithm with context", | |
| "cde0f129aad9018c": "Peripheral voltage monitoring", | |
| "cde8c9c385fbdaa7": "Channel sequencer", | |
| "ce07acbb79da6069": "All APB domain freeze", | |
| "ce0d9734b9d9176b": "Lines 38, 40-42 interrupt masks", | |
| "ce102a31a799a1ec": "Request identification for channels 0-2", | |
| "ce166652f4f32b50": "Break 2 Comparators 5-7", | |
| "ce3718b349ff9221": "CAN bus interface", | |
| "ce403ed320cb81f5": "TIM6 and TIM7 Interrupts", | |
| "ce727e517defb5bd": "Tamper 1 control", | |
| "ce7bb9dac65df4b3": "Option Register", | |
| "ce82cd13f1695d85": "CPU2 freeze control", | |
| "ce8746f4df6d7274": "Line 33 interrupt and event masking", | |
| "ce883a5902c72564": "Babble error interrupts", | |
| "ce9005facf7d5c1e": "Differential calibration and internal paths", | |
| "ce94ab67c1fa2613": "I2S 2, 3 clock selection", | |
| "ceb83cf28145aa9c": "SDRAM read burst and timing", | |
| "cec2dadedf325dcf": "DFSDM1 clock source", | |
| "cec3eb485c690a6b": "Complementary output 2", | |
| "ced81465bc24a03d": "BackUp SRAM Parity Timer Break", | |
| "cee8ca44e6078156": "Identification and configuration", | |
| "ceeb2df8828ce049": "CAN remapping", | |
| "cefcd2d602da9a7e": "Extended key and suspend", | |
| "cf23335f9a68c1f1": "Graphics and JPEG Processing", | |
| "cf365696eba22635": "Line 20 pending mask", | |
| "cf46ce605314d477": "Synchronization interrupt and event", | |
| "cf4c3e47b50ba57a": "ECC monitor 5", | |
| "cf516f7cc1d01290": "Buffered Output", | |
| "cf6672d2c8519250": "Secondary bank operations", | |
| "cf66cd8327db11ea": "Event mask for line 37", | |
| "cf9e3eef6ad53b0a": "Buffered software trigger", | |
| "cfb7507b4e7ee53c": "Counter and capture/compare", | |
| "cfbaae9c078fddeb": "Wakeup timer control", | |
| "cfce8dfd7557a8ea": "Pin security configuration", | |
| "cfd6f8b30eb5c463": "APB1 dual freeze registers", | |
| "cfe9084049d39e75": "Capture/Compare Channels 2-4", | |
| "cff1272933ebfaa3": "Write protection pages 8-16", | |
| "d00189c8567a0d54": "Backup registers", | |
| "d00276d26e1cf8bb": "Advanced Timer Modes and Triggers", | |
| "d015d6dd11a7030d": "Extended word length", | |
| "d01ef8c30a45bb20": "Bank mapping", | |
| "d022e33fc6c969af": "Line 17 trigger and interrupt", | |
| "d02e93af5bb13a47": "Low-speed oscillator and RTC", | |
| "d05057bb0f3ba8f3": "Backup regulator", | |
| "d06a5c4fae5ec626": "External oscillator mode", | |
| "d06d30591d63145f": "Linked-list transfers", | |
| "d0a14c4ae93852b6": "Parallel bank access mode", | |
| "d0a29a0e96dc4d5a": "TIM2 and TIM3 freeze", | |
| "d0a7d99bb71f3d8e": "Analog watchdog with filtering", | |
| "d0b1cc3cce94603a": "Input hysteresis", | |
| "d0d616732d65e03e": "Advanced watchdog and channel selection", | |
| "d0eba2237297dd19": "Differential mode", | |
| "d1130a1e5b5fcc5c": "Continue on buffer not available", | |
| "d118d2f0fe68d2b7": "Configuration register 2", | |
| "d14e12e0e315b39a": "Watchdog and detector monitoring", | |
| "d160717aed94b620": "Wake-Up Pin 5 and GPIO", | |
| "d184d4c6f3e3a797": "Line 41 trigger control", | |
| "d186fccfa2b426a8": "Security and privilege configuration", | |
| "d18ee291ba1f5ca8": "DMA channel freeze", | |
| "d18f50ad6c9889fb": "Watchdog 2 and 3 interrupts", | |
| "d19fbd65cd588bee": "Channel 1 output data", | |
| "d1a6059216b4eb5d": "Clear FIFO request", | |
| "d1ae7e746e84cc81": "Basic timers freeze", | |
| "d1b5628e9a64b667": "Display Serial Interface", | |
| "d1c3e113fa517c2e": "Bit reset", | |
| "d1c58db8ff10d2f0": "SRAM2 write protection pages 16-19", | |
| "d1ed5a1c13dbfcbd": "Internal ADC2 and user configuration", | |
| "d1f46860120699fd": "VDDIO compensation cell control", | |
| "d2276a6d5654de1a": "Code read-out protection", | |
| "d23dff8f32a213f9": "TIM4 stop in debug", | |
| "d2505600692ccbf6": "Extended trigger event selection", | |
| "d274647982db33f9": "Comparator and CAN interrupt", | |
| "d279619d90dc4964": "Injected data register 4", | |
| "d27cb4c6e0e21312": "External interrupt line configuration", | |
| "d286b8a6cc529be9": "Event counter", | |
| "d2888d98103b326c": "SPI1 I2C1 USART remapping", | |
| "d28e146ea4aca185": "Tamper 1 input", | |
| "d2a984d1fe98b322": "SRAM2B write protection", | |
| "d2ce6e349c285b6e": "Peripheral voltage monitoring output 3", | |
| "d2db43eee34f029b": "Error interrupt", | |
| "d2f68d6a5400be05": "Secure privilege configuration", | |
| "d2f8c49035a58f3d": "Port H0-H1 pull-up and pull-down", | |
| "d333208c76758ff1": "Capture/Compare Channels 5-6", | |
| "d349c80f76690570": "Line 38 event mask", | |
| "d34a118cd553df93": "Linked list DMA with FIFO and buffer", | |
| "d36e16ed6fcc8c38": "Extended operation modes", | |
| "d38adcf56a85a34d": "Freeze TIM17", | |
| "d3b1c440715a2c79": "Port H2 pull control", | |
| "d3c0f321df8cc47c": "Dual ADC DMA remapping", | |
| "d3cfe8575acb430e": "Secure muxing", | |
| "d3d00914a41d4082": "Transmit FIFO empty flag", | |
| "d3dc99a4cd759c8b": "Extended regular sequencer", | |
| "d3fd3bd3dad25e13": "Continuous clock enable", | |
| "d411dc4b0b9f0010": "Extended sample rate", | |
| "d42708ea512e5d35": "Capture/Compare 5 register", | |
| "d4432e58e3f420c0": "Line 17 event masking", | |
| "d4544b1ad2524b29": "I2C2 Port A fast mode plus", | |
| "d45497a3c2acc53e": "AHB error detection", | |
| "d469846b80008b08": "Port B extended GPIO pulls", | |
| "d485160c5be58405": "Internal event timestamp status", | |
| "d4a1dd515085dcda": "ECC error detection and correction", | |
| "d4aaa50eb6845387": "Block repeat and address offset", | |
| "d4ac68519364877c": "Input 1 remapping", | |
| "d4b748526383d6c1": "Debug in standby mode", | |
| "d4b9a9e284b45725": "Port C GPIO pull configuration", | |
| "d4ba81e7e6764abb": "Input selection", | |
| "d4c33bf0f6251356": "Non-inverting input selection", | |
| "d4f092ac27b47f9e": "Graphics processor", | |
| "d5084757186c828b": "Initialization and status", | |
| "d524a5098b9d4d35": "MCO prescaler", | |
| "d526902ca6694fe0": "PA0 pull-up and pull-down", | |
| "d56544ff9122e0ee": "Capture/Compare 2 value", | |
| "d5861ae022172a5b": "USART7 request remapping", | |
| "d5943a43ee96a172": "I2C4 global interrupt", | |
| "d5bc4623302ecdcd": "APB1 freeze", | |
| "d5cb1d9e994aef5b": "Boot acknowledgment", | |
| "d5d05e2f199a08cf": "SRAM4 fast wakeup", | |
| "d5e05e800c278cec": "Secure configuration and lock control", | |
| "d5ee3f869bbdf519": "Peripheral remapping", | |
| "d5f331c065dffb1c": "PLLSAI and SAI1", | |
| "d6296a49e7144b30": "Power modes and voltage control", | |
| "d65349d00144dd10": "Alternate key mode selection", | |
| "d6590e90263af301": "Flash option control", | |
| "d6721d1c4f9add9e": "Programmable gain amplifier", | |
| "d68222fc7d794134": "Wakeup status clear and flags", | |
| "d68fb20941ae9b91": "Channel context ID configuration", | |
| "d6a032244d47663f": "Input 5 secure detection", | |
| "d6ae397577108f57": "Bidirectional Break Input", | |
| "d6e43baefc3ed047": "Extended interrupt and event masking", | |
| "d6f3135b0c2f3754": "Port F14-F15 and G0-G1 pull biasing", | |
| "d713cd8838bd47b1": "Channel 1 data output", | |
| "d726d90b36ebf8c4": "Complementary output 4 polarity", | |
| "d7401697f1289587": "Cryptographic accelerators", | |
| "d74fcaf4f0ed4ef3": "Calibration output selection", | |
| "d764d84e240bf2ee": "Extended security configuration", | |
| "d79172ecb76dae17": "Memory remap and system configuration", | |
| "d79724363b001d9f": "Fm+ mode and auto-clear", | |
| "d79786d4c98542fc": "Sub-second rollover update status", | |
| "d7c550fd8c077305": "Lock violation trap", | |
| "d7de4d3fcf0af5d5": "Ethernet MAC with Math Accelerator", | |
| "d7e57dd6302cb062": "Timer 4 freeze", | |
| "d8200a2b3cb189fa": "Cache hierarchy and neural processor", | |
| "d82194855778caac": "Debug authentication", | |
| "d82475048836551b": "Low-power features and clock distribution", | |
| "d8347dc2e02ed4f0": "Comprehensive extended support", | |
| "d847e480dad9e291": "Wakeup flag clearing", | |
| "d87ddaf95595b385": "Wakeup timer", | |
| "d88331e42449eb6c": "ECC monitor 3", | |
| "d8972a24dcb4cfca": "Security and debug options", | |
| "d8afa5c4335a6a1d": "Request source selection", | |
| "d8b2d14536e3986c": "PKA SRAM power-down", | |
| "d8bd122b50382ea4": "CAN 2", | |
| "d8d6db069e98133b": "CR2 register", | |
| "d8eb76055f8ccd95": "Advanced encryption modes", | |
| "d904a7e75ed4424d": "SDMMC card interface", | |
| "d9101a0002acb9f2": "External tamper inputs 4-8", | |
| "d9466f983c5bbe8d": "Output and blanking", | |
| "d9500148bf7c602b": "Secondary input selection", | |
| "d957b39e87be3ec1": "Extended AES key storage", | |
| "d96fcbbb20a3e61d": "Peripheral mode configuration", | |
| "d97070a10a1985b6": "Line 0 pending flags", | |
| "d97df1389665ff59": "Hardware configuration 3", | |
| "d9aad999dc8e3bbb": "LPTIM1 output routing", | |
| "d9c70f257bb5d9e4": "USB and MCO outputs", | |
| "d9c8553b6683c206": "External memory and ADC control", | |
| "d9d12c5c09fcc11c": "Comparator 3 break2 input", | |
| "d9e916501bc8ba6c": "TIM3 freeze", | |
| "d9ee1d0e36cb428e": "Master-slave status register", | |
| "d9f57b2edb936ff7": "Extended timer and peripheral DMA remap", | |
| "d9fd0b8dab47c559": "Trigger Input Selection", | |
| "da12598c08ff05d5": "Floating point unit interrupts", | |
| "da35330f43a499da": "Line 18 trigger and pending", | |
| "da6b76b5d3e63e79": "SRAM3 single error correction", | |
| "da74dea118ede7e8": "Bank 2 access and operations", | |
| "da90c405ad93b207": "I2C2 Fast-mode Plus", | |
| "daa1a4a22aedf70f": "ECC monitor 6", | |
| "daa3855c024adf32": "CAN and ADC trigger remapping", | |
| "daba60f0438dae50": "Temperature sensor", | |
| "dae33d73bd7a65a6": "I2C4 interface", | |
| "daf0d5f818b57ebc": "STOP mode wake-up interrupt", | |
| "daf5043915c2cfd2": "Extended line CPU2 interrupt support", | |
| "daf632a70c69eb5b": "Test mode", | |
| "db08c55cfcbed051": "Extended interconnect with long burst", | |
| "db3cef047ac20b3b": "Peripheral request routing", | |
| "db4562c56681b31e": "2D graphics acceleration", | |
| "db69912d96c2da3e": "Extended UART, CAN, and SAI support", | |
| "db69efd4a19d2a9f": "Interrupt flags", | |
| "dbc068cbb3039405": "Output Compare 1 mode extension", | |
| "dbc2170b39f78303": "Write Protection Pages 32-63", | |
| "dbe08972b5c02d27": "Backup registers 16-31", | |
| "dc0b65ea09e752b6": "Pin input/output data", | |
| "dc13949ecdc84c43": "Analog Comparator", | |
| "dc438971c5f4f527": "Cortex LOCKUP output", | |
| "dc4e18ad20f8f8e4": "Analog and LCD support", | |
| "dc5c28f065fc8b3a": "HSPI I/O compensation", | |
| "dc61655398ecc93e": "PLL predivider", | |
| "dc73095a65348d79": "Flash programming operations", | |
| "dc8b80d2861ec238": "Extended peripheral interfaces", | |
| "dca3a3dc8129b6dd": "Ethernet PHY interface mode", | |
| "dca8a096465242f4": "GPDMA debug suspend", | |
| "dcb66b4c78331bb2": "NPU QoS and RAM interleaving", | |
| "dcbecb81e6c413c2": "Output compare reference clear", | |
| "dce593002291e6bd": "Channels 5 and 6 capture/compare", | |
| "dd135e92881d5ccc": "Window and blanking", | |
| "dd28007e855eff37": "ECC monitor 4", | |
| "dd39085ae8577a82": "Break input enable and polarity", | |
| "dd399f7fed51aaab": "Bank 2 write protection", | |
| "dd3b9ef1626f8566": "Secure flash sizing", | |
| "dd51e20bab2589c8": "Line 17 security and privilege", | |
| "dd55f860257feeb6": "VDD compensation cell control", | |
| "dd618a84fd473f80": "D3 pending clear select", | |
| "dd67fecb4688cb38": "Secure area size", | |
| "dd991af6ddf31784": "Bank 4 NAND and PC Card interface", | |
| "ddaba947c860ddb3": "GPIO D and memory controller", | |
| "ddabfdc6eba81438": "AES accelerator", | |
| "ddd7ade4aaac5309": "Lines 10-11 pending mask", | |
| "ddf6af7cbdaed50b": "Dual SRAM ECC Error Protection", | |
| "de002ffe14f38ce5": "FIFO mode with prescaler", | |
| "de2999cb31516bcd": "Channel 1 DMA underrun", | |
| "de3d618760d46110": "I2S PLL input divider", | |
| "de485a7643d644ee": "USB switch", | |
| "de5036eb44a94a25": "Programming and cache management", | |
| "de5263fbd3847d8d": "Extended channel selection", | |
| "de5b642baa2da245": "PLL multiplication factor", | |
| "de869b87c81ea805": "Advanced tamper detection", | |
| "dec66c07d14d7c74": "Oscillator 1-3 control", | |
| "dedaa84cb546d6fb": "Commutation interrupt and DMA", | |
| "deed35519dc4bc45": "Line 23 privilege configuration", | |
| "defc60001d0f1f6f": "Event masking for select lines", | |
| "df023c65c991b50c": "Trace and debug freeze", | |
| "df07dd9fd3d84f6a": "Display and USB", | |
| "df114693a7d31e4a": "Extended interrupt configuration", | |
| "df12fa985245a056": "DSI pad pull-down disable", | |
| "df281f0d682db81c": "VREFINT and ADC references", | |
| "df338423d3fc701f": "Input selection", | |
| "df389548e86bd247": "GPIOE port and peripheral routing", | |
| "df3f3986e9d28a19": "Page protection configuration", | |
| "df8f783513df49fb": "Tamper 4 active mode selection", | |
| "dfb916fa9e8be169": "Write protection region 1", | |
| "dff813abd770f760": "Memory and USB power control", | |
| "e000c1a8b4e9e2f3": "Secondary PLL and USB OTG support", | |
| "e007cdf65168cf9d": "Digital filter modulator", | |
| "e010f4dbc44a97dd": "Line 0 trigger and interrupt", | |
| "e01d5b1527242560": "Output Compare Clear and Input Remap", | |
| "e0279d776bfd217a": "TIM9-11 remapping", | |
| "e02d2939fa3f9337": "RAM retention configuration", | |
| "e033f72531eb06f1": "Channel 2 capture/compare", | |
| "e0704b24149a313f": "Slave Mode Synchronization", | |
| "e090b01b3a52291e": "High-range security and privilege", | |
| "e093124f2daa7d56": "Control and configuration", | |
| "e0966fb15a064725": "GPIO pull-up and pull-down", | |
| "e096f4951af352c5": "TIM1 TIM6-7 DAC DMA remapping", | |
| "e09b54c9e86277c4": "Tamper detection output", | |
| "e0a6329de7d77aab": "Tamper 3 input", | |
| "e0db443bceaa4157": "Line 28 interrupt and event mask", | |
| "e0dd9b5ca7e73aa0": "Falling interrupt pending flags", | |
| "e0ee2770e83eee4b": "Offset trimming", | |
| "e11b75d568c7f8a6": "LCD and USB support", | |
| "e11d5801bd07ae17": "General and advanced timers freeze", | |
| "e1288bc43b985680": "Component identity registers", | |
| "e13b0b4c6fd2e198": "Break2 bidirectional input", | |
| "e13cf7469e32a974": "Line 21 pending mask", | |
| "e1455b576e22dfeb": "Trace port clock enable", | |
| "e148037aaf76150c": "Extended interrupt and event", | |
| "e15b78fe29a6b919": "CAN freeze", | |
| "e18b87f5bbdd7901": "Backup registers 2-4", | |
| "e18f59ca9d623d6a": "I2C3 fast mode plus", | |
| "e195182f316e5479": "Comparator 3 break input", | |
| "e1d2bf0bb52bd1bd": "ADC 1", | |
| "e1fc75ef2bc7de53": "Port F GPIO and SRAM4 power-down", | |
| "e20b1a779716d011": "PLL input divider selection", | |
| "e2144028704aba62": "DMA2 request line remapping", | |
| "e216764983a84324": "Peripheral voltage monitoring output 4", | |
| "e21f91f9731ca39a": "Dual CAN filter allocation", | |
| "e22084ec1f5b1158": "AES interrupt", | |
| "e240a0be63e06432": "USB supply monitor", | |
| "e254a61379590610": "Internal timestamp", | |
| "e264feb06399c8fd": "Channel 0-1 input delay", | |
| "e28f428909c1f6e6": "Internal voltage reference", | |
| "e2b1cfd7eefeb472": "I2C 3 freeze", | |
| "e2e4c329ba4205db": "I2C3 and TIM1 stop", | |
| "e2f10f8cfd6ae056": "OUT status phase received interrupt", | |
| "e306a20745edbffc": "Voltage detection", | |
| "e31e258728da7203": "Pending interrupt flags", | |
| "e330b7be72a7646d": "Large digest with word counter", | |
| "e3370bf3bee19ebd": "Line 37 trigger control", | |
| "e33c595f95b90043": "Timestamp recording", | |
| "e34aeaabecd09781": "Write Protection Pages 0-7", | |
| "e354ffbc2651531a": "I2C3 debug freeze", | |
| "e362b0f00de5ba82": "Line 39 interrupt and event", | |
| "e36a98f7edb0d6f1": "Comparator 1 break source", | |
| "e3777b6f5c83316c": "CPU2 extended interrupt masking", | |
| "e37aa78d90807bee": "SRAM6 power-down", | |
| "e38e484c863a6dad": "Line 0 interrupt configuration", | |
| "e3a7b49636a03e7e": "TrustZone and privilege control", | |
| "e3ccdf6f216ca635": "External trigger remap", | |
| "e3d97c63e1867966": "Timers 16 and 17 freeze", | |
| "e3dfe797dd8fb0d2": "System Break and Alternate Functions", | |
| "e3e7f491fcbd5db4": "Write protection areas", | |
| "e3f7fda21d8b9be4": "Extended mask register variants", | |
| "e40dd4629ba9885a": "Line 25 event and interrupt masking", | |
| "e43a1c04761974c9": "Request source selection", | |
| "e444f48f5aa41549": "SAI1 audio interface", | |
| "e44b6c82bc08b5ef": "SRAM2B write protection pages", | |
| "e45476995353c679": "Internal inputs 1-2 detection and control", | |
| "e46d5873d92031f8": "Secure flash operations", | |
| "e470aa5a10301617": "Dual-bank power-down and lock", | |
| "e4776d49a0924236": "Extended interrupt status", | |
| "e4bb2db27ace6df2": "Analog signal processing", | |
| "e4c11cb1c75e9e2b": "Bank 2 block protection", | |
| "e4cc8a7f1eac8ac0": "Debug freeze register set", | |
| "e4f1318e3626c3a3": "GPIO ports F/G and FSMC", | |
| "e4f8a8a3185a821e": "Early interrupt acknowledge", | |
| "e50cd7e037c28700": "Lines 57 and 59 masking", | |
| "e51ea69937483a2c": "Backup register access control", | |
| "e548952f8f273b14": "TIM4 remapping", | |
| "e54bb124bfe27479": "SMPS security control", | |
| "e5598e3af9588c89": "Analog and RF edge detection", | |
| "e567fb9cc175b211": "OCREF clear input selection", | |
| "e568e5c82a60a2fc": "I2C 3 clock source selection", | |
| "e57640810bbfcfb6": "CPU interrupt masking", | |
| "e578da060484855d": "Extended write protection", | |
| "e5865b6e3a3a4491": "GPDMA high channels freeze", | |
| "e5880cf4bb763941": "Fractional baud rate divisor", | |
| "e58c935edc001270": "HSI48 DIV6 output", | |
| "e59470f3d758de46": "Trigger Configuration", | |
| "e5c3319e7eb82619": "Port G pull-up", | |
| "e5d64623a5f7c403": "Infrared modulation control", | |
| "e5e18dea9b583021": "Input line 22", | |
| "e5f632c8ed9184a1": "Line 45 event mask", | |
| "e622f7103a8a0145": "TIM6 and I2C2 freeze", | |
| "e6237a35046bf951": "Alternate channel selection", | |
| "e64013573474821b": "Hardware request selection", | |
| "e685508aa15de16c": "Channel 2 and slave mode", | |
| "e6a8b337a6d02d98": "Timer 6 freeze", | |
| "e6aa194b639ab479": "Dual-core inter-processor communication", | |
| "e6cf06efa67aaf0b": "Channels 5 and 6", | |
| "e6eadada38d3f823": "State suspension", | |
| "e6fbfac74b2e8681": "HRTIM1 counter halt", | |
| "e725e7ac283060c0": "Single and double error correction", | |
| "e7374bb8d5c3033e": "Dual ADC mode", | |
| "e74df72e67950931": "DMA1 request remapping variants", | |
| "e74eb9925cec1646": "Multimode operation", | |
| "e7666b53df33f429": "RTC stop in debug", | |
| "e77dff04e12f0ede": "External wake-up line control", | |
| "e79866cccdf6d3fd": "Write protection and validation", | |
| "e7a2cc7fd0bd1bc3": "CAN freeze", | |
| "e7c23add9710fd9b": "Internal tampers 3, 5, 6", | |
| "e7c8d8b64310a5bb": "Timer 2 freeze", | |
| "e7e6a53a56d7893e": "Guard time transmission complete", | |
| "e806f04d9961398c": "TIM16/17 freeze", | |
| "e8186760623f0b34": "External clock input", | |
| "e81d796e5bd0efa3": "Lines 40-41 pending flags", | |
| "e81eac613d25ad3f": "Capture/Compare Channels 3-6", | |
| "e837e604eb181a98": "Advanced health testing", | |
| "e83c1579499db996": "Cipher algorithm modes and context", | |
| "e858b9c835be09ee": "AHB error detection", | |
| "e85d41714e9b8514": "AES accelerator clock enable", | |
| "e85d56f5c1829c02": "Alarm B register", | |
| "e874e591af5e11d8": "ADC and USART DMA remap", | |
| "e879be1046dfcbf4": "Channels 8-11 secure state", | |
| "e8a2de93bed40fcc": "HDP area configuration", | |
| "e8a7148e969e4798": "CAN2 stop in debug", | |
| "e8c24950641e4c19": "Random value output", | |
| "e8c2e6d60fb769ce": "LCD clock", | |
| "e8c3ce2055a80496": "Pin 11 high-speed low voltage", | |
| "e8f7f18b43db8400": "TAMP3 output selection", | |
| "e91cbc5a249412c4": "Port F/G pull and SRAM power", | |
| "e91e4dd3b0165f3d": "Line 17 edge selection", | |
| "e93113e1e0954b87": "APB peripheral clock control", | |
| "e932925ce3d06472": "Line 17 privilege enable", | |
| "e9440ef5fd8c686c": "ECC Write Protection", | |
| "e97ffd5ba1a18bed": "Apply pull-up and pull-down", | |
| "e98cd1e9715ea880": "Core power mode and voltage control", | |
| "e98d8b32226ff9c6": "Window mode", | |
| "e9995471cbe98585": "Sigma-Delta ADC and Timer 18", | |
| "e9b469f928ca2ef6": "Channel 18 sampling time", | |
| "e9cf6b487aa996d2": "Library Segment Configuration", | |
| "e9d20ab32d8c6df8": "Internal tamper 4", | |
| "e9d77805a42a19df": "Extended wake-up and debug", | |
| "e9e9e481967bcf64": "Repetition and update control", | |
| "ea164aa692fa13fb": "Algorithm mode selection", | |
| "ea1f3e1188e976e3": "SRAM1 Page 5 and Port E", | |
| "ea28a6fc86e735c8": "Random number output", | |
| "ea2b56d9f9907160": "SRAM6 power-down", | |
| "ea47319266186058": "Power monitoring features", | |
| "ea572e6040edcb46": "SRAM2B write protection pages", | |
| "ea733b7c4519a01c": "Enable wake-up pin 4", | |
| "ea73f7f46742e09b": "I2C Fast mode plus and compensation", | |
| "ea76f2807275d225": "Extended PDM clocking", | |
| "ea7b19c5ff0ba12a": "Dual supply compensation and security locking", | |
| "eab08c568b1b588a": "UCPD2 interrupt", | |
| "eada675c24ef1ba9": "DFSDM multi-channel delay control", | |
| "eae9fe403b171b5e": "UCPD standby and dead battery", | |
| "eaf5c117ba90aea8": "Serial Interface and Digital Filtering", | |
| "eafd6c050d094cf1": "Line 26 event mask", | |
| "eb11cc3a0b8ee6d8": "Memory and I2C fast-mode configuration", | |
| "eb25ffe64bc03e2a": "Timer 2, I2C 3, and TSC", | |
| "eb3428ebd7ad737e": "General and advanced timers freeze", | |
| "eb5bebf748d408ff": "FIFO Threshold Interrupt", | |
| "eb7909a1c0fe4cb1": "Multimedia and memory interfaces", | |
| "eb865e16272dc970": "Option register", | |
| "eb9c3ad90e059ab6": "CRAM page size", | |
| "eb9f352ee2f4ac11": "I2C2 Fast Mode Plus", | |
| "eba7ed8f2f275891": "Write protection pages 64-79", | |
| "ebb23737e1ba26b7": "Wake-up flag 3", | |
| "ebb484214a21164c": "CCB access control", | |
| "ebcddd69c865635e": "Privileged region access control", | |
| "ebdf2d29e7de738f": "PA4 GPIO retention", | |
| "ebfd246190219b73": "GPIO source selection, EXTI 0-15", | |
| "ec0b97869e6c9cc2": "Input line 54", | |
| "ec0cff8c2cbcfb2b": "Extended APB1 freeze", | |
| "ec13aa82d8076da4": "Touch sensing comparator configuration", | |
| "ec15774bcf872fa2": "OEM boot key storage", | |
| "ec403e65a5921f9a": "HSE/32 clock enable", | |
| "ec470c3161be4cab": "Event mask", | |
| "ec5581902f7ab0b9": "Lines 10-11 interrupt and event masking", | |
| "ec79a0234aadd623": "Line 66 trigger and privilege control", | |
| "ec85ceb3a30c9558": "Synchronization for channels 5-6", | |
| "ecc10f9f63a8d010": "Port configuration", | |
| "ecc509b7df7bc143": "General peripheral support", | |
| "ecd86f317ccc045f": "Line 35 interrupt and event masks", | |
| "ece182a35ebfefd5": "Segment configuration", | |
| "ececbf910973d78d": "Backup domain features", | |
| "ecf3f4a82abae4f7": "LIN Break Detection and Wake-up", | |
| "ed03acff98929499": "SRAM6 parity error address", | |
| "ed05c8d5f729eba2": "Line 35 trigger control", | |
| "ed1ea0b4482db75a": "Touch sense comparator mode", | |
| "ed2126d7a762ad65": "Calibration output", | |
| "ed22430ba3860a10": "I2C3 fast mode plus", | |
| "ed383e332ef1d317": "LDO power management", | |
| "ed396f31041df1a8": "Flash watermark protection", | |
| "ed3ab668b5d8989b": "Secure memory operations", | |
| "ed479f8a3618c175": "Flash power-down and Wake-Up Pin 6", | |
| "edba5929f37cecec": "SRAM1 and GPIO standby retention", | |
| "eddb318e6917aad2": "Write protection regions 6-7", | |
| "eddbe076bb0c2150": "FM+ I2C and compensation", | |
| "eddda3b391dbc91d": "Layer 1 window vertical stop", | |
| "ede50e578ddbc2de": "Configuration control", | |
| "edfc0811cfdf0d10": "Peripheral signal remapping", | |
| "edfd30c384216834": "RTC and CAN debug stop", | |
| "ee102eaf79391f8d": "Alternate function option register 2", | |
| "ee27b8c3ed0d6825": "Memory Wrap Mode", | |
| "ee4b1eeda92a3540": "First bank trigger and event configuration", | |
| "ee4fa9083c2964b9": "Wakeup pins 2-3 interrupt flags", | |
| "ee5d301b99f579fb": "SRAM protection and ADC trigger remapping", | |
| "ee6e34166c2d0024": "PWM output with autoreload", | |
| "ee824f9b96bc726a": "Input remap selection", | |
| "ee9fcb6f5658270e": "Memory and boot configuration", | |
| "eeae8fc5dd00cdf4": "Extended mode selection", | |
| "eebbf544ad16ff04": "Write protection regions 2-3", | |
| "eec9c24ffe13df8f": "High Speed and Range", | |
| "ef0b41d902a54fee": "Analog watchdog thresholds", | |
| "ef23d3bc40a7f0e4": "Multi-core interrupt masking", | |
| "ef3414a5f8434ec1": "Master/slave mode", | |
| "ef36335819939c5c": "Internal tampers 7-9, 11", | |
| "ef37072f5d6f7a51": "Debug freeze capability", | |
| "ef383e4636a0aa93": "Graphics and extended connectivity", | |
| "ef3ae71dfe54794b": "Interrupt control", | |
| "ef55debfb2b30d5e": "SRAM1 page 4 power-down", | |
| "ef57e8bdb28e0942": "Synchronization overrun status for channels 5-6", | |
| "ef5cdfbbfa01fdbf": "Channels 1 and 7 configuration lock", | |
| "ef620b517def3f18": "Privilege security control", | |
| "ef73283460b48f8d": "COMP2 inverting input selection", | |
| "ef74ef2299d148ac": "Break input source configuration", | |
| "ef7653a8e2acc9cf": "Port F and extended interfaces", | |
| "ef7efb7049991724": "Interrupt line 28", | |
| "eff5b4c470ef0d58": "Voltage monitoring and GPIO pull", | |
| "effcf81fc3f36700": "Extended peripheral access control", | |
| "f008ee3e3bee89b4": "External interrupt configuration", | |
| "f06d9b2d966106d6": "SDMMC2 clock selection", | |
| "f07a62d95a5b1e48": "MCO and HSI14 oscillator", | |
| "f07d809f9c9f89bd": "Autonomous safety control", | |
| "f0806a48bd31c791": "Regulator and Port D Pulls", | |
| "f092783bf90548ac": "Ethernet interface", | |
| "f0b57a890acc41a5": "Debug and bias current", | |
| "f0bb8e165700443c": "SmartCard support", | |
| "f0be5c1d1b7a139a": "Timestamp edge", | |
| "f0c12b9a71607c17": "TIM7 freeze", | |
| "f0d7d1b7c15c7b1b": "Flash operation address fields", | |
| "f10e2f90c02274c2": "Channel 2 Slave Mode", | |
| "f11702c695a79960": "USART2 clock selection", | |
| "f121eb39bf9d17b4": "TIM10 stop in debug", | |
| "f1222e3ecaf5aa25": "TIM12 stop in debug", | |
| "f12f6a359141222a": "Peripheral flow control", | |
| "f1507f08dc62b315": "USB interrupt", | |
| "f16d24ee5570ab69": "Analog output selection 5-6", | |
| "f175d7e32e66393a": "Independent I/Os supply monitoring", | |
| "f17a2a72ec9b4d8b": "Non-secure unlock and configuration", | |
| "f188ece12b58dc2f": "HSI48 oscillator and advanced peripherals", | |
| "f195bd7abee4aacf": "DFSDM1 break input", | |
| "f1a11ab21a09a9d0": "Regular and injected conversion", | |
| "f1a65be54e0aa94c": "Peripheral voltage monitoring 1 enable", | |
| "f1b8eb91c63cd51b": "Extended USART channels", | |
| "f1fbe87f33be8699": "Line 46 event mask", | |
| "f2105a57c204ce24": "Interrupt line 30", | |
| "f2153713e765b72b": "Analog comparator access control", | |
| "f2153af657ff3ed7": "USB and audio interfaces", | |
| "f230e1fec0a88c4d": "Interrupt line 0", | |
| "f2336a7d95051409": "Line 21 interrupt and event masking", | |
| "f23fff669f94d624": "GPIO port selection and masking", | |
| "f25f574f34eaf51b": "Voltage monitor interrupt", | |
| "f27a748955fe4993": "Advanced multi-channel PWM", | |
| "f287bba4f3a89f29": "Pin PE7 pull control", | |
| "f29902bb150f07d9": "Hamming ECC result", | |
| "f2a72057c1a343e9": "Random value output", | |
| "f2b90e181daa1eea": "Auto Baud-Rate Detection", | |
| "f2ef3f84c6f6bfdb": "Output configuration", | |
| "f3165e49b252362d": "Backup registers 20-31", | |
| "f32f686cc329f816": "Line 18 interrupt and event masking", | |
| "f342953b45a591d0": "Comparator interrupt masking", | |
| "f3516d6350f0cc79": "Timer 16 and 17 freeze", | |
| "f36d7bbcb1b0329c": "Hash accelerator", | |
| "f37dcda44d48b4b9": "Extended edge triggering", | |
| "f3867ed8a964d70f": "Low-voltage and ECC support", | |
| "f3870f3b51f20608": "IP identification and configuration", | |
| "f395bfa45c5a9f4e": "SRAM1 page 6 power-down", | |
| "f39c766afd4bcb92": "Power mode and hysteresis", | |
| "f3c0164a7b4fa33e": "Regular sequencer", | |
| "f3c08d18bd4eab5d": "External interrupt configuration", | |
| "f3c2931d9d630dc6": "USB Device interface", | |
| "f3c80285bddc5f7b": "Secure address and boot", | |
| "f3ca0fa56bf792de": "Wakeup timer", | |
| "f3d99007f76dc31c": "Capture/Compare 6", | |
| "f40d91fe78985fbd": "Read protection and options", | |
| "f41356f130f56f46": "Break and Commutation", | |
| "f42b9603a955231c": "QSPI interface", | |
| "f4344d5a31c1da7f": "Bank 1 security blocks", | |
| "f4427d3dff804897": "Break and repetition counter", | |
| "f4645d7f629333ac": "CPU2 I2C freeze", | |
| "f4665aa7a9228de7": "Capture/Compare Channels 3-4", | |
| "f4668e599945e31d": "Channels 1 and 2 capture/compare", | |
| "f46ea5471f606416": "Debug freeze control", | |
| "f470327de5a69dbf": "Interrupt mask configuration", | |
| "f475cfb54a870b3e": "Line 19 interrupt masking", | |
| "f47723947aa55176": "FMPI2C1 Fast Mode Plus drive", | |
| "f47ff2dcc6830dec": "Advanced timers freeze", | |
| "f49940ac389d42da": "Burst write programming", | |
| "f4ae3772ae1f6d9c": "CPU1 line 31 interrupt mask", | |
| "f4b1e076b39c2ed8": "General and advanced timer freeze", | |
| "f4d933c802429abb": "System locking", | |
| "f4ecbbed378df3b1": "Tamper control", | |
| "f4f3d4d9d4de7ad2": "Extended operation modes", | |
| "f4fa6bbe7ea55b05": "Port F pull-down", | |
| "f4fe646625766804": "Line 34 trigger configuration", | |
| "f50744ccf585fab3": "SMPS step-down converter", | |
| "f5227405b08f2453": "USB and FDCAN SRAM power-down", | |
| "f5423b2587e6774c": "Display serial interface", | |
| "f547c99580084487": "Tamper 3 input", | |
| "f554443ce4a10a5c": "Active tampering clock selection", | |
| "f55907c1138a1909": "Early interrupt support", | |
| "f56468cf0a082637": "Memory mapping and ADC decoupling", | |
| "f56c9d9aca458463": "D2 domain reset control", | |
| "f580e43e487da579": "DFSDM data path routing", | |
| "f5902402295c4036": "Extended output compare mode", | |
| "f59a32100dd33f5e": "Extended interrupt trigger and masking", | |
| "f59c7fb48025b809": "Context suspension", | |
| "f5ad17f382f67c17": "Optional features", | |
| "f5b0498327a5c5da": "I2C3 SMBUS timeout stop in debug", | |
| "f5bd376bdb4ef969": "RNG interrupt", | |
| "f5db4aa2b069678b": "Internal wakeup interrupts", | |
| "f630caeb70632e44": "Capture/Compare channels 3 and 4", | |
| "f63fc5c70540d070": "Break input filter", | |
| "f648b953862fe972": "Transfer security attributes", | |
| "f68fa3ceeabf919b": "Voltage scaling ready", | |
| "f69c752f164f1728": "Slave ADC with watchdogs", | |
| "f6af41a7b483e30a": "Memory watermark regions", | |
| "f6c0cabd95d0381f": "Clock error detection", | |
| "f6c9855d14d92957": "Backup registers 5-9", | |
| "f6ca8a30d46c9c51": "Cache and bank 1 PCROP", | |
| "f6ccc6193bcf288f": "PVD interrupt routing", | |
| "f6d412386c02cc96": "Context ID filtering", | |
| "f75e16a4f75f694c": "Capture/compare channels 5 and 6", | |
| "f75f33e83af5ef7f": "Hardware configuration and identification", | |
| "f76b2fc64d5a7fa6": "Synchronization overrun status for channels 14-15", | |
| "f78a2bfaeca35546": "Channel 8 configuration", | |
| "f7a981a85c8346e5": "Break Comparator 4 Polarity", | |
| "f7c164e247ac6041": "Wake-up pin 5 full control", | |
| "f7cb3f7e449f7c45": "Comparator and DAC interrupts", | |
| "f7d35892f85c8c91": "Boot address and status", | |
| "f7ec0f5d92dfd145": "USB OTG HS, camera, and audio", | |
| "f7ed62f68a4388ce": "Window stop position", | |
| "f8054312a246e472": "Output status and lock", | |
| "f807814c58cb6223": "Advanced timer freeze", | |
| "f8231bd43b9f1c8d": "Channel 7 configuration and addressing", | |
| "f84358fff27a2712": "External trigger source selection", | |
| "f84e410e3099ce41": "Wakeup and retention control", | |
| "f86aee568ccc5b77": "Advanced timer 1", | |
| "f86b76fb2e8a5a91": "FIFO threshold", | |
| "f893e1374e822744": "Break comparator control", | |
| "f89e4f447c9038f7": "Channel 4-5 transfer count", | |
| "f8a4a812be0b4c18": "Calibration register", | |
| "f8a7ee9e94f74072": "Motor control interrupts", | |
| "f8b3e4eb2fdde5d6": "Watchdog channel selection", | |
| "f8c3b2196ebe9948": "Infrared polarity and FPU interrupts", | |
| "f8e77f066b7c95f2": "Channel 2 sample and hold", | |
| "f8f20b662e7c7fc6": "Gain compensation calibration", | |
| "f90df17bd93eca50": "TIM1-3 oscillator debug configuration", | |
| "f915ed0875803e44": "Standby D2 debugging", | |
| "f92380cdb733e10c": "Secure detection flags 7 and 1-2", | |
| "f94fd2e7d79d0043": "Port D7 pull-up and pull-down", | |
| "f95925945ae6f570": "Dual-bank write protection", | |
| "f95d6fb6ea364fb2": "Line 29 edge trigger", | |
| "f96bfca1db413f19": "Core ID for semaphore access", | |
| "f975c4e69821b9cc": "Alarm A ready flag", | |
| "f9837c867ca004f9": "Buffer not available interrupts", | |
| "f99c4a7dfffc14a9": "Flexible CAN stop in debug", | |
| "f9bbfc5d13712696": "Lines 88-91 interrupt masking", | |
| "f9c3a8fe659f42b5": "Secure configuration and CPU locks", | |
| "f9cb3e0083389201": "Timer clock prescaler", | |
| "f9dac1af311efcd7": "Channel bank selection", | |
| "f9dbd7eb6f54b055": "SAI2 privilege configuration", | |
| "f9dc3ddd57ba9527": "Capture/Compare 1 value", | |
| "f9e63be4708830c0": "Device identification code", | |
| "fa0363ebb6c05d64": "Extended Write Protection", | |
| "fa0fccd112ef99a1": "PHY interface selection", | |
| "fa2197499b301d19": "Dead Time and Break", | |
| "fa28ed229c13e395": "CAN remapping", | |
| "fa5e5450f1d94739": "Configuration lock", | |
| "fa944289b91ca06a": "Dual-processor interrupt masks", | |
| "fa95a94ed26ee0a9": "Audio filter and FDCAN", | |
| "fa993603818502dd": "I2C2 freeze", | |
| "faa120ae94a4c4a5": "Groups 1 and 3 I/O configuration", | |
| "faa34917197dcb09": "Channels 3 and 4 values", | |
| "faa8549b71395db1": "Comparator power mode", | |
| "fabb723a5ce13177": "Timer 15 and SPI 4", | |
| "fac9108f6218d437": "Lines 81, 82 trigger and interrupt control", | |
| "fad50e42464d8793": "Extended sampling time", | |
| "fadae1d1aa4e5bbc": "SDA Hold Timing", | |
| "fae690b7a6cde8d9": "Line 57 interrupt and event mask", | |
| "faf5c22233a24e6d": "Control with alternate outputs", | |
| "fb0b227a305be992": "Calibration and watchdog monitoring", | |
| "fb0f78545e87da52": "Seed error and data output", | |
| "fb114a7952f4a5d5": "Channel 6 memory address", | |
| "fb18cfa9ed9d2bac": "Extended EXTI lines 61-66", | |
| "fb2106795ea034b4": "Cryptographic accelerator and timer", | |
| "fb22dbef546bf05a": "APB freeze and trace", | |
| "fb2c42153551b6e8": "Line 22 interrupt masking", | |
| "fb3659215b6f0652": "Port D high pins pull", | |
| "fb4873c2b8dcd040": "TIM5 channel 4 internal remapping", | |
| "fb4acfdb67880bff": "Line 39 trigger configuration", | |
| "fb819b47ebb524d0": "Extended UART support", | |
| "fb82398bf9d49c40": "LCD-TFT Display Controller", | |
| "fb8350c4bd0fab24": "Capture/Compare 2", | |
| "fb920c93c620baba": "Mode register", | |
| "fb9858b3879bfae9": "SRAM Parity Timer Break", | |
| "fb9d431ef6b51709": "Parity error address", | |
| "fb9e21f6ef89e29b": "SRAM3 ECC and Protection", | |
| "fba6354c49478c08": "Wake-Up Pin 3 and GPIO", | |
| "fbadf0741afd721e": "Line 17 trigger and pending", | |
| "fbc1bcd832053ffb": "Extended write protection", | |
| "fbca157070dd95e7": "USB security control", | |
| "fbd2723e327c1785": "Secondary detection mode", | |
| "fbddd70f74833150": "SRAM4 Power-down", | |
| "fbe8f3dd92a4ba40": "System PLL configuration", | |
| "fbf538530fabc9cb": "Extended interrupt and event masking", | |
| "fc1ed02de784b47b": "Display Serial Interface", | |
| "fc2f34944b6ec42f": "UCPD Strobe Signals", | |
| "fc3010b84cbbabb7": "Secure encryption and MCE support", | |
| "fc333a68ccaefe11": "D3 pending mask control", | |
| "fc399428d56c07bf": "Synchronous timing configuration", | |
| "fc3f82a5c61563d9": "SRAM2 run mode power-down", | |
| "fc6378930093421e": "COMP2 output polarity", | |
| "fc6705e573fa2153": "I2C Fast Mode Plus PA10", | |
| "fc6b8bbfeb638e43": "Channel 4 complementary output", | |
| "fc8a9a0687717c72": "Alarm B", | |
| "fc991ea1b03f68d9": "Voltage scaling ready", | |
| "fca21c57154ad73e": "Crop enable", | |
| "fcacddaa47d54678": "Memory and specialized accelerators", | |
| "fcb26f4a7eb91297": "Dual-core processor support", | |
| "fcb90f10c308daeb": "Dual buffer DMA with FIFO", | |
| "fcbdb9630c13cded": "Power control basics", | |
| "fcbf8b563dc22614": "Line 23 event masking", | |
| "fcc6c01cea516c85": "Unified pending interrupt status", | |
| "fcc9e1d27f538917": "I3C interface", | |
| "fccd935f33d651d7": "Lines 32-33 interrupt and event masks", | |
| "fccde78647d7dcf5": "External tamper 4", | |
| "fcf297e85580c7c2": "Memory power-down and USB-C", | |
| "fd1638b46a77a03e": "PLLSAI R divider", | |
| "fd3bd20bf2ab3fec": "Comparator access control", | |
| "fd550e05cdcb0e72": "TIM16/17 freeze", | |
| "fd74932b48fcddc5": "SRAM3 error correction", | |
| "fd8e153adfec963d": "Continuous clock and write FIFO control", | |
| "fdb78fe9d47a7c4d": "Channels 1 and 7 secure state", | |
| "fdcc6455b9fe7a7a": "SRAM2 write protection pages 20-31", | |
| "fde70b512800928a": "Low-power DMA freeze", | |
| "fdf003830b275887": "USB HS PHY tuning", | |
| "fe0af59ebc9af4c8": "ECC error detection", | |
| "fe3a8f55b6905e74": "Timer DMA remapping", | |
| "fe3b16652ecb7ebb": "Main interrupt pending", | |
| "fe3f27d5608352c2": "TIM16 Interrupt", | |
| "fe49d920bd06bcb2": "SRAM protection and sector erase", | |
| "fe514750a3e3e713": "GPIO ports F and G", | |
| "fe5ea7d2ba8dc6c3": "Master-Slave ADC status and data", | |
| "fe6c1a963987bb35": "Data register", | |
| "fe7b5e97f6d43753": "Analog watchdog 2 and 3", | |
| "fe803c892f687876": "PVD lock", | |
| "fe8ec67b4f1e6f7f": "VDDIO compensation code", | |
| "fe929c1a3f904993": "QSPI controller and low-power support", | |
| "fea5fbbb1c4ae63b": "Autonomous mode", | |
| "febac888d542e369": "Configurable hysteresis", | |
| "fec4679d4319587e": "Timer 16 stop in debug", | |
| "fec8156e966d1e1c": "External tamper 6, 7, and 8", | |
| "fefe6fe5dd1a573a": "SRAM2 page 2 retention", | |
| "ff04626db87b5651": "Timestamp on internal event", | |
| "ff1c6cda4ee973ce": "Cryptographic accelerators", | |
| "ff1d31afc247f0aa": "Voltage detection and SRAM power-down", | |
| "ff269f8ac447c402": "Advanced FIFO and DMA", | |
| "ff449e2abe919bdb": "CPU interrupt masking", | |
| "ff4574d475380465": "TIM5 stop in debug", | |
| "ff5bbcb4228e3f9c": "SRAM1 partial page power-down", | |
| "ff60556fedbe535b": "Line 35 pending flag", | |
| "ff7610a528b25406": "RTC stop in debug", | |
| "ff962299ab20075a": "HSI48 oscillator and recovery", | |
| "ffa0d0d09002385d": "VREFINT or 48 MHz oscillator", | |
| "ffca6788981cd735": "Calibration and oversampling", | |
| "ffd465ee31420b7d": "Power voltage detection output", | |
| "ffd4721c60611853": "All peripherals", | |
| "ffeeae3a2dc20550": "Port signal routing" | |
| } |
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| --ground: #F3F5F4; | |
| --surface: #FFFFFF; | |
| --band: #F8FAF9; | |
| --ink: #16201C; | |
| --muted: #5B6863; | |
| --faint: #85918C; | |
| --rule: #DDE3E0; | |
| --rule-strong: #C3CCC8; | |
| --accent: #1C6B56; | |
| --accent-ink: #FFFFFF; | |
| --accent-soft: #E2EFEA; | |
| --hover: #EEF4F1; | |
| --mark: #FBE3A0; | |
| --mark-ink: #16201C; | |
| --error: #B42318; | |
| --periph: #F1F4F2; | |
| --hatch: #CDD6D2; | |
| --reg-rw: #D3E8DF; | |
| --reg-rw-line: #2F7A64; | |
| --reg-ro: #DCE4EF; | |
| --reg-ro-line: #4A6A90; | |
| --reg-wo: #F2E6CF; | |
| --reg-wo-line: #946524; | |
| --font-sans: "IBM Plex Sans", system-ui, -apple-system, "Segoe UI", Roboto, sans-serif; | |
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| } | |
| @media (prefers-color-scheme: dark) { | |
| :root:not([data-theme="light"]) { | |
| --ground: #0E1311; | |
| --surface: #141A18; | |
| --band: #111715; | |
| --ink: #E2E8E5; | |
| --muted: #9AA8A2; | |
| --faint: #6E7B76; | |
| --rule: #232D29; | |
| --rule-strong: #34403B; | |
| --accent: #5FC0A0; | |
| --accent-ink: #0B1512; | |
| --accent-soft: #16302A; | |
| --hover: #19231F; | |
| --mark: #6A5616; | |
| --mark-ink: #FFF4D1; | |
| --error: #F4A39B; | |
| --periph: #111916; | |
| --hatch: #2A3531; | |
| --reg-rw: #1C3A31; | |
| --reg-rw-line: #5FC0A0; | |
| --reg-ro: #1D2837; | |
| --reg-ro-line: #8FB1D9; | |
| --reg-wo: #35291A; | |
| --reg-wo-line: #D8A85A; | |
| color-scheme: dark; | |
| } | |
| } | |
| :root[data-theme="dark"] { | |
| --ground: #0E1311; | |
| --surface: #141A18; | |
| --band: #111715; | |
| --ink: #E2E8E5; | |
| --muted: #9AA8A2; | |
| --faint: #6E7B76; | |
| --rule: #232D29; | |
| --rule-strong: #34403B; | |
| --accent: #5FC0A0; | |
| --accent-ink: #0B1512; | |
| --accent-soft: #16302A; | |
| --hover: #19231F; | |
| --mark: #6A5616; | |
| --mark-ink: #FFF4D1; | |
| --error: #F4A39B; | |
| --periph: #111916; | |
| --hatch: #2A3531; | |
| --reg-rw: #1C3A31; | |
| --reg-rw-line: #5FC0A0; | |
| --reg-ro: #1D2837; | |
| --reg-ro-line: #8FB1D9; | |
| --reg-wo: #35291A; | |
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| color-scheme: dark; | |
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| body { | |
| margin: 0; | |
| background: var(--ground); | |
| color: var(--ink); | |
| font: 14px/1.45 var(--font-sans); | |
| display: flex; | |
| flex-direction: column; | |
| gap: 14px; | |
| padding-inline: clamp(16px, 3vw, 32px); | |
| padding-block: 18px 16px; | |
| height: 100dvh; | |
| } | |
| .visually-hidden { | |
| position: absolute; width: 1px; height: 1px; overflow: hidden; | |
| clip: rect(0 0 0 0); white-space: nowrap; | |
| } | |
| /* Top bar */ | |
| .top { | |
| display: flex; flex-wrap: wrap; align-items: flex-end; justify-content: space-between; gap: 10px 24px; | |
| } | |
| .brand { display: grid; gap: 2px; min-width: 0; } | |
| h1 { | |
| margin: 0; font-size: 19px; font-weight: 600; letter-spacing: -0.01em; text-wrap: balance; | |
| } | |
| .file-line { | |
| margin: 0; color: var(--muted); font-size: 13px; | |
| display: flex; flex-wrap: wrap; align-items: center; gap: 4px 10px; | |
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| color: var(--accent); background: var(--accent-soft); border-radius: 4px; padding: 1px 6px; | |
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| .open { display: flex; align-items: center; gap: 10px; flex-wrap: wrap; } | |
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| .btn { | |
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| background: var(--surface); border: 1px solid var(--rule-strong); border-radius: 6px; | |
| padding: 7px 12px; cursor: pointer; white-space: nowrap; | |
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| .btn:hover { background: var(--hover); } | |
| .btn.primary { background: var(--accent); border-color: var(--accent); color: var(--accent-ink); } | |
| .btn.primary:hover { filter: brightness(1.08); } | |
| .btn.icon { width: 30px; padding-inline: 0; text-align: center; font-size: 15px; } | |
| .btn:focus-visible, .tw:focus-visible, .check input:focus-visible, .check select:focus-visible, | |
| .tab:focus-visible, .crumb:focus-visible { outline: 2px solid var(--accent); outline-offset: 2px; } | |
| #file-input:focus-visible + .btn { outline: 2px solid var(--accent); outline-offset: 2px; } | |
| /* Layout */ | |
| .layout { | |
| flex: 1; min-height: 0; | |
| display: grid; grid-template-columns: minmax(210px, 250px) minmax(0, 1fr); gap: 16px; | |
| } | |
| .main { min-width: 0; min-height: 0; display: flex; flex-direction: column; gap: 12px; } | |
| .panel { flex: 1; min-height: 0; display: flex; flex-direction: column; gap: 10px; } | |
| /* File menu */ | |
| .menu { | |
| min-height: 0; display: flex; flex-direction: column; gap: 8px; | |
| background: var(--surface); border: 1px solid var(--rule); border-radius: 8px; padding-top: 11px; | |
| } | |
| .menu-head { display: flex; align-items: baseline; justify-content: space-between; gap: 8px; padding-inline: 12px; } | |
| .menu h2 { | |
| margin: 0; font-size: 11px; font-weight: 500; letter-spacing: 0.07em; text-transform: uppercase; color: var(--muted); | |
| } | |
| .menu-count { font-size: 12px; color: var(--faint); font-variant-numeric: tabular-nums; } | |
| .menu .search { flex: none; margin-inline: 10px; font-size: 13px; padding-inline: 8px; } | |
| .menu .search input { padding: 6px 4px; } | |
| .menu-list { list-style: none; margin: 0; padding: 0 0 8px; overflow: auto; flex: 1; min-height: 0; } | |
| .menu-group { | |
| position: sticky; top: 0; background: var(--surface); | |
| padding: 9px 14px 3px; font-size: 11px; letter-spacing: 0.07em; color: var(--faint); | |
| } | |
| .menu-item { | |
| display: block; width: 100%; text-align: left; border: 0; background: transparent; cursor: pointer; | |
| color: var(--ink); font: 13px/1.35 var(--font-mono); padding: 3px 14px; | |
| } | |
| .menu-item:hover { background: var(--hover); } | |
| .menu-item[aria-current="true"] { background: var(--accent-soft); color: var(--accent); font-weight: 500; } | |
| .menu-item:focus-visible { outline: 2px solid var(--accent); outline-offset: -2px; } | |
| .menu-note { padding: 10px 14px; color: var(--muted); font-size: 12.5px; display: grid; gap: 6px; } | |
| .menu-note p { margin: 0; } | |
| .menu-note code { | |
| font-family: var(--font-mono); font-size: 11.5px; color: var(--ink); overflow-wrap: anywhere; | |
| background: var(--band); border: 1px solid var(--rule); border-radius: 4px; padding: 1px 4px; | |
| } | |
| /* Tools */ | |
| .tools { display: flex; flex-wrap: wrap; align-items: center; gap: 10px 18px; } | |
| .tabs { display: inline-flex; border: 1px solid var(--rule-strong); border-radius: 6px; overflow: hidden; background: var(--surface); } | |
| .tab { | |
| font: 500 13px/1 var(--font-sans); color: var(--muted); background: transparent; border: 0; | |
| padding: 8px 14px; cursor: pointer; | |
| } | |
| .tab + .tab { border-left: 1px solid var(--rule-strong); } | |
| .tab:hover { color: var(--ink); background: var(--hover); } | |
| .tab[aria-selected="true"] { color: var(--accent); background: var(--accent-soft); } | |
| .search { | |
| flex: 1 1 320px; min-width: 0; display: flex; align-items: center; | |
| background: var(--surface); border: 1px solid var(--rule-strong); border-radius: 6px; | |
| font-family: var(--font-mono); font-size: 14px; padding-inline: 10px; | |
| } | |
| .search:focus-within { border-color: var(--accent); box-shadow: 0 0 0 1px var(--accent); } | |
| .search.invalid { border-color: var(--error); box-shadow: 0 0 0 1px var(--error); } | |
| .delim { color: var(--faint); user-select: none; } | |
| .search input { | |
| flex: 1; min-width: 0; border: 0; outline: 0; background: transparent; color: var(--ink); | |
| font: inherit; padding: 7px 4px; | |
| } | |
| .search input::placeholder { color: var(--faint); } | |
| .check { display: inline-flex; align-items: center; gap: 6px; color: var(--muted); font-size: 13px; cursor: pointer; } | |
| .check input { accent-color: var(--accent); margin: 0; } | |
| .check select { | |
| font: 13px var(--font-sans); color: var(--ink); background: var(--surface); | |
| border: 1px solid var(--rule-strong); border-radius: 5px; padding: 3px 4px; | |
| } | |
| .actions { display: flex; gap: 6px; } | |
| .status { margin: 0; flex-basis: 100%; color: var(--muted); font-size: 12.5px; min-height: 1.45em; } | |
| .status code { font-family: var(--font-mono); color: var(--ink); } | |
| .status.error { color: var(--error); } | |
| .message { | |
| margin: 0; padding: 8px 12px; border: 1px solid var(--error); border-radius: 6px; | |
| color: var(--error); background: var(--surface); | |
| } | |
| /* Table */ | |
| .table-wrap { | |
| flex: 1; min-height: 220px; overflow: auto; | |
| background: var(--surface); border: 1px solid var(--rule); border-radius: 8px; | |
| } | |
| table { width: 100%; border-collapse: separate; border-spacing: 0; font-size: 13px; } | |
| th { | |
| position: sticky; top: 0; z-index: 1; background: var(--surface); | |
| text-align: left; font-weight: 500; font-size: 11px; letter-spacing: 0.07em; text-transform: uppercase; | |
| color: var(--muted); padding: 9px 12px; border-bottom: 1px solid var(--rule-strong); white-space: nowrap; | |
| } | |
| td { padding: 4px 12px; border-bottom: 1px solid var(--rule); vertical-align: top; white-space: nowrap; } | |
| tbody tr:hover td { background: var(--hover); } | |
| .num { font-family: var(--font-mono); font-variant-numeric: tabular-nums; } | |
| .off { color: var(--faint); margin-left: 6px; } | |
| td.c-name { padding-left: calc(6px + var(--d, 0) * 20px); } | |
| td.c-desc { white-space: normal; min-width: 260px; max-width: 70ch; color: var(--muted); } | |
| .nm { font-family: var(--font-mono); } | |
| .tw { | |
| width: 20px; height: 20px; padding: 0; margin: 0 2px 0 0; border: 0; border-radius: 4px; | |
| background: transparent; color: var(--muted); cursor: pointer; vertical-align: middle; | |
| display: inline-grid; place-items: center; | |
| } | |
| .tw:hover { color: var(--ink); background: var(--accent-soft); } | |
| .tw::before { | |
| content: ""; width: 6px; height: 6px; border: solid currentColor; border-width: 0 1.5px 1.5px 0; | |
| transform: translateX(-1px) rotate(-45deg); transition: transform 120ms ease; | |
| } | |
| .tw[aria-expanded="true"]::before { transform: translateY(-1px) rotate(45deg); } | |
| .tw-gap { display: inline-block; width: 22px; } | |
| .locate { | |
| position: relative; width: 16px; height: 16px; padding: 0; margin: 0 6px 0 -4px; border: 0; border-radius: 50%; | |
| background: transparent; color: var(--accent); cursor: pointer; vertical-align: -3px; opacity: 0; | |
| } | |
| .locate::before { content: ""; position: absolute; inset: 3px; border: 1.5px solid currentColor; border-radius: 50%; } | |
| .locate::after { content: ""; position: absolute; left: 7px; top: 7px; width: 2px; height: 2px; border-radius: 50%; background: currentColor; } | |
| tbody tr:hover .locate, .locate:focus-visible { opacity: 1; } | |
| .locate:hover { background: var(--accent-soft); } | |
| .locate:focus-visible { outline: 2px solid var(--accent); outline-offset: 1px; } | |
| @media (hover: none) { .locate { opacity: 0.7; } } | |
| .locate-gap { display: inline-block; width: 16px; margin: 0 6px 0 -4px; } | |
| tr.lv-peripheral td { background: var(--band); border-bottom-color: var(--rule-strong); } | |
| tr.lv-peripheral .nm { font-weight: 600; font-size: 13.5px; } | |
| tr.lv-cluster .nm { font-weight: 600; } | |
| tr.lv-register .nm { font-weight: 500; } | |
| tr.lv-field td.c-bits { color: var(--ink); } | |
| tr.lv-enum td { color: var(--muted); } | |
| tr.lv-enum .nm { color: var(--ink); } | |
| tr.flash td { animation: flash 1.6s ease-out; } | |
| @keyframes flash { from { background: var(--mark); } } | |
| mark { background: var(--mark); color: var(--mark-ink); border-radius: 2px; padding: 0 1px; } | |
| .tag { | |
| display: inline-block; margin-left: 8px; padding: 0 5px; border: 1px solid var(--rule-strong); border-radius: 4px; | |
| font: 11px/1.5 var(--font-mono); color: var(--muted); white-space: nowrap; vertical-align: 1px; | |
| } | |
| td.c-desc .tag:first-child { margin-left: 0; } | |
| .acc { | |
| display: inline-block; padding: 0 6px; border-radius: 4px; border: 1px solid var(--rule-strong); | |
| font: 11px/1.6 var(--font-mono); color: var(--muted); | |
| } | |
| .acc-ro { border-color: transparent; background: var(--accent-soft); color: var(--accent); } | |
| .acc-wo { border-style: dashed; } | |
| .bar { | |
| display: inline-block; width: 64px; height: 7px; margin-left: 10px; vertical-align: 1px; border-radius: 1px; | |
| background: | |
| repeating-linear-gradient(90deg, transparent 0 calc(25% - 1px), var(--surface) calc(25% - 1px) 25%), | |
| linear-gradient(90deg, transparent var(--l), var(--accent) var(--l) calc(var(--l) + var(--w)), transparent calc(var(--l) + var(--w))), | |
| var(--rule); | |
| } | |
| .empty td { padding: 28px 16px; color: var(--muted); white-space: normal; } | |
| .more { margin: 0; color: var(--muted); font-size: 12.5px; } | |
| /* Map */ | |
| .map-bar { display: flex; flex-wrap: wrap; align-items: center; justify-content: space-between; gap: 8px 16px; } | |
| .crumbs { display: flex; flex-wrap: wrap; align-items: center; gap: 2px; font: 13px var(--font-mono); min-width: 0; } | |
| .crumb { | |
| font: inherit; color: var(--muted); background: transparent; border: 0; border-radius: 4px; | |
| padding: 3px 5px; cursor: pointer; | |
| } | |
| .crumb:hover { color: var(--ink); background: var(--hover); } | |
| .crumb[aria-current="true"] { color: var(--ink); font-weight: 600; } | |
| .crumb-sep { color: var(--faint); } | |
| .map-controls { display: flex; flex-wrap: wrap; align-items: center; gap: 8px 16px; } | |
| .map-frame { | |
| position: relative; flex: 1; min-height: 320px; overflow: hidden; | |
| background: var(--surface); border: 1px solid var(--rule); border-radius: 8px; | |
| } | |
| #map { position: absolute; left: 0; top: 0; touch-action: none; cursor: grab; } | |
| #map.dragging { cursor: grabbing; } | |
| #map:focus-visible { outline: 2px solid var(--accent); outline-offset: -2px; } | |
| #overview { position: absolute; right: 0; top: 0; border-left: 1px solid var(--rule); cursor: pointer; touch-action: none; } | |
| .map-tip { | |
| position: absolute; z-index: 2; pointer-events: none; display: grid; gap: 1px; max-width: 360px; | |
| padding: 5px 8px; border-radius: 5px; background: var(--ink); color: var(--surface); font-size: 12px; | |
| } | |
| .map-tip strong { font: 500 12px var(--font-mono); overflow-wrap: anywhere; } | |
| .map-tip span { opacity: 0.8; font-family: var(--font-mono); font-size: 11.5px; } | |
| .map-card { | |
| position: absolute; z-index: 3; right: 68px; bottom: 12px; width: min(330px, calc(100% - 92px)); | |
| max-height: calc(100% - 24px); overflow: auto; display: grid; gap: 8px; | |
| padding: 12px 14px; background: var(--surface); border: 1px solid var(--rule-strong); border-radius: 8px; | |
| box-shadow: 0 8px 28px rgb(0 0 0 / 0.14); | |
| } | |
| .card-head { display: flex; align-items: center; justify-content: space-between; } | |
| .kind { font-size: 11px; letter-spacing: 0.07em; text-transform: uppercase; color: var(--muted); } | |
| .card-close { | |
| width: 24px; height: 24px; border: 0; border-radius: 4px; background: transparent; color: var(--muted); | |
| font-size: 18px; line-height: 1; cursor: pointer; | |
| } | |
| .card-close:hover { background: var(--hover); color: var(--ink); } | |
| .card-name { margin: 0; font: 600 14px var(--font-mono); overflow-wrap: anywhere; } | |
| .map-card dl { margin: 0; display: grid; grid-template-columns: auto 1fr; gap: 3px 12px; font-size: 12.5px; } | |
| .map-card dl div { display: contents; } | |
| .map-card dt { color: var(--muted); } | |
| .map-card dd { margin: 0; overflow-wrap: anywhere; } | |
| .card-desc { margin: 0; color: var(--muted); font-size: 13px; } | |
| .card-actions { display: flex; flex-wrap: wrap; gap: 6px; } | |
| .map-foot { display: flex; flex-wrap: wrap; align-items: center; justify-content: space-between; gap: 6px 16px; } | |
| .map-hint { margin: 0; color: var(--faint); font-size: 12.5px; } | |
| .legend { display: flex; flex-wrap: wrap; align-items: center; gap: 4px 12px; color: var(--muted); font-size: 12.5px; } | |
| .legend span { display: inline-flex; align-items: center; gap: 5px; } | |
| .key { width: 14px; height: 10px; border: 1px solid; border-radius: 2px; } | |
| .key-rw { background: var(--reg-rw); border-color: var(--reg-rw-line); } | |
| .key-ro { background: var(--reg-ro); border-color: var(--reg-ro-line); } | |
| .key-wo { background: var(--reg-wo); border-color: var(--reg-wo-line); } | |
| .key-free { | |
| border-color: var(--rule-strong); | |
| background: repeating-linear-gradient(135deg, var(--hatch) 0 1px, var(--periph) 1px 4px); | |
| } | |
| /* Drop overlay */ | |
| .drop { | |
| position: fixed; inset: 0; z-index: 10; display: grid; place-items: center; | |
| background: color-mix(in srgb, var(--ground) 82%, transparent); | |
| } | |
| .drop > div { | |
| padding: 36px 52px; border: 2px dashed var(--accent); border-radius: 12px; | |
| background: var(--surface); font-size: 16px; font-weight: 500; | |
| } | |
| @media (prefers-reduced-motion: reduce) { | |
| .tw::before { transition: none; } | |
| tr.flash td { animation: none; background: var(--mark); } | |
| } | |
| @media (max-width: 800px) { | |
| body { height: auto; min-height: 100dvh; } | |
| .layout { grid-template-columns: minmax(0, 1fr); } | |
| .menu-list { max-height: 32vh; } | |
| .table-wrap { min-height: 65vh; } | |
| .map-frame { min-height: 70vh; } | |
| } | |
| </style> | |
| <header class="top"> | |
| <div class="brand"> | |
| <h1>SVD Register Explorer</h1> | |
| <p class="file-line" id="file-line">No file loaded</p> | |
| </div> | |
| <div class="open"> | |
| <input id="file-input" class="visually-hidden" type="file" accept=".svd,.xml,text/xml,application/xml"> | |
| <label class="btn primary" for="file-input">Open SVD file</label> | |
| <span class="hint">or drop one anywhere on the page</span> | |
| </div> | |
| </header> | |
| <div class="layout"> | |
| <nav class="menu" aria-labelledby="menu-title"> | |
| <div class="menu-head"> | |
| <h2 id="menu-title">SVD files</h2> | |
| <span class="menu-count" id="menu-count"></span> | |
| </div> | |
| <label for="menu-query" class="visually-hidden">Filter SVD files by regular expression</label> | |
| <div class="search" id="menu-search"> | |
| <span class="delim" aria-hidden="true">/</span> | |
| <input id="menu-query" type="search" spellcheck="false" autocomplete="off" placeholder="f4|h7.*cm7"> | |
| <span class="delim" aria-hidden="true">/i</span> | |
| </div> | |
| <ul class="menu-list" id="menu-list"></ul> | |
| </nav> | |
| <main class="main"> | |
| <section class="tools" aria-label="View and filter"> | |
| <div class="tabs" role="tablist" aria-label="View" id="tabs"> | |
| <button class="tab" role="tab" type="button" id="tab-table" aria-controls="panel-table" aria-selected="true">Table</button> | |
| <button class="tab" role="tab" type="button" id="tab-map" aria-controls="panel-map" aria-selected="false" tabindex="-1">Map</button> | |
| </div> | |
| <label for="query" class="visually-hidden">Filter by regular expression</label> | |
| <div class="search" id="search"> | |
| <span class="delim" aria-hidden="true">/</span> | |
| <input id="query" type="search" spellcheck="false" autocomplete="off" | |
| placeholder="^USART\d+$ or CR1\.(RE|TE)"> | |
| <span class="delim" id="flags" aria-hidden="true">/i</span> | |
| </div> | |
| <label class="check"><input type="checkbox" id="scope-desc"> Descriptions</label> | |
| <label class="check"><input type="checkbox" id="match-case"> Match case</label> | |
| <div class="actions" id="table-actions"> | |
| <button class="btn" type="button" id="expand-all">Expand all</button> | |
| <button class="btn" type="button" id="collapse-all">Collapse all</button> | |
| </div> | |
| <p class="status" id="status" role="status"></p> | |
| </section> | |
| <p class="message" id="message" role="alert" hidden></p> | |
| <section class="panel" id="panel-table" role="tabpanel" aria-labelledby="tab-table"> | |
| <div class="table-wrap"> | |
| <table> | |
| <thead> | |
| <tr> | |
| <th scope="col">Name</th> | |
| <th scope="col">Address</th> | |
| <th scope="col">Bits</th> | |
| <th scope="col">Access</th> | |
| <th scope="col">Reset</th> | |
| <th scope="col">Description</th> | |
| </tr> | |
| </thead> | |
| <tbody id="rows"></tbody> | |
| </table> | |
| </div> | |
| <p class="more" id="more" hidden></p> | |
| </section> | |
| <section class="panel" id="panel-map" role="tabpanel" aria-labelledby="tab-map" hidden> | |
| <div class="map-bar"> | |
| <nav class="crumbs" id="crumbs" aria-label="Map location"></nav> | |
| <div class="map-controls"> | |
| <label class="check"><input type="checkbox" id="map-dense"> Hide empty rows</label> | |
| <label class="check">Words per row | |
| <select id="map-row"> | |
| <option value="16">4</option> | |
| <option value="32">8</option> | |
| <option value="64" selected>16</option> | |
| <option value="128">32</option> | |
| <option value="256">64</option> | |
| </select> | |
| </label> | |
| <div class="actions"> | |
| <button class="btn icon" type="button" id="zoom-out" aria-label="Zoom out">−</button> | |
| <button class="btn icon" type="button" id="zoom-in" aria-label="Zoom in">+</button> | |
| <button class="btn" type="button" id="zoom-fit">Fit width</button> | |
| </div> | |
| </div> | |
| </div> | |
| <div class="map-frame" id="map-frame"> | |
| <canvas id="map" tabindex="0" aria-describedby="map-hint" | |
| aria-label="Address space map. Arrow keys move, plus and minus zoom, Escape clears the selection."></canvas> | |
| <canvas id="overview" aria-hidden="true"></canvas> | |
| <div class="map-tip" id="map-tip" hidden></div> | |
| <aside class="map-card" id="map-card" aria-live="polite" hidden></aside> | |
| </div> | |
| <div class="map-foot"> | |
| <p class="map-hint" id="map-hint">Scroll to move · Ctrl or ⌘ + scroll, or pinch, to zoom · Double-click to zoom in · Click for details</p> | |
| <div class="legend"> | |
| <span><i class="key key-rw"></i>read-write</span> | |
| <span><i class="key key-ro"></i>read-only</span> | |
| <span><i class="key key-wo"></i>write-only</span> | |
| <span><i class="key key-free"></i>unused</span> | |
| </div> | |
| </div> | |
| </section> | |
| </main> | |
| </div> | |
| <div class="drop" id="drop" hidden><div>Drop the SVD file to open it</div></div> | |
| <script type="text/plain" id="example-svd"><?xml version="1.0" encoding="utf-8"?> | |
| <device schemaVersion="1.3"> | |
| <vendor>Example</vendor> | |
| <name>EXAMPLE_MCU</name> | |
| <version>1.0</version> | |
| <description>Example device with a few typical peripherals</description> | |
| <addressUnitBits>8</addressUnitBits> | |
| <width>32</width> | |
| <size>32</size> | |
| <access>read-write</access> | |
| <resetValue>0x00000000</resetValue> | |
| <resetMask>0xFFFFFFFF</resetMask> | |
| <peripherals> | |
| <peripheral> | |
| <name>TIM2</name> | |
| <description>General-purpose timer</description> | |
| <groupName>TIM</groupName> | |
| <baseAddress>0x40000000</baseAddress> | |
| <interrupt><name>TIM2</name><description>TIM2 global interrupt</description><value>28</value></interrupt> | |
| <registers> | |
| <register> | |
| <name>CR1</name><description>Control register 1</description><addressOffset>0x00</addressOffset> | |
| <fields> | |
| <field><name>CEN</name><description>Counter enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>UDIS</name><description>Update disable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>URS</name><description>Update request source</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>OPM</name><description>One-pulse mode</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>DIR</name><description>Direction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth> | |
| <enumeratedValues> | |
| <enumeratedValue><name>UP</name><description>Counter used as upcounter</description><value>0</value></enumeratedValue> | |
| <enumeratedValue><name>DOWN</name><description>Counter used as downcounter</description><value>1</value></enumeratedValue> | |
| </enumeratedValues> | |
| </field> | |
| <field><name>CMS</name><description>Center-aligned mode selection</description><bitRange>[6:5]</bitRange> | |
| <enumeratedValues> | |
| <enumeratedValue><name>EDGE</name><description>Edge-aligned mode</description><value>0b00</value></enumeratedValue> | |
| <enumeratedValue><name>CENTER_1</name><description>Center-aligned mode 1</description><value>0b01</value></enumeratedValue> | |
| <enumeratedValue><name>CENTER_2</name><description>Center-aligned mode 2</description><value>0b10</value></enumeratedValue> | |
| <enumeratedValue><name>CENTER_3</name><description>Center-aligned mode 3</description><value>0b11</value></enumeratedValue> | |
| </enumeratedValues> | |
| </field> | |
| <field><name>ARPE</name><description>Auto-reload preload enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field> | |
| </fields> | |
| </register> | |
| <register> | |
| <name>DIER</name><description>DMA and interrupt enable register</description><addressOffset>0x0C</addressOffset> | |
| <fields> | |
| <field><name>UIE</name><description>Update interrupt enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><dim>4</dim><dimIncrement>1</dimIncrement><dimIndex>1-4</dimIndex><name>CC%sIE</name><description>Capture/compare interrupt enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field> | |
| </fields> | |
| </register> | |
| <register> | |
| <name>SR</name><description>Status register</description><addressOffset>0x10</addressOffset> | |
| <fields> | |
| <field><name>UIF</name><description>Update interrupt flag</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><modifiedWriteValues>zeroToClear</modifiedWriteValues></field> | |
| <field><dim>4</dim><dimIncrement>1</dimIncrement><dimIndex>1-4</dimIndex><name>CC%sIF</name><description>Capture/compare interrupt flag</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><modifiedWriteValues>zeroToClear</modifiedWriteValues></field> | |
| </fields> | |
| </register> | |
| <register> | |
| <name>CNT</name><description>Counter</description><addressOffset>0x24</addressOffset> | |
| <fields><field><name>CNT</name><description>Counter value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields> | |
| </register> | |
| <register> | |
| <name>ARR</name><description>Auto-reload register</description><addressOffset>0x2C</addressOffset><resetValue>0xFFFFFFFF</resetValue> | |
| <fields><field><name>ARR</name><description>Auto-reload value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields> | |
| </register> | |
| <register> | |
| <dim>4</dim><dimIncrement>4</dimIncrement> | |
| <name>CCR[%s]</name><description>Capture/compare register</description><addressOffset>0x34</addressOffset> | |
| <fields><field><name>CCR</name><description>Capture/compare value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields> | |
| </register> | |
| </registers> | |
| </peripheral> | |
| <peripheral> | |
| <name>USART1</name> | |
| <description>Universal synchronous asynchronous receiver transmitter</description> | |
| <groupName>USART</groupName> | |
| <baseAddress>0x40013800</baseAddress> | |
| <interrupt><name>USART1</name><description>USART1 global interrupt</description><value>37</value></interrupt> | |
| <registers> | |
| <register> | |
| <name>CR1</name><description>Control register 1</description><addressOffset>0x00</addressOffset> | |
| <fields> | |
| <field><name>UE</name><description>USART enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>RE</name><description>Receiver enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>TE</name><description>Transmitter enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>RXNEIE</name><description>RXNE interrupt enable</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>PS</name><description>Parity selection</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth> | |
| <enumeratedValues> | |
| <enumeratedValue><name>EVEN</name><description>Even parity</description><value>0</value></enumeratedValue> | |
| <enumeratedValue><name>ODD</name><description>Odd parity</description><value>1</value></enumeratedValue> | |
| </enumeratedValues> | |
| </field> | |
| <field><name>PCE</name><description>Parity control enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>M0</name><description>Word length, bit 0</description><lsb>12</lsb><msb>12</msb></field> | |
| <field><name>OVER8</name><description>Oversampling mode</description><bitRange>[15:15]</bitRange> | |
| <enumeratedValues> | |
| <enumeratedValue><name>OVERSAMPLING_16</name><description>Oversampling by 16</description><value>0</value></enumeratedValue> | |
| <enumeratedValue><name>OVERSAMPLING_8</name><description>Oversampling by 8</description><value>1</value></enumeratedValue> | |
| </enumeratedValues> | |
| </field> | |
| </fields> | |
| </register> | |
| <register> | |
| <name>BRR</name><description>Baud rate register</description><addressOffset>0x0C</addressOffset> | |
| <fields><field><name>BRR</name><description>Baud rate divider</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields> | |
| </register> | |
| <register> | |
| <name>ISR</name><description>Interrupt and status register</description><addressOffset>0x1C</addressOffset> | |
| <access>read-only</access><resetValue>0x000000C0</resetValue> | |
| <fields> | |
| <field><name>ORE</name><description>Overrun error</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>RXNE</name><description>Read data register not empty</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>TC</name><description>Transmission complete</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>TXE</name><description>Transmit data register empty</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field> | |
| </fields> | |
| </register> | |
| <register> | |
| <name>ICR</name><description>Interrupt flag clear register</description><addressOffset>0x20</addressOffset><access>write-only</access> | |
| <fields> | |
| <field><name>ORECF</name><description>Overrun error clear flag</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><modifiedWriteValues>oneToClear</modifiedWriteValues></field> | |
| <field><name>TCCF</name><description>Transmission complete clear flag</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth><modifiedWriteValues>oneToClear</modifiedWriteValues></field> | |
| </fields> | |
| </register> | |
| <register> | |
| <name>RDR</name><description>Receive data register</description><addressOffset>0x24</addressOffset><access>read-only</access> | |
| <fields><field><name>RDR</name><description>Receive data value</description><bitOffset>0</bitOffset><bitWidth>9</bitWidth></field></fields> | |
| </register> | |
| <register> | |
| <name>TDR</name><description>Transmit data register</description><addressOffset>0x28</addressOffset> | |
| <fields><field><name>TDR</name><description>Transmit data value</description><bitOffset>0</bitOffset><bitWidth>9</bitWidth></field></fields> | |
| </register> | |
| </registers> | |
| </peripheral> | |
| <peripheral> | |
| <name>GPIOA</name> | |
| <description>General-purpose I/O port A</description> | |
| <groupName>GPIO</groupName> | |
| <baseAddress>0x48000000</baseAddress> | |
| <registers> | |
| <register> | |
| <name>MODER</name><description>Port mode register</description><addressOffset>0x00</addressOffset><resetValue>0xABFFFFFF</resetValue> | |
| <fields> | |
| <field><dim>16</dim><dimIncrement>2</dimIncrement><name>MODE%s</name><description>Pin mode</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth> | |
| <enumeratedValues> | |
| <enumeratedValue><name>INPUT</name><description>Input mode</description><value>0</value></enumeratedValue> | |
| <enumeratedValue><name>OUTPUT</name><description>General-purpose output mode</description><value>1</value></enumeratedValue> | |
| <enumeratedValue><name>ALTERNATE</name><description>Alternate function mode</description><value>2</value></enumeratedValue> | |
| <enumeratedValue><name>ANALOG</name><description>Analog mode</description><value>3</value></enumeratedValue> | |
| </enumeratedValues> | |
| </field> | |
| </fields> | |
| </register> | |
| <register> | |
| <name>IDR</name><description>Port input data register</description><addressOffset>0x10</addressOffset><access>read-only</access> | |
| <fields><field><dim>16</dim><dimIncrement>1</dimIncrement><name>ID%s</name><description>Port input data</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields> | |
| </register> | |
| <register> | |
| <name>ODR</name><description>Port output data register</description><addressOffset>0x14</addressOffset> | |
| <fields><field><dim>16</dim><dimIncrement>1</dimIncrement><name>OD%s</name><description>Port output data</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields> | |
| </register> | |
| <register> | |
| <name>BSRR</name><description>Port bit set/reset register</description><addressOffset>0x18</addressOffset><access>write-only</access> | |
| <fields> | |
| <field><dim>16</dim><dimIncrement>1</dimIncrement><name>BR%s</name><description>Port reset bit</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><dim>16</dim><dimIncrement>1</dimIncrement><name>BS%s</name><description>Port set bit</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field> | |
| </fields> | |
| </register> | |
| </registers> | |
| </peripheral> | |
| <peripheral derivedFrom="GPIOA"> | |
| <name>GPIOB</name> | |
| <description>General-purpose I/O port B</description> | |
| <baseAddress>0x48000400</baseAddress> | |
| </peripheral> | |
| <peripheral> | |
| <name>ADC1</name> | |
| <description>Analog-to-digital converter</description> | |
| <groupName>ADC</groupName> | |
| <baseAddress>0x50040000</baseAddress> | |
| <interrupt><name>ADC1_2</name><description>ADC1 and ADC2 global interrupt</description><value>18</value></interrupt> | |
| <registers> | |
| <register> | |
| <name>CR</name><description>Control register</description><addressOffset>0x08</addressOffset><resetValue>0x20000000</resetValue> | |
| <fields> | |
| <field><name>ADEN</name><description>ADC enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>ADDIS</name><description>ADC disable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>ADSTART</name><description>ADC start of regular conversion</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>ADVREGEN</name><description>ADC voltage regulator enable</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>DEEPPWD</name><description>Deep-power-down enable</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>ADCAL</name><description>ADC calibration</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field> | |
| </fields> | |
| </register> | |
| <register> | |
| <name>CFGR</name><description>Configuration register</description><addressOffset>0x0C</addressOffset><resetValue>0x80000000</resetValue> | |
| <fields> | |
| <field><name>RES</name><description>Data resolution</description><bitOffset>3</bitOffset><bitWidth>2</bitWidth> | |
| <enumeratedValues> | |
| <enumeratedValue><name>RESOLUTION_12B</name><description>12-bit resolution</description><value>0</value></enumeratedValue> | |
| <enumeratedValue><name>RESOLUTION_10B</name><description>10-bit resolution</description><value>1</value></enumeratedValue> | |
| <enumeratedValue><name>RESOLUTION_8B</name><description>8-bit resolution</description><value>2</value></enumeratedValue> | |
| <enumeratedValue><name>RESOLUTION_6B</name><description>6-bit resolution</description><value>3</value></enumeratedValue> | |
| </enumeratedValues> | |
| </field> | |
| <field><name>ALIGN</name><description>Data alignment</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>CONT</name><description>Single or continuous conversion mode</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>JQDIS</name><description>Injected queue disable</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field> | |
| </fields> | |
| </register> | |
| <cluster> | |
| <name>COMMON</name><description>Registers shared by ADC1 and ADC2</description><addressOffset>0x300</addressOffset> | |
| <register> | |
| <name>CSR</name><description>Common status register</description><addressOffset>0x00</addressOffset><access>read-only</access> | |
| <fields> | |
| <field><name>ADRDY_MST</name><description>Master ADC ready</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>EOC_MST</name><description>End of regular conversion of the master ADC</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field> | |
| </fields> | |
| </register> | |
| <register> | |
| <name>CCR</name><description>Common control register</description><addressOffset>0x08</addressOffset> | |
| <fields> | |
| <field><name>PRESC</name><description>ADC prescaler</description><bitOffset>18</bitOffset><bitWidth>4</bitWidth> | |
| <enumeratedValues> | |
| <enumeratedValue><name>DIV1</name><description>Input clock not divided</description><value>0</value></enumeratedValue> | |
| <enumeratedValue><name>DIV2</name><description>Input clock divided by 2</description><value>1</value></enumeratedValue> | |
| <enumeratedValue><name>DIV4</name><description>Input clock divided by 4</description><value>2</value></enumeratedValue> | |
| <enumeratedValue><name>DIV256</name><description>Input clock divided by 256</description><value>11</value></enumeratedValue> | |
| </enumeratedValues> | |
| </field> | |
| <field><name>VREFEN</name><description>VREFINT enable</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field> | |
| <field><name>TSEN</name><description>Temperature sensor enable</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field> | |
| </fields> | |
| </register> | |
| </cluster> | |
| </registers> | |
| </peripheral> | |
| </peripherals> | |
| </device> | |
| </script> | |
| <script> | |
| (() => { | |
| "use strict"; | |
| const ROW_LIMIT = 5000; | |
| const MAX_DIM = 64; | |
| const VIEW_KEY = "svd-explorer:view"; | |
| const MANIFEST = "svd-files.json"; | |
| const EXAMPLE = "example"; | |
| const ACCESS = { "read-write": "rw", "read-only": "ro", "write-only": "wo", "writeOnce": "w1", "read-writeOnce": "rw1" }; | |
| const WRITES = { | |
| oneToClear: "w1c", oneToSet: "w1s", oneToToggle: "w1t", zeroToClear: "w0c", | |
| zeroToSet: "w0s", zeroToToggle: "w0t", clear: "wc", set: "ws", modify: "wm", | |
| }; | |
| const $ = (id) => document.getElementById(id); | |
| const els = { | |
| fileInput: $("file-input"), fileLine: $("file-line"), query: $("query"), search: $("search"), | |
| flags: $("flags"), desc: $("scope-desc"), cased: $("match-case"), expandAll: $("expand-all"), | |
| collapseAll: $("collapse-all"), status: $("status"), message: $("message"), rows: $("rows"), | |
| more: $("more"), drop: $("drop"), menuQuery: $("menu-query"), menuSearch: $("menu-search"), | |
| menuList: $("menu-list"), menuCount: $("menu-count"), tabs: $("tabs"), tabTable: $("tab-table"), | |
| tabMap: $("tab-map"), panelTable: $("panel-table"), panelMap: $("panel-map"), tableActions: $("table-actions"), | |
| crumbs: $("crumbs"), mapDense: $("map-dense"), mapRow: $("map-row"), zoomIn: $("zoom-in"), | |
| zoomOut: $("zoom-out"), zoomFit: $("zoom-fit"), mapFrame: $("map-frame"), map: $("map"), | |
| overview: $("overview"), mapTip: $("map-tip"), mapCard: $("map-card"), | |
| }; | |
| let model = null; | |
| let expanded = new Set(); // open nodes without filter | |
| let toggles = new Map(); // open state chosen by the user while filtering | |
| let filter = null; // { re, reG, useDesc, matched, keep, ancestors } | |
| let currentView = "table"; | |
| /* ---------- XML helpers ---------- */ | |
| const kids = (el, tag) => (el ? Array.from(el.children).filter((c) => c.localName === tag) : []); | |
| const kid = (el, tag) => (el ? Array.from(el.children).find((c) => c.localName === tag) || null : null); | |
| const txt = (el, tag) => { const k = kid(el, tag); return k ? k.textContent.trim() : null; }; | |
| const clean = (s) => (s ? s.replace(/\s+/g, " ").trim() : ""); | |
| function num(value) { | |
| if (value == null) return null; | |
| let s = String(value).trim().toLowerCase(); | |
| if (s.startsWith("#")) { s = s.slice(1).replace(/x/g, "0"); return /^[01]+$/.test(s) ? parseInt(s, 2) : null; } | |
| if (/^0x[0-9a-f]+$/.test(s)) return parseInt(s, 16); | |
| if (/^0b[01]+$/.test(s)) return parseInt(s.slice(2), 2); | |
| const m = s.match(/^(\d+)([kmg])?$/); | |
| if (m) return parseInt(m[1], 10) * ({ k: 1024, m: 1048576, g: 1073741824 }[m[2]] || 1); | |
| return null; | |
| } | |
| const range = (a, b) => Array.from({ length: b - a + 1 }, (_, i) => String(a + i)); | |
| /* Expands dim arrays and lists, e.g. CCR[%s] or MODE%s */ | |
| function expand(el, name) { | |
| const dim = num(txt(el, "dim")); | |
| if (!dim || !name || !name.includes("%s")) return [{ name, step: 0, dim: 0 }]; | |
| const increment = num(txt(el, "dimIncrement")) || 0; | |
| const raw = txt(el, "dimIndex"); | |
| let indices = null; | |
| if (raw) { | |
| const r = raw.match(/^\s*(\d+)\s*-\s*(\d+)\s*$/); | |
| indices = r ? range(+r[1], +r[2]) : raw.split(",").map((s) => s.trim()); | |
| } | |
| if (!indices || indices.length !== dim) indices = range(0, dim - 1); | |
| if (dim > MAX_DIM) { | |
| return [{ name: name.replace("%s", `${indices[0]}…${indices[dim - 1]}`), step: 0, dim, increment }]; | |
| } | |
| return indices.map((index, i) => ({ name: name.replace("%s", index), step: i * increment, dim: 0 })); | |
| } | |
| /* ---------- SVD parser ---------- */ | |
| function parseSvd(text) { | |
| const doc = new DOMParser().parseFromString(text, "application/xml"); | |
| if (doc.getElementsByTagName("parsererror").length) throw new Error("the file is not well-formed XML"); | |
| const device = doc.documentElement; | |
| if (!device || device.localName !== "device") { | |
| throw new Error("it has no <device> root element, so it is not a CMSIS-SVD file"); | |
| } | |
| const nodes = []; | |
| const stats = { peripheral: 0, cluster: 0, register: 0, field: 0, enum: 0 }; | |
| const make = (type, props) => { | |
| const node = Object.assign({ id: nodes.length, type, children: [], parent: null }, props); | |
| nodes.push(node); | |
| stats[type]++; | |
| return node; | |
| }; | |
| const deviceProps = { | |
| size: num(txt(device, "size")) ?? 32, | |
| access: txt(device, "access"), | |
| reset: num(txt(device, "resetValue")), | |
| }; | |
| const peripheralEls = kids(kid(device, "peripherals"), "peripheral"); | |
| const byName = new Map(peripheralEls.map((p) => [txt(p, "name"), p])); | |
| // Child element of a peripheral, falling back to the peripheral it is derived from | |
| const inherited = (p, tag, seen = new Set()) => { | |
| const own = kid(p, tag); | |
| if (own || seen.has(p)) return own; | |
| seen.add(p); | |
| const base = byName.get(p.getAttribute("derivedFrom")); | |
| return base ? inherited(base, tag, seen) : null; | |
| }; | |
| const inheritedText = (p, tag) => { const k = inherited(p, tag); return k ? k.textContent.trim() : null; }; | |
| function parseFields(fieldsEl, register) { | |
| const fields = []; | |
| for (const f of kids(fieldsEl, "field")) { | |
| let lsb = num(txt(f, "bitOffset")); | |
| let width = num(txt(f, "bitWidth")); | |
| if (lsb == null) { | |
| const l = num(txt(f, "lsb")), m = num(txt(f, "msb")); | |
| const r = (txt(f, "bitRange") || "").match(/\[\s*(\d+)\s*:\s*(\d+)\s*\]/); | |
| if (l != null && m != null) { lsb = l; width = m - l + 1; } | |
| else if (r) { lsb = +r[2]; width = +r[1] - +r[2] + 1; } | |
| } | |
| lsb = lsb ?? 0; | |
| width = width ?? 1; | |
| const access = txt(f, "access") ?? register.access; | |
| const writes = txt(f, "modifiedWriteValues"); | |
| const readAction = txt(f, "readAction"); | |
| const desc = clean(txt(f, "description")); | |
| for (const { name, step } of expand(f, txt(f, "name"))) { | |
| const position = lsb + step; | |
| const field = make("field", { | |
| name, path: `${register.path}.${name}`, lsb: position, msb: position + width - 1, width, | |
| registerSize: register.size, access, writes, readAction, desc, | |
| reset: fieldValue(register.reset, position, width), | |
| }); | |
| for (const values of kids(f, "enumeratedValues")) { | |
| for (const v of kids(values, "enumeratedValue")) { | |
| const isDefault = txt(v, "isDefault") === "true"; | |
| const vname = txt(v, "name") || (isDefault ? "default" : "?"); | |
| field.children.push(make("enum", { | |
| name: vname, path: `${field.path}.${vname}`, raw: txt(v, "value"), value: num(txt(v, "value")), | |
| isDefault, width, usage: txt(values, "usage"), desc: clean(txt(v, "description")), | |
| })); | |
| } | |
| } | |
| fields.push(field); | |
| } | |
| } | |
| // Most significant bit first, as in reference manuals | |
| return fields.sort((a, b) => b.msb - a.msb || b.lsb - a.lsb); | |
| } | |
| function parseBlock(container, parent, base, props) { | |
| const children = []; | |
| const siblings = new Map(kids(container, "register").map((r) => [txt(r, "name"), r])); | |
| for (const el of Array.from(container.children)) { | |
| if (el.localName === "register") children.push(...parseRegister(el, parent, base, props, siblings)); | |
| else if (el.localName === "cluster") children.push(...parseCluster(el, parent, base, props)); | |
| } | |
| return children.sort((a, b) => a.offset - b.offset); | |
| } | |
| function parseRegister(el, parent, base, props, siblings) { | |
| const derivedFrom = el.getAttribute("derivedFrom"); | |
| const source = derivedFrom ? siblings.get(derivedFrom) : null; | |
| const get = (tag) => txt(el, tag) ?? (source ? txt(source, tag) : null); | |
| const offset = num(get("addressOffset")) ?? 0; | |
| const size = num(get("size")) ?? props.size ?? 32; | |
| const access = get("access") ?? props.access; | |
| const resetText = get("resetValue"); | |
| const reset = resetText != null ? num(resetText) : props.reset; | |
| const desc = clean(get("description")); | |
| const fieldsEl = kid(el, "fields") || (source ? kid(source, "fields") : null); | |
| return expand(el, get("name")).map(({ name, step, dim, increment }) => { | |
| const register = make("register", { | |
| name, path: `${parent.path}.${name}`, address: base + offset + step, offset: offset + step, | |
| size, access, reset, desc, derivedFrom, alternate: get("alternateRegister"), dim, increment, | |
| }); | |
| if (fieldsEl) register.children = parseFields(fieldsEl, register); | |
| return register; | |
| }); | |
| } | |
| function parseCluster(el, parent, base, props) { | |
| const offset = num(txt(el, "addressOffset")) ?? 0; | |
| const resetText = txt(el, "resetValue"); | |
| const clusterProps = { | |
| size: num(txt(el, "size")) ?? props.size, | |
| access: txt(el, "access") ?? props.access, | |
| reset: resetText != null ? num(resetText) : props.reset, | |
| }; | |
| return expand(el, txt(el, "name")).map(({ name, step, dim }) => { | |
| const cluster = make("cluster", { | |
| name, path: `${parent.path}.${name}`, address: base + offset + step, offset: offset + step, | |
| desc: clean(txt(el, "description")), dim, | |
| }); | |
| cluster.children = parseBlock(el, cluster, base + offset + step, clusterProps); | |
| return cluster; | |
| }); | |
| } | |
| const peripherals = []; | |
| for (const p of peripheralEls) { | |
| const name = txt(p, "name"); | |
| const address = num(inheritedText(p, "baseAddress")) ?? 0; | |
| const resetText = inheritedText(p, "resetValue"); | |
| const props = { | |
| size: num(inheritedText(p, "size")) ?? deviceProps.size, | |
| access: inheritedText(p, "access") ?? deviceProps.access, | |
| reset: resetText != null ? num(resetText) : deviceProps.reset, | |
| }; | |
| // Registers address blocks of reasonable size, large memory blocks are not drawn | |
| const blocks = kids(p, "addressBlock").length ? kids(p, "addressBlock") | |
| : kids(byName.get(p.getAttribute("derivedFrom")), "addressBlock"); | |
| let blockSize = 0; | |
| for (const block of blocks) { | |
| const usage = txt(block, "usage"); | |
| const end = (num(txt(block, "offset")) ?? 0) + (num(txt(block, "size")) ?? 0); | |
| if ((!usage || usage === "registers") && end <= 0x10000) blockSize = Math.max(blockSize, end); | |
| } | |
| const peripheral = make("peripheral", { | |
| name, path: name, address, offset: 0, blockSize, | |
| desc: clean(inheritedText(p, "description")), | |
| derivedFrom: p.getAttribute("derivedFrom"), | |
| interrupts: kids(p, "interrupt").map((i) => ({ name: txt(i, "name"), value: txt(i, "value") })), | |
| }); | |
| const registers = inherited(p, "registers"); | |
| if (registers) peripheral.children = parseBlock(registers, peripheral, address, props); | |
| peripherals.push(peripheral); | |
| } | |
| peripherals.sort((a, b) => a.address - b.address || a.name.localeCompare(b.name)); | |
| const link = (node) => { for (const child of node.children) { child.parent = node; link(child); } }; | |
| peripherals.forEach(link); | |
| return { name: txt(device, "name") || "Unnamed device", peripherals, nodes, stats }; | |
| } | |
| function fieldValue(reset, lsb, width) { | |
| if (reset == null) return null; | |
| return Number((BigInt(reset) >> BigInt(lsb)) & ((1n << BigInt(width)) - 1n)); | |
| } | |
| /* ---------- Formatting ---------- */ | |
| const esc = (s) => String(s ?? "").replace(/[&<>"]/g, (c) => ({ "&": "&", "<": "<", ">": ">", '"': """ }[c])); | |
| const hex = (value, bits) => "0x" + value.toString(16).toUpperCase().padStart(Math.max(1, Math.ceil(bits / 4)), "0"); | |
| const offsetText = (value) => "+0x" + value.toString(16).toUpperCase().padStart(2, "0"); | |
| const bitsValue = (value, width) => { | |
| if (width === 1) return String(value); | |
| if (width <= 4) return "0b" + value.toString(2).padStart(width, "0"); | |
| return hex(value, width); | |
| }; | |
| const bitRange = (field) => (field.msb === field.lsb ? `[${field.lsb}]` : `[${field.msb}:${field.lsb}]`); | |
| const plural = (n, word) => `${n.toLocaleString()} ${word}${n === 1 ? "" : "s"}`; | |
| const sizeText = (bytes) => { | |
| if (bytes >= 1048576 && bytes % 1048576 === 0) return `${bytes / 1048576} MiB`; | |
| if (bytes >= 1024 && bytes % 1024 === 0) return `${bytes / 1024} KiB`; | |
| if (bytes >= 1024) return `${(bytes / 1024).toFixed(1)} KiB`; | |
| return plural(bytes, "byte"); | |
| }; | |
| const clamp = (value, lo, hi) => Math.min(hi, Math.max(lo, value)); | |
| function highlight(text) { | |
| if (!filter || !text) return esc(text); | |
| let out = "", last = 0; | |
| for (const m of text.matchAll(filter.reG)) { | |
| if (!m[0].length) continue; | |
| out += esc(text.slice(last, m.index)) + "<mark>" + esc(m[0]) + "</mark>"; | |
| last = m.index + m[0].length; | |
| } | |
| return out + esc(text.slice(last)); | |
| } | |
| function accessHtml(node) { | |
| const short = ACCESS[node.access] || node.access || ""; | |
| const extra = [node.readAction === "clear" ? "rc" : node.readAction, WRITES[node.writes] || node.writes]; | |
| const label = [short, ...extra].filter(Boolean).join(" "); | |
| if (!label) return ""; | |
| const kind = short === "ro" ? "ro" : short === "wo" ? "wo" : "rw"; | |
| const title = [node.access, node.readAction && `read: ${node.readAction}`, node.writes].filter(Boolean).join(", "); | |
| return `<span class="acc acc-${kind}" title="${esc(title)}">${esc(label)}</span>`; | |
| } | |
| /* ---------- Filter ---------- */ | |
| function nodeMatches(node) { | |
| if (filter.re.test(node.name)) return true; | |
| if (node.path.length > node.name.length) { | |
| // Dotted paths like USART1.CR1.UE match when the match ends in the last segment | |
| const start = node.path.length - node.name.length; | |
| for (const m of node.path.matchAll(filter.reG)) { | |
| if (m[0].length && m.index + m[0].length > start) return true; | |
| } | |
| } | |
| return filter.useDesc && !!node.desc && filter.re.test(node.desc); | |
| } | |
| function computeFilter() { | |
| const matched = new Set(), keep = new Set(), ancestors = new Set(); | |
| const visit = (node) => { | |
| let childHit = false; | |
| for (const child of node.children) if (visit(child)) childHit = true; | |
| const hit = nodeMatches(node); | |
| if (hit) matched.add(node.id); | |
| if (childHit) ancestors.add(node.id); | |
| if (hit || childHit) keep.add(node.id); | |
| return hit || childHit; | |
| }; | |
| model.peripherals.forEach(visit); | |
| Object.assign(filter, { matched, keep, ancestors }); | |
| } | |
| function applyQuery() { | |
| const query = els.query.value; | |
| const flags = els.cased.checked ? "" : "i"; | |
| els.flags.textContent = `/${flags}`; | |
| toggles = new Map(); | |
| if (!query) { | |
| filter = null; | |
| els.search.classList.remove("invalid"); | |
| els.query.removeAttribute("aria-invalid"); | |
| render(); | |
| scheduleDraw(); | |
| return; | |
| } | |
| let re, reG; | |
| try { | |
| re = new RegExp(query, flags); | |
| reG = new RegExp(query, flags + "g"); | |
| } catch (error) { | |
| els.search.classList.add("invalid"); | |
| els.query.setAttribute("aria-invalid", "true"); | |
| setStatus(`${esc(error.message)}. Escape special characters like <code>\\.</code> or <code>\\[</code>.`, true); | |
| return; | |
| } | |
| els.search.classList.remove("invalid"); | |
| els.query.removeAttribute("aria-invalid"); | |
| filter = { re, reG, useDesc: els.desc.checked }; | |
| if (model) computeFilter(); | |
| render(); | |
| scheduleDraw(); | |
| } | |
| /* ---------- Table ---------- */ | |
| function isOpen(node, unfiltered) { | |
| if (!filter) return expanded.has(node.id); | |
| if (toggles.has(node.id)) return toggles.get(node.id); | |
| return !unfiltered && filter.ancestors.has(node.id); | |
| } | |
| function rowHtml(node, depth, open) { | |
| const hit = filter && filter.matched.has(node.id); | |
| const name = hit ? highlight(node.name) : esc(node.name); | |
| const desc = hit && filter.useDesc ? highlight(node.desc) : esc(node.desc); | |
| const toggle = node.children.length | |
| ? `<button class="tw" type="button" aria-expanded="${open}" aria-label="${open ? "Collapse" : "Expand"} ${esc(node.path)}"></button>` | |
| : `<span class="tw-gap"></span>`; | |
| const locate = node.type === "enum" | |
| ? `<span class="locate-gap"></span>` | |
| : `<button class="locate" type="button" data-locate="${node.id}" title="Show on map" aria-label="Show ${esc(node.path)} on the map"></button>`; | |
| let address = "", bits = "", access = "", reset = "", nameTags = "", descTags = ""; | |
| switch (node.type) { | |
| case "peripheral": | |
| address = hex(node.address, 32); | |
| if (node.derivedFrom) descTags += `<span class="tag">derived from ${esc(node.derivedFrom)}</span>`; | |
| for (const irq of node.interrupts) descTags += `<span class="tag">IRQ ${esc(irq.value)} ${esc(irq.name)}</span>`; | |
| break; | |
| case "cluster": | |
| address = `${hex(node.address, 32)}<span class="off">${offsetText(node.offset)}</span>`; | |
| if (node.dim) nameTags += `<span class="tag">×${node.dim}</span>`; | |
| break; | |
| case "register": | |
| address = `${hex(node.address, 32)}<span class="off">${offsetText(node.offset)}</span>`; | |
| bits = String(node.size); | |
| access = accessHtml(node); | |
| reset = node.reset != null ? hex(node.reset, node.size) : ""; | |
| if (node.dim) nameTags += `<span class="tag">×${node.dim} +0x${node.increment.toString(16).toUpperCase()}</span>`; | |
| if (node.alternate) descTags += `<span class="tag">alternate of ${esc(node.alternate)}</span>`; | |
| if (node.derivedFrom) descTags += `<span class="tag">derived from ${esc(node.derivedFrom)}</span>`; | |
| break; | |
| case "field": { | |
| const size = node.registerSize || 32; | |
| const left = Math.max(0, ((size - 1 - node.msb) / size) * 100); | |
| const width = Math.min(100, (node.width / size) * 100); | |
| bits = bitRange(node) + | |
| `<span class="bar" style="--l:${left.toFixed(3)}%;--w:${width.toFixed(3)}%" aria-hidden="true"></span>`; | |
| access = accessHtml(node); | |
| reset = node.reset != null ? bitsValue(node.reset, node.width) : ""; | |
| break; | |
| } | |
| case "enum": | |
| bits = node.value != null ? bitsValue(node.value, node.width) : esc(node.raw ?? ""); | |
| if (node.isDefault) nameTags += `<span class="tag">default</span>`; | |
| if (node.usage && node.usage !== "read-write") descTags += `<span class="tag">${esc(node.usage)}</span>`; | |
| break; | |
| } | |
| const text = desc ? `<span class="text">${desc}</span>` : ""; | |
| return `<tr class="lv-${node.type}" data-id="${node.id}" data-open="${open ? 1 : 0}">` + | |
| `<td class="c-name" style="--d:${depth}">${toggle}<span class="nm">${name}</span>${nameTags}</td>` + | |
| `<td class="num">${locate}${address}</td><td class="c-bits num">${bits}</td><td>${access}</td>` + | |
| `<td class="num">${reset}</td><td class="c-desc">${text}${descTags}</td></tr>`; | |
| } | |
| function render() { | |
| if (!model) { els.rows.innerHTML = ""; return; } | |
| const rows = []; | |
| let total = 0; | |
| const walk = (list, depth, unfiltered) => { | |
| for (const node of list) { | |
| if (filter && !unfiltered && !filter.keep.has(node.id)) continue; | |
| const open = node.children.length > 0 && isOpen(node, unfiltered); | |
| total++; | |
| if (rows.length < ROW_LIMIT) rows.push(rowHtml(node, depth, open)); | |
| // A matched node without matching descendants shows all of its children when opened | |
| if (open) walk(node.children, depth + 1, unfiltered || (filter && !filter.ancestors.has(node.id))); | |
| } | |
| }; | |
| walk(model.peripherals, 0, false); | |
| if (filter && !filter.keep.size) { | |
| els.rows.innerHTML = `<tr class="empty"><td colspan="6">Nothing in ${esc(model.name)} matches ` + | |
| `<code class="num">/${esc(els.query.value)}/${els.cased.checked ? "" : "i"}</code>. ` + | |
| `${filter.useDesc ? "" : "Turn on Descriptions to search the description text too."}</td></tr>`; | |
| } else { | |
| els.rows.innerHTML = rows.join(""); | |
| } | |
| els.more.hidden = total <= ROW_LIMIT; | |
| els.more.textContent = `Showing the first ${ROW_LIMIT.toLocaleString()} of ${total.toLocaleString()} rows. ` + | |
| `Collapse some peripherals or narrow the filter to see the rest.`; | |
| if (filter) { | |
| const peripherals = model.peripherals.filter((p) => filter.keep.has(p.id)).length; | |
| setStatus(`${plural(filter.matched.size, "match")} across ${plural(peripherals, "peripheral")}`); | |
| } else { | |
| setStatus(`Filter by name or by dotted path, for example <code>USART1\\.CR1\\.</code> or <code>^CC\\dIF$</code>`); | |
| } | |
| } | |
| function setStatus(html, error = false) { | |
| els.status.innerHTML = html; | |
| els.status.classList.toggle("error", error); | |
| } | |
| function revealInTable(node) { | |
| if (filter && !filter.keep.has(node.id)) { | |
| els.query.value = ""; | |
| applyQuery(); | |
| } | |
| for (let parent = node.parent; parent; parent = parent.parent) { | |
| if (filter) toggles.set(parent.id, true); | |
| else expanded.add(parent.id); | |
| } | |
| switchView("table"); | |
| render(); | |
| const row = els.rows.querySelector(`tr[data-id="${node.id}"]`); | |
| if (!row) return; | |
| row.scrollIntoView({ block: "center" }); | |
| row.classList.add("flash"); | |
| setTimeout(() => row.classList.remove("flash"), 1700); | |
| row.querySelector(".tw, .locate")?.focus({ preventScroll: true }); | |
| } | |
| function updateFileLine(fileName, size, example) { | |
| const s = model.stats; | |
| const parts = [ | |
| `<span class="dev">${esc(model.name)}</span>`, | |
| `<span>${esc(fileName)}${size != null ? ` · ${formatBytes(size)}` : ""}</span>`, | |
| `<span>${plural(s.peripheral, "peripheral")} · ${plural(s.register, "register")} · ${plural(s.field, "field")}</span>`, | |
| ]; | |
| els.fileLine.innerHTML = parts.join(`<span class="sep" aria-hidden="true">/</span>`) + | |
| (example ? `<span class="chip">Example file</span>` : ""); | |
| } | |
| function formatBytes(bytes) { | |
| if (bytes < 1024) return `${bytes} B`; | |
| if (bytes < 1048576) return `${(bytes / 1024).toFixed(1)} KB`; | |
| return `${(bytes / 1048576).toFixed(1)} MB`; | |
| } | |
| /* ---------- Loading ---------- */ | |
| function load(text, fileName, size, example = false) { | |
| let parsed; | |
| try { | |
| parsed = parseSvd(text); | |
| } catch (error) { | |
| els.message.textContent = `Could not open ${fileName}: ${error.message}.`; | |
| els.message.hidden = false; | |
| return false; | |
| } | |
| els.message.hidden = true; | |
| model = parsed; | |
| expanded = new Set(); | |
| updateFileLine(fileName, size, example); | |
| resetMap(); | |
| return true; | |
| } | |
| async function loadFile(file) { | |
| try { | |
| const text = await file.text(); | |
| if (load(text, file.name, file.size)) { | |
| current = null; | |
| history.replaceState(null, "", location.pathname + location.search); | |
| renderMenu(); | |
| applyQuery(); | |
| els.rows.closest(".table-wrap").scrollTop = 0; | |
| } | |
| } catch (error) { | |
| els.message.textContent = `Could not read ${file.name}: ${error.message}.`; | |
| els.message.hidden = false; | |
| } | |
| } | |
| /* ---------- File menu ---------- */ | |
| let files = []; // { file, name, group } | |
| let menuNote = "<p>Looking for SVD files next to this page…</p>"; | |
| let current = null; // file shown, EXAMPLE, or null for opened files | |
| let loading = 0; | |
| const displayName = (file) => | |
| decodeURIComponent(file.split(/[?#]/)[0].split("/").pop()).replace(/^header_/, "").replace(/\.svd$/i, ""); | |
| const groupName = (name) => (/^stm32/i.test(name) ? name.slice(0, 7).toUpperCase() : "Other"); | |
| const fileFromHash = () => (location.hash.length > 1 ? decodeURIComponent(location.hash.slice(1)) : EXAMPLE); | |
| async function discoverFiles() { | |
| const found = []; | |
| // A list of file names, e.g. ["header_stm32f407xx.svd"], works on any static host | |
| try { | |
| const response = await fetch(MANIFEST, { cache: "no-cache" }); | |
| if (response.ok) { | |
| for (const item of await response.json()) { | |
| const file = typeof item === "string" ? item : item?.file; | |
| if (file) found.push(file); | |
| } | |
| } | |
| } catch { /* no list */ } | |
| // Otherwise the directory listing of a local server, e.g. python3 -m http.server | |
| if (!found.length) { | |
| try { | |
| const response = await fetch("./", { cache: "no-cache" }); | |
| if (response.ok && (response.headers.get("content-type") || "").includes("html")) { | |
| const doc = new DOMParser().parseFromString(await response.text(), "text/html"); | |
| for (const link of doc.querySelectorAll("a[href]")) { | |
| const href = link.getAttribute("href"); | |
| if (/\.svd$/i.test(href.split(/[?#]/)[0])) found.push(href); | |
| } | |
| } | |
| } catch { /* no listing */ } | |
| } | |
| files = [...new Set(found)] | |
| .map((file) => ({ file, name: displayName(file) })) | |
| .sort((a, b) => (a.name < b.name ? -1 : a.name > b.name ? 1 : 0)) | |
| .map((entry) => ({ ...entry, group: groupName(entry.name) })); | |
| const manifestCommand = `python3 -c "import glob, json; json.dump(sorted(glob.glob('*.svd')), open('${MANIFEST}', 'w'))"`; | |
| if (files.length) { | |
| menuNote = ""; | |
| } else if (location.protocol === "file:") { | |
| menuNote = `<p>The browser cannot list the files next to a page opened from disk.</p>` + | |
| `<p>Run <code>python3 -m http.server</code> in this folder and open <code>http://localhost:8000</code>.</p>`; | |
| } else { | |
| menuNote = `<p>No SVD files found next to this page.</p>` + | |
| `<p>Put the SVD files into this folder and list them in <code>${MANIFEST}</code>:</p>` + | |
| `<p><code>${esc(manifestCommand)}</code></p>`; | |
| } | |
| renderMenu(); | |
| } | |
| function renderMenu() { | |
| const query = els.menuQuery.value; | |
| let re = null; | |
| if (query) { | |
| try { re = new RegExp(query, "i"); } | |
| catch { els.menuSearch.classList.add("invalid"); els.menuQuery.setAttribute("aria-invalid", "true"); return; } | |
| } | |
| els.menuSearch.classList.remove("invalid"); | |
| els.menuQuery.removeAttribute("aria-invalid"); | |
| const mark = (text) => { | |
| if (!re) return esc(text); | |
| let out = "", last = 0; | |
| for (const m of text.matchAll(new RegExp(re.source, "gi"))) { | |
| if (!m[0].length) continue; | |
| out += esc(text.slice(last, m.index)) + "<mark>" + esc(m[0]) + "</mark>"; | |
| last = m.index + m[0].length; | |
| } | |
| return out + esc(text.slice(last)); | |
| }; | |
| const item = (file, label) => | |
| `<li><button class="menu-item" type="button" data-file="${esc(file)}" aria-current="${file === current}">${label}</button></li>`; | |
| const visible = files.filter((f) => !re || re.test(f.name)); | |
| let html = ""; | |
| if (!re || re.test("example")) html += `<li class="menu-group">BUILT-IN</li>` + item(EXAMPLE, mark("example")); | |
| let group = null; | |
| for (const f of visible) { | |
| if (f.group !== group) { group = f.group; html += `<li class="menu-group">${esc(group)}</li>`; } | |
| html += item(f.file, mark(f.name)); | |
| } | |
| if (menuNote) html += `<li class="menu-note">${menuNote}</li>`; | |
| else if (!visible.length && query) html += `<li class="menu-note"><p>No file name matches this expression.</p></li>`; | |
| els.menuList.innerHTML = html; | |
| els.menuCount.textContent = files.length ? (query ? `${visible.length} of ${files.length}` : `${files.length} files`) : ""; | |
| } | |
| function loadExample() { | |
| const example = $("example-svd").textContent.trim(); | |
| if (!load(example, "example.svd", new Blob([example]).size, true)) return false; | |
| const usart = model.peripherals.find((p) => p.name === "USART1"); | |
| const cr1 = usart?.children.find((r) => r.name === "CR1"); | |
| const ps = cr1?.children.find((f) => f.name === "PS"); | |
| for (const node of [usart, cr1, ps]) if (node) expanded.add(node.id); | |
| return true; | |
| } | |
| async function openFile(file) { | |
| const token = ++loading; | |
| const name = file === EXAMPLE ? "example.svd" : decodeURIComponent(file.split(/[?#]/)[0].split("/").pop()); | |
| let ok = false; | |
| if (file === EXAMPLE) { | |
| ok = loadExample(); | |
| } else { | |
| setStatus(`Loading <code>${esc(name)}</code>…`); | |
| try { | |
| const response = await fetch(file); | |
| if (!response.ok) throw new Error(`the server answered ${response.status} ${response.statusText}`.trim()); | |
| const text = await response.text(); | |
| if (token !== loading) return false; | |
| ok = load(text, name, Number(response.headers.get("content-length")) || new Blob([text]).size); | |
| } catch (error) { | |
| if (token !== loading) return false; | |
| els.message.textContent = `Could not load ${name}: ${error.message}.`; | |
| els.message.hidden = false; | |
| } | |
| } | |
| if (ok) { | |
| current = file; | |
| applyQuery(); | |
| els.rows.closest(".table-wrap").scrollTop = 0; | |
| } else { | |
| render(); | |
| } | |
| renderMenu(); | |
| return ok; | |
| } | |
| function navigate(file) { | |
| const target = file === EXAMPLE ? location.pathname + location.search : `#${encodeURIComponent(file)}`; | |
| if (fileFromHash() !== file) history.pushState(null, "", target); | |
| openFile(file); | |
| } | |
| /* ---------- Views ---------- */ | |
| function switchView(view, focus = false) { | |
| const isMap = view === "map"; | |
| currentView = isMap ? "map" : "table"; | |
| els.tabTable.setAttribute("aria-selected", String(!isMap)); | |
| els.tabMap.setAttribute("aria-selected", String(isMap)); | |
| els.tabTable.tabIndex = isMap ? -1 : 0; | |
| els.tabMap.tabIndex = isMap ? 0 : -1; | |
| els.panelTable.hidden = isMap; | |
| els.panelMap.hidden = !isMap; | |
| els.tableActions.hidden = isMap; | |
| try { localStorage.setItem(VIEW_KEY, currentView); } catch { /* storage unavailable */ } | |
| if (isMap) { | |
| resizeMap(); | |
| ensureLayout(); | |
| scheduleDraw(); | |
| } | |
| if (focus) (isMap ? els.tabMap : els.tabTable).focus(); | |
| } | |
| /* ---------- Map ---------- */ | |
| const GUTTER = 168; // address labels on the left | |
| const OVERVIEW = 56; // overview strip on the right | |
| const ROW_UNITS = 1; // row height in bytes, so a 32-bit register is 4:1 and a bit 8:1 | |
| const headerHeight = (h) => (h >= 44 ? 16 : 0); // register name above the bit fields | |
| const bitNumbersHeight = (h, bitW) => (bitW >= 15 && h >= 90 ? 14 : 0); | |
| const MAX_GAP_BYTES = 0x800; // larger gaps between peripherals are folded | |
| const FOLD_ROWS = 1.5; | |
| const HIDDEN_ROWS = 0.5; // marker height for hidden empty rows | |
| const BLOCK = 0x400; // assumed address block size without addressBlock | |
| const K_MAX = 360; | |
| const FONT_MONO = '"IBM Plex Mono", ui-monospace, Menlo, Consolas, monospace'; | |
| const FONT_SANS = '"IBM Plex Sans", system-ui, -apple-system, sans-serif'; | |
| const map = { | |
| layout: null, rowBytes: 64, dense: false, k: 1, ox: GUTTER + 12, oy: 12, width: 0, height: 0, dpr: 1, | |
| selected: null, hover: null, colors: null, hatch: null, frame: 0, anim: 0, | |
| }; | |
| const mapCtx = els.map.getContext("2d"); | |
| const overviewCtx = els.overview.getContext("2d"); | |
| function resetMap() { | |
| map.layout = null; | |
| map.selected = null; | |
| map.hover = null; | |
| els.mapTip.hidden = true; | |
| renderCard(); | |
| renderCrumbs(); | |
| if (currentView === "map") { ensureLayout(); scheduleDraw(); } | |
| } | |
| function readColors() { | |
| const style = getComputedStyle(document.documentElement); | |
| const v = (name) => style.getPropertyValue(name).trim(); | |
| map.colors = { | |
| surface: v("--surface"), band: v("--band"), ink: v("--ink"), muted: v("--muted"), faint: v("--faint"), | |
| rule: v("--rule"), ruleStrong: v("--rule-strong"), accent: v("--accent"), accentSoft: v("--accent-soft"), | |
| mark: v("--mark"), periph: v("--periph"), hatch: v("--hatch"), | |
| rw: [v("--reg-rw"), v("--reg-rw-line")], ro: [v("--reg-ro"), v("--reg-ro-line")], wo: [v("--reg-wo"), v("--reg-wo-line")], | |
| }; | |
| const tile = document.createElement("canvas"); | |
| tile.width = tile.height = 8; | |
| const t = tile.getContext("2d"); | |
| t.strokeStyle = map.colors.hatch; | |
| t.lineWidth = 1.2; | |
| t.beginPath(); | |
| t.moveTo(-1, 9); t.lineTo(9, -1); | |
| t.moveTo(-1, 1); t.lineTo(1, -1); | |
| t.moveTo(7, 9); t.lineTo(9, 7); | |
| t.stroke(); | |
| map.hatch = mapCtx.createPattern(tile, "repeat"); | |
| } | |
| const registerBytes = (node) => { | |
| const bytes = Math.max(1, Math.ceil((node.size || 32) / 8)); | |
| return node.dim ? (node.dim - 1) * Math.max(node.increment || 0, bytes) + bytes : bytes; | |
| }; | |
| const lastIndex = (list, key, value) => { | |
| let lo = 0, hi = list.length; | |
| while (lo < hi) { const mid = (lo + hi) >> 1; if (list[mid][key] <= value) lo = mid + 1; else hi = mid; } | |
| return lo - 1; | |
| }; | |
| function buildLayout() { | |
| const R = map.rowBytes; | |
| const pers = []; | |
| for (const node of model.peripherals) { | |
| const regs = []; | |
| const visit = (parent) => { | |
| for (const child of parent.children) { | |
| if (child.type === "register") regs.push(child); | |
| else if (child.type === "cluster") visit(child); | |
| } | |
| }; | |
| visit(node); | |
| regs.sort((a, b) => a.address - b.address); | |
| let registersEnd = node.address; | |
| for (const r of regs) registersEnd = Math.max(registersEnd, r.address + registerBytes(r)); | |
| pers.push({ node, start: node.address, registersEnd, regs, inferred: !node.blockSize }); | |
| } | |
| pers.sort((a, b) => a.start - b.start || a.registersEnd - b.registersEnd); | |
| // The extent is the address block, or the registers rounded up to a block without overlapping the next peripheral | |
| pers.forEach((P, i) => { | |
| let end = P.node.blockSize ? P.start + P.node.blockSize : P.start + Math.ceil(Math.max(4, P.registersEnd - P.start) / BLOCK) * BLOCK; | |
| const next = pers.slice(i + 1).find((o) => o.start > P.start); | |
| if (P.inferred && next && next.start < end) end = Math.max(next.start, P.registersEnd); | |
| P.end = Math.max(end, P.registersEnd, P.start + 4); | |
| }); | |
| const segs = [], folds = [], regs = []; | |
| if (!map.dense) { | |
| let seg = null, segEnd = 0; | |
| for (const P of pers) { | |
| const rowAddress = Math.floor(P.start / R) * R; | |
| const endAddress = Math.ceil(P.end / R) * R; | |
| if (!seg) { | |
| seg = { v: rowAddress, y: 0 }; | |
| segs.push(seg); | |
| segEnd = endAddress; | |
| } else if (rowAddress > segEnd && rowAddress - segEnd > MAX_GAP_BYTES) { | |
| seg.rows = (segEnd - seg.v) / R; | |
| const y = seg.y + seg.rows; | |
| folds.push({ y, rows: FOLD_ROWS, from: segEnd, to: rowAddress }); | |
| seg = { v: rowAddress, y: y + FOLD_ROWS }; | |
| segs.push(seg); | |
| segEnd = endAddress; | |
| } else { | |
| segEnd = Math.max(segEnd, endAddress); | |
| } | |
| P.v = P.start; | |
| P.vend = P.end; | |
| for (const r of P.regs) regs.push({ node: r, v: r.address, bytes: registerBytes(r), per: P }); | |
| } | |
| if (seg) seg.rows = (segEnd - seg.v) / R; | |
| } else { | |
| // Only rows without any register are hidden, the space between registers is kept | |
| const occupied = new Set(); | |
| for (const P of pers) { | |
| P.v = P.start; | |
| P.vend = P.end; | |
| occupied.add(Math.floor(P.start / R) * R); | |
| for (const r of P.regs) { | |
| const bytes = registerBytes(r); | |
| regs.push({ node: r, v: r.address, bytes, per: P }); | |
| for (let row = Math.floor(r.address / R) * R; row < r.address + bytes; row += R) occupied.add(row); | |
| } | |
| } | |
| let seg = null; | |
| for (const row of [...occupied].sort((a, b) => a - b)) { | |
| if (seg && row === seg.v + seg.rows * R) { seg.rows++; continue; } | |
| if (seg) { | |
| const y = seg.y + seg.rows; | |
| folds.push({ y, rows: HIDDEN_ROWS, from: seg.v + seg.rows * R, to: row, hidden: true }); | |
| seg = { v: row, y: y + HIDDEN_ROWS, rows: 1 }; | |
| } else { | |
| seg = { v: row, y: 0, rows: 1 }; | |
| } | |
| segs.push(seg); | |
| } | |
| } | |
| regs.sort((a, b) => a.v - b.v || b.bytes - a.bytes); | |
| const byNode = new Map(); | |
| for (const P of pers) byNode.set(P.node.id, P); | |
| for (const r of regs) byNode.set(r.node.id, r); | |
| const last = segs[segs.length - 1]; | |
| const layout = { | |
| R, pers, regs, segs, folds, byNode, dense: map.dense, | |
| rows: last ? last.y + last.rows : 0, | |
| maxBytes: regs.reduce((max, r) => Math.max(max, r.bytes), 4), | |
| }; | |
| // Visible rows of each peripheral | |
| for (const P of pers) { | |
| const rects = spanRects(P.v, P.vend - P.v, layout); | |
| P.r0 = rects.length ? rects[0].row : 0; | |
| P.r1 = rects.length ? rects[rects.length - 1].row + rects[rects.length - 1].rows : 0; | |
| P.drawn = rects.length > 0; | |
| } | |
| return layout; | |
| } | |
| function ensureLayout() { | |
| if (!model || map.layout) return; | |
| map.layout = buildLayout(); | |
| fitWidth(); | |
| } | |
| /* Geometry: columns are bytes, rows are multiples of rowBytes */ | |
| const sx = (col) => map.ox + col * map.k; | |
| const sy = (row) => map.oy + row * ROW_UNITS * map.k; | |
| function spanRects(v, len, L = map.layout) { | |
| const R = L.R, rects = []; | |
| const end = v + len; | |
| let a = v; | |
| while (a < end) { | |
| const index = Math.max(0, lastIndex(L.segs, "v", a)); | |
| const s = L.segs[index]; | |
| if (a < s.v) { a = s.v; continue; } | |
| const d = a - s.v, rowIndex = Math.floor(d / R), row = s.y + rowIndex, col = d % R; | |
| // Continue with the next segment after folded or hidden rows | |
| if (rowIndex >= s.rows) { | |
| const next = L.segs[index + 1]; | |
| if (!next || next.v >= end) break; | |
| a = next.v; | |
| continue; | |
| } | |
| if (col === 0 && end - a >= 2 * R) { | |
| const full = Math.min(Math.floor((end - a) / R), s.rows - rowIndex); | |
| rects.push({ row, col: 0, rows: full, cols: R }); | |
| a += full * R; | |
| } else { | |
| const n = Math.min(end - a, R - col); | |
| rects.push({ row, col, rows: 1, cols: n }); | |
| a += n; | |
| } | |
| } | |
| return rects; | |
| } | |
| /* Outline of an address span, e.g. a peripheral that starts and ends within a row */ | |
| function spanPath(ctx, v, len) { | |
| const rects = spanRects(v, len), R = map.layout.R; | |
| ctx.beginPath(); | |
| const contiguous = rects.every((r, i) => !i || Math.abs(r.row - (rects[i - 1].row + rects[i - 1].rows)) < 1e-6); | |
| if (rects.length === 1 || rects.length > 3 || !contiguous) { | |
| for (const r of rects) ctx.rect(sx(r.col), sy(r.row), r.cols * map.k, r.rows * ROW_UNITS * map.k); | |
| return rects; | |
| } | |
| const first = rects[0], last = rects[rects.length - 1]; | |
| const top = first.row, bottom = last.row + last.rows, startCol = first.col, endCol = last.col + last.cols; | |
| ctx.moveTo(sx(startCol), sy(top)); | |
| ctx.lineTo(sx(R), sy(top)); | |
| if (endCol < R) { | |
| ctx.lineTo(sx(R), sy(bottom - 1)); | |
| ctx.lineTo(sx(endCol), sy(bottom - 1)); | |
| ctx.lineTo(sx(endCol), sy(bottom)); | |
| } else { | |
| ctx.lineTo(sx(R), sy(bottom)); | |
| } | |
| ctx.lineTo(sx(0), sy(bottom)); | |
| if (startCol > 0) { | |
| ctx.lineTo(sx(0), sy(top + 1)); | |
| ctx.lineTo(sx(startCol), sy(top + 1)); | |
| } else { | |
| ctx.lineTo(sx(0), sy(top)); | |
| } | |
| ctx.closePath(); | |
| return rects; | |
| } | |
| function spanOf(node) { | |
| const L = map.layout; | |
| if (!L || !node) return null; | |
| if (node.type === "enum") node = node.parent; | |
| if (node.type === "field") { | |
| const item = L.byNode.get(node.parent.id); | |
| return item ? { v: item.v, len: item.bytes, item, field: node } : null; | |
| } | |
| if (node.type === "cluster") { | |
| let lo = Infinity, hi = -Infinity; | |
| const visit = (parent) => { | |
| for (const child of parent.children) { | |
| const item = L.byNode.get(child.id); | |
| if (child.type === "register" && item) { lo = Math.min(lo, item.v); hi = Math.max(hi, item.v + item.bytes); } | |
| else if (child.type === "cluster") visit(child); | |
| } | |
| }; | |
| visit(node); | |
| return lo < hi ? { v: lo, len: hi - lo } : null; | |
| } | |
| const item = L.byNode.get(node.id); | |
| if (!item) return null; | |
| return node.type === "peripheral" ? { v: item.v, len: item.vend - item.v, item } : { v: item.v, len: item.bytes, item }; | |
| } | |
| const colorsFor = (access) => { | |
| const short = ACCESS[access]; | |
| return short === "ro" ? map.colors.ro : short === "wo" ? map.colors.wo : map.colors.rw; | |
| }; | |
| const widths = new Map(); | |
| function fitText(ctx, text, x, y, maxWidth) { | |
| const key = ctx.font + "|" + text; | |
| let width = widths.get(key); | |
| if (width === undefined) { | |
| width = ctx.measureText(text).width; | |
| if (widths.size > 50000) widths.clear(); | |
| widths.set(key, width); | |
| } | |
| if (width > maxWidth) return false; | |
| ctx.fillText(text, x, y); | |
| return true; | |
| } | |
| function fitTextRotated(ctx, text, cx, cy, maxLength, maxThickness, fontSize) { | |
| if (fontSize > maxThickness) return false; | |
| const key = ctx.font + "|" + text; | |
| let width = widths.get(key); | |
| if (width === undefined) { width = ctx.measureText(text).width; widths.set(key, width); } | |
| if (width > maxLength) return false; | |
| ctx.save(); | |
| ctx.translate(cx, cy); | |
| ctx.rotate(-Math.PI / 2); | |
| ctx.fillText(text, 0, 0); | |
| ctx.restore(); | |
| return true; | |
| } | |
| function drawRegister(ctx, item) { | |
| const C = map.colors, node = item.node, k = map.k, rowPx = ROW_UNITS * k; | |
| const rects = spanRects(item.v, item.bytes); | |
| const [fill, line] = colorsFor(node.access); | |
| const dimmed = filter && !filter.keep.has(node.id); | |
| const matched = filter && filter.matched.has(node.id); | |
| const r = rects[0]; | |
| const x = sx(r.col), y = sy(r.row), w = r.cols * k, h = r.rows * rowPx; | |
| const bits = item.bytes * 8; | |
| const bitW = w / bits; | |
| const showFields = rects.length === 1 && !node.dim && bitW >= 2.5 && node.children.length > 0 && h >= 6; | |
| ctx.globalAlpha = dimmed ? 0.25 : 1; | |
| for (const piece of rects) { | |
| const px = sx(piece.col), py = sy(piece.row), pw = piece.cols * k, ph = piece.rows * rowPx; | |
| // With bit fields, the register shows its unused bits like unused address space | |
| ctx.fillStyle = showFields ? C.periph : matched ? C.mark : fill; | |
| ctx.fillRect(px, py, pw, ph); | |
| if (showFields && map.hatch) { ctx.fillStyle = map.hatch; ctx.fillRect(px, py, pw, ph); } | |
| if (rowPx >= 4 && pw >= 3) { | |
| ctx.strokeStyle = line; | |
| ctx.lineWidth = 1; | |
| ctx.strokeRect(px + 0.5, py + 0.5, Math.max(0, pw - 1), Math.max(0, ph - 1)); | |
| } | |
| } | |
| if (y > map.height || y + h < 0) { ctx.globalAlpha = 1; return; } | |
| ctx.fillStyle = C.ink; | |
| ctx.textBaseline = "middle"; | |
| if (showFields) { | |
| const top = headerHeight(h), bottom = bitNumbersHeight(h, bitW); | |
| const fy = y + top, fh = h - top; | |
| ctx.save(); | |
| ctx.beginPath(); | |
| ctx.rect(x, y, w, h); | |
| ctx.clip(); | |
| // The register name strip is not bit space | |
| if (top) { ctx.fillStyle = C.periph; ctx.fillRect(x, y, w, top); } | |
| for (const f of node.children) { | |
| const fx = x + (bits - 1 - f.msb) * bitW, fw = f.width * bitW; | |
| const fieldMatched = filter && filter.matched.has(f.id); | |
| ctx.globalAlpha = dimmed || (filter && !filter.keep.has(f.id) && !matched) ? 0.35 : 1; | |
| ctx.fillStyle = fieldMatched || matched ? C.mark : fill; | |
| ctx.fillRect(fx, fy, fw, fh); | |
| ctx.strokeStyle = line; | |
| ctx.strokeRect(fx + 0.5, fy + 0.5, Math.max(0, fw - 1), Math.max(0, fh - 1)); | |
| } | |
| ctx.globalAlpha = dimmed ? 0.25 : 1; | |
| // The outline of the register stays on top of its bit fields | |
| ctx.strokeStyle = line; | |
| ctx.lineWidth = 1.5; | |
| ctx.strokeRect(x + 0.75, y + 0.75, Math.max(0, w - 1.5), Math.max(0, h - 1.5)); | |
| if (top) { | |
| ctx.lineWidth = 1; | |
| ctx.beginPath(); | |
| ctx.moveTo(x, Math.round(fy) + 0.5); | |
| ctx.lineTo(x + w, Math.round(fy) + 0.5); | |
| ctx.stroke(); | |
| } | |
| ctx.fillStyle = C.ink; | |
| if (top) { | |
| ctx.textAlign = "left"; | |
| ctx.font = `600 11px ${FONT_MONO}`; | |
| fitText(ctx, node.name, x + 5, y + top / 2 + 0.5, w - 10); | |
| } | |
| // Field names are horizontal when they fit, otherwise rotated along the bits | |
| const labelTop = fy, labelHeight = fh - bottom, mid = labelTop + labelHeight / 2; | |
| ctx.textAlign = "center"; | |
| let labelled = false; | |
| for (const f of node.children) { | |
| const fx = x + (bits - 1 - f.msb) * bitW, fw = f.width * bitW, cx = fx + fw / 2; | |
| if (fw < 7 || labelHeight < 9) continue; | |
| ctx.font = `11px ${FONT_MONO}`; | |
| if (labelHeight >= 14 && fitText(ctx, f.name, cx, mid, fw - 6)) { labelled = true; continue; } | |
| if (fitTextRotated(ctx, f.name, cx, mid, labelHeight - 6, fw - 2, 11)) { labelled = true; continue; } | |
| ctx.font = `9px ${FONT_MONO}`; | |
| labelled = fitTextRotated(ctx, f.name, cx, mid, labelHeight - 4, fw - 1, 9) || labelled; | |
| } | |
| if (!top && !labelled && h >= 12) { | |
| ctx.font = `500 11px ${FONT_MONO}`; | |
| fitText(ctx, node.name, x + w / 2, y + h / 2, w - 4); | |
| } | |
| if (bottom) { | |
| ctx.font = `9.5px ${FONT_MONO}`; | |
| ctx.fillStyle = C.muted; | |
| for (let b = 0; b < bits; b++) ctx.fillText(String(b), x + (bits - 1 - b + 0.5) * bitW, y + h - bottom / 2); | |
| } | |
| ctx.restore(); | |
| } else if (h >= 12 && w >= 16) { | |
| ctx.textAlign = "center"; | |
| ctx.font = `${h >= 22 ? "500 11px" : "10px"} ${FONT_MONO}`; | |
| fitText(ctx, node.name, x + w / 2, y + Math.min(h, rowPx) / 2, w - 4); | |
| } | |
| ctx.globalAlpha = 1; | |
| } | |
| function outline(ctx, node, color, width) { | |
| const span = spanOf(node); | |
| if (!span) return; | |
| if (span.field) { | |
| const r = spanRects(span.v, span.len); | |
| const x = sx(r[0].col), y = sy(r[0].row), w = r[0].cols * map.k, h = ROW_UNITS * map.k; | |
| const bits = span.item.bytes * 8, bitW = w / bits, top = headerHeight(h); | |
| ctx.beginPath(); | |
| if (r.length === 1 && bitW >= 2.5) ctx.rect(x + (bits - 1 - span.field.msb) * bitW, y + top, span.field.width * bitW, h - top); | |
| else ctx.rect(x, y, w, h); | |
| } else { | |
| spanPath(ctx, span.v, span.len); | |
| } | |
| ctx.strokeStyle = color; | |
| ctx.lineWidth = width; | |
| ctx.stroke(); | |
| } | |
| function drawMap() { | |
| map.frame = 0; | |
| const L = map.layout, C = map.colors, ctx = mapCtx; | |
| const W = map.width, H = map.height; | |
| if (!W || !H || !C) return; | |
| ctx.setTransform(map.dpr, 0, 0, map.dpr, 0, 0); | |
| ctx.fillStyle = C.surface; | |
| ctx.fillRect(0, 0, W, H); | |
| if (!L || !L.rows) { | |
| ctx.fillStyle = C.muted; | |
| ctx.font = `13px ${FONT_SANS}`; | |
| ctx.textBaseline = "middle"; | |
| ctx.textAlign = "left"; | |
| ctx.fillText(model ? "This file has no peripherals to draw." : "No file loaded.", 20, 28); | |
| drawOverview(); | |
| return; | |
| } | |
| const k = map.k, rowPx = ROW_UNITS * k, R = L.R; | |
| const rowTop = -map.oy / rowPx - 1, rowBottom = (H - map.oy) / rowPx + 1; | |
| const visible = (row, rows) => row + rows >= rowTop && row <= rowBottom; | |
| ctx.save(); | |
| ctx.beginPath(); | |
| ctx.rect(GUTTER, 0, W - GUTTER, H); | |
| ctx.clip(); | |
| // Word grid of the address space | |
| if (rowPx >= 10) { | |
| ctx.strokeStyle = C.rule; | |
| ctx.lineWidth = 1; | |
| ctx.beginPath(); | |
| for (const s of L.segs) { | |
| if (!visible(s.y, s.rows)) continue; | |
| const r0 = Math.max(0, Math.floor(rowTop - s.y)), r1 = Math.min(s.rows, Math.ceil(rowBottom - s.y)); | |
| for (let r = r0; r <= r1; r++) { | |
| const y = Math.round(sy(s.y + r)) + 0.5; | |
| ctx.moveTo(sx(0), y); | |
| ctx.lineTo(sx(R), y); | |
| } | |
| const y0 = sy(s.y + r0), y1 = sy(s.y + r1); | |
| for (let c = 0; c <= R; c += 4) { | |
| const x = Math.round(sx(c)) + 0.5; | |
| ctx.moveTo(x, y0); | |
| ctx.lineTo(x, y1); | |
| } | |
| } | |
| ctx.stroke(); | |
| } | |
| // Folded gaps between peripherals | |
| ctx.textBaseline = "middle"; | |
| for (const f of L.folds) { | |
| if (!visible(f.y, f.rows)) continue; | |
| const y0 = sy(f.y), y1 = sy(f.y + f.rows), mid = Math.round((y0 + y1) / 2) + 0.5; | |
| ctx.strokeStyle = C.ruleStrong; | |
| ctx.lineWidth = 1; | |
| ctx.setLineDash([5, 4]); | |
| ctx.beginPath(); | |
| ctx.moveTo(sx(0), mid); | |
| ctx.lineTo(sx(R), mid); | |
| ctx.stroke(); | |
| ctx.setLineDash([]); | |
| if (y1 - y0 >= 12) { | |
| const label = f.hidden | |
| ? `${plural((f.to - f.from) / R, "empty row")} hidden · ${hex(f.from, 32)} – ${hex(f.to - 1, 32)}` | |
| : `unused ${hex(f.from, 32)} – ${hex(f.to - 1, 32)} · ${sizeText(f.to - f.from)}`; | |
| ctx.font = `11px ${FONT_MONO}`; | |
| ctx.textAlign = "center"; | |
| const cx = clamp(sx(R / 2), GUTTER + 160, W - 160); | |
| const width = ctx.measureText(label).width + 12; | |
| ctx.fillStyle = C.surface; | |
| ctx.fillRect(cx - width / 2, mid - 8, width, 16); | |
| ctx.fillStyle = C.muted; | |
| ctx.fillText(label, cx, mid); | |
| } | |
| } | |
| // Peripherals with their unused space | |
| for (const P of L.pers) { | |
| if (!P.drawn || !visible(P.r0, P.r1 - P.r0)) continue; | |
| spanPath(ctx, P.v, P.vend - P.v); | |
| ctx.globalAlpha = filter && !filter.keep.has(P.node.id) ? 0.45 : 1; | |
| ctx.fillStyle = C.periph; | |
| ctx.fill(); | |
| if (rowPx >= 3 && map.hatch) { ctx.fillStyle = map.hatch; ctx.fill(); } | |
| ctx.strokeStyle = C.ruleStrong; | |
| ctx.lineWidth = 1; | |
| ctx.stroke(); | |
| ctx.globalAlpha = 1; | |
| } | |
| // Registers and bit fields | |
| for (const s of L.segs) { | |
| if (!visible(s.y, s.rows)) continue; | |
| const vStart = s.v + Math.max(0, Math.floor(rowTop - s.y)) * R; | |
| const vEnd = s.v + Math.min(s.rows, Math.ceil(rowBottom - s.y) + 1) * R; | |
| for (let i = Math.max(0, lastIndex(L.regs, "v", vStart - L.maxBytes)); i < L.regs.length && L.regs[i].v < vEnd; i++) { | |
| const item = L.regs[i]; | |
| if (item.v + item.bytes > vStart) drawRegister(ctx, item); | |
| } | |
| } | |
| if (map.hover && map.hover !== map.selected) outline(ctx, map.hover, C.accent, 1.5); | |
| if (map.selected) outline(ctx, map.selected, C.ink, 2); | |
| ctx.restore(); | |
| // Gutter with peripheral names and row addresses | |
| ctx.fillStyle = C.surface; | |
| ctx.fillRect(0, 0, GUTTER, H); | |
| ctx.fillStyle = C.rule; | |
| ctx.fillRect(GUTTER - 1, 0, 1, H); | |
| ctx.textBaseline = "middle"; | |
| const labelY = (row) => sy(row) + Math.min(rowPx, 18) / 2; | |
| const step = rowPx >= 15 ? 1 : 2 ** Math.ceil(Math.log2(15 / rowPx)); | |
| ctx.font = `10.5px ${FONT_MONO}`; | |
| ctx.textAlign = "right"; | |
| ctx.fillStyle = C.faint; | |
| for (const s of L.segs) { | |
| if (!visible(s.y, s.rows)) continue; | |
| const from = Math.max(0, Math.floor(rowTop - s.y)), to = Math.min(s.rows - 1, Math.ceil(rowBottom - s.y)); | |
| for (let r = Math.ceil(from / step) * step; r <= to; r += step) { | |
| ctx.fillText(hex(s.v + r * R, 32), GUTTER - 10, labelY(s.y + r)); | |
| } | |
| } | |
| for (const f of L.folds) { | |
| if (!visible(f.y, f.rows)) continue; | |
| ctx.fillText("⋮", GUTTER - 40, (sy(f.y) + sy(f.y + f.rows)) / 2); | |
| } | |
| ctx.textAlign = "left"; | |
| let lastLabel = -Infinity; | |
| const selectedSpan = map.selected ? spanOf(map.selected) : null; | |
| for (const P of L.pers) { | |
| if (!P.drawn) continue; | |
| const y = labelY(P.r0); | |
| if (y < -12 || y > H + 12) continue; | |
| const selected = selectedSpan?.item?.per === P || map.selected === P.node; | |
| if (y - lastLabel < 15 && !selected) continue; | |
| ctx.font = `600 11.5px ${FONT_SANS}`; | |
| ctx.fillStyle = selected ? C.accent : filter && !filter.keep.has(P.node.id) ? C.faint : C.ink; | |
| let name = P.node.name; | |
| while (name.length > 3 && ctx.measureText(name).width > 76) name = name.slice(0, -2) + "…"; | |
| if (name !== P.node.name && !name.endsWith("…")) name += "…"; | |
| ctx.fillText(name, 10, y); | |
| lastLabel = y; | |
| } | |
| drawOverview(); | |
| } | |
| function drawOverview() { | |
| const ctx = overviewCtx, L = map.layout, C = map.colors, H = map.height; | |
| if (!H || !C) return; | |
| ctx.setTransform(map.dpr, 0, 0, map.dpr, 0, 0); | |
| ctx.fillStyle = C.band; | |
| ctx.fillRect(0, 0, OVERVIEW, H); | |
| if (!L || !L.rows) return; | |
| const scale = (H - 8) / L.rows; | |
| const selectedPeripheral = map.selected ? (spanOf(map.selected)?.item?.per ?? L.byNode.get(map.selected.id)) : null; | |
| for (const P of L.pers) { | |
| if (!P.drawn) continue; | |
| const kept = !filter || filter.keep.has(P.node.id); | |
| ctx.fillStyle = P === selectedPeripheral ? C.accent : filter && kept ? C.mark : kept ? C.ruleStrong : C.rule; | |
| ctx.fillRect(10, 4 + P.r0 * scale, OVERVIEW - 20, Math.max(1, (P.r1 - P.r0) * scale - 0.5)); | |
| } | |
| ctx.fillStyle = C.faint; | |
| for (const f of L.folds) ctx.fillRect(18, 4 + (f.y + f.rows / 2) * scale, OVERVIEW - 36, 1); | |
| const rowPx = ROW_UNITS * map.k; | |
| const y0 = 4 + clamp(-map.oy / rowPx, 0, L.rows) * scale, y1 = 4 + clamp((H - map.oy) / rowPx, 0, L.rows) * scale; | |
| ctx.globalAlpha = 0.25; | |
| ctx.fillStyle = C.accent; | |
| ctx.fillRect(3, y0, OVERVIEW - 6, Math.max(3, y1 - y0)); | |
| ctx.globalAlpha = 1; | |
| ctx.strokeStyle = C.accent; | |
| ctx.lineWidth = 1.5; | |
| ctx.strokeRect(3.5, y0, OVERVIEW - 7, Math.max(3, y1 - y0)); | |
| } | |
| function scheduleDraw() { | |
| if (currentView !== "map" || map.frame || map.anim) return; | |
| map.frame = requestAnimationFrame(drawMap); | |
| } | |
| function resizeMap() { | |
| const rect = els.mapFrame.getBoundingClientRect(); | |
| const dpr = window.devicePixelRatio || 1; | |
| const W = Math.max(0, Math.floor(rect.width - 2 - OVERVIEW)), H = Math.max(0, Math.floor(rect.height - 2)); | |
| if (W === map.width && H === map.height && dpr === map.dpr) return false; | |
| map.width = W; | |
| map.height = H; | |
| map.dpr = dpr; | |
| for (const [canvas, width] of [[els.map, W], [els.overview, OVERVIEW]]) { | |
| canvas.width = Math.round(width * dpr); | |
| canvas.height = Math.round(H * dpr); | |
| canvas.style.width = `${width}px`; | |
| canvas.style.height = `${H}px`; | |
| } | |
| return true; | |
| } | |
| const minZoom = () => { | |
| const L = map.layout; | |
| if (!L || !L.rows) return 0.01; | |
| return Math.min((map.width - GUTTER - 24) / L.R, (map.height - 24) / (L.rows * ROW_UNITS)) * 0.9; | |
| }; | |
| function fitTarget() { | |
| const L = map.layout; | |
| return { k: L ? clamp((map.width - GUTTER - 24) / L.R, minZoom(), K_MAX) : map.k, ox: GUTTER + 12, oy: 12 }; | |
| } | |
| function fitWidth() { | |
| if (map.layout) Object.assign(map, fitTarget()); | |
| } | |
| function clampView() { | |
| const L = map.layout; | |
| if (!L) return; | |
| const W = map.width - GUTTER, H = map.height; | |
| const contentW = L.R * map.k, contentH = L.rows * ROW_UNITS * map.k; | |
| map.ox = clamp(map.ox, GUTTER + W / 2 - contentW, GUTTER + W / 2); | |
| map.oy = clamp(map.oy, H / 2 - contentH, H / 2); | |
| } | |
| function zoomAt(px, py, factor) { | |
| cancelAnimationFrame(map.anim); | |
| map.anim = 0; | |
| const k = clamp(map.k * factor, minZoom(), K_MAX), f = k / map.k; | |
| map.ox = px - (px - map.ox) * f; | |
| map.oy = py - (py - map.oy) * f; | |
| map.k = k; | |
| clampView(); | |
| scheduleDraw(); | |
| } | |
| function animateTo(target, animate = true) { | |
| cancelAnimationFrame(map.anim); | |
| map.anim = 0; | |
| const W = map.width - GUTTER, H = map.height; | |
| if (!animate || matchMedia("(prefers-reduced-motion: reduce)").matches) { | |
| Object.assign(map, target); | |
| clampView(); | |
| scheduleDraw(); | |
| return; | |
| } | |
| const center = (s) => ({ x: (GUTTER + W / 2 - s.ox) / s.k, y: (H / 2 - s.oy) / s.k }); | |
| const from = { k: map.k, ...center(map) }, to = { k: target.k, ...center(target) }; | |
| const start = performance.now(), duration = 320; | |
| const step = (now) => { | |
| const t = Math.min(1, (now - start) / duration), e = 1 - Math.pow(1 - t, 3); | |
| const k = Math.exp(Math.log(from.k) + (Math.log(to.k) - Math.log(from.k)) * e); | |
| map.k = k; | |
| map.ox = GUTTER + W / 2 - (from.x + (to.x - from.x) * e) * k; | |
| map.oy = H / 2 - (from.y + (to.y - from.y) * e) * k; | |
| drawMap(); | |
| if (t < 1) { map.anim = requestAnimationFrame(step); } | |
| else { map.anim = 0; clampView(); scheduleDraw(); } | |
| }; | |
| map.anim = requestAnimationFrame(step); | |
| } | |
| function zoomTo(node, animate = true) { | |
| const span = spanOf(node); | |
| if (!span) return; | |
| const rects = spanRects(span.v, span.len); | |
| let x0 = Math.min(...rects.map((r) => r.col)), x1 = Math.max(...rects.map((r) => r.col + r.cols)); | |
| const y0 = rects[0].row, y1 = rects[rects.length - 1].row + rects[rects.length - 1].rows; | |
| if (span.field && rects.length === 1) { | |
| const bits = span.item.bytes * 8, byteW = (x1 - x0) / bits; | |
| x0 = rects[0].col + (bits - 1 - span.field.msb) * byteW; | |
| x1 = x0 + span.field.width * byteW; | |
| } | |
| const W = map.width - GUTTER, H = map.height; | |
| const k = clamp(Math.min((W * 0.86) / Math.max(x1 - x0, 1e-3), (H * 0.62) / ((y1 - y0) * ROW_UNITS)), minZoom(), K_MAX); | |
| const cx = (x0 + x1) / 2, cy = ((y0 + y1) / 2) * ROW_UNITS; | |
| animateTo({ k, ox: GUTTER + W / 2 - cx * k, oy: H / 2 - cy * k }, animate); | |
| } | |
| function hitTest(px, py) { | |
| const L = map.layout; | |
| if (!L || px < GUTTER) return null; | |
| const k = map.k, rowPx = ROW_UNITS * k; | |
| const rowF = (py - map.oy) / rowPx, col = Math.floor((px - map.ox) / k); | |
| if (col < 0 || col >= L.R || rowF < 0) return null; | |
| const s = L.segs[lastIndex(L.segs, "y", rowF)]; | |
| if (!s || rowF >= s.y + s.rows) return null; | |
| const v = s.v + Math.floor(rowF - s.y) * L.R + col; | |
| for (let i = lastIndex(L.regs, "v", v); i >= 0 && L.regs[i].v > v - L.maxBytes; i--) { | |
| const item = L.regs[i]; | |
| if (v < item.v || v >= item.v + item.bytes) continue; | |
| const rects = spanRects(item.v, item.bytes); | |
| if (rects.length === 1 && !item.node.dim) { | |
| const bits = item.bytes * 8, bitW = (rects[0].cols * k) / bits; | |
| const inHeader = py - sy(rects[0].row) < headerHeight(rowPx); | |
| if (bitW >= 2.5 && !inHeader) { | |
| const bit = bits - 1 - Math.floor((px - sx(rects[0].col)) / bitW); | |
| const field = item.node.children.find((f) => bit >= f.lsb && bit <= f.msb); | |
| if (field) return field; | |
| } | |
| } | |
| return item.node; | |
| } | |
| let peripheral = null; | |
| for (const P of L.pers) if (v >= P.v && v < P.vend) peripheral = P.node; | |
| return peripheral; | |
| } | |
| function describe(node) { | |
| const L = map.layout; | |
| switch (node.type) { | |
| case "peripheral": { | |
| const P = L?.byNode.get(node.id); | |
| return P ? `${hex(P.start, 32)} – ${hex(P.end - 1, 32)} · ${sizeText(P.end - P.start)}` : hex(node.address, 32); | |
| } | |
| case "cluster": return `${hex(node.address, 32)} · cluster`; | |
| case "register": | |
| return `${hex(node.address, 32)} · ${node.size} bits${node.access ? ` · ${ACCESS[node.access] || node.access}` : ""}`; | |
| case "field": | |
| return `${bitRange(node)} · ${plural(node.width, "bit")}${node.access ? ` · ${ACCESS[node.access] || node.access}` : ""}`; | |
| default: return ""; | |
| } | |
| } | |
| const countOf = (node, type) => node.children.reduce((n, c) => n + (c.type === type ? 1 : 0) + countOf(c, type), 0); | |
| function renderCard() { | |
| const node = map.selected; | |
| els.mapCard.hidden = !node; | |
| if (!node) return; | |
| const rows = []; | |
| const add = (label, value, mono = true) => { | |
| if (value !== "" && value != null) rows.push(`<div><dt>${label}</dt><dd${mono ? ' class="num"' : ""}>${value}</dd></div>`); | |
| }; | |
| const P = map.layout?.byNode.get(node.id); | |
| switch (node.type) { | |
| case "peripheral": | |
| if (P) { | |
| add("Address", `${hex(P.start, 32)} – ${hex(P.end - 1, 32)}`); | |
| add("Size", `${sizeText(P.end - P.start)}${P.inferred ? " (rounded up to 1 KiB, the file has no address block)" : ""}`, false); | |
| } | |
| add("Registers", countOf(node, "register").toLocaleString(), false); | |
| if (node.derivedFrom) add("Derived from", esc(node.derivedFrom)); | |
| if (node.interrupts.length) add("Interrupts", node.interrupts.map((i) => `${esc(i.name)} (${esc(i.value)})`).join(", ")); | |
| break; | |
| case "cluster": | |
| add("Address", hex(node.address, 32)); | |
| add("Offset", offsetText(node.offset)); | |
| add("Registers", countOf(node, "register").toLocaleString(), false); | |
| break; | |
| case "register": | |
| add("Address", hex(node.address, 32)); | |
| add("Offset", offsetText(node.offset)); | |
| add("Size", node.dim ? `${node.dim} × ${node.size} bits` : `${node.size} bits`, false); | |
| add("Access", esc(ACCESS[node.access] || node.access || "")); | |
| add("Reset", node.reset != null ? hex(node.reset, node.size) : ""); | |
| add("Bit fields", node.children.length ? node.children.length.toLocaleString() : "", false); | |
| break; | |
| case "field": | |
| add("Bits", bitRange(node)); | |
| add("Width", plural(node.width, "bit"), false); | |
| add("Access", esc([ACCESS[node.access] || node.access, WRITES[node.writes] || node.writes].filter(Boolean).join(" "))); | |
| add("Reset", node.reset != null ? bitsValue(node.reset, node.width) : ""); | |
| add("Values", node.children.map((v) => `${esc(v.name)} = ${v.value != null ? bitsValue(v.value, v.width) : esc(v.raw)}`).join("<br>")); | |
| break; | |
| } | |
| const kind = { peripheral: "Peripheral", cluster: "Cluster", register: "Register", field: "Bit field" }[node.type] || ""; | |
| els.mapCard.innerHTML = | |
| `<div class="card-head"><span class="kind">${kind}</span>` + | |
| `<button class="card-close" type="button" data-action="close" aria-label="Close details">×</button></div>` + | |
| `<h3 class="card-name">${esc(node.path)}</h3>` + | |
| (rows.length ? `<dl>${rows.join("")}</dl>` : "") + | |
| (node.desc ? `<p class="card-desc">${esc(node.desc)}</p>` : "") + | |
| `<div class="card-actions"><button class="btn" type="button" data-action="zoom">Zoom to</button>` + | |
| `<button class="btn" type="button" data-action="table">Show in table</button></div>`; | |
| } | |
| function renderCrumbs() { | |
| if (!model) { els.crumbs.innerHTML = ""; return; } | |
| const chain = []; | |
| for (let node = map.selected; node; node = node.parent) chain.unshift(node); | |
| els.crumbs.innerHTML = `<button class="crumb" type="button" data-crumb="device" aria-current="${!chain.length}">${esc(model.name)}</button>` + | |
| chain.map((node) => `<span class="crumb-sep" aria-hidden="true">/</span>` + | |
| `<button class="crumb" type="button" data-crumb="${node.id}" aria-current="${node === map.selected}">${esc(node.name)}</button>`).join(""); | |
| } | |
| function select(node) { | |
| map.selected = node && node.type === "enum" ? node.parent : node; | |
| renderCard(); | |
| renderCrumbs(); | |
| scheduleDraw(); | |
| } | |
| function showOnMap(node) { | |
| switchView("map"); | |
| ensureLayout(); | |
| select(node); | |
| zoomTo(map.selected, false); | |
| } | |
| function rebuildMap() { | |
| if (!model) return; | |
| map.layout = buildLayout(); | |
| if (map.selected && spanOf(map.selected)) zoomTo(map.selected, false); | |
| else { fitWidth(); scheduleDraw(); } | |
| } | |
| /* ---------- Map events ---------- */ | |
| const pointers = new Map(); | |
| let drag = null; | |
| let pinch = null; | |
| els.map.addEventListener("pointerdown", (e) => { | |
| cancelAnimationFrame(map.anim); | |
| map.anim = 0; | |
| els.map.focus({ preventScroll: true }); | |
| els.map.setPointerCapture(e.pointerId); | |
| pointers.set(e.pointerId, { x: e.offsetX, y: e.offsetY }); | |
| if (pointers.size === 2) { | |
| const [a, b] = [...pointers.values()]; | |
| pinch = { distance: Math.hypot(a.x - b.x, a.y - b.y) }; | |
| drag = null; | |
| } else { | |
| drag = { x: e.offsetX, y: e.offsetY, ox: map.ox, oy: map.oy, moved: false }; | |
| } | |
| }); | |
| els.map.addEventListener("pointermove", (e) => { | |
| if (pointers.has(e.pointerId)) pointers.set(e.pointerId, { x: e.offsetX, y: e.offsetY }); | |
| if (pinch && pointers.size === 2) { | |
| const [a, b] = [...pointers.values()]; | |
| const distance = Math.hypot(a.x - b.x, a.y - b.y); | |
| if (pinch.distance > 0) zoomAt((a.x + b.x) / 2, (a.y + b.y) / 2, distance / pinch.distance); | |
| pinch.distance = distance; | |
| return; | |
| } | |
| if (drag && pointers.has(e.pointerId)) { | |
| const dx = e.offsetX - drag.x, dy = e.offsetY - drag.y; | |
| if (!drag.moved && Math.hypot(dx, dy) > 3) { drag.moved = true; els.map.classList.add("dragging"); els.mapTip.hidden = true; } | |
| if (drag.moved) { | |
| map.ox = drag.ox + dx; | |
| map.oy = drag.oy + dy; | |
| clampView(); | |
| scheduleDraw(); | |
| } | |
| return; | |
| } | |
| const hit = hitTest(e.offsetX, e.offsetY); | |
| if (hit !== map.hover) { map.hover = hit; scheduleDraw(); } | |
| if (!hit) { els.mapTip.hidden = true; return; } | |
| els.mapTip.innerHTML = `<strong>${esc(hit.path)}</strong><span>${esc(describe(hit))}</span>`; | |
| els.mapTip.hidden = false; | |
| const tipW = els.mapTip.offsetWidth, tipH = els.mapTip.offsetHeight; | |
| els.mapTip.style.left = `${Math.min(e.offsetX + 14, map.width - tipW - 8)}px`; | |
| els.mapTip.style.top = `${e.offsetY + 18 + tipH > map.height ? e.offsetY - tipH - 10 : e.offsetY + 18}px`; | |
| }); | |
| const endPointer = (e) => { | |
| const wasClick = drag && !drag.moved && pointers.size === 1 && e.type === "pointerup"; | |
| pointers.delete(e.pointerId); | |
| if (pointers.size < 2) pinch = null; | |
| els.map.classList.remove("dragging"); | |
| if (wasClick) select(hitTest(e.offsetX, e.offsetY)); | |
| drag = null; | |
| }; | |
| els.map.addEventListener("pointerup", endPointer); | |
| els.map.addEventListener("pointercancel", endPointer); | |
| els.map.addEventListener("pointerleave", () => { | |
| if (drag) return; | |
| els.mapTip.hidden = true; | |
| if (map.hover) { map.hover = null; scheduleDraw(); } | |
| }); | |
| els.map.addEventListener("dblclick", (e) => { | |
| const hit = hitTest(e.offsetX, e.offsetY); | |
| if (hit) { select(hit); zoomTo(hit); } | |
| else zoomAt(e.offsetX, e.offsetY, 2); | |
| }); | |
| els.map.addEventListener("wheel", (e) => { | |
| e.preventDefault(); | |
| const scale = e.deltaMode === 1 ? 16 : e.deltaMode === 2 ? map.height : 1; | |
| if (e.ctrlKey || e.metaKey) { | |
| zoomAt(e.offsetX, e.offsetY, Math.exp(-e.deltaY * scale * 0.0025)); | |
| } else { | |
| cancelAnimationFrame(map.anim); | |
| map.anim = 0; | |
| map.ox -= (e.shiftKey && !e.deltaX ? e.deltaY : e.deltaX) * scale; | |
| map.oy -= (e.shiftKey && !e.deltaX ? 0 : e.deltaY) * scale; | |
| clampView(); | |
| scheduleDraw(); | |
| } | |
| }, { passive: false }); | |
| els.map.addEventListener("keydown", (e) => { | |
| const cx = GUTTER + (map.width - GUTTER) / 2, cy = map.height / 2; | |
| switch (e.key) { | |
| case "ArrowUp": map.oy += 80; break; | |
| case "ArrowDown": map.oy -= 80; break; | |
| case "ArrowLeft": map.ox += 80; break; | |
| case "ArrowRight": map.ox -= 80; break; | |
| case "PageUp": map.oy += map.height * 0.9; break; | |
| case "PageDown": map.oy -= map.height * 0.9; break; | |
| case "+": case "=": zoomAt(cx, cy, 1.5); break; | |
| case "-": case "_": zoomAt(cx, cy, 1 / 1.5); break; | |
| case "0": fitWidth(); break; | |
| case "Enter": if (map.selected) zoomTo(map.selected); break; | |
| case "Escape": select(null); break; | |
| default: return; | |
| } | |
| e.preventDefault(); | |
| clampView(); | |
| scheduleDraw(); | |
| }); | |
| let overviewDrag = false; | |
| const jump = (y) => { | |
| const L = map.layout; | |
| if (!L || !L.rows) return; | |
| const row = clamp((y - 4) / (map.height - 8), 0, 1) * L.rows; | |
| map.oy = map.height / 2 - row * ROW_UNITS * map.k; | |
| clampView(); | |
| scheduleDraw(); | |
| }; | |
| els.overview.addEventListener("pointerdown", (e) => { els.overview.setPointerCapture(e.pointerId); overviewDrag = true; jump(e.offsetY); }); | |
| els.overview.addEventListener("pointermove", (e) => { if (overviewDrag) jump(e.offsetY); }); | |
| els.overview.addEventListener("pointerup", () => { overviewDrag = false; }); | |
| els.overview.addEventListener("wheel", (e) => { | |
| e.preventDefault(); | |
| map.oy -= e.deltaY * (e.deltaMode === 1 ? 16 : 1); | |
| clampView(); | |
| scheduleDraw(); | |
| }, { passive: false }); | |
| els.mapCard.addEventListener("click", (e) => { | |
| const action = e.target.closest("[data-action]")?.dataset.action; | |
| if (!action || !map.selected) return; | |
| if (action === "close") { select(null); els.map.focus(); } | |
| else if (action === "zoom") zoomTo(map.selected); | |
| else if (action === "table") revealInTable(map.selected); | |
| }); | |
| els.crumbs.addEventListener("click", (e) => { | |
| const crumb = e.target.closest("[data-crumb]"); | |
| if (!crumb) return; | |
| if (crumb.dataset.crumb === "device") { | |
| select(null); | |
| animateTo(fitTarget()); | |
| } else { | |
| const node = model.nodes[+crumb.dataset.crumb]; | |
| select(node); | |
| zoomTo(node); | |
| } | |
| }); | |
| els.mapDense.addEventListener("change", () => { map.dense = els.mapDense.checked; rebuildMap(); }); | |
| els.mapRow.addEventListener("change", () => { map.rowBytes = +els.mapRow.value; rebuildMap(); }); | |
| els.zoomIn.addEventListener("click", () => zoomAt(GUTTER + (map.width - GUTTER) / 2, map.height / 2, 1.5)); | |
| els.zoomOut.addEventListener("click", () => zoomAt(GUTTER + (map.width - GUTTER) / 2, map.height / 2, 1 / 1.5)); | |
| els.zoomFit.addEventListener("click", () => { | |
| // Keep the row at the top of the view | |
| const top = Math.max(0, -map.oy / (ROW_UNITS * map.k)); | |
| const target = fitTarget(); | |
| target.oy = 12 - top * ROW_UNITS * target.k; | |
| animateTo(target); | |
| }); | |
| new ResizeObserver(() => { | |
| if (currentView !== "map") return; | |
| if (resizeMap()) { | |
| if (!map.layout) ensureLayout(); | |
| clampView(); | |
| drawMap(); | |
| } | |
| }).observe(els.mapFrame); | |
| const refreshColors = () => { readColors(); scheduleDraw(); }; | |
| matchMedia("(prefers-color-scheme: dark)").addEventListener?.("change", refreshColors); | |
| new MutationObserver(refreshColors).observe(document.documentElement, { attributes: true, attributeFilter: ["data-theme"] }); | |
| document.fonts?.ready.then(() => { widths.clear(); scheduleDraw(); }); | |
| /* ---------- Events ---------- */ | |
| els.menuList.addEventListener("click", (e) => { | |
| const button = e.target.closest(".menu-item"); | |
| if (button) navigate(button.dataset.file); | |
| }); | |
| let menuDebounce = 0; | |
| els.menuQuery.addEventListener("input", () => { clearTimeout(menuDebounce); menuDebounce = setTimeout(renderMenu, 80); }); | |
| els.menuQuery.addEventListener("keydown", (e) => { | |
| if (e.key === "Enter") { | |
| const first = els.menuList.querySelector(".menu-item"); | |
| if (first) navigate(first.dataset.file); | |
| } else if (e.key === "Escape" && els.menuQuery.value) { | |
| els.menuQuery.value = ""; | |
| renderMenu(); | |
| } | |
| }); | |
| window.addEventListener("popstate", () => { if (fileFromHash() !== current) openFile(fileFromHash()); }); | |
| els.tabs.addEventListener("click", (e) => { | |
| const tab = e.target.closest('[role="tab"]'); | |
| if (tab) switchView(tab === els.tabMap ? "map" : "table"); | |
| }); | |
| els.tabs.addEventListener("keydown", (e) => { | |
| if (e.key === "ArrowLeft" || e.key === "ArrowRight") { | |
| e.preventDefault(); | |
| switchView(currentView === "map" ? "table" : "map", true); | |
| } | |
| }); | |
| els.fileInput.addEventListener("change", () => { | |
| const file = els.fileInput.files[0]; | |
| if (file) loadFile(file); | |
| els.fileInput.value = ""; | |
| }); | |
| let debounce = 0; | |
| els.query.addEventListener("input", () => { clearTimeout(debounce); debounce = setTimeout(applyQuery, 140); }); | |
| els.query.addEventListener("keydown", (e) => { | |
| if (e.key === "Escape" && els.query.value) { els.query.value = ""; applyQuery(); } | |
| }); | |
| els.desc.addEventListener("change", applyQuery); | |
| els.cased.addEventListener("change", applyQuery); | |
| document.addEventListener("keydown", (e) => { | |
| const typing = /^(INPUT|TEXTAREA|SELECT)$/.test(document.activeElement?.tagName); | |
| if (e.key === "/" && !typing && !e.metaKey && !e.ctrlKey) { e.preventDefault(); els.query.focus(); els.query.select(); } | |
| }); | |
| els.rows.addEventListener("click", (e) => { | |
| const row = e.target.closest("tr[data-id]"); | |
| if (!row || !model) return; | |
| const node = model.nodes[+row.dataset.id]; | |
| if (e.target.closest(".locate")) { showOnMap(node); return; } | |
| const onToggle = e.target.closest(".tw"); | |
| const onName = e.target.closest("td.c-name"); | |
| if (!onToggle && !(onName && window.getSelection().isCollapsed)) return; | |
| if (!node.children.length) return; | |
| const open = row.dataset.open !== "1"; | |
| if (filter) toggles.set(node.id, open); | |
| else if (open) expanded.add(node.id); | |
| else expanded.delete(node.id); | |
| render(); | |
| document.querySelector(`tr[data-id="${node.id}"] .tw`)?.focus({ preventScroll: true }); | |
| }); | |
| els.expandAll.addEventListener("click", () => { | |
| if (!model) return; | |
| for (const node of model.nodes) { | |
| if (!node.children.length) continue; | |
| if (filter) toggles.set(node.id, true); | |
| else expanded.add(node.id); | |
| } | |
| render(); | |
| }); | |
| els.collapseAll.addEventListener("click", () => { | |
| if (!model) return; | |
| if (filter) { for (const node of model.nodes) if (node.children.length) toggles.set(node.id, false); } | |
| else expanded.clear(); | |
| render(); | |
| }); | |
| const hasFiles = (e) => Array.from(e.dataTransfer?.types || []).includes("Files"); | |
| let dragDepth = 0; | |
| window.addEventListener("dragenter", (e) => { | |
| if (!hasFiles(e)) return; | |
| e.preventDefault(); | |
| dragDepth++; | |
| els.drop.hidden = false; | |
| }); | |
| window.addEventListener("dragover", (e) => { | |
| if (!hasFiles(e)) return; | |
| e.preventDefault(); | |
| e.dataTransfer.dropEffect = "copy"; | |
| }); | |
| window.addEventListener("dragleave", (e) => { | |
| if (!hasFiles(e)) return; | |
| dragDepth = Math.max(0, dragDepth - 1); | |
| if (!dragDepth) els.drop.hidden = true; | |
| }); | |
| window.addEventListener("drop", (e) => { | |
| if (!hasFiles(e)) return; | |
| e.preventDefault(); | |
| dragDepth = 0; | |
| els.drop.hidden = true; | |
| const file = e.dataTransfer.files[0]; | |
| if (file) loadFile(file); | |
| }); | |
| /* ---------- Start with the file in the URL or the example ---------- */ | |
| readColors(); | |
| renderMenu(); | |
| let savedView = "table"; | |
| try { savedView = localStorage.getItem(VIEW_KEY) || "table"; } catch { /* storage unavailable */ } | |
| const initial = fileFromHash(); | |
| openFile(initial).then((ok) => { | |
| if (!ok && initial !== EXAMPLE) return openFile(EXAMPLE); | |
| return ok; | |
| }).then(() => switchView(savedView)); | |
| discoverFiles(); | |
| })(); | |
| </script> |
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| <!doctype html> | |
| <html lang="en"> | |
| <meta charset="utf-8"> | |
| <meta name="viewport" content="width=device-width, initial-scale=1"> | |
| <title>Peripheral Variant Explorer</title> | |
| <meta name="description" content="How many different silicon implementations of each STM32 peripheral exist: the register maps of every peripheral instance of every device merged into a common core and its optional features."> | |
| <link rel="preconnect" href="https://fonts.googleapis.com"> | |
| <link rel="preconnect" href="https://fonts.gstatic.com" crossorigin> | |
| <link rel="stylesheet" href="https://fonts.googleapis.com/css2?family=IBM+Plex+Mono:wght@400;500;600&family=IBM+Plex+Sans:wght@400;500;600&display=swap"> | |
| <style> | |
| :root { | |
| --ground: #F3F5F4; | |
| --surface: #FFFFFF; | |
| --band: #F8FAF9; | |
| --ink: #16201C; | |
| --muted: #5B6863; | |
| --faint: #85918C; | |
| --rule: #DDE3E0; | |
| --rule-strong: #C3CCC8; | |
| --accent: #1C6B56; | |
| --accent-ink: #FFFFFF; | |
| --accent-soft: #E2EFEA; | |
| --hover: #EEF4F1; | |
| --mark: #FBE3A0; | |
| --error: #B42318; | |
| --hatch: #CDD6D2; | |
| --core-bg: #E7ECEA; | |
| --core-line: #8A9993; | |
| --feat-s: 55%; | |
| --feat-line-l: 38%; | |
| --feat-bg-l: 88%; | |
| --feat-ink-l: 24%; | |
| --font-sans: "IBM Plex Sans", system-ui, -apple-system, "Segoe UI", Roboto, sans-serif; | |
| --font-mono: "IBM Plex Mono", ui-monospace, "SF Mono", Menlo, Consolas, monospace; | |
| color-scheme: light; | |
| } | |
| @media (prefers-color-scheme: dark) { | |
| :root:not([data-theme="light"]) { | |
| --ground: #0E1311; | |
| --surface: #141A18; | |
| --band: #111715; | |
| --ink: #E2E8E5; | |
| --muted: #9AA8A2; | |
| --faint: #6E7B76; | |
| --rule: #232D29; | |
| --rule-strong: #34403B; | |
| --accent: #5FC0A0; | |
| --accent-ink: #0B1512; | |
| --accent-soft: #16302A; | |
| --hover: #19231F; | |
| --mark: #6A5616; | |
| --error: #F4A39B; | |
| --hatch: #2A3531; | |
| --core-bg: #1B2320; | |
| --core-line: #4A5853; | |
| --feat-s: 48%; | |
| --feat-line-l: 58%; | |
| --feat-bg-l: 22%; | |
| --feat-ink-l: 78%; | |
| color-scheme: dark; | |
| } | |
| } | |
| :root[data-theme="dark"] { | |
| --ground: #0E1311; | |
| --surface: #141A18; | |
| --band: #111715; | |
| --ink: #E2E8E5; | |
| --muted: #9AA8A2; | |
| --faint: #6E7B76; | |
| --rule: #232D29; | |
| --rule-strong: #34403B; | |
| --accent: #5FC0A0; | |
| --accent-ink: #0B1512; | |
| --accent-soft: #16302A; | |
| --hover: #19231F; | |
| --mark: #6A5616; | |
| --error: #F4A39B; | |
| --hatch: #2A3531; | |
| --core-bg: #1B2320; | |
| --core-line: #4A5853; | |
| --feat-s: 48%; | |
| --feat-line-l: 58%; | |
| --feat-bg-l: 22%; | |
| --feat-ink-l: 78%; | |
| color-scheme: dark; | |
| } | |
| * { box-sizing: border-box; } | |
| [hidden] { display: none !important; } | |
| html, body { height: 100%; } | |
| body { | |
| margin: 0; background: var(--ground); color: var(--ink); | |
| font: 14px/1.45 var(--font-sans); | |
| display: flex; flex-direction: column; gap: 10px; | |
| padding-inline: clamp(16px, 3vw, 32px); padding-block: 12px 14px; | |
| height: 100dvh; | |
| } | |
| /* Top bar */ | |
| .top { display: flex; flex-wrap: wrap; align-items: center; justify-content: space-between; gap: 8px 24px; } | |
| .visually-hidden { | |
| position: absolute; width: 1px; height: 1px; overflow: hidden; | |
| clip: rect(0 0 0 0); white-space: nowrap; | |
| } | |
| .links { display: flex; gap: 14px; font-size: 12px; color: var(--muted); } | |
| .totals { display: flex; gap: 18px; font-variant-numeric: tabular-nums; } | |
| .total { display: grid; gap: 1px; text-align: right; } | |
| .total b { font: 600 17px/1.1 var(--font-mono); } | |
| .total span { color: var(--faint); font-size: 11px; text-transform: uppercase; letter-spacing: 0.06em; } | |
| /* Shell */ | |
| .shell { flex: 1; min-height: 0; display: grid; grid-template-columns: minmax(200px, 250px) 1fr; gap: 12px; } | |
| .panel { | |
| background: var(--surface); border: 1px solid var(--rule); border-radius: 10px; | |
| min-height: 0; display: flex; flex-direction: column; overflow: hidden; | |
| } | |
| /* Sidebar */ | |
| .side-head { padding: 10px; border-bottom: 1px solid var(--rule); display: grid; gap: 8px; } | |
| .modes { display: grid; grid-template-columns: 1fr 1fr 1fr; gap: 4px; } | |
| .modes button { | |
| padding: 5px 4px; border: 1px solid var(--rule-strong); border-radius: 7px; cursor: pointer; | |
| background: var(--band); color: var(--muted); font: 600 11px var(--font-sans); display: grid; gap: 1px; | |
| } | |
| .modes button span { font: 400 10px var(--font-mono); color: var(--faint); } | |
| .modes button:hover { background: var(--hover); } | |
| .modes button[aria-pressed="true"] { border-color: var(--accent); background: var(--accent-soft); color: var(--accent); } | |
| .modes button[aria-pressed="true"] span { color: inherit; } | |
| input[type="search"], input[type="text"] { | |
| width: 100%; padding: 7px 9px; border: 1px solid var(--rule-strong); border-radius: 7px; | |
| background: var(--band); color: var(--ink); font: 13px var(--font-mono); | |
| } | |
| input:focus-visible { outline: 2px solid var(--accent); outline-offset: 1px; } | |
| input.bad { border-color: var(--error); } | |
| .side-list { overflow: auto; padding: 6px; } | |
| .group-row { | |
| display: grid; grid-template-columns: 1fr auto auto; gap: 8px; align-items: baseline; | |
| width: 100%; text-align: left; padding: 5px 8px; border: 0; border-radius: 6px; | |
| background: none; color: inherit; font: 13px var(--font-sans); cursor: pointer; | |
| } | |
| .group-row:hover { background: var(--hover); } | |
| .group-row[aria-current="true"] { background: var(--accent-soft); color: var(--accent); font-weight: 600; } | |
| .group-row .name { font-family: var(--font-mono); overflow: hidden; text-overflow: ellipsis; white-space: nowrap; } | |
| .group-row .count { font: 600 12px var(--font-mono); font-variant-numeric: tabular-nums; } | |
| .group-row .inst { color: var(--faint); font: 11px var(--font-mono); font-variant-numeric: tabular-nums; } | |
| .empty { padding: 14px; color: var(--faint); font-size: 13px; } | |
| /* Main */ | |
| .main { overflow: hidden; } | |
| .main-head { padding: 12px 16px; border-bottom: 1px solid var(--rule); background: var(--band); position: sticky; top: 0; z-index: 3; } | |
| .main-head h2 { margin: 0; font: 600 17px var(--font-mono); } | |
| .main-head p { margin: 3px 0 0; color: var(--muted); font-size: 13px; } | |
| .variants { display: flex; flex-wrap: wrap; gap: 6px; padding: 10px 16px 0; min-width: 0; } | |
| .variant-tab { | |
| display: grid; gap: 1px; text-align: left; padding: 7px 11px; cursor: pointer; | |
| border: 1px solid var(--rule-strong); border-radius: 8px; background: var(--surface); color: inherit; | |
| font: 13px var(--font-sans); | |
| } | |
| .variant-tab:hover { background: var(--hover); } | |
| .variant-tab[aria-current="true"] { border-color: var(--accent); background: var(--accent-soft); color: var(--accent); } | |
| .variant-tab b { font: 600 13px var(--font-mono); } | |
| .variant-tab span { color: var(--muted); font-size: 11px; font-variant-numeric: tabular-nums; } | |
| .variant-tab[aria-current="true"] span { color: inherit; } | |
| .variant-tab.match { box-shadow: inset 0 0 0 2px var(--mark); } | |
| .body { | |
| padding: 12px 16px 16px; flex: 1; min-height: 0; min-width: 0; | |
| display: grid; grid-template-rows: auto minmax(0, 1fr); gap: 10px; | |
| } | |
| .meta { display: grid; gap: 10px; align-content: start; overflow: auto; max-height: min(38vh, 380px); min-width: 0; } | |
| .cards { display: flex; flex-wrap: wrap; gap: 10px; } | |
| .card { border: 1px solid var(--rule); border-radius: 9px; padding: 9px 12px; min-width: 120px; } | |
| .card b { display: block; font: 600 17px var(--font-mono); font-variant-numeric: tabular-nums; } | |
| .card span { color: var(--faint); font-size: 11px; text-transform: uppercase; letter-spacing: 0.05em; } | |
| details { border: 1px solid var(--rule); border-radius: 9px; background: var(--band); } | |
| details > summary { | |
| cursor: pointer; padding: 8px 12px; font-weight: 600; font-size: 13px; | |
| display: flex; gap: 8px; align-items: baseline; | |
| } | |
| details > summary::marker { color: var(--faint); } | |
| details > summary em { font-style: normal; color: var(--faint); font-weight: 400; font-size: 12px; } | |
| details > div { padding: 0 12px 12px; max-height: 230px; overflow: auto; } | |
| .chips { display: flex; flex-wrap: wrap; gap: 4px; } | |
| .chip { | |
| font: 11px var(--font-mono); padding: 2px 6px; border-radius: 5px; | |
| background: var(--surface); border: 1px solid var(--rule); color: var(--muted); | |
| } | |
| .chip.on { background: var(--mark); color: var(--ink); border-color: transparent; } | |
| .lines { margin: 0; font: 12px/1.6 var(--font-mono); color: var(--muted); display: grid; gap: 1px; } | |
| .lines li { list-style: none; } | |
| .lines b { color: var(--ink); font-weight: 600; } | |
| /* Feature legend */ | |
| .legend { display: flex; flex-wrap: wrap; gap: 6px; } | |
| .feat { | |
| display: flex; align-items: center; gap: 7px; padding: 5px 9px; cursor: pointer; | |
| border: 1px solid var(--rule-strong); border-radius: 7px; background: var(--surface); | |
| color: inherit; font: 12px var(--font-sans); text-align: left; | |
| } | |
| .feat:hover { background: var(--hover); } | |
| .feat[aria-pressed="true"] { border-color: hsl(var(--h) var(--feat-s) var(--feat-line-l)); background: hsl(var(--h) var(--feat-s) var(--feat-bg-l)); } | |
| .swatch { width: 11px; height: 11px; border-radius: 3px; flex: none; | |
| background: hsl(var(--h) var(--feat-s) var(--feat-bg-l)); border: 1px solid hsl(var(--h) var(--feat-s) var(--feat-line-l)); } | |
| .feat .num { font: 600 12px var(--font-mono); flex: none; } | |
| .feat .label { max-width: 34ch; overflow: hidden; text-overflow: ellipsis; white-space: nowrap; } | |
| .feat .meta { color: var(--faint); font: 11px var(--font-mono); font-variant-numeric: tabular-nums; } | |
| .feat.core .swatch { background: var(--core-bg); border-color: var(--core-line); } | |
| /* Register map */ | |
| .stage { display: grid; grid-template-columns: minmax(0, 1fr) minmax(240px, 300px); gap: 10px; min-height: 0; } | |
| .canvas-wrap { | |
| position: relative; border: 1px solid var(--rule); border-radius: 9px; overflow: hidden; min-width: 0; | |
| background: var(--surface); height: 100%; min-height: 320px; | |
| } | |
| canvas { display: block; width: 100%; height: 100%; min-width: 0; touch-action: none; cursor: default; } | |
| canvas.dragging { cursor: grabbing; } | |
| canvas:focus-visible { outline: 2px solid var(--accent); outline-offset: -2px; } | |
| .tip { | |
| position: absolute; pointer-events: none; z-index: 5; max-width: 320px; | |
| background: var(--surface); border: 1px solid var(--rule-strong); border-radius: 7px; | |
| padding: 5px 8px; display: grid; gap: 1px; box-shadow: 0 6px 20px rgb(0 0 0 / 0.18); | |
| } | |
| .tip strong { font: 600 12px var(--font-mono); } | |
| .tip span { color: var(--muted); font-size: 11px; } | |
| .zoom { position: absolute; right: 8px; bottom: 8px; display: flex; gap: 4px; z-index: 4; } | |
| .zoom button { | |
| width: 28px; height: 28px; border: 1px solid var(--rule-strong); border-radius: 6px; | |
| background: var(--surface); color: inherit; font: 15px var(--font-mono); cursor: pointer; line-height: 1; | |
| } | |
| .zoom button:hover { background: var(--hover); } | |
| .hint { | |
| position: absolute; left: 8px; bottom: 8px; z-index: 4; color: var(--faint); | |
| font-size: 11px; background: var(--surface); border-radius: 6px; padding: 2px 7px; | |
| } | |
| /* Inspector */ | |
| .inspect { | |
| border: 1px solid var(--rule); border-radius: 9px; background: var(--band); | |
| padding: 10px 12px; display: grid; gap: 8px; align-content: start; | |
| max-height: 100%; overflow: auto; | |
| } | |
| .inspect h3 { margin: 0; font: 600 14px var(--font-mono); overflow-wrap: anywhere; } | |
| .inspect .sub { color: var(--muted); font: 12px var(--font-mono); } | |
| .inspect p { margin: 0; font-size: 12px; color: var(--muted); } | |
| .inspect .badge { | |
| justify-self: start; font: 600 11px var(--font-mono); padding: 2px 7px; border-radius: 5px; | |
| background: var(--core-bg); border: 1px solid var(--core-line); | |
| } | |
| .inspect .badge.opt { | |
| background: hsl(var(--h) var(--feat-s) var(--feat-bg-l)); | |
| border-color: hsl(var(--h) var(--feat-s) var(--feat-line-l)); | |
| color: hsl(var(--h) var(--feat-s) var(--feat-ink-l)); | |
| } | |
| .inspect dl { margin: 0; display: grid; grid-template-columns: auto 1fr; gap: 2px 10px; font-size: 12px; } | |
| .inspect dt { color: var(--faint); } | |
| .inspect dd { margin: 0; font-family: var(--font-mono); overflow-wrap: anywhere; } | |
| .inspect hr { border: 0; border-top: 1px solid var(--rule); margin: 2px 0; width: 100%; } | |
| @media (max-width: 1000px) { | |
| .main { overflow: auto; } | |
| .body { grid-template-rows: none; } | |
| .meta { max-height: none; overflow: visible; } | |
| .stage { grid-template-columns: 1fr; } | |
| .canvas-wrap { height: 60vh; } | |
| .inspect { max-height: none; } | |
| } | |
| @media (max-width: 720px) { | |
| .shell { grid-template-columns: 1fr; grid-template-rows: minmax(120px, 28vh) 1fr; } | |
| .reg { grid-template-columns: 62px 1fr; } | |
| .reg .bits, .reg .scale { grid-column: 1 / -1; } | |
| } | |
| </style> | |
| <header class="top"> | |
| <h1 class="visually-hidden">Peripheral Variant Explorer</h1> | |
| <div class="links"> | |
| <a href="../svd/">SVD Register Explorer</a> | |
| <a href="https://github.com/modm-io/modm-data">modm-data</a> | |
| </div> | |
| <div class="totals"> | |
| <div class="total"><b id="t-instances">–</b><span>instances</span></div> | |
| <div class="total"><b id="t-shapes">–</b><span>register maps</span></div> | |
| <div class="total"><b id="t-variants">–</b><span>variants</span></div> | |
| </div> | |
| </header> | |
| <div class="shell"> | |
| <nav class="panel" aria-label="Peripheral groups"> | |
| <div class="side-head"> | |
| <div class="modes" id="modes" role="group" aria-label="Compatibility mode"> | |
| <button type="button" data-mode="binary" aria-pressed="true">binary<span>by address</span></button> | |
| <button type="button" data-mode="source" aria-pressed="false">source<span>by name</span></button> | |
| <button type="button" data-mode="similar" aria-pressed="false">similar<span>docs aside</span></button> | |
| </div> | |
| <input id="filter" type="search" placeholder="filter groups, e.g. ^(TIM|GPIO)" aria-label="Filter peripheral groups by regular expression" autocomplete="off" spellcheck="false"> | |
| <input id="device" type="text" placeholder="highlight a device, e.g. F407" aria-label="Highlight the variants used by a device" autocomplete="off" spellcheck="false"> | |
| </div> | |
| <div class="side-list" id="groups"></div> | |
| </nav> | |
| <main class="panel main" id="main"> | |
| <div class="main-head"> | |
| <h2 id="g-name">Loading…</h2> | |
| <p id="g-sub"></p> | |
| </div> | |
| <div class="variants" id="tabs"></div> | |
| <div class="body" id="detail"></div> | |
| </main> | |
| </div> | |
| <script> | |
| "use strict"; | |
| const state = {all: null, index: null, mode: "binary", group: null, data: null, | |
| variant: 0, feature: null, device: "", filter: "", map: ""}; | |
| const $ = (id) => document.getElementById(id); | |
| const el = (tag, cls, text) => { | |
| const node = document.createElement(tag); | |
| if (cls) node.className = cls; | |
| if (text !== undefined) node.textContent = text; | |
| return node; | |
| }; | |
| const num = (value) => value.toLocaleString("en-US"); | |
| const clamp = (value, low, high) => Math.min(Math.max(value, low), high); | |
| // Golden angle keeps neighbouring features far apart in hue | |
| const hue = (index) => Math.round((index * 137.508 + 8) % 360); | |
| const hex = (value) => `0x${value.toString(16).padStart(3, "0")}`; | |
| const range = (position, width) => (width === 1 ? `${position}` : `${position + width - 1}:${position}`); | |
| function regex(pattern) { | |
| if (!pattern) return null; | |
| try { return new RegExp(pattern, "i"); } catch { return undefined; } | |
| } | |
| /* ---------------------------------------------------------------- groups */ | |
| function renderGroups() { | |
| const list = $("groups"); | |
| list.textContent = ""; | |
| const pattern = regex(state.filter); | |
| $("filter").classList.toggle("bad", pattern === undefined); | |
| const groups = state.index.groups.filter((g) => !pattern || pattern.test(g.name)); | |
| if (!groups.length) { | |
| list.append(el("p", "empty", "No peripheral group matches.")); | |
| return; | |
| } | |
| for (const group of groups) { | |
| const row = el("button", "group-row"); | |
| row.type = "button"; | |
| row.setAttribute("aria-current", String(group.name === state.group)); | |
| row.append(el("span", "name", group.name)); | |
| row.append(el("span", "inst", num(group.instances))); | |
| const count = el("span", "count", String(group.variants.length)); | |
| count.title = `${group.variants.length} variants of ${group.shapes} distinct register maps`; | |
| row.append(count); | |
| row.addEventListener("click", () => selectGroup(group.name)); | |
| list.append(row); | |
| } | |
| } | |
| /* --------------------------------------------------------------- loading */ | |
| async function selectGroup(name, variant = 0) { | |
| if (name !== state.group) view.meta = 0; | |
| state.group = name; | |
| state.variant = variant; | |
| state.feature = null; | |
| state.map = ""; | |
| renderGroups(); | |
| $("g-name").textContent = name; | |
| $("g-sub").textContent = "Loading…"; | |
| $("tabs").textContent = ""; | |
| $("detail").textContent = ""; | |
| try { | |
| const response = await fetch(`${state.mode}/${encodeURIComponent(name)}.json`); | |
| if (!response.ok) throw new Error(`${response.status} ${response.statusText}`); | |
| state.data = await response.json(); | |
| } catch (error) { | |
| $("g-sub").textContent = `Could not load ${state.mode}/${name}.json: ${error.message}`; | |
| return; | |
| } | |
| history.replaceState(null, "", `#${state.mode}/${name}/${variant}`); | |
| renderGroup(); | |
| } | |
| function renderGroup() { | |
| const data = state.data; | |
| const maps = data.variants.reduce((sum, v) => sum + v.members.length, 0); | |
| $("g-name").textContent = data.name; | |
| $("g-sub").textContent = | |
| `${num(data.instances)} instances on ${num(data.devices.length)} devices, ` + | |
| `${num(maps)} distinct register maps, ${data.variants.length} ` + | |
| `${data.variants.length === 1 ? "variant" : "variants"}` + | |
| (data.ignored && data.ignored.length ? ` · not compared: ${data.ignored.join(", ")}` : ""); | |
| const device = regex(state.device); | |
| const tabs = $("tabs"); | |
| tabs.textContent = ""; | |
| data.variants.forEach((variant, index) => { | |
| const tab = el("button", "variant-tab"); | |
| tab.type = "button"; | |
| tab.setAttribute("aria-current", String(index === state.variant)); | |
| if (device && variant.devices.some((d) => device.test(data.devices[d]))) tab.classList.add("match"); | |
| tab.append(el("b", null, `variant ${index}`)); | |
| tab.append(el("span", null, | |
| `${num(variant.instances)} inst · ${variant.devices.length} dev · ${variant.members.length} maps`)); | |
| tab.addEventListener("click", () => { | |
| state.variant = index; | |
| state.feature = null; | |
| history.replaceState(null, "", `#${state.mode}/${data.name}/${index}`); | |
| renderGroup(); | |
| }); | |
| tabs.append(tab); | |
| }); | |
| renderVariant(); | |
| } | |
| /* -------------------------------------------------------------- variants */ | |
| function renderVariant() { | |
| const variant = state.data.variants[state.variant]; | |
| const body = $("detail"); | |
| const previous = body.querySelector(".meta"); | |
| if (previous) view.meta = previous.scrollTop; | |
| body.textContent = ""; | |
| if (!variant) return; | |
| const meta = el("div", "meta"); | |
| body.append(meta); | |
| const core = variant.registers.reduce( | |
| (sum, r) => sum + (r.feature < 0 ? 1 : 0) + r.fields.filter((f) => f.feature < 0).length, 0); | |
| const total = variant.registers.reduce((sum, r) => sum + 1 + r.fields.length, 0); | |
| meta.append(cards([ | |
| [num(variant.instances), "instances"], | |
| [num(variant.devices.length), "devices"], | |
| [num(variant.members.length), "register maps"], | |
| [num(variant.registers.length), "registers"], | |
| [`${num(core)}/${num(total)}`, "core elements"], | |
| [num(variant.features.length), "features"], | |
| ])); | |
| meta.append(legend(variant)); | |
| if (Object.keys(variant.conflicts).length) meta.append(conflicts(variant)); | |
| if (variant.renames.length) meta.append(renames(variant)); | |
| if (variant.relocated?.length) meta.append(relocated(variant)); | |
| meta.append(devices(variant, state.data)); | |
| meta.append(mapFilter()); | |
| body.append(stage(variant)); | |
| } | |
| function cards(entries) { | |
| const wrap = el("div", "cards"); | |
| for (const [value, label] of entries) { | |
| const card = el("div", "card"); | |
| card.append(el("b", null, value)); | |
| card.append(el("span", null, label)); | |
| wrap.append(card); | |
| } | |
| return wrap; | |
| } | |
| function legend(variant) { | |
| const wrap = el("div", "legend"); | |
| const all = el("button", "feat core"); | |
| all.type = "button"; | |
| all.setAttribute("aria-pressed", String(state.feature === null)); | |
| all.append(el("span", "swatch")); | |
| all.append(el("span", "num", "core")); | |
| all.append(el("span", "meta", "in every instance")); | |
| all.addEventListener("click", () => { state.feature = null; select(null); redraw(); renderLegend(); }); | |
| wrap.append(all); | |
| variant.features.forEach((feature, index) => { | |
| const button = el("button", "feat"); | |
| button.type = "button"; | |
| button.style.setProperty("--h", hue(index)); | |
| button.setAttribute("aria-pressed", String(state.feature === index)); | |
| button.append(el("span", "swatch")); | |
| button.append(el("span", "num", `${index}`)); | |
| if (feature.name) button.append(el("span", "label", feature.name)); | |
| button.append(el("span", "meta", | |
| `${feature.elements} el · ${feature.members.length}/${variant.members.length} maps · ${feature.devices.length} dev`)); | |
| button.title = | |
| `${feature.name ? feature.name + "\n" : ""}` + | |
| `${feature.elements} elements in ${feature.registers} registers, ` + | |
| `implemented by ${feature.instances} instances on ${feature.devices.length} devices`; | |
| button.addEventListener("click", () => { | |
| state.feature = state.feature === index ? null : index; | |
| select(state.feature === null ? null : {kind: "feature", index}); | |
| redraw(); | |
| renderLegend(); | |
| }); | |
| wrap.append(button); | |
| }); | |
| wrap.id = "legend"; | |
| return wrap; | |
| } | |
| function renderLegend() { | |
| $("legend").replaceWith(legend(state.data.variants[state.variant])); | |
| } | |
| function details(summaryText, count, build, open = false) { | |
| const box = el("details"); | |
| box.open = open; | |
| const summary = el("summary"); | |
| summary.append(document.createTextNode(summaryText)); | |
| summary.append(el("em", null, count)); | |
| box.append(summary); | |
| const inner = el("div"); | |
| build(inner); | |
| box.append(inner); | |
| return box; | |
| } | |
| function conflicts(variant) { | |
| const entries = Object.entries(variant.conflicts); | |
| const total = entries.reduce((sum, [, lines]) => sum + lines.length, 0); | |
| return details("Why this is a separate variant", `${total} conflicts`, (inner) => { | |
| inner.append(el("p", "note", | |
| "These names sit at a different address in the other variant, so no single driver can address both.")); | |
| for (const [other, lines] of entries) { | |
| const list = el("ul", "lines"); | |
| const head = el("li"); | |
| head.append(el("b", null, `vs variant ${other}`)); | |
| list.append(head); | |
| for (const line of lines.slice(0, 40)) list.append(el("li", null, line)); | |
| if (lines.length > 40) list.append(el("li", null, `… and ${lines.length - 40} more`)); | |
| inner.append(list); | |
| } | |
| }); | |
| } | |
| function renames(variant) { | |
| return details("Renamed, but the same silicon", `${variant.renames.length} aliases`, (inner) => { | |
| inner.append(el("p", "note", | |
| "Same address, different name: these were merged and every name is kept as an alias.")); | |
| const list = el("ul", "lines"); | |
| for (const line of variant.renames.slice(0, 200)) list.append(el("li", null, line)); | |
| if (variant.renames.length > 200) list.append(el("li", null, `… and ${variant.renames.length - 200} more`)); | |
| inner.append(list); | |
| }); | |
| } | |
| function relocated(variant) { | |
| return details("Moved, but the same bit field", `${variant.relocated.length} relocation${variant.relocated.length === 1 ? "" : "s"}`, (inner) => { | |
| inner.append(el("p", "note", | |
| "Same name inside the same register, but at another bit position. A CMSIS header hides this " | |
| + "behind its _Pos and _Msk macros, so these were merged and the field is drawn at every position.")); | |
| const list = el("ul", "lines"); | |
| for (const line of variant.relocated.slice(0, 200)) list.append(el("li", null, line)); | |
| if (variant.relocated.length > 200) list.append(el("li", null, `… and ${variant.relocated.length - 200} more`)); | |
| inner.append(list); | |
| }); | |
| } | |
| function deviceChips(names) { | |
| const pattern = regex(state.device); | |
| const chips = el("div", "chips"); | |
| for (const name of names) { | |
| const chip = el("span", "chip", name); | |
| if (pattern && pattern.test(name)) chip.classList.add("on"); | |
| chips.append(chip); | |
| } | |
| return chips; | |
| } | |
| function devices(variant, data) { | |
| return details("Devices and instances", `${variant.devices.length} devices`, (inner) => { | |
| inner.append(deviceChips(variant.names)); | |
| inner.append(el("p", "note", "Implemented by these devices:")); | |
| inner.append(deviceChips(variant.devices.map((index) => data.devices[index]))); | |
| }, true); | |
| } | |
| function mapFilter() { | |
| const wrap = el("div"); | |
| const input = el("input"); | |
| input.type = "search"; | |
| input.value = state.map; | |
| input.placeholder = "filter registers and bit fields, e.g. ^CCMR"; | |
| input.setAttribute("aria-label", "Filter the register map by regular expression"); | |
| input.autocomplete = "off"; | |
| input.spellcheck = false; | |
| input.addEventListener("input", () => { | |
| state.map = input.value; | |
| input.classList.toggle("bad", regex(state.map) === undefined); | |
| redraw(); | |
| }); | |
| wrap.append(input); | |
| return wrap; | |
| } | |
| /* ---------------------------------------------------------- register map */ | |
| const GUTTER = 150; // fixed left column with the register names | |
| const ROW_RATIO = 2; // a bit is this many times taller than it is wide | |
| const K_MIN = 1, K_MAX = 90; // pixels per bit | |
| const FONT_MONO = '"IBM Plex Mono", ui-monospace, Menlo, Consolas, monospace'; | |
| const FONT_SANS = '"IBM Plex Sans", system-ui, -apple-system, sans-serif'; | |
| const map = { | |
| variant: null, layout: null, k: 8, ox: GUTTER, oy: 0, width: 0, height: 0, dpr: 1, | |
| hover: null, selected: null, colors: null, hatch: null, frame: 0, canvas: null, ctx: null, | |
| }; | |
| const widths = new Map(); | |
| const view = {group: null, k: null, ox: 0, oy: 0, meta: 0}; | |
| function stage(variant) { | |
| const wrap = el("div", "stage"); | |
| const holder = el("div", "canvas-wrap"); | |
| const canvas = el("canvas"); | |
| canvas.tabIndex = 0; | |
| canvas.setAttribute("aria-label", "Zoomable register map, drag to pan and ctrl+scroll to zoom"); | |
| holder.append(canvas); | |
| const tip = el("div", "tip"); | |
| tip.id = "tip"; | |
| tip.hidden = true; | |
| holder.append(tip); | |
| const zoom = el("div", "zoom"); | |
| for (const [label, factor] of [["−", 1 / 1.6], ["+", 1.6]]) { | |
| const button = el("button", null, label); | |
| button.type = "button"; | |
| button.title = label === "+" ? "Zoom in" : "Zoom out"; | |
| button.addEventListener("click", () => zoomAt(GUTTER + (map.width - GUTTER) / 2, map.height / 2, factor)); | |
| zoom.append(button); | |
| } | |
| holder.append(zoom); | |
| holder.append(el("span", "hint", "drag to pan · ctrl+scroll to zoom · click for details")); | |
| wrap.append(holder); | |
| const inspect = el("div", "inspect"); | |
| inspect.id = "inspect"; | |
| wrap.append(inspect); | |
| map.variant = variant; | |
| map.canvas = canvas; | |
| map.ctx = canvas.getContext("2d"); | |
| map.layout = buildLayout(variant); | |
| map.hover = null; | |
| map.selected = null; | |
| attach(canvas); | |
| requestAnimationFrame(() => { | |
| resize(); | |
| // Keep the zoom everywhere, so that the shapes of peripherals and variants can be compared. | |
| // Another peripheral starts at its first register, a variant of the same one where it was. | |
| if (view.k) { | |
| map.k = view.k; | |
| map.ox = view.ox; | |
| map.oy = view.group === state.group ? view.oy : 10; | |
| clampView(); | |
| draw(); | |
| } else { | |
| fitView(); | |
| } | |
| const meta = $("detail").querySelector(".meta"); | |
| if (meta) meta.scrollTop = view.meta; | |
| renderInspector(); | |
| }); | |
| return wrap; | |
| } | |
| function buildLayout(variant) { | |
| const rows = []; | |
| let y = 0; | |
| for (const register of variant.registers) { | |
| const bits = register.width * 8; | |
| const lanes = []; | |
| const items = []; | |
| // Alternates of the same register overlap, so pack them into extra lanes | |
| for (const field of [...register.fields].sort((a, b) => b.position - a.position || b.width - a.width)) { | |
| const start = bits - (field.position + field.width); | |
| let lane = lanes.findIndex((used) => used.every(([s, w]) => start >= s + w || start + field.width <= s)); | |
| if (lane < 0) lane = lanes.push([]) - 1; | |
| lanes[lane].push([start, field.width]); | |
| items.push({field, lane, start}); | |
| } | |
| const height = Math.max(1, lanes.length); | |
| rows.push({register, bits, y, height, items}); | |
| y += height; | |
| } | |
| return {rows, rowCount: Math.max(y, 1)}; | |
| } | |
| function readColors() { | |
| const style = getComputedStyle(document.documentElement); | |
| const value = (name) => style.getPropertyValue(name).trim(); | |
| map.colors = { | |
| surface: value("--surface"), band: value("--band"), ink: value("--ink"), | |
| muted: value("--muted"), faint: value("--faint"), rule: value("--rule"), | |
| ruleStrong: value("--rule-strong"), accent: value("--accent"), mark: value("--mark"), | |
| coreBg: value("--core-bg"), coreLine: value("--core-line"), | |
| s: value("--feat-s"), lineL: value("--feat-line-l"), bgL: value("--feat-bg-l"), inkL: value("--feat-ink-l"), | |
| }; | |
| const tile = document.createElement("canvas"); | |
| tile.width = tile.height = 6; | |
| const ctx = tile.getContext("2d"); | |
| ctx.strokeStyle = value("--hatch"); | |
| ctx.lineWidth = 1; | |
| ctx.beginPath(); | |
| ctx.moveTo(-1, 5); ctx.lineTo(5, -1); | |
| ctx.moveTo(1, 7); ctx.lineTo(7, 1); | |
| ctx.stroke(); | |
| map.hatch = map.ctx.createPattern(tile, "repeat"); | |
| } | |
| const featureFill = (index) => `hsl(${hue(index)} ${map.colors.s} ${map.colors.bgL})`; | |
| const featureLine = (index) => `hsl(${hue(index)} ${map.colors.s} ${map.colors.lineL})`; | |
| const featureInk = (index) => `hsl(${hue(index)} ${map.colors.s} ${map.colors.inkL})`; | |
| const rowHeight = () => map.k * ROW_RATIO; | |
| const sx = (bit) => map.ox + bit * map.k; | |
| const sy = (row) => map.oy + row * rowHeight(); | |
| function resize() { | |
| const canvas = map.canvas; | |
| if (!canvas) return; | |
| const rect = canvas.getBoundingClientRect(); | |
| map.dpr = window.devicePixelRatio || 1; | |
| map.width = rect.width; | |
| map.height = rect.height; | |
| canvas.width = Math.round(rect.width * map.dpr); | |
| canvas.height = Math.round(rect.height * map.dpr); | |
| readColors(); | |
| draw(); | |
| } | |
| function minZoom() { | |
| return K_MIN; | |
| } | |
| function fitView() { | |
| map.k = clamp((map.width - GUTTER - 24) / 32, K_MIN, 56); | |
| map.ox = GUTTER + 12; | |
| map.oy = 10; | |
| clampView(); | |
| draw(); | |
| } | |
| function clampView() { | |
| const width = map.width - GUTTER, height = map.height; | |
| view.group = state.group; | |
| const contentW = 32 * map.k, contentH = map.layout.rowCount * rowHeight(); | |
| map.ox = clamp(map.ox, GUTTER + Math.min(12, width - contentW), GUTTER + Math.max(12, width - contentW)); | |
| map.oy = clamp(map.oy, Math.min(10, height - contentH - 10), 10); | |
| view.k = map.k; | |
| view.ox = map.ox; | |
| view.oy = map.oy; | |
| } | |
| function zoomAt(px, py, factor) { | |
| const k = clamp(map.k * factor, minZoom(), K_MAX), f = k / map.k; | |
| map.ox = px - (px - map.ox) * f; | |
| map.oy = py - (py - map.oy) * f; | |
| map.k = k; | |
| clampView(); | |
| draw(); | |
| } | |
| function redraw() { draw(); } | |
| function draw() { | |
| if (!map.frame) map.frame = requestAnimationFrame(() => { map.frame = 0; paint(); }); | |
| } | |
| /* ------------------------------------------------------------------ text */ | |
| function textWidth(ctx, text) { | |
| const key = `${ctx.font}|${text}`; | |
| let width = widths.get(key); | |
| if (width === undefined) { width = ctx.measureText(text).width; widths.set(key, width); } | |
| return width; | |
| } | |
| function fitText(ctx, text, x, y, maxWidth) { | |
| if (textWidth(ctx, text) > maxWidth) return false; | |
| ctx.fillText(text, x, y); | |
| return true; | |
| } | |
| function fitTextRotated(ctx, text, cx, cy, maxLength) { | |
| if (textWidth(ctx, text) > maxLength) return false; | |
| ctx.save(); | |
| ctx.translate(cx, cy); | |
| ctx.rotate(-Math.PI / 2); | |
| ctx.fillText(text, 0, 0); | |
| ctx.restore(); | |
| return true; | |
| } | |
| /* --------------------------------------------------------------- drawing */ | |
| function paint() { | |
| const ctx = map.ctx, C = map.colors, W = map.width, H = map.height; | |
| if (!ctx || !C || !W) return; | |
| const L = map.layout, variant = map.variant; | |
| const pattern = regex(state.map); | |
| const rowH = rowHeight(); | |
| ctx.setTransform(map.dpr, 0, 0, map.dpr, 0, 0); | |
| ctx.fillStyle = C.surface; | |
| ctx.fillRect(0, 0, W, H); | |
| ctx.textBaseline = "middle"; | |
| const first = Math.max(0, Math.floor((-map.oy) / rowH) - 2); | |
| const last = Math.min(L.rowCount, Math.ceil((H - map.oy) / rowH) + 2); | |
| ctx.save(); | |
| ctx.beginPath(); | |
| ctx.rect(GUTTER, 0, W - GUTTER, H); | |
| ctx.clip(); | |
| for (const row of L.rows) { | |
| if (row.y + row.height < first || row.y > last) continue; | |
| drawRegister(ctx, row, pattern); | |
| } | |
| if (map.hover && map.hover !== map.selected) outline(ctx, map.hover, C.accent, 1.5); | |
| if (map.selected && map.selected.kind !== "feature") outline(ctx, map.selected, C.ink, 2); | |
| ctx.restore(); | |
| // Gutter with the register names | |
| ctx.fillStyle = C.surface; | |
| ctx.fillRect(0, 0, GUTTER, H); | |
| ctx.fillStyle = C.rule; | |
| ctx.fillRect(GUTTER - 1, 0, 1, H); | |
| // Zoomed out, the rows are thinner than a label, so only label as many as fit | |
| let lastLabel = -Infinity; | |
| const selectedRow = map.selected && map.selected.row; | |
| for (const row of L.rows) { | |
| if (row.y + row.height < first || row.y > last) continue; | |
| const top = sy(row.y), height = row.height * rowH; | |
| if (top > H || top + height < 0) continue; | |
| const y = top + Math.min(height, 20) / 2; | |
| const dimmed = pattern && !matches(pattern, row); | |
| if (y - lastLabel < 14 && row !== selectedRow) continue; | |
| lastLabel = y; | |
| ctx.font = `10.5px ${FONT_MONO}`; | |
| ctx.textAlign = "left"; | |
| ctx.fillStyle = dimmed ? C.faint : C.muted; | |
| ctx.fillText((row.register.offsets ? "~" : "") + hex(row.register.offset), 10, y); | |
| ctx.font = `600 11.5px ${FONT_SANS}`; | |
| ctx.fillStyle = dimmed ? C.faint : row.register.feature < 0 ? C.ink : featureLine(row.register.feature); | |
| let name = row.register.names[0] || "?"; | |
| const tag = accessTag(row.register); | |
| const room = GUTTER - 68 - (tag ? 18 : 0); | |
| while (name.length > 3 && textWidth(ctx, name) > room) name = name.slice(0, -2) + "…"; | |
| ctx.fillText(name, 58, y); | |
| if (tag) { | |
| ctx.font = `600 9px ${FONT_MONO}`; | |
| ctx.fillStyle = C.faint; | |
| ctx.textAlign = "right"; | |
| ctx.fillText(tag, GUTTER - 8, y); | |
| } | |
| } | |
| } | |
| const ACCESS = {"read-only": "ro", "write-only": "wo", "read-write": "rw"}; | |
| // Almost every register is declared read-write, so only the exceptions are marked | |
| function accessTag(register) { | |
| const access = register.access || []; | |
| if (!access.length || (access.length === 1 && access[0] === "read-write")) return ""; | |
| return access.map((a) => ACCESS[a] || a).join("/"); | |
| } | |
| function matches(pattern, row) { | |
| return pattern.test(row.register.names.join(" ")) || | |
| row.items.some(({field}) => field.names.some((n) => pattern.test(n))); | |
| } | |
| function drawRegister(ctx, row, pattern) { | |
| const C = map.colors, rowH = rowHeight(); | |
| const x = sx(32 - row.bits), y = sy(row.y); | |
| const w = row.bits * map.k, h = row.height * rowH; | |
| if (y > map.height || y + h < 0) return; | |
| const dimmed = pattern && !matches(pattern, row); | |
| ctx.globalAlpha = dimmed ? 0.25 : 1; | |
| // The register itself, with the bits that no field covers left hatched. Too small for the | |
| // hatching and the outline, the register is filled solid so that its extent stays visible. | |
| const outlined = h >= 4; | |
| ctx.fillStyle = outlined ? C.band : C.rule; | |
| ctx.fillRect(x, y, w, h); | |
| if (map.hatch && outlined) { ctx.fillStyle = map.hatch; ctx.fillRect(x, y, w, h); } | |
| const showText = rowH >= 13; | |
| for (const {field, lane, start} of row.items) { | |
| const fx = sx(32 - row.bits + start), fy = y + lane * rowH; | |
| const fw = field.width * map.k, fh = rowH; | |
| const hit = pattern && field.names.some((n) => pattern.test(n)); | |
| if (state.feature !== null && field.feature !== state.feature) { | |
| ctx.globalAlpha = dimmed ? 0.12 : 0.28; | |
| } | |
| ctx.fillStyle = hit ? C.mark : field.feature < 0 ? C.coreBg : featureFill(field.feature); | |
| ctx.fillRect(fx, fy, fw, fh); | |
| ctx.strokeStyle = field.feature < 0 ? C.coreLine : featureLine(field.feature); | |
| ctx.lineWidth = 1; | |
| // A field that moved inside its register is drawn at every position it takes, dashed apart | |
| if (field.relocated) ctx.setLineDash([3, 2]); | |
| if (fw >= 3 && fh >= 4) ctx.strokeRect(fx + 0.5, fy + 0.5, fw - 1, fh - 1); | |
| ctx.setLineDash([]); | |
| if (showText) { | |
| ctx.fillStyle = field.feature < 0 ? C.ink : featureInk(field.feature); | |
| const name = field.names[0] || ""; | |
| ctx.textAlign = "center"; | |
| const size = clamp(Math.min(fw, fh) * 0.62, 7.5, 12); | |
| ctx.font = `${size.toFixed(1)}px ${FONT_MONO}`; | |
| // Bit fields are taller than they are wide, so their names read vertically | |
| if (fh >= fw) { | |
| if (fw >= 8 && !fitTextRotated(ctx, name, fx + fw / 2 + size / 3, fy + fh / 2, fh - 6)) { | |
| fitText(ctx, name, fx + fw / 2, fy + fh / 2, fw - 4); | |
| } | |
| } else if (!fitText(ctx, name, fx + fw / 2, fy + fh / 2, fw - 5)) { | |
| if (fw >= 8) fitTextRotated(ctx, name, fx + fw / 2 + size / 3, fy + fh / 2, fh - 6); | |
| } | |
| } | |
| ctx.globalAlpha = dimmed ? 0.25 : 1; | |
| } | |
| if (outlined) { | |
| ctx.strokeStyle = row.register.feature < 0 ? C.ruleStrong : featureLine(row.register.feature); | |
| ctx.lineWidth = 1.5; | |
| ctx.strokeRect(x + 0.75, y + 0.75, w - 1.5, h - 1.5); | |
| } | |
| // Bit numbers below the register once there is room for them | |
| if (map.k >= 15 && rowH >= 56) { | |
| ctx.font = `9.5px ${FONT_MONO}`; | |
| ctx.fillStyle = C.faint; | |
| ctx.textAlign = "center"; | |
| ctx.globalAlpha = dimmed ? 0.25 : 0.8; | |
| for (let bit = 0; bit < row.bits; bit++) { | |
| ctx.fillText(String(bit), sx(32 - 1 - bit) + map.k / 2, y + h - 7); | |
| } | |
| } | |
| ctx.globalAlpha = 1; | |
| } | |
| function rectOf(target) { | |
| const rowH = rowHeight(); | |
| const row = target.row; | |
| if (target.kind === "register") { | |
| return [sx(32 - row.bits), sy(row.y), row.bits * map.k, row.height * rowH]; | |
| } | |
| return [sx(32 - row.bits + target.item.start), sy(row.y) + target.item.lane * rowH, | |
| target.item.field.width * map.k, rowH]; | |
| } | |
| function outline(ctx, target, color, width) { | |
| const [x, y, w, h] = rectOf(target); | |
| ctx.strokeStyle = color; | |
| ctx.lineWidth = width; | |
| ctx.strokeRect(x, y, w, h); | |
| } | |
| /* ------------------------------------------------------------ hit testing */ | |
| function hitTest(px, py) { | |
| if (px < GUTTER) return null; | |
| const L = map.layout, rowH = rowHeight(); | |
| const rowIndex = (py - map.oy) / rowH; | |
| const row = L.rows.find((r) => rowIndex >= r.y && rowIndex < r.y + r.height); | |
| if (!row) return null; | |
| const bit = (px - map.ox) / map.k; | |
| if (bit < 32 - row.bits || bit > 32) return null; | |
| const start = bit - (32 - row.bits); | |
| const lane = Math.floor(rowIndex - row.y); | |
| const item = row.items.find((i) => i.lane === lane && start >= i.start && start < i.start + i.field.width); | |
| return item ? {kind: "field", row, item} : {kind: "register", row}; | |
| } | |
| function describe(target) { | |
| if (target.kind === "register") { | |
| const r = target.row.register; | |
| const tag = accessTag(r); | |
| return `${(r.offsets || [r.offset]).map(hex).join("/")} · ${r.width * 8} bit · ${r.fields.length} fields` + | |
| (tag ? ` · ${tag}` : ""); | |
| } | |
| const f = target.item.field; | |
| const variant = map.variant; | |
| const feature = f.feature < 0 ? "core" : | |
| `feature ${f.feature}${variant.features[f.feature].name ? ": " + variant.features[f.feature].name : ""}`; | |
| return `[${range(f.position, f.width)}] · ${feature}` + (f.relocated ? " · relocated" : ""); | |
| } | |
| function label(target) { | |
| return target.kind === "register" | |
| ? target.row.register.names.join(" = ") | |
| : target.item.field.names.join(" = "); | |
| } | |
| function select(target) { | |
| map.selected = target; | |
| renderInspector(); | |
| draw(); | |
| } | |
| /* ------------------------------------------------------------- inspector */ | |
| function renderInspector() { | |
| const box = $("inspect"); | |
| if (!box) return; | |
| box.textContent = ""; | |
| const variant = map.variant, data = state.data; | |
| const target = map.selected; | |
| if (target && target.kind === "feature") { | |
| const feature = variant.features[target.index]; | |
| box.append(el("h3", null, feature.name || `Feature ${target.index}`)); | |
| box.append(el("div", "sub", `feature ${target.index}`)); | |
| const badge = el("span", "badge opt", "optional"); | |
| badge.style.setProperty("--h", hue(target.index)); | |
| box.append(badge); | |
| box.append(el("p", null, | |
| `${feature.elements} elements in ${feature.registers} registers that appear in exactly the same instances, ` + | |
| `so they are enabled and disabled together.`)); | |
| box.append(facts([ | |
| ["register maps", `${feature.members.length} of ${variant.members.length}`], | |
| ["instances", num(feature.instances)], | |
| ["devices", num(feature.devices.length)], | |
| ])); | |
| box.append(el("hr")); | |
| box.append(el("p", null, "Implemented by:")); | |
| box.append(deviceChips(feature.devices.map((index) => data.devices[index]))); | |
| return; | |
| } | |
| if (!target) { | |
| box.append(el("h3", null, `${data.name} variant ${state.variant}`)); | |
| box.append(el("p", null, "Click a register or a bit field in the map to see what it is and which devices have it.")); | |
| box.append(facts([ | |
| ["instances", num(variant.instances)], | |
| ["devices", num(variant.devices.length)], | |
| ["register maps", num(variant.members.length)], | |
| ["registers", num(variant.registers.length)], | |
| ["features", num(variant.features.length)], | |
| ])); | |
| box.append(el("hr")); | |
| box.append(el("p", null, "Instance names:")); | |
| box.append(deviceChips(variant.names)); | |
| return; | |
| } | |
| const isField = target.kind === "field"; | |
| const node = isField ? target.item.field : target.row.register; | |
| const feature = node.feature; | |
| box.append(el("h3", null, node.names[0] || "?")); | |
| box.append(el("div", "sub", | |
| isField | |
| ? `${target.row.register.names[0]} [${range(node.position, node.width)}]` | |
| : `${hex(node.offset)} · ${node.width * 8} bit`)); | |
| const badge = el("span", `badge${feature < 0 ? "" : " opt"}`, feature < 0 ? "core" : `feature ${feature}`); | |
| if (feature >= 0) { | |
| badge.style.setProperty("--h", hue(feature)); | |
| badge.title = variant.features[feature].name || ""; | |
| } | |
| box.append(badge); | |
| if (feature >= 0 && variant.features[feature].name) { | |
| box.append(el("div", "sub", variant.features[feature].name)); | |
| } | |
| if (node.description) box.append(el("p", null, node.description)); | |
| const facts_ = []; | |
| if (node.names.length > 1) facts_.push(["also named", node.names.slice(1).join(", ")]); | |
| if (isField) { | |
| facts_.push(["bits", range(node.position, node.width)]); | |
| facts_.push(["width", `${node.width} bit`]); | |
| facts_.push(["register", target.row.register.names.join(" = ")]); | |
| facts_.push([target.row.register.offsets ? "offsets" : "offset", | |
| (target.row.register.offsets || [target.row.register.offset]).map(hex).join(", ")]); | |
| if (target.row.register.access && target.row.register.access.length) { | |
| facts_.push(["access", target.row.register.access.join(", ")]); | |
| } | |
| } else { | |
| facts_.push(node.offsets ? ["offsets", node.offsets.map(hex).join(", ")] : ["offset", hex(node.offset)]); | |
| facts_.push(["size", `${node.width * 8} bit`]); | |
| if (node.access && node.access.length) facts_.push(["access", node.access.join(", ")]); | |
| if (node.dim) facts_.push(["array", `${node.dim} entries`]); | |
| facts_.push(["fields", String(node.fields.length)]); | |
| } | |
| box.append(facts(facts_)); | |
| box.append(el("hr")); | |
| const devicesOf = feature < 0 ? variant.devices : variant.features[feature].devices; | |
| const maps = feature < 0 ? variant.members.length : variant.features[feature].members.length; | |
| box.append(el("p", null, | |
| feature < 0 | |
| ? `Part of the core: present in all ${maps} register maps of this variant, on ${devicesOf.length} devices.` | |
| : `Optional: present in ${maps} of ${variant.members.length} register maps, on ${devicesOf.length} devices.`)); | |
| box.append(deviceChips(devicesOf.map((index) => data.devices[index]))); | |
| } | |
| function facts(entries) { | |
| const list = el("dl"); | |
| for (const [key, value] of entries) { | |
| list.append(el("dt", null, key)); | |
| list.append(el("dd", null, value)); | |
| } | |
| return list; | |
| } | |
| /* ---------------------------------------------------------- interactions */ | |
| function attach(canvas) { | |
| const pointers = new Map(); | |
| let drag = null, pinch = null; | |
| canvas.addEventListener("pointerdown", (event) => { | |
| canvas.focus({preventScroll: true}); | |
| canvas.setPointerCapture(event.pointerId); | |
| pointers.set(event.pointerId, {x: event.offsetX, y: event.offsetY}); | |
| if (pointers.size === 2) { | |
| const [a, b] = [...pointers.values()]; | |
| pinch = {distance: Math.hypot(a.x - b.x, a.y - b.y)}; | |
| drag = null; | |
| } else { | |
| drag = {x: event.offsetX, y: event.offsetY, ox: map.ox, oy: map.oy, moved: false}; | |
| } | |
| }); | |
| canvas.addEventListener("pointermove", (event) => { | |
| if (pointers.has(event.pointerId)) pointers.set(event.pointerId, {x: event.offsetX, y: event.offsetY}); | |
| if (pinch && pointers.size === 2) { | |
| const [a, b] = [...pointers.values()]; | |
| const distance = Math.hypot(a.x - b.x, a.y - b.y); | |
| if (pinch.distance > 0) zoomAt((a.x + b.x) / 2, (a.y + b.y) / 2, distance / pinch.distance); | |
| pinch.distance = distance; | |
| return; | |
| } | |
| if (drag && pointers.has(event.pointerId)) { | |
| const dx = event.offsetX - drag.x, dy = event.offsetY - drag.y; | |
| if (!drag.moved && Math.hypot(dx, dy) > 3) { | |
| drag.moved = true; | |
| canvas.classList.add("dragging"); | |
| $("tip").hidden = true; | |
| } | |
| if (drag.moved) { | |
| map.ox = drag.ox + dx; | |
| map.oy = drag.oy + dy; | |
| clampView(); | |
| draw(); | |
| } | |
| return; | |
| } | |
| const hit = hitTest(event.offsetX, event.offsetY); | |
| if (!same(hit, map.hover)) { map.hover = hit; draw(); } | |
| const tip = $("tip"); | |
| if (!hit) { tip.hidden = true; return; } | |
| tip.textContent = ""; | |
| tip.append(el("strong", null, label(hit))); | |
| tip.append(el("span", null, describe(hit))); | |
| tip.hidden = false; | |
| tip.style.left = `${Math.min(event.offsetX + 14, map.width - tip.offsetWidth - 8)}px`; | |
| tip.style.top = `${event.offsetY + 18 + tip.offsetHeight > map.height | |
| ? event.offsetY - tip.offsetHeight - 10 : event.offsetY + 18}px`; | |
| }); | |
| const end = (event) => { | |
| const wasClick = drag && !drag.moved && pointers.size === 1 && event.type === "pointerup"; | |
| pointers.delete(event.pointerId); | |
| if (pointers.size < 2) pinch = null; | |
| canvas.classList.remove("dragging"); | |
| if (wasClick) select(hitTest(event.offsetX, event.offsetY)); | |
| drag = null; | |
| }; | |
| canvas.addEventListener("pointerup", end); | |
| canvas.addEventListener("pointercancel", end); | |
| canvas.addEventListener("pointerleave", () => { | |
| if (drag) return; | |
| $("tip").hidden = true; | |
| if (map.hover) { map.hover = null; draw(); } | |
| }); | |
| canvas.addEventListener("dblclick", (event) => { | |
| const hit = hitTest(event.offsetX, event.offsetY); | |
| if (hit) { select(hit); zoomTo(hit); } else { zoomAt(event.offsetX, event.offsetY, 2); } | |
| }); | |
| canvas.addEventListener("wheel", (event) => { | |
| event.preventDefault(); | |
| const scale = event.deltaMode === 1 ? 16 : event.deltaMode === 2 ? map.height : 1; | |
| if (event.ctrlKey || event.metaKey) { | |
| zoomAt(event.offsetX, event.offsetY, Math.exp(-event.deltaY * scale * 0.0025)); | |
| } else { | |
| map.ox -= (event.shiftKey && !event.deltaX ? event.deltaY : event.deltaX) * scale; | |
| map.oy -= (event.shiftKey && !event.deltaX ? 0 : event.deltaY) * scale; | |
| clampView(); | |
| draw(); | |
| } | |
| }, {passive: false}); | |
| canvas.addEventListener("keydown", (event) => { | |
| const cx = GUTTER + (map.width - GUTTER) / 2, cy = map.height / 2; | |
| switch (event.key) { | |
| case "ArrowUp": map.oy += 80; break; | |
| case "ArrowDown": map.oy -= 80; break; | |
| case "ArrowLeft": map.ox += 80; break; | |
| case "ArrowRight": map.ox -= 80; break; | |
| case "PageUp": map.oy += map.height * 0.9; break; | |
| case "PageDown": map.oy -= map.height * 0.9; break; | |
| case "+": case "=": zoomAt(cx, cy, 1.5); break; | |
| case "-": case "_": zoomAt(cx, cy, 1 / 1.5); break; | |
| case "0": fitView(); return; | |
| case "Escape": select(null); return; | |
| default: return; | |
| } | |
| event.preventDefault(); | |
| clampView(); | |
| draw(); | |
| }); | |
| new ResizeObserver(() => resize()).observe(canvas); | |
| } | |
| function same(a, b) { | |
| if (a === b) return true; | |
| if (!a || !b || a.kind !== b.kind || a.row !== b.row) return false; | |
| return a.kind === "register" || a.item === b.item; | |
| } | |
| function zoomTo(target) { | |
| const width = target.kind === "field" ? target.item.field.width : target.row.bits; | |
| const k = clamp(((map.width - GUTTER) * 0.7) / width, minZoom(), K_MAX); | |
| const bit = target.kind === "field" | |
| ? 32 - target.row.bits + target.item.start + width / 2 : 32 - target.row.bits / 2; | |
| const row = target.row.y + (target.kind === "field" ? target.item.lane + 0.5 : target.row.height / 2); | |
| map.k = k; | |
| map.ox = GUTTER + (map.width - GUTTER) / 2 - bit * k; | |
| map.oy = map.height / 2 - row * rowHeight(); | |
| clampView(); | |
| draw(); | |
| } | |
| /* ----------------------------------------------------------------- setup */ | |
| $("filter").addEventListener("input", (event) => { | |
| state.filter = event.target.value; | |
| renderGroups(); | |
| }); | |
| $("device").addEventListener("input", (event) => { | |
| state.device = event.target.value; | |
| if (state.data) renderGroup(); | |
| }); | |
| matchMedia("(prefers-color-scheme: dark)").addEventListener("change", () => { readColors(); draw(); }); | |
| $("modes").addEventListener("click", (event) => { | |
| const button = event.target.closest("button[data-mode]"); | |
| if (!button || button.dataset.mode === state.mode) return; | |
| setMode(button.dataset.mode); | |
| selectGroup(state.group); | |
| }); | |
| function setMode(mode) { | |
| state.mode = mode; | |
| state.index = state.all.modes[mode]; | |
| state.index.groups.sort((a, b) => b.variants.length - a.variants.length || a.name.localeCompare(b.name)); | |
| for (const button of $("modes").querySelectorAll("button[data-mode]")) { | |
| button.setAttribute("aria-pressed", String(button.dataset.mode === mode)); | |
| } | |
| $("t-instances").textContent = num(state.index.instances); | |
| $("t-shapes").textContent = num(state.index.shapes); | |
| $("t-variants").textContent = num(state.index.variants); | |
| renderGroups(); | |
| } | |
| async function start() { | |
| try { | |
| const response = await fetch("variants.json"); | |
| if (!response.ok) throw new Error(`${response.status} ${response.statusText}`); | |
| state.all = await response.json(); | |
| } catch (error) { | |
| $("g-name").textContent = "Could not load variants.json"; | |
| $("g-sub").textContent = `${error.message}. Serve this folder over HTTP, the JSON files sit next to this page.`; | |
| return; | |
| } | |
| const parts = decodeURIComponent(location.hash.slice(1)).split("/"); | |
| const [mode, name, variant] = parts.length > 2 ? parts : ["binary", ...parts]; | |
| setMode(state.all.modes[mode] ? mode : "binary"); | |
| const known = state.index.groups.find((g) => g.name === name); | |
| selectGroup(known ? name : state.index.groups[0].name, known ? Number(variant) || 0 : 0); | |
| } | |
| start(); | |
| </script> |
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