elfobj

SPEC.md

libelfobj — Specification

1. Purpose

libelfobj is a portable, zero-dependency C library for reading, creating, modifying, validating, and writing ELF (Executable and Linkable Format) object files. It serves as the sole ELF manipulation layer for all Substrate binutils (as, ld, nm, objcopy, objdump, readelf, strip, size, strings, ar, addr2line, elfedit).

2. Scope

Attribute	Value
Library name	libelfobj
Install path	/usr/lib/libelfobj.a (static library)
Public header	<elfobj.h>
ELF classes	ELF32, ELF64
Byte orders	Little-endian (ELFDATA2LSB), Big-endian (ELFDATA2MSB)
Architectures	i386 (EM_386), x86-64 (EM_X86_64), ARMv7 (EM_ARM), AArch64 (EM_AARCH64), MIPS/MIPS64 (EM_MIPS), RISC-V (EM_RISCV), LoongArch (EM_LOONGARCH), M68K (EM_68K), VAX (EM_VAX), Alpha (EM_ALPHA), PowerPC/PowerPC64 (EM_PPC/EM_PPC64), IA-64 (EM_IA_64)
Host build	NATIVE_BUILD=1 for development/test on Linux/BSD host
Dependencies	None (freestanding C99; uses only libc for malloc/stdio)

3. Definitions

Term	Definition
EARS	Easy Approach to Requirements Syntax (ISO/IEC/IEEE 29148 compatible)
ET_REL	Relocatable object file (.o)
ET_EXEC	Executable file
ET_DYN	Shared object / PIE
ET_CORE	Core dump file
Relocation	A fixup record binding a symbol reference to its definition at link time
REL	Relocation without explicit addend (i386, ARM); addend in instruction
RELA	Relocation with explicit addend (x86-64, AArch64)
Section	Named region of an ELF file with type, flags, and content
Segment	Runtime-visible region described by a program header
Backend	Architecture-specific relocation engine plug-in
Build attribute	ARM EABI vendor-specific metadata tag in .ARM.attributes
GNU property	Feature flag in .note.gnu.property (ISA level, BTI, PAC)
GP-relative	Addressing mode relative to the Global Pointer register (MIPS, RISC-V)
PLT stub	Procedure Linkage Table trampoline for lazy symbol resolution
TOC	Table of Contents — PowerPC64 ELFv2 per-function data pointer table
ABIFLAGS	MIPS .MIPS.abiflags section encoding ABI/ISA/ASE/FP mode metadata

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4. Functional Requirements

4.1 ELF Reading

REQ-ELF-010 (Ubiquitous) The library shall parse ELF files from a file path via elf_open_file() or from a memory buffer via elf_open_memory().

REQ-ELF-011 (Ubiquitous) The library shall parse both ELF32 and ELF64 file headers and expose class, endianness, machine type, entry point, and flags.

REQ-ELF-012 (Ubiquitous) The library shall parse section headers and provide indexed access to sections by name or by index.

REQ-ELF-013 (Ubiquitous) The library shall parse symbol tables (.symtab, .dynsym) and provide access to each symbol's name, value, size, type, binding, visibility, and section index.

REQ-ELF-014 (Ubiquitous) The library shall parse relocation sections (SHT_REL, SHT_RELA) and expose each relocation's offset, type, symbol reference, and addend.

REQ-ELF-015 (Ubiquitous) The library shall parse program headers and expose each segment's type, flags, offset, virtual address, physical address, file size, memory size, and alignment.

REQ-ELF-016 (Ubiquitous) The library shall parse string tables (SHT_STRTAB) with bounds checking on all index accesses.

REQ-ELF-017 (Event-driven) When the input file is truncated or contains invalid offsets, the library shall return an error code and set a diagnostic message without crashing.

REQ-ELF-018 (Ubiquitous) The library shall perform all multi-byte reads using the endianness specified in e_ident[EI_DATA], supporting both little-endian and big-endian files.

REQ-ELF-019 (Event-driven) When elf_open_file() is called with a path that cannot be opened, the library shall return ELF_ERR_IO with a diagnostic message.

4.2 ELF Creation

REQ-ELF-020 (Ubiquitous) The library shall create new ELF objects via elf_create() with specified class, endianness, and machine type.

REQ-ELF-021 (Ubiquitous) The library shall provide convenience initializers: elf_init_i386(), elf_init_x86_64(), elf_init_arm(), elf_init_aarch64().

REQ-ELF-022 (Ubiquitous) The library shall allow adding sections with elf_add_section(), specifying name, type, flags, alignment, entry size, and initial data.

REQ-ELF-023 (Ubiquitous) The library shall allow adding symbols with elf_add_symbol(), specifying name, value, size, type, binding, visibility, and section index.

REQ-ELF-024 (Ubiquitous) The library shall allow adding relocations with elf_add_relocation(), specifying section, offset, symbol, type, and addend.

REQ-ELF-025 (Ubiquitous) The library shall allow adding program headers / segments with elf_add_segment(), specifying type, flags, alignment, and member sections.

REQ-ELF-026 (Ubiquitous) The library shall automatically generate .symtab, .strtab, and .shstrtab sections during finalization.

REQ-ELF-027 (Ubiquitous) The library shall set e_flags via elf_set_flags() and expose it via elf_flags().

4.3 ELF Writing

REQ-ELF-030 (Ubiquitous) The library shall write finalized ELF objects to a file path via elf_write_file() or to a memory buffer via elf_write_buffer().

REQ-ELF-031 (Ubiquitous) The library shall compute section offsets, sizes, and string table indices during a layout pass before writing.

REQ-ELF-032 (Ubiquitous) The library shall write all multi-byte values in the endianness specified at creation time.

REQ-ELF-033 (Ubiquitous) The library shall emit REL-format relocations for ELF32 objects (i386, ARM) and RELA-format relocations for ELF64 objects (x86-64, AArch64) by default.

REQ-ELF-034 (State-driven) While an object is marked read-only or finalized, the library shall reject mutation calls with ELF_ERR_STATE.

REQ-ELF-035 (Ubiquitous) The library shall produce deterministic output: identical API calls in identical order shall produce byte-identical ELF files.

4.4 Relocation Engine

REQ-ELF-040 (Ubiquitous) The library shall provide a pluggable relocation backend interface: apply_reloc, reloc_size, is_pc_relative.

REQ-ELF-041 (Ubiquitous) The library shall register built-in backends for EM_386 and EM_X86_64 at initialization.

REQ-ELF-042 (Ubiquitous) The library shall register built-in backends for EM_ARM and EM_AARCH64 at initialization.

REQ-ELF-043 (Ubiquitous) The library shall allow external registration of custom backends via elf_register_reloc_backend().

REQ-ELF-044 (Ubiquitous) The library shall apply relocations via elf_apply_relocation(), computing the result value using the appropriate backend.

REQ-ELF-045 (Event-driven) When a relocation result overflows the target field width, the library shall return ELF_ERR_RELOC with a diagnostic identifying the relocation type and overflow.

REQ-ELF-046 (Event-driven) When a relocation type is not recognized by any backend, the library shall return ELF_ERR_UNSUPPORTED with the machine and type in the diagnostic.

REQ-ELF-047 (Ubiquitous) The library shall provide elf_reloc_size_for_machine() returning the byte width of a relocation result for a given machine and type.

REQ-ELF-048 (Ubiquitous) The library shall provide elf_reloc_is_pc_relative_for_machine() and elf_reloc_is_tls_for_machine() classification functions.

REQ-ELF-049 (Ubiquitous) The library shall provide elf_reloc_name_for_machine() returning a human-readable string (e.g., "R_X86_64_PC32") for any known relocation type.

4.5 i386 Relocation Backend

REQ-ELF-050 (Ubiquitous) The i386 backend shall compute relocations for: R_386_NONE, R_386_32, R_386_PC32, R_386_GOT32, R_386_PLT32, R_386_RELATIVE, R_386_GOTOFF, R_386_GOTPC, and all R_386_TLS_* types.

REQ-ELF-051 (Ubiquitous) The i386 backend shall compute relocations for: R_386_COPY, R_386_GLOB_DAT, R_386_JMP_SLOT, R_386_IRELATIVE, R_386_GOT32X, R_386_SIZE32.

REQ-ELF-052 (Ubiquitous) The i386 backend shall compute relocations for 16-bit and 8-bit types: R_386_16, R_386_PC16, R_386_8, R_386_PC8.

REQ-ELF-053 (Ubiquitous) The i386 backend shall check overflow: 32-bit unsigned for R_386_32, 32-bit signed for R_386_PC32, 16-bit for R_386_16/R_386_PC16, 8-bit for R_386_8/R_386_PC8.

4.6 x86-64 Relocation Backend

REQ-ELF-060 (Ubiquitous) The x86-64 backend shall compute relocations for: R_X86_64_NONE, R_X86_64_64, R_X86_64_PC32, R_X86_64_GOT32, R_X86_64_PLT32, R_X86_64_GOTPCREL, R_X86_64_32, R_X86_64_32S, and all R_X86_64_TLS* types.

REQ-ELF-061 (Ubiquitous) The x86-64 backend shall compute relocations for: R_X86_64_COPY, R_X86_64_GLOB_DAT, R_X86_64_JUMP_SLOT, R_X86_64_RELATIVE, R_X86_64_IRELATIVE, R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX.

REQ-ELF-062 (Ubiquitous) The x86-64 backend shall compute: R_X86_64_PC64, R_X86_64_GOTOFF64, R_X86_64_GOTPC32, R_X86_64_SIZE32, R_X86_64_SIZE64.

REQ-ELF-063 (Ubiquitous) The x86-64 backend shall compute TLSDESC relocations: R_X86_64_GOTPC32_TLSDESC, R_X86_64_TLSDESC_CALL, R_X86_64_TLSDESC.

4.7 ARMv7 Relocation Backend

REQ-ELF-070 (Ubiquitous) The ARM backend shall compute relocations for all static types: R_ARM_ABS32, R_ARM_REL32, R_ARM_PC24, R_ARM_CALL, R_ARM_JUMP24, R_ARM_PLT32, R_ARM_GOTOFF32, R_ARM_GOTPC, R_ARM_GOT_BREL, R_ARM_PREL31.

REQ-ELF-071 (Ubiquitous) The ARM backend shall compute MOVW/MOVT relocations by extracting and reinserting the 16-bit immediate from ARM instruction fields (bits[19:16] + bits[11:0]).

REQ-ELF-072 (Ubiquitous) The ARM backend shall compute Thumb branch relocations (R_ARM_THM_CALL, R_ARM_THM_JUMP24) by decoding and re-encoding J1/J2/imm10/imm11 fields.

REQ-ELF-073 (Ubiquitous) The ARM backend shall compute Thumb MOVW/MOVT relocations by extracting and reinserting the 16-bit immediate from Thumb-2 fields (imm4:i:imm3:imm8).

REQ-ELF-074 (Ubiquitous) The ARM backend shall apply the Thumb interwork bit (T) when the target symbol is a Thumb function.

REQ-ELF-075 (Ubiquitous) The ARM backend shall compute group relocations (R_ARM_ALU_PC_G*, R_ARM_LDR_PC_G*, SB variants) per ARM EABI §4.6.1.4.

REQ-ELF-076 (Ubiquitous) The ARM backend shall handle R_ARM_V4BX by rewriting BX Rm to MOV PC, Rm.

4.8 AArch64 Relocation Backend

REQ-ELF-080 (Ubiquitous) The AArch64 backend shall compute page-relative relocations: R_AARCH64_ADR_PREL_PG_HI21 using Page(S+A) - Page(P), and R_AARCH64_ADD_ABS_LO12_NC using (S+A) & 0xFFF.

REQ-ELF-081 (Ubiquitous) The AArch64 backend shall compute branch relocations: R_AARCH64_JUMP26 and R_AARCH64_CALL26 using (S+A-P) >> 2 with ±128MB range check.

REQ-ELF-082 (Ubiquitous) The AArch64 backend shall compute conditional branch and test-branch relocations: R_AARCH64_CONDBR19 (±1MB), R_AARCH64_TSTBR14 (±32KB).

REQ-ELF-083 (Ubiquitous) The AArch64 backend shall compute load/store offset relocations with alignment checking: R_AARCH64_LDST8/16/32/64/128_ABS_LO12_NC.

REQ-ELF-084 (Ubiquitous) The AArch64 backend shall compute MOVW relocations for all groups G0–G3, including signed variants that may flip MOVZ↔MOVN.

REQ-ELF-085 (Ubiquitous) The AArch64 backend shall provide instruction field helper functions for extracting and inserting imm26, imm19, imm14, ADR imm, imm12, and MOVW imm16.

4.9 MIPS / MIPS64 Relocation Backend

REQ-ELF-150 (Ubiquitous) The library shall register built-in backends for EM_MIPS covering both MIPS32 (ELF32, O32/N32 ABIs) and MIPS64 (ELF64, N64 ABI).

REQ-ELF-151 (Ubiquitous) The MIPS backend shall compute static relocations: R_MIPS_NONE, R_MIPS_16, R_MIPS_32, R_MIPS_REL32, R_MIPS_26, R_MIPS_HI16, R_MIPS_LO16, R_MIPS_GPREL16, R_MIPS_LITERAL, R_MIPS_GOT16, R_MIPS_PC16, R_MIPS_CALL16, R_MIPS_GPREL32.

REQ-ELF-152 (Ubiquitous) The MIPS backend shall handle paired R_MIPS_HI16/R_MIPS_LO16 relocations with correct AHL computation: AHL = (AHI << 16) + (int16_t)ALO.

REQ-ELF-153 (Ubiquitous) The MIPS backend shall compute TLS relocations: R_MIPS_TLS_DTPMOD32/64, R_MIPS_TLS_DTPREL32/64, R_MIPS_TLS_TPREL32/64, R_MIPS_TLS_GD, R_MIPS_TLS_LDM, R_MIPS_TLS_DTPREL_HI16/LO16, R_MIPS_TLS_GOTTPREL, R_MIPS_TLS_TPREL_HI16/LO16.

REQ-ELF-154 (Ubiquitous) The MIPS backend shall handle MIPS-specific section types: SHT_MIPS_DWARF, SHT_MIPS_ABIFLAGS, and the .MIPS.abiflags section structure.

REQ-ELF-155 (Ubiquitous) The MIPS backend shall parse and validate e_flags for ABI (O32/N32/N64), ISA level (MIPS I–VI, MIPS32/64 r1–r6), ASE flags (MDMX, MIPS16, MICROMIPS, DSP, DSPr2, MSA), and FP mode (FR=0/FR=1).

REQ-ELF-156 (Ubiquitous) The library shall provide elf_init_mips32() and elf_init_mips64() convenience initializers.

REQ-ELF-157 (Ubiquitous) The MIPS backend shall parse .MIPS.abiflags sections and expose ISA level, ISA revision, GPR/CPR sizes, FP ABI, and ASE flags.

4.10 RISC-V Relocation Backend

REQ-ELF-160 (Ubiquitous) The library shall register built-in backends for EM_RISCV covering RV32 (ELF32), RV64 (ELF64), and RV128 (ELF64 with 128-bit addressing, draft spec) when toolchain support matures.

REQ-ELF-161 (Ubiquitous) The RISC-V backend shall compute static relocations: R_RISCV_NONE, R_RISCV_32, R_RISCV_64, R_RISCV_BRANCH, R_RISCV_JAL, R_RISCV_CALL, R_RISCV_CALL_PLT, R_RISCV_GOT_HI20, R_RISCV_HI20, R_RISCV_LO12_I, R_RISCV_LO12_S, R_RISCV_PCREL_HI20, R_RISCV_PCREL_LO12_I, R_RISCV_PCREL_LO12_S.

REQ-ELF-162 (Ubiquitous) The RISC-V backend shall compute TLS relocations: R_RISCV_TLS_DTPMOD32/64, R_RISCV_TLS_DTPREL32/64, R_RISCV_TLS_TPREL32/64, R_RISCV_TLS_GD_HI20, R_RISCV_TLS_GOT_HI20, R_RISCV_TPREL_HI20, R_RISCV_TPREL_LO12_I, R_RISCV_TPREL_LO12_S, R_RISCV_TPREL_ADD.

REQ-ELF-163 (Ubiquitous) The RISC-V backend shall handle relaxation-related relocations: R_RISCV_RELAX, R_RISCV_ALIGN, R_RISCV_RVC_BRANCH, R_RISCV_RVC_JUMP, R_RISCV_RVC_LUI.

REQ-ELF-164 (Ubiquitous) The RISC-V backend shall parse and validate e_flags for float ABI (EF_RISCV_FLOAT_ABI_SOFT/SINGLE/DOUBLE/QUAD), RVC (EF_RISCV_RVC), and TSO (EF_RISCV_TSO).

REQ-ELF-165 (Ubiquitous) The library shall provide elf_init_riscv32() and elf_init_riscv64() convenience initializers.

REQ-ELF-166 (Ubiquitous) The RISC-V backend shall handle .riscv.attributes sections (SHT_RISCV_ATTRIBUTES) for ISA string and stack alignment tags.

4.11 LoongArch Relocation Backend

REQ-ELF-170 (Ubiquitous) The library shall register built-in backends for EM_LOONGARCH covering LA32 (ELF32) and LA64 (ELF64).

REQ-ELF-171 (Ubiquitous) The LoongArch backend shall compute static relocations: R_LARCH_NONE, R_LARCH_32, R_LARCH_64, R_LARCH_B16, R_LARCH_B21, R_LARCH_B26, R_LARCH_ABS_HI20, R_LARCH_ABS_LO12, R_LARCH_ABS64_LO20, R_LARCH_ABS64_HI12, R_LARCH_PCALA_HI20, R_LARCH_PCALA_LO12, R_LARCH_PCALA64_LO20, R_LARCH_PCALA64_HI12, R_LARCH_GOT_PC_HI20, R_LARCH_GOT_PC_LO12.

REQ-ELF-172 (Ubiquitous) The LoongArch backend shall compute TLS relocations: R_LARCH_TLS_LE_HI20/LO12/LO12_R, R_LARCH_TLS_IE_PC_HI20/LO12, R_LARCH_TLS_GD_PC_HI20, R_LARCH_TLS_LD_PC_HI20, R_LARCH_TLS_DESC_PC_HI20/PC_LO12/LD/CALL.

REQ-ELF-173 (Ubiquitous) The LoongArch backend shall handle relaxation relocations: R_LARCH_RELAX, R_LARCH_ALIGN.

REQ-ELF-174 (Ubiquitous) The LoongArch backend shall parse and validate e_flags for ABI modifier (EF_LARCH_ABI_MODIFIER_MASK), float ABI (EF_LARCH_ABI_SOFT_FLOAT/SINGLE_FLOAT/DOUBLE_FLOAT), and object ABI version (EF_LARCH_OBJABI_V1).

REQ-ELF-175 (Ubiquitous) The library shall provide elf_init_loongarch32() and elf_init_loongarch64() convenience initializers.

4.12 Motorola 68000 (M68K) Relocation Backend

REQ-ELF-180 (Ubiquitous) The library shall register a built-in backend for EM_68K (ELF32, big-endian).

REQ-ELF-181 (Ubiquitous) The M68K backend shall compute static relocations: R_68K_NONE, R_68K_32, R_68K_16, R_68K_8, R_68K_PC32, R_68K_PC16, R_68K_PC8, R_68K_GOT32, R_68K_GOT16, R_68K_GOT8, R_68K_GOT32O, R_68K_GOT16O, R_68K_GOT8O, R_68K_PLT32, R_68K_PLT16, R_68K_PLT8, R_68K_PLT32O, R_68K_PLT16O, R_68K_PLT8O, R_68K_RELATIVE, R_68K_GLOB_DAT, R_68K_JMP_SLOT, R_68K_COPY.

REQ-ELF-182 (Ubiquitous) The M68K backend shall compute TLS relocations: R_68K_TLS_GD32, R_68K_TLS_GD16, R_68K_TLS_GD8, R_68K_TLS_LDM32, R_68K_TLS_LDM16, R_68K_TLS_LDM8, R_68K_TLS_LDO32, R_68K_TLS_LDO16, R_68K_TLS_LDO8, R_68K_TLS_IE32, R_68K_TLS_IE16, R_68K_TLS_IE8, R_68K_TLS_LE32, R_68K_TLS_LE16, R_68K_TLS_LE8, R_68K_TLS_DTPMOD32, R_68K_TLS_DTPREL32, R_68K_TLS_TPREL32.

REQ-ELF-183 (Ubiquitous) The M68K backend shall validate EM_68K with ELFCLASS32 and ELFDATA2MSB only.

REQ-ELF-184 (Ubiquitous) The library shall provide elf_init_m68k() convenience initializer setting ELF32/EM_68K/ELFDATA2MSB.

4.13 VAX Relocation Backend

REQ-ELF-190 (Ubiquitous) The library shall register a built-in backend for EM_VAX (ELF32, little-endian).

REQ-ELF-191 (Ubiquitous) The VAX backend shall compute static relocations: R_VAX_NONE, R_VAX_32, R_VAX_16, R_VAX_8, R_VAX_PC32, R_VAX_PC16, R_VAX_PC8, R_VAX_GOT32, R_VAX_PLT32, R_VAX_COPY, R_VAX_GLOB_DAT, R_VAX_JMP_SLOT, R_VAX_RELATIVE.

REQ-ELF-192 (Ubiquitous) The VAX backend shall validate EM_VAX with ELFCLASS32 and ELFDATA2LSB only.

REQ-ELF-193 (Ubiquitous) The library shall provide elf_init_vax() convenience initializer setting ELF32/EM_VAX/ELFDATA2LSB.

4.14 PowerPC / PowerPC64 Relocation Backend

REQ-ELF-200 (Ubiquitous) The library shall register built-in backends for EM_PPC (ELF32) and EM_PPC64 (ELF64).

REQ-ELF-201 (Ubiquitous) The PowerPC32 backend shall compute static relocations: R_PPC_NONE, R_PPC_ADDR32, R_PPC_ADDR24, R_PPC_ADDR16, R_PPC_ADDR16_LO, R_PPC_ADDR16_HI, R_PPC_ADDR16_HA, R_PPC_ADDR14, R_PPC_REL24, R_PPC_REL14, R_PPC_REL32, R_PPC_GOT16, R_PPC_GOT16_LO, R_PPC_GOT16_HI, R_PPC_GOT16_HA, R_PPC_PLT32, R_PPC_PLTREL24, R_PPC_COPY, R_PPC_GLOB_DAT, R_PPC_JMP_SLOT, R_PPC_RELATIVE, R_PPC_LOCAL24PC, R_PPC_UADDR32, R_PPC_UADDR16, R_PPC_SDAREL16, R_PPC_SECTOFF, R_PPC_IRELATIVE.

REQ-ELF-202 (Ubiquitous) The PowerPC64 backend shall compute static relocations: R_PPC64_ADDR64, R_PPC64_ADDR16_HIGHER, R_PPC64_ADDR16_HIGHERA, R_PPC64_ADDR16_HIGHEST, R_PPC64_ADDR16_HIGHESTA, R_PPC64_ADDR16_DS, R_PPC64_ADDR16_LO_DS, R_PPC64_GOT16_DS, R_PPC64_GOT16_LO_DS, R_PPC64_PLT16_LO_DS, R_PPC64_TOC16, R_PPC64_TOC16_LO, R_PPC64_TOC16_HI, R_PPC64_TOC16_HA, R_PPC64_TOC16_DS, R_PPC64_TOC16_LO_DS, R_PPC64_TOC, R_PPC64_REL64, R_PPC64_ENTRY, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34, R_PPC64_PLT_PCREL34.

REQ-ELF-203 (Ubiquitous) The PowerPC backend shall compute TLS relocations for both PPC32 and PPC64: R_PPC{64}_TLS, R_PPC{64}_DTPMOD32/64, R_PPC{64}_DTPREL32/64/16, R_PPC{64}_TPREL32/64/16, R_PPC{64}_GOT_TLSGD16{_LO/_HI/_HA}, R_PPC{64}_GOT_TLSLD16{_LO/_HI/_HA}, R_PPC{64}_GOT_TPREL16{_LO/_HI/_HA/_DS}.

REQ-ELF-204 (Ubiquitous) The PowerPC backend shall parse and validate e_flags including EF_PPC_EMB, EF_PPC64_ABI_V1, EF_PPC64_ABI_V2 (ELFv2 ABI).

REQ-ELF-205 (Ubiquitous) The PowerPC64 backend shall handle .opd (official procedure descriptors) for ELFv1 ABI and TOC pointer management for ELFv2.

REQ-ELF-206 (Ubiquitous) The library shall provide elf_init_ppc32() and elf_init_ppc64() convenience initializers.

4.15 Alpha Relocation Backend

REQ-ELF-210 (Ubiquitous) The library shall register a built-in backend for EM_ALPHA (0x9026, ELF64, little-endian only).

REQ-ELF-211 (Ubiquitous) The Alpha backend shall compute static relocations: R_ALPHA_NONE, R_ALPHA_REFLONG, R_ALPHA_REFQUAD, R_ALPHA_GPREL32, R_ALPHA_LITERAL, R_ALPHA_LITUSE, R_ALPHA_GPDISP, R_ALPHA_BRADDR, R_ALPHA_HINT, R_ALPHA_SREL16, R_ALPHA_SREL32, R_ALPHA_SREL64, R_ALPHA_GPRELHIGH, R_ALPHA_GPRELLOW, R_ALPHA_GPREL16.

REQ-ELF-212 (Ubiquitous) The Alpha backend shall compute dynamic relocations: R_ALPHA_COPY, R_ALPHA_GLOB_DAT, R_ALPHA_JMP_SLOT, R_ALPHA_RELATIVE.

REQ-ELF-213 (Ubiquitous) The Alpha backend shall compute TLS relocations: R_ALPHA_TLSGD, R_ALPHA_TLSLDM, R_ALPHA_DTPMOD64, R_ALPHA_GOTDTPREL, R_ALPHA_DTPREL64, R_ALPHA_DTPRELHI, R_ALPHA_DTPRELLO, R_ALPHA_DTPREL16, R_ALPHA_GOTTPREL, R_ALPHA_TPREL64, R_ALPHA_TPRELHI, R_ALPHA_TPRELLO, R_ALPHA_TPREL16.

REQ-ELF-214 (Ubiquitous) The Alpha backend shall validate EM_ALPHA with ELFCLASS64 and ELFDATA2LSB only.

REQ-ELF-215 (Ubiquitous) The library shall provide elf_init_alpha() convenience initializer setting ELF64/EM_ALPHA/ELFDATA2LSB.

4.16 IA-64 (Itanium) Relocation Backend

REQ-ELF-220 (Ubiquitous) The library shall register a built-in backend for EM_IA_64 (50, ELF64).

REQ-ELF-221 (Ubiquitous) The IA-64 backend shall compute static relocations: R_IA64_NONE, R_IA64_IMM14, R_IA64_IMM22, R_IA64_IMM64, R_IA64_DIR32MSB, R_IA64_DIR32LSB, R_IA64_DIR64MSB, R_IA64_DIR64LSB, R_IA64_GPREL22, R_IA64_GPREL64I, R_IA64_GPREL32MSB, R_IA64_GPREL32LSB, R_IA64_GPREL64MSB, R_IA64_GPREL64LSB, R_IA64_LTOFF22, R_IA64_LTOFF64I, R_IA64_PLTOFF22, R_IA64_PLTOFF64I, R_IA64_PLTOFF64MSB, R_IA64_PLTOFF64LSB, R_IA64_PCREL21B, R_IA64_PCREL21M, R_IA64_PCREL21F, R_IA64_PCREL32MSB, R_IA64_PCREL32LSB, R_IA64_PCREL64MSB, R_IA64_PCREL64LSB, R_IA64_FPTR64I, R_IA64_FPTR32MSB, R_IA64_FPTR32LSB, R_IA64_FPTR64MSB, R_IA64_FPTR64LSB, R_IA64_SEGREL32MSB, R_IA64_SEGREL32LSB, R_IA64_SEGREL64MSB, R_IA64_SEGREL64LSB, R_IA64_SECREL32MSB, R_IA64_SECREL32LSB, R_IA64_SECREL64MSB, R_IA64_SECREL64LSB, R_IA64_LTOFF_FPTR22, R_IA64_LTOFF_FPTR64I, R_IA64_LTOFF_FPTR32MSB, R_IA64_LTOFF_FPTR32LSB, R_IA64_LTOFF_FPTR64MSB, R_IA64_LTOFF_FPTR64LSB.

REQ-ELF-222 (Ubiquitous) The IA-64 backend shall compute dynamic relocations: R_IA64_COPY, R_IA64_GLOB_DAT (alias R_IA64_DIR64LSB), R_IA64_JMP_SLOT (alias R_IA64_IPLTLSB), R_IA64_RELATIVE, R_IA64_REL32MSB, R_IA64_REL32LSB, R_IA64_REL64MSB, R_IA64_REL64LSB.

REQ-ELF-223 (Ubiquitous) The IA-64 backend shall compute TLS relocations: R_IA64_LTOFF_DTPMOD22, R_IA64_DTPMOD64MSB, R_IA64_DTPMOD64LSB, R_IA64_LTOFF_DTPREL22, R_IA64_DTPREL14, R_IA64_DTPREL22, R_IA64_DTPREL64I, R_IA64_DTPREL32MSB, R_IA64_DTPREL32LSB, R_IA64_DTPREL64MSB, R_IA64_DTPREL64LSB, R_IA64_LTOFF_TPREL22, R_IA64_TPREL14, R_IA64_TPREL22, R_IA64_TPREL64I, R_IA64_TPREL64MSB, R_IA64_TPREL64LSB.

REQ-ELF-224 (Ubiquitous) The IA-64 backend shall handle instruction bundle slot encoding: IA-64 instructions are packed in 128-bit bundles with 3 slots; relocations targeting slot-specific immediates shall decode the template byte and extract/insert the correct slot.

REQ-ELF-225 (Ubiquitous) The IA-64 backend shall parse and validate e_flags including EF_IA_64_ABI64 (ELF64 flag) and EF_IA_64_ARCH (architecture version).

REQ-ELF-226 (Ubiquitous) The IA-64 backend shall validate EM_IA_64 with ELFCLASS64 only, accepting both ELFDATA2LSB and ELFDATA2MSB.

REQ-ELF-227 (Ubiquitous) The library shall provide elf_init_ia64() convenience initializer setting ELF64/EM_IA_64/ELFDATA2LSB.

4.17 Validation

REQ-ELF-090 (Ubiquitous) The library shall validate ELF structure via elf_validate(), checking magic bytes, class, data encoding, header sizes, and section/program header consistency.

REQ-ELF-091 (Ubiquitous) The library shall detect and report overlapping sections, out-of-bounds offsets, and invalid string table references.

REQ-ELF-092 (State-driven) While validating an EM_386 object, the library shall reject ELFCLASS64 and ELFDATA2MSB.

REQ-ELF-093 (State-driven) While validating an EM_X86_64 object, the library shall reject ELFCLASS32 and ELFDATA2MSB.

REQ-ELF-094 (State-driven) While validating an EM_ARM object, the library shall reject ELFCLASS64 and validate e_flags EABI version and float ABI consistency.

REQ-ELF-095 (State-driven) While validating an EM_AARCH64 object, the library shall reject ELFCLASS32.

REQ-ELF-095a (State-driven) While validating an EM_MIPS object, the library shall accept ELFCLASS32 (O32/N32) or ELFCLASS64 (N64), accept both endiannesses, and validate e_flags ISA level and ABI fields.

REQ-ELF-095b (State-driven) While validating an EM_RISCV object, the library shall accept ELFCLASS32 (RV32) or ELFCLASS64 (RV64), reject ELFDATA2MSB, and validate e_flags float ABI and RVC flags.

REQ-ELF-095c (State-driven) While validating an EM_LOONGARCH object, the library shall accept ELFCLASS32 or ELFCLASS64, reject ELFDATA2MSB, and validate e_flags ABI modifier and float ABI.

REQ-ELF-095d (State-driven) While validating an EM_68K object, the library shall reject ELFCLASS64 and ELFDATA2LSB.

REQ-ELF-095e (State-driven) While validating an EM_VAX object, the library shall reject ELFCLASS64 and ELFDATA2MSB.

REQ-ELF-095f (State-driven) While validating an EM_PPC object, the library shall reject ELFCLASS64. While validating an EM_PPC64 object, the library shall reject ELFCLASS32. Both shall accept either endianness (PPC has both LE and BE variants).

REQ-ELF-095g (State-driven) While validating an EM_ALPHA object, the library shall reject ELFCLASS32 and ELFDATA2MSB.

REQ-ELF-095h (State-driven) While validating an EM_IA_64 object, the library shall reject ELFCLASS32 and validate e_flags ABI64 and architecture version.

REQ-ELF-096 (Ubiquitous) The library shall accumulate multiple validation diagnostics (up to a configurable limit) rather than stopping at the first error.

REQ-ELF-097 (Ubiquitous) The library shall classify diagnostics by severity level: error, warning, info.

4.18 ARM Build Attributes

REQ-ELF-100 (Event-driven) When an EM_ARM object contains a SHT_ARM_ATTRIBUTES section, the library shall parse it into vendor subsections and tag-value pairs per ARM EABI §2.2.3.

REQ-ELF-101 (Ubiquitous) The library shall decode all standard aeabi tags (Tag_CPU_name through Tag_Virtualization_use) and expose them via elf_arm_attribute_tag_at() and elf_arm_attribute_value_at().

REQ-ELF-102 (Ubiquitous) The library shall skip unknown vendor subsections without error.

REQ-ELF-103 (Ubiquitous) The library shall provide elf_arm_attribute_count() for the number of parsed tags.

4.11 GNU Properties and Notes

REQ-ELF-110 (Ubiquitous) The library shall parse .note.gnu.property sections and expose individual properties via elf_gnu_property_at().

REQ-ELF-111 (Ubiquitous) The library shall provide elf_x86_isa_level() returning the GNU_PROPERTY_X86_ISA_1_NEEDED bitmask (0 if absent).

REQ-ELF-112 (Ubiquitous) The library shall provide elf_x86_feature_flags() returning the GNU_PROPERTY_X86_FEATURE_1_AND bitmask.

REQ-ELF-113 (Ubiquitous) The library shall provide elf_aarch64_feature_flags() returning the GNU_PROPERTY_AARCH64_FEATURE_1_AND bitmask (BTI, PAC).

REQ-ELF-114 (Ubiquitous) The library shall provide elf_build_id() to extract .note.gnu.build-id contents.

REQ-ELF-115 (Ubiquitous) The library shall provide elf_add_gnu_property_x86() and elf_add_gnu_property_aarch64() for creating properties during ELF construction.

4.12 DWARF Support

REQ-ELF-120 (Ubiquitous) The library shall parse .debug_line sections (DWARF versions 2–5) and expose file/line/column mappings via elf_dwarf_line_find().

REQ-ELF-121 (Ubiquitous) The library shall parse .debug_info and .debug_abbrev for DIE traversal.

REQ-ELF-122 (Ubiquitous) The library shall support per-architecture DWARF register number mappings.

4.13 Link Planning

REQ-ELF-130 (Ubiquitous) The library shall provide a link planning API (elf_link_plan_t) for collecting multiple input objects, resolving symbols, and merging sections.

REQ-ELF-131 (Event-driven) When link inputs have mismatched e_machine values, the library shall reject the link with ELF_ERR_STATE.

REQ-ELF-132 (Event-driven) When merging ARM objects with conflicting float ABI flags, the library shall report an error.

REQ-ELF-133 (Ubiquitous) The library shall provide hooks for section merge policy, archive extraction, GC, incremental linking, and symbol versioning.

4.14 Architecture-Specific Sections

REQ-ELF-140 (State-driven) While processing EM_ARM objects, the library shall handle SHT_ARM_EXIDX sections with SHF_LINK_ORDER semantics and PT_ARM_EXIDX segments.

REQ-ELF-141 (State-driven) While processing EM_AARCH64 objects, the library shall handle PT_AARCH64_MEMTAG_MTE segments.

REQ-ELF-142 (Ubiquitous) The library shall preserve and expose ARM mapping symbols ($a, $t, $d) and AArch64 mapping symbols ($x, $d).

---

5. Non-Functional Requirements

REQ-ELF-200 (Ubiquitous) The library shall be written in C99 with no platform-specific dependencies beyond standard libc.

REQ-ELF-201 (Ubiquitous) The library shall be safe to use in multi-threaded programs: global state (backend registry) shall be protected by atomic operations.

REQ-ELF-202 (Ubiquitous) The library shall not crash, invoke undefined behavior, or leak memory on any input, including adversarial or malformed ELF files.

REQ-ELF-203 (Ubiquitous) The library shall perform bounds checking on all offsets and sizes read from ELF headers before accessing file data.

REQ-ELF-204 (Ubiquitous) The library shall handle objects with up to 65,536 sections (using SHT_SYMTAB_SHNDX extended indices) and up to 16 million symbols.

REQ-ELF-205 (Ubiquitous) The library shall compile cleanly with -Wall -Wextra -Werror on GCC and Clang.

REQ-ELF-206 (Ubiquitous) The library shall have zero ASAN, UBSAN, or Valgrind findings on the test suite.

REQ-ELF-207 (Ubiquitous) The library shall be buildable as a host tool (NATIVE_BUILD=1) and as a Substrate native library.

---

6. User Stories

US-01: Binutil Reading an Object File

As a binutil developer (nm, readelf, objdump, size), I want to open an ELF file and iterate its symbols, sections, and relocations so that I can display meaningful information to the user.

REQ-US-01-A (Ubiquitous) The library shall provide elf_symbol_count(), elf_symbol_at(), elf_section_count(), elf_section_at(), elf_section_get(), elf_reloc_count(), and elf_reloc_at() accessors for sequential iteration.

REQ-US-01-B (Ubiquitous) The library shall provide elf_symbol_name(), elf_symbol_value(), elf_symbol_size(), elf_symbol_type(), elf_symbol_bind(), elf_symbol_vis(), and elf_symbol_shndx() for per-symbol queries.

REQ-US-01-C (Ubiquitous) The library shall provide elf_section_name(), elf_section_type(), elf_section_flags(), elf_section_addr(), elf_section_size(), elf_section_data(), and elf_section_entsize() for per-section queries.

REQ-US-01-D (Ubiquitous) The library shall provide elf_reloc_offset(), elf_reloc_type(), elf_reloc_addend(), elf_reloc_symbol(), and elf_reloc_section() for per-relocation queries.

US-02: Assembler Producing an Object File

As an assembler developer, I want to create an ELF object from scratch, add sections with machine code, add symbols, and add relocations so that the output is linkable by the Substrate or GNU linker.

REQ-US-02-A (Ubiquitous) The library shall allow setting the entry point via elf_set_entry().

REQ-US-02-B (Ubiquitous) The library shall allow appending raw data to a section after creation.

REQ-US-02-C (Event-driven) When elf_write_file() is called, the library shall finalize layout and produce a valid ELF file in a single call.

REQ-US-02-D (Unwanted behavior) If elf_add_relocation() is called with a symbol from a different object, then the library shall return ELF_ERR_STATE.

US-03: Linker Resolving Relocations

As a linker developer, I want to apply relocations across multiple input objects so that I can produce a final executable or shared library.

REQ-US-03-A (Ubiquitous) The library shall provide elf_apply_relocation() which computes the relocated value using the registered backend for the object's machine type.

REQ-US-03-B (Ubiquitous) The library shall provide relocation hooks (before_apply, after_apply, incremental_note) for linker-specific relaxation and logging.

REQ-US-03-C (Event-driven) When a relocation overflows, the library shall return ELF_ERR_RELOC with the machine type, relocation type, place address, and symbol value in the diagnostic.

REQ-US-03-D (Ubiquitous) The library shall provide elf_link_plan_add_input() to register objects for multi-object linking.

US-04: Strip Tool Removing Debug Info

As a strip developer, I want to selectively copy sections from an input object to an output object, omitting debug and symbol table sections, so that I can produce a smaller binary.

REQ-US-04-A (Ubiquitous) The library shall allow creating an output object that copies selected sections from an input object while preserving section indices and inter-section references.

REQ-US-04-B (Event-driven) When a section referenced by a program header is not copied, the library shall flag the inconsistency via diagnostic.

REQ-US-04-C (Ubiquitous) The library shall preserve program headers and segment structure when copying ET_EXEC/ET_DYN objects.

US-05: readelf Displaying ARM Build Attributes

As a readelf developer, I want to parse and display ARM build attributes so that users can inspect compiler settings, ABI choices, and ISA features of ARM objects.

REQ-US-05-A (Event-driven) When an EM_ARM object contains .ARM.attributes, the library shall expose each parsed tag via indexed accessors.

REQ-US-05-B (Ubiquitous) The library shall distinguish between integer-valued and string-valued attribute tags.

REQ-US-05-C (Ubiquitous) The library shall expose the vendor name (e.g., "aeabi") for each attribute subsection.

US-06: Linker Merging GNU Properties

As a linker developer, I want to merge .note.gnu.property notes across multiple inputs using the correct merge rules (OR for ISA levels, AND for feature flags) so that the output correctly reflects the combined requirements.

REQ-US-06-A (Ubiquitous) The library shall provide elf_x86_isa_level() and elf_aarch64_feature_flags() to read properties from input objects.

REQ-US-06-B (Ubiquitous) The library shall provide elf_add_gnu_property_x86() and elf_add_gnu_property_aarch64() to write merged properties to the output object.

REQ-US-06-C (Event-driven) When an input object has no .note.gnu.property, the library shall return 0 from the property query functions rather than failing.

US-07: addr2line Resolving Debug Information

As an addr2line developer, I want to look up source file and line number for a given program address so that users can map crash addresses to source code.

REQ-US-07-A (Ubiquitous) The library shall provide elf_dwarf_line_find(obj, address, &file, &line, &column) that searches the .debug_line program.

REQ-US-07-B (Event-driven) When the address is not covered by any compilation unit, the library shall return ELF_ERR_NOT_FOUND.

REQ-US-07-C (Ubiquitous) The library shall handle DWARF versions 2, 3, 4, and 5 .debug_line formats.

US-08: Fuzz Testing the Library

As an elfobj developer, I want the library to be crash-free on arbitrary input so that binutils using it are safe against malicious ELF files.

REQ-US-08-A (Ubiquitous) The library shall validate all header fields before using them as offsets or sizes.

REQ-US-08-B (Ubiquitous) The library shall use checked arithmetic for offset + size calculations to prevent integer overflow.

REQ-US-08-C (Ubiquitous) The library shall return error codes (never abort/assert) for all recoverable error conditions.

REQ-US-08-D (Ubiquitous) The library shall provide a fuzz harness entry point that accepts a raw byte buffer and exercises the full read path.

---

7. Error Model

Error Code	Meaning
ELF_OK	Success
ELF_ERR_IO	File I/O failure
ELF_ERR_FORMAT	Invalid ELF structure (bad magic, truncated, corrupt)
ELF_ERR_OOM	Memory allocation failure
ELF_ERR_STATE	API misuse (mutation of finalized object, cross-object ref)
ELF_ERR_UNSUPPORTED	Unsupported machine type, relocation type, or feature
ELF_ERR_RELOC	Relocation overflow or application error
ELF_ERR_NOT_FOUND	Requested item (symbol, address, property) not found

REQ-ELF-300 (Ubiquitous) Every public API function shall return elf_err_t or a pointer (NULL on error), and set a diagnostic string retrievable via elf_last_error().

---

8. Traceability Matrix

Requirement	User Story	Tasklist Section
REQ-ELF-010–019	US-01	§5 (Read)
REQ-ELF-020–027	US-02	§7 (Create)
REQ-ELF-030–035	US-02, US-04	§6 (Write)
REQ-ELF-040–049	US-03	§2, §3, §12
REQ-ELF-050–053	US-03	§12a (i386)
REQ-ELF-060–063	US-03	§12b (x86-64)
REQ-ELF-070–076	US-03	§2 (ARM)
REQ-ELF-080–085	US-03	§3 (AArch64)
REQ-ELF-090–097	US-01, US-08	§4, §13 (Validate)
REQ-ELF-100–103	US-05	§10 (Build Attr)
REQ-ELF-110–115	US-06	§14 (GNU Prop)
REQ-ELF-120–122	US-07	§8 (DWARF)
REQ-ELF-130–133	US-03	§9 (Link)
REQ-ELF-140–142	US-01, US-05	§1f–1h, §5
REQ-ELF-150–157	US-03	MIPS backend
REQ-ELF-160–166	US-03	RISC-V backend
REQ-ELF-170–175	US-03	LoongArch backend
REQ-ELF-180–184	US-03	M68K backend
REQ-ELF-190–193	US-03	VAX backend
REQ-ELF-200–206	US-03	PowerPC backend
REQ-ELF-210–215	US-03	Alpha backend
REQ-ELF-220–227	US-03	IA-64 backend
REQ-ELF-300	US-08	(Error model)

---

9. Acceptance Criteria

1. libelfobj.a builds cleanly on host Linux and Substrate target.
2. All twelve architecture backends pass encoding unit tests for every relocation type.
3. Read→write round-trip produces byte-identical output for i386, x86-64, ARM, AArch64, MIPS, RISC-V, LoongArch, M68K, VAX, Alpha, PowerPC, and IA-64 test objects.
4. readelf -a structural validation passes on all library-generated objects.
5. Objects produced by Substrate as via libelfobj are linkable by GNU ld and Substrate ld.
6. ARM build attributes from GCC-produced objects are parsed and all standard tags decoded.
7. GNU property ISA level and feature flags are correctly read, merged, and written.
8. Validation rejects class/endian mismatches per architecture (all 12).
9. MIPS .MIPS.abiflags and RISC-V .riscv.attributes parsed and validated correctly.
10. 24-hour fuzz run produces zero crashes (0 ASAN/UBSAN findings) across all architectures.
11. nm, readelf, strip, size, objdump, objcopy, ar, addr2line all use libelfobj exclusively (no BFD, no libelf).

TASKLIST_ELFOBJ.md

usr.lib/elfobj — Multi-Architecture Tasklist

Goal: extend libelfobj with complete multi-architecture support for i386, x86-64, ARMv7 (ELF32, EM_ARM), AArch64 (ELF64, EM_AARCH64), MIPS/MIPS64 (EM_MIPS), RISC-V 32/64/128 (EM_RISCV), LoongArch 32/64 (EM_LOONGARCH), M68K (EM_68K), VAX (EM_VAX), Alpha (EM_ALPHA), PowerPC/PowerPC64 (EM_PPC/EM_PPC64), and IA-64 (EM_IA_64) across all library subsystems — constants, relocation backends, validation, ELF creation, DWARF, link planning, and testing.

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0. Generic Tooling API Support

• Add indexed section accessor elf_section_get(const elfobj_t *, size_t) for consumer utilities (size, objdump, readelf) that need stable section iteration.
• Add section address accessor elf_section_addr(const elf_section_t *) for utilities that emit per-section address tables (for example SysV size -A).

---

1. ELF Constants and Header Definitions

1a. Machine Types (elf_private.h or upstream elf.h)

• Define EM_ARM (40).
• Define EM_AARCH64 (183).

1b. ARM-Specific ELF Header Flags (e_flags)

• EF_ARM_ABI_VER5 (0x05000000) — EABI version 5.
• EF_ARM_ABI_FLOAT_HARD (0x00000400) — hard-float ABI.
• EF_ARM_ABI_FLOAT_SOFT (0x00000200) — soft-float ABI.
• EF_ARM_BE8 (0x00800000) — BE8 data format.
• EF_ARM_INTERWORK (0x00000004) — ARM/Thumb interwork support.
• EF_ARM_APCS_26 (0x00000008).
• EF_ARM_APCS_FLOAT (0x00000010).
• EF_ARM_VFP_FLOAT (0x00000400).
• EF_ARM_MAVERICK_FLOAT (0x00000800).
• Parse and expose e_flags for ARM objects via elf_flags() accessor.
• Validate e_flags ABI version field on read.

1c. AArch64-Specific ELF Header Flags

• EF_AARCH64_CHERI_PURECAP (reserved).
• AArch64 has no mandatory e_flags bits; validate that flags is 0 or recognized optional.

1d. ARM Relocation Type Constants

Every relocation type used by GCC/LLVM for ARM targets must be defined:

• R_ARM_NONE (0)
• R_ARM_PC24 (1)
• R_ARM_ABS32 (2)
• R_ARM_REL32 (3)
• R_ARM_LDR_PC_G0 (4)
• R_ARM_ABS16 (5)
• R_ARM_ABS12 (6)
• R_ARM_THM_ABS5 (7)
• R_ARM_ABS8 (8)
• R_ARM_SBREL32 (9)
• R_ARM_THM_CALL (10)
• R_ARM_THM_PC8 (11)
• R_ARM_BREL_ADJ (12)
• R_ARM_TLS_DESC (13)
• R_ARM_THM_SWI8 (14)
• R_ARM_XPC25 (15)
• R_ARM_THM_XPC22 (16)
• R_ARM_TLS_DTPMOD32 (17)
• R_ARM_TLS_DTPOFF32 (18)
• R_ARM_TLS_TPOFF32 (19)
• R_ARM_COPY (20)
• R_ARM_GLOB_DAT (21)
• R_ARM_JUMP_SLOT (22)
• R_ARM_RELATIVE (23)
• R_ARM_GOTOFF32 (24)
• R_ARM_BASE_PREL (25) / R_ARM_GOTPC
• R_ARM_GOT_BREL (26) / R_ARM_GOT32
• R_ARM_PLT32 (27)
• R_ARM_CALL (28)
• R_ARM_JUMP24 (29)
• R_ARM_THM_JUMP24 (30)
• R_ARM_BASE_ABS (31)
• R_ARM_ALU_PCREL_7_0 (32)
• R_ARM_ALU_PCREL_15_8 (33)
• R_ARM_ALU_PCREL_23_16 (34)
• R_ARM_LDR_SBREL_11_0_NC (35)
• R_ARM_ALU_SBREL_19_12_NC (36)
• R_ARM_ALU_SBREL_27_20_CK (37)
• R_ARM_TARGET1 (38)
• R_ARM_SBREL31 (39)
• R_ARM_V4BX (40)
• R_ARM_TARGET2 (41)
• R_ARM_PREL31 (42)
• R_ARM_MOVW_ABS_NC (43)
• R_ARM_MOVT_ABS (44)
• R_ARM_MOVW_PREL_NC (45)
• R_ARM_MOVT_PREL (46)
• R_ARM_THM_MOVW_ABS_NC (47)
• R_ARM_THM_MOVT_ABS (48)
• R_ARM_THM_MOVW_PREL_NC (49)
• R_ARM_THM_MOVT_PREL (50)
• R_ARM_THM_JUMP19 (51)
• R_ARM_THM_JUMP6 (52)
• R_ARM_THM_ALU_PREL_11_0 (53)
• R_ARM_THM_PC12 (54)
• R_ARM_ABS32_NOI (55)
• R_ARM_REL32_NOI (56)
• R_ARM_ALU_PC_G0_NC (57)
• R_ARM_ALU_PC_G0 (58)
• R_ARM_ALU_PC_G1_NC (59)
• R_ARM_ALU_PC_G1 (60)
• R_ARM_ALU_PC_G2 (61)
• R_ARM_LDR_PC_G1 (62)
• R_ARM_LDR_PC_G2 (63)
• R_ARM_LDRS_PC_G0 (64)
• R_ARM_LDRS_PC_G1 (65)
• R_ARM_LDRS_PC_G2 (66)
• R_ARM_LDC_PC_G0 (67)
• R_ARM_LDC_PC_G1 (68)
• R_ARM_LDC_PC_G2 (69)
• R_ARM_ALU_SB_G0_NC (70)
• R_ARM_ALU_SB_G0 (71)
• R_ARM_ALU_SB_G1_NC (72)
• R_ARM_ALU_SB_G1 (73)
• R_ARM_ALU_SB_G2 (74)
• R_ARM_LDR_SB_G0 (75)
• R_ARM_LDR_SB_G1 (76)
• R_ARM_LDR_SB_G2 (77)
• R_ARM_LDRS_SB_G0 (78)
• R_ARM_LDRS_SB_G1 (79)
• R_ARM_LDRS_SB_G2 (80)
• R_ARM_LDC_SB_G0 (81)
• R_ARM_LDC_SB_G1 (82)
• R_ARM_LDC_SB_G2 (83)
• R_ARM_MOVW_BREL_NC (84)
• R_ARM_MOVT_BREL (85)
• R_ARM_MOVW_BREL (86)
• R_ARM_THM_MOVW_BREL_NC (87)
• R_ARM_THM_MOVT_BREL (88)
• R_ARM_THM_MOVW_BREL (89)
• R_ARM_TLS_GOTDESC (90)
• R_ARM_TLS_CALL (91)
• R_ARM_TLS_DESCSEQ (92)
• R_ARM_THM_TLS_CALL (93)
• R_ARM_PLT32_ABS (94)
• R_ARM_GOT_ABS (95)
• R_ARM_GOT_PREL (96)
• R_ARM_GOT_BREL12 (97)
• R_ARM_GOTOFF12 (98)
• R_ARM_GOTRELAX (99)
• R_ARM_GNU_VTENTRY (100)
• R_ARM_GNU_VTINHERIT (101)
• R_ARM_THM_JUMP11 (102)
• R_ARM_THM_JUMP8 (103)
• R_ARM_TLS_GD32 (104)
• R_ARM_TLS_LDM32 (105)
• R_ARM_TLS_LDO32 (106)
• R_ARM_TLS_IE32 (107)
• R_ARM_TLS_LE32 (108)
• R_ARM_TLS_LDO12 (109)
• R_ARM_TLS_LE12 (110)
• R_ARM_TLS_IE12GP (111)
• R_ARM_IRELATIVE (160)
• R_ARM_RXPC25 (249)
• R_ARM_RSBREL32 (250)
• R_ARM_THM_RPC22 (251)
• R_ARM_RREL32 (252)
• R_ARM_RABS32 (253)
• R_ARM_RPC24 (254)
• R_ARM_RBASE (255)

1e. AArch64 Relocation Type Constants

• R_AARCH64_NONE (0)
• R_AARCH64_ABS64 (257), R_AARCH64_ABS32 (258), R_AARCH64_ABS16 (259)
• R_AARCH64_PREL64 (260), R_AARCH64_PREL32 (261), R_AARCH64_PREL16 (262)
• R_AARCH64_MOVW_UABS_G0 (263), _G0_NC (264), _G1 (265), _G1_NC (266), _G2 (267), _G2_NC (268), _G3 (269)
• R_AARCH64_MOVW_SABS_G0 (270), _G1 (271), _G2 (272)
• R_AARCH64_LD_PREL_LO19 (273), R_AARCH64_ADR_PREL_LO21 (274)
• R_AARCH64_ADR_PREL_PG_HI21 (275), _NC (276)
• R_AARCH64_ADD_ABS_LO12_NC (277)
• R_AARCH64_LDST8_ABS_LO12_NC (278)
• R_AARCH64_TSTBR14 (279), R_AARCH64_CONDBR19 (280)
• R_AARCH64_JUMP26 (282), R_AARCH64_CALL26 (283)
• R_AARCH64_LDST16_ABS_LO12_NC (284), R_AARCH64_LDST32_ABS_LO12_NC (285), R_AARCH64_LDST64_ABS_LO12_NC (286), R_AARCH64_LDST128_ABS_LO12_NC (299)
• R_AARCH64_MOVW_PREL_G0 (287), _G0_NC (288), _G1 (289), _G1_NC (290), _G2 (291), _G2_NC (292), _G3 (293)
• R_AARCH64_GOT_LD_PREL19 (309), R_AARCH64_ADR_GOT_PAGE (311), R_AARCH64_LD64_GOT_LO12_NC (312)
• R_AARCH64_LD64_GOTPAGE_LO15 (313)
• R_AARCH64_TLSGD_ADR_PREL21 (512), R_AARCH64_TLSGD_ADR_PAGE21 (513), R_AARCH64_TLSGD_ADD_LO12_NC (514), R_AARCH64_TLSGD_MOVW_G1 (515), R_AARCH64_TLSGD_MOVW_G0_NC (516)
• R_AARCH64_TLSLD_ADR_PREL21 (517), R_AARCH64_TLSLD_ADR_PAGE21 (518), R_AARCH64_TLSLD_ADD_LO12_NC (519), R_AARCH64_TLSLD_ADD_DTPREL_HI12 (528), R_AARCH64_TLSLD_ADD_DTPREL_LO12 (529), _NC (530)
• R_AARCH64_TLSLD_LDST8_DTPREL_LO12 (531), _NC (532)
• R_AARCH64_TLSLD_LDST16/32/64/128_DTPREL_LO12{_NC} (533–540)
• R_AARCH64_TLSLD_MOVW_DTPREL_G0{_NC} (520,521), _G1{_NC} (522,523), _G2 (524)
• R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 (539), _G0_NC (540)
• R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 (541), R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC (542), R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 (543)
• R_AARCH64_TLSLE_MOVW_TPREL_G2 (544), _G1{_NC} (545,546), _G0{_NC} (547,548)
• R_AARCH64_TLSLE_ADD_TPREL_HI12 (549), R_AARCH64_TLSLE_ADD_TPREL_LO12 (550), _NC (551)
• R_AARCH64_TLSLE_LDST8/16/32/64/128_TPREL_LO12{_NC} (552–561)
• R_AARCH64_TLSDESC_LD_PREL19 (560), R_AARCH64_TLSDESC_ADR_PREL21 (561), R_AARCH64_TLSDESC_ADR_PAGE21 (562), R_AARCH64_TLSDESC_LD64_LO12 (563), R_AARCH64_TLSDESC_ADD_LO12 (564), R_AARCH64_TLSDESC_OFF_G1 (565), R_AARCH64_TLSDESC_OFF_G0_NC (566), R_AARCH64_TLSDESC_LDR (567), R_AARCH64_TLSDESC_ADD (568), R_AARCH64_TLSDESC_CALL (569), R_AARCH64_TLSDESC (1031)
• Dynamic relocations: R_AARCH64_COPY (1024), R_AARCH64_GLOB_DAT (1025), R_AARCH64_JUMP_SLOT (1026), R_AARCH64_RELATIVE (1027), R_AARCH64_TLS_DTPMOD64 (1028), R_AARCH64_TLS_DTPREL64 (1029), R_AARCH64_TLS_TPREL64 (1030), R_AARCH64_IRELATIVE (1032)

1f. ARM Section Types and Flags

• SHT_ARM_EXIDX (0x70000001) — exception index table.
• SHT_ARM_PREEMPTMAP (0x70000002).
• SHT_ARM_ATTRIBUTES (0x70000003) — build attributes.
• SHF_ARM_PURECODE (0x20000000) — execute-only section.
• PT_ARM_EXIDX (0x70000001) — exception unwind segment.

1g. AArch64 Section Types

• SHT_AARCH64_ATTRIBUTES (0x70000003).
• PT_AARCH64_MEMTAG_MTE (0x70000002).

1h. ARM Special Section Names

• .ARM.exidx — exception index table.
• .ARM.extab — exception table data.
• .ARM.attributes — build attributes.
• .note.gnu.property — BTI/PAC properties (AArch64).

1i. Expanded x86 Relocation Type Constants

Beyond the currently-implemented core set, add the full x86 relocation roster:

i386 Missing Relocations

• R_386_NONE (0)
• R_386_COPY (5), R_386_GLOB_DAT (6), R_386_JMP_SLOT (7), R_386_RELATIVE (8)
• R_386_16 (20), R_386_PC16 (21), R_386_8 (22), R_386_PC8 (23)
• R_386_TLS_DTPMOD32 (35), R_386_TLS_DTPOFF32 (36)
• R_386_TLS_LE_32 (33), R_386_TLS_TPOFF32 (37)
• R_386_SIZE32 (38)
• R_386_GOT32X (43)
• R_386_IRELATIVE (42)

x86-64 Missing Relocations

• R_X86_64_COPY (5), R_X86_64_GLOB_DAT (6), R_X86_64_JUMP_SLOT (7), R_X86_64_RELATIVE (8)
• R_X86_64_16 (12), R_X86_64_PC16 (13), R_X86_64_8 (14), R_X86_64_PC8 (15)
• R_X86_64_DTPMOD64 (16), R_X86_64_DTPOFF64 (17), R_X86_64_TPOFF64 (18)
• R_X86_64_TLSLD (20), R_X86_64_DTPOFF32 (21)
• R_X86_64_PC64 (24), R_X86_64_GOTOFF64 (25), R_X86_64_GOTPC32 (26)
• R_X86_64_SIZE32 (32), R_X86_64_SIZE64 (33)
• R_X86_64_GOTPCRELX (41), R_X86_64_REX_GOTPCRELX (42)
• R_X86_64_IRELATIVE (37)
• R_X86_64_GOTPC32_TLSDESC (34), R_X86_64_TLSDESC_CALL (35), R_X86_64_TLSDESC (36)

1j. x86 GNU Property Constants

• GNU_PROPERTY_X86_ISA_1_NEEDED (0xc0008002)
• GNU_PROPERTY_X86_ISA_1_USED (0xc0010002)
• ISA level bits: GNU_PROPERTY_X86_ISA_1_BASELINE (1), _V2 (2), _V3 (4), _V4 (8)
• GNU_PROPERTY_X86_FEATURE_1_AND (0xc0000002)
• Feature bits: GNU_PROPERTY_X86_FEATURE_1_IBT (1), _SHSTK (2)
• GNU_PROPERTY_AARCH64_FEATURE_1_AND (0xc0000000)
• AArch64 feature bits: _BTI (1), _PAC (2)

---

2. ARMv7 Relocation Backend (elf_reloc.c)

2a. arm_reloc_size() — Size of Each Relocation Result

• R_ARM_NONE → 0
• R_ARM_ABS32, R_ARM_REL32, R_ARM_GOTOFF32, R_ARM_GOTPC, R_ARM_GOT_BREL, R_ARM_PLT32, R_ARM_CALL, R_ARM_JUMP24, R_ARM_TARGET1, R_ARM_TARGET2, R_ARM_PREL31, R_ARM_MOVW_ABS_NC, R_ARM_MOVT_ABS, R_ARM_MOVW_PREL_NC, R_ARM_MOVT_PREL, R_ARM_ABS32_NOI, R_ARM_REL32_NOI → 4
• R_ARM_PC24 → 4 (24-bit field in 32-bit instruction)
• R_ARM_ABS16 → 2
• R_ARM_ABS12 → 4 (12-bit field in 32-bit instruction)
• R_ARM_ABS8 → 1
• R_ARM_THM_CALL, R_ARM_THM_JUMP24 → 4 (two 16-bit Thumb instructions)
• R_ARM_THM_JUMP11 → 2, R_ARM_THM_JUMP8 → 2
• R_ARM_THM_MOVW_ABS_NC, R_ARM_THM_MOVT_ABS, R_ARM_THM_MOVW_PREL_NC, R_ARM_THM_MOVT_PREL → 4
• R_ARM_THM_JUMP19 → 4, R_ARM_THM_JUMP6 → 2
• All TLS relocations (R_ARM_TLS_GD32 through R_ARM_TLS_LE12) → 4
• R_ARM_COPY, R_ARM_GLOB_DAT, R_ARM_JUMP_SLOT, R_ARM_RELATIVE → 4
• R_ARM_IRELATIVE → 4
• R_ARM_V4BX → 4 (instruction rewrite)
• All group relocations (R_ARM_ALU_PC_G*, R_ARM_LDR_PC_G*, R_ARM_LDRS_PC_G*, R_ARM_LDC_PC_G*, SB variants) → 4

2b. arm_is_pc_relative() — Identify PC-Relative Relocations

• PC-relative: R_ARM_PC24, R_ARM_REL32, R_ARM_PLT32, R_ARM_CALL, R_ARM_JUMP24, R_ARM_THM_CALL, R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP11, R_ARM_THM_JUMP8, R_ARM_PREL31, R_ARM_MOVW_PREL_NC, R_ARM_MOVT_PREL, R_ARM_THM_MOVW_PREL_NC, R_ARM_THM_MOVT_PREL, R_ARM_GOTPC, R_ARM_BASE_PREL, R_ARM_GOT_PREL, R_ARM_REL32_NOI, all ALU_PC_G*/LDR_PC_G*/LDRS_PC_G*/LDC_PC_G*
• Absolute: R_ARM_ABS32, R_ARM_ABS16, R_ARM_ABS12, R_ARM_ABS8, R_ARM_MOVW_ABS_NC, R_ARM_MOVT_ABS, R_ARM_THM_MOVW_ABS_NC, R_ARM_THM_MOVT_ABS, R_ARM_ABS32_NOI, R_ARM_GOTOFF32, R_ARM_GOT_BREL

2c. arm_is_tls() — Identify TLS Relocations

• TLS: R_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPOFF32, R_ARM_TLS_TPOFF32, R_ARM_TLS_GD32, R_ARM_TLS_LDM32, R_ARM_TLS_LDO32, R_ARM_TLS_IE32, R_ARM_TLS_LE32, R_ARM_TLS_LDO12, R_ARM_TLS_LE12, R_ARM_TLS_IE12GP, R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL, R_ARM_TLS_DESCSEQ, R_ARM_THM_TLS_CALL

2d. arm_apply() — Relocation Application

• R_ARM_NONE → no-op
• R_ARM_ABS32 → S + A
• R_ARM_REL32 → S + A − P (signed 32-bit)
• R_ARM_PC24 → extract bits[23:0], compute ((S + A) | T) − P, check ±32MB range, reinsert with instruction mask
• R_ARM_CALL → ((S + A) | T) − P, range ±32MB, encode in bits[23:0]
• R_ARM_JUMP24 → ((S + A) | T) − P, range ±32MB, encode in bits[23:0]
• R_ARM_PLT32 → ((S + A) | T) − P
• R_ARM_GOTOFF32 → ((S + A) | T) − GOT_ORG
• R_ARM_GOTPC / R_ARM_BASE_PREL → GOT_ORG + A − P
• R_ARM_GOT_BREL → GOT(S) + A − GOT_ORG
• R_ARM_PREL31 → (S + A − P) masked to 31 bits, preserve bit[31]
• R_ARM_MOVW_ABS_NC → extract imm16 from instruction (bits[19:16]+bits[11:0]), compute (S + A) & 0xFFFF, reinsert; no overflow check
• R_ARM_MOVT_ABS → ((S + A) >> 16) & 0xFFFF into imm16 field
• R_ARM_MOVW_PREL_NC → ((S + A) | T) − P, low 16 bits
• R_ARM_MOVT_PREL → (((S + A) | T) − P) >> 16, high 16 bits
• R_ARM_THM_CALL → decode Thumb BL/BLX pair, compute ((S + A) | T) − P, range ±16MB (BL) / ±16MB even (BLX), re-encode J1/J2/imm10/imm11
• R_ARM_THM_JUMP24 → like THM_CALL but unconditional
• R_ARM_THM_JUMP19 → Thumb B.cond, 20-bit signed offset
• R_ARM_THM_JUMP11 → Thumb B, 11-bit unsigned offset
• R_ARM_THM_JUMP8 → Thumb B.cond, 8-bit signed offset
• R_ARM_THM_MOVW_ABS_NC → extract Thumb MOVW imm16 (imm4:i:imm3:imm8), compute, reinsert
• R_ARM_THM_MOVT_ABS → extract Thumb MOVT imm16, compute, reinsert
• R_ARM_THM_MOVW_PREL_NC → PC-relative low 16 bits into Thumb MOVW
• R_ARM_THM_MOVT_PREL → PC-relative high 16 bits into Thumb MOVT
• R_ARM_V4BX → rewrite BX Rm to MOV PC, Rm for ARMv4 compat
• R_ARM_TARGET1 → platform-defined, typically R_ARM_ABS32 or R_ARM_REL32
• R_ARM_TARGET2 → platform-defined, typically R_ARM_GOT_PREL
• R_ARM_ABS16 → S + A, check ±32K range or 0–64K unsigned
• R_ARM_ABS12 → (S + A) encoded in LDR immediate field, 12-bit unsigned
• R_ARM_ABS8 → S + A, check 0–255
• R_ARM_SBREL32 → S + A − B(S) (static base relative)
• Group relocations (ALU_PC/SB, LDR_PC/SB, LDRS_PC/SB, LDC_PC/SB with G0/G1/G2): extract instruction-format-specific field width, apply group masking per ARM EABI §4.6.1.4
• All TLS relocations: S + A (raw value passthrough for linker to fixup GOT/TP offsets)
• Dynamic: R_ARM_COPY, R_ARM_GLOB_DAT, R_ARM_JUMP_SLOT, R_ARM_RELATIVE, R_ARM_IRELATIVE — produce raw S + A or B(S) + A

2e. ARM Thumb Interwork Bit (T)

• Detect if target symbol is Thumb (STT_FUNC with st_value bit 0 set or $t mapping symbol).
• Set T=1 for Thumb targets in branch relocations.

2f. ARM Relocation Backend Registration

• Register arm_apply, arm_reloc_size, arm_is_pc_relative under EM_ARM in register_builtin_backends_locked().
• Add arm_is_tls to elf_reloc_is_tls_for_machine().

---

3. AArch64 Relocation Backend (elf_reloc.c)

3a. aarch64_reloc_size()

• R_AARCH64_NONE → 0
• R_AARCH64_ABS64, R_AARCH64_PREL64 → 8
• R_AARCH64_ABS32, R_AARCH64_PREL32 → 4
• R_AARCH64_ABS16, R_AARCH64_PREL16 → 2
• All instruction-embedded relocations (ADR_PREL_*, ADD_ABS_*, LDST*, MOVW_*, JUMP26, CALL26, CONDBR19, TSTBR14) → 4 (instruction width)
• All GOT/TLS instruction-embedded → 4
• Dynamic (COPY, GLOB_DAT, JUMP_SLOT, RELATIVE, IRELATIVE, TLS_DTPMOD64, TLS_DTPREL64, TLS_TPREL64, TLSDESC) → 8

3b. aarch64_is_pc_relative()

• PC-relative: R_AARCH64_PREL64, R_AARCH64_PREL32, R_AARCH64_PREL16, R_AARCH64_ADR_PREL_LO21, R_AARCH64_ADR_PREL_PG_HI21{_NC}, R_AARCH64_JUMP26, R_AARCH64_CALL26, R_AARCH64_CONDBR19, R_AARCH64_TSTBR14, R_AARCH64_LD_PREL_LO19, R_AARCH64_GOT_LD_PREL19, R_AARCH64_ADR_GOT_PAGE, R_AARCH64_MOVW_PREL_G*, all TLSGD_ADR_PREL21, TLSLD_ADR_PREL21, TLSIE_LD_GOTTPREL_PREL19, TLSDESC_LD_PREL19, TLSDESC_ADR_PREL21
• Absolute: R_AARCH64_ABS64/32/16, R_AARCH64_ADD_ABS_LO12_NC, R_AARCH64_LDST*_ABS_LO12_NC, R_AARCH64_MOVW_UABS_G*, R_AARCH64_MOVW_SABS_G*

3c. aarch64_is_tls()

• All TLSGD_*, TLSLD_*, TLSIE_*, TLSLE_*, TLSDESC_*, TLS_DTPMOD64, TLS_DTPREL64, TLS_TPREL64

3d. aarch64_apply() — Relocation Application

• R_AARCH64_ABS64 → S + A (64-bit)
• R_AARCH64_ABS32 → S + A, check unsigned 32-bit or signed 32-bit
• R_AARCH64_ABS16 → S + A, check ±32K
• R_AARCH64_PREL64 → S + A − P
• R_AARCH64_PREL32 → S + A − P, check signed 32-bit
• R_AARCH64_PREL16 → S + A − P, check signed 16-bit
• R_AARCH64_ADR_PREL_LO21 → extract ADR immediate (imm:immlo), compute S + A − P, check ±1MB, re-encode bits[23:5]+bits[30:29]
• R_AARCH64_ADR_PREL_PG_HI21 → Page(S + A) − Page(P), check ±4GB, encode as ADRP immediate (immhi:immlo)
• R_AARCH64_ADR_PREL_PG_HI21_NC → same without overflow check
• R_AARCH64_ADD_ABS_LO12_NC → (S + A) & 0xFFF, encode in ADD imm12 field (bits[21:10])
• R_AARCH64_LDST8_ABS_LO12_NC → (S + A) & 0xFFF, encode in LDR/STR imm12 (no shift)
• R_AARCH64_LDST16_ABS_LO12_NC → ((S + A) & 0xFFF) >> 1, check alignment
• R_AARCH64_LDST32_ABS_LO12_NC → ((S + A) & 0xFFF) >> 2, check alignment
• R_AARCH64_LDST64_ABS_LO12_NC → ((S + A) & 0xFFF) >> 3, check alignment
• R_AARCH64_LDST128_ABS_LO12_NC → ((S + A) & 0xFFF) >> 4, check alignment
• R_AARCH64_MOVW_UABS_G0 → (S + A) & 0xFFFF, encode in MOVZ/MOVK imm16 (bits[20:5])
• R_AARCH64_MOVW_UABS_G0_NC → same, no overflow check
• R_AARCH64_MOVW_UABS_G1 → ((S + A) >> 16) & 0xFFFF; G2 → >>32; G3 → >>48
• R_AARCH64_MOVW_SABS_G0 → signed version, may flip MOVZ↔MOVN
• R_AARCH64_JUMP26 → (S + A − P) >> 2, check ±128MB, encode in bits[25:0]
• R_AARCH64_CALL26 → same as JUMP26
• R_AARCH64_CONDBR19 → (S + A − P) >> 2, check ±1MB, encode in bits[23:5]
• R_AARCH64_TSTBR14 → (S + A − P) >> 2, check ±32KB, encode in bits[18:5]
• R_AARCH64_LD_PREL_LO19 → (S + A − P) >> 2, check ±1MB, encode in bits[23:5]
• GOT relocations: compute GOT slot address, output GOT(S) + A or Page(GOT(S)) − Page(P)
• TLS relocations: S + A passthrough (linker resolves GOT/TP offsets)
• Dynamic: R_AARCH64_COPY/GLOB_DAT/JUMP_SLOT/RELATIVE/IRELATIVE → S + A or B(S) + A

3e. AArch64 Instruction Field Helpers

• aarch64_extract_imm26(uint32_t insn) — bits[25:0] for B/BL
• aarch64_insert_imm26(uint32_t insn, int32_t value) — encode into bits[25:0]
• aarch64_extract_imm19(uint32_t insn) — bits[23:5] for B.cond/CBZ/LDR literal
• aarch64_insert_imm19(uint32_t insn, int32_t value)
• aarch64_extract_imm14(uint32_t insn) — bits[18:5] for TBZ
• aarch64_insert_imm14(uint32_t insn, int32_t value)
• aarch64_extract_adr_imm(uint32_t insn) — immhi(bits[23:5]):immlo(bits[30:29]) for ADR/ADRP
• aarch64_insert_adr_imm(uint32_t insn, int32_t value)
• aarch64_extract_imm12(uint32_t insn) — bits[21:10] for ADD/LDR
• aarch64_insert_imm12(uint32_t insn, uint32_t value)
• aarch64_extract_movw_imm16(uint32_t insn) — bits[20:5]
• aarch64_insert_movw_imm16(uint32_t insn, uint16_t value)
• aarch64_page(uint64_t addr) → addr & ~0xFFF

3f. AArch64 Relocation Backend Registration

• Register aarch64_apply, aarch64_reloc_size, aarch64_is_pc_relative under EM_AARCH64.
• Add aarch64_is_tls to elf_reloc_is_tls_for_machine().

---

4. Validation (elf_validate.c)

4a. ARM Validation Rules

• Accept EM_ARM with ELFCLASS32 only.
• Accept both ELFDATA2LSB (little-endian, common) and ELFDATA2MSB (big-endian).
• Validate e_flags EABI version (≥ EF_ARM_ABI_VER5 for modern toolchains).
• Validate float ABI flags consistency (HARD/SOFT not both set).
• Validate SHT_ARM_EXIDX sections have SHF_LINK_ORDER flag.
• Validate .ARM.attributes section if present.
• Validate alignment constraints for ARM instructions (4 for ARM, 2 for Thumb).
• Validate PT_ARM_EXIDX segment if present points to SHT_ARM_EXIDX section.
• Validate mapping symbols ($a, $t, $d) are present in code sections.

4b. AArch64 Validation Rules

• Accept EM_AARCH64 with ELFCLASS64 only.
• Accept both ELFDATA2LSB and ELFDATA2MSB.
• Validate e_flags is 0 or recognized optional flags only.
• Validate instruction alignment: all code sections 4-byte aligned.
• Validate .note.gnu.property for BTI (GNU_PROPERTY_AARCH64_FEATURE_1_BTI) and PAC (GNU_PROPERTY_AARCH64_FEATURE_1_PAC) if present.
• Validate ADRP+ADD/LDR pairs have consistent page references.
• Check for unrecognized relocation types.
• Validate mapping symbols ($x, $d) in code sections.

---

5. ELF Read (elf_read.c)

• Recognize EM_ARM and EM_AARCH64 as valid machine types.
• ARM: parse REL relocations (no addend in struct; addend encoded in instruction).
• AArch64: parse RELA relocations (explicit addend).
• Parse SHT_ARM_EXIDX sections with proper sh_link interpretation.
• Parse SHT_ARM_ATTRIBUTES / SHT_AARCH64_ATTRIBUTES build attribute sections.
• Handle ARM SHF_ARM_PURECODE flag in section flags.
• Read PT_ARM_EXIDX and PT_AARCH64_MEMTAG_MTE segment types.
• Endian-aware reads: ARM objects can be big-endian (BE32 or BE8).

---

6. ELF Write (elf_write.c)

• Write ELF32 (EM_ARM) with REL relocations.
• Write ELF64 (EM_AARCH64) with RELA relocations.
• Write correct e_flags for ARM: EABI version, float ABI, interwork.
• Write SHT_ARM_EXIDX and SHT_ARM_ATTRIBUTES sections.
• Write PT_ARM_EXIDX segment.
• Write .note.gnu.property with BTI/PAC flags for AArch64.
• Endian-correct output for big-endian ARM.
• Correct e_entry with Thumb bit for ARM entry points.

---

7. ELF Creation (elf_util.c)

• elf_init_arm() convenience: set up ELF32/EM_ARM/ELFDATA2LSB with EABI v5 flags, default .text/.data/.bss sections.
• elf_init_aarch64() convenience: set up ELF64/EM_AARCH64/ELFDATA2LSB with empty flags.
• elf_set_flags() / elf_flags() for manipulating e_flags.
• elf_add_arm_exidx() helper for creating .ARM.exidx + .ARM.extab section pairs.
• elf_add_arm_attributes() helper for adding build attributes.
• elf_add_gnu_property_aarch64() helper for BTI/PAC feature bits.

---

8. DWARF Support (elf_dwarf.c)

• ARM DWARF register mapping: R0–R15 → 0–15, VFP D0–D31 → 256–287.
• AArch64 DWARF register mapping: X0–X30 → 0–30, SP → 31, V0–V31 → 64–95.
• ARM CFA rules: typical frame pointer is R11 (FP) or R13 (SP).
• AArch64 CFA rules: frame pointer is X29, link register is X30.
• Handle .debug_frame vs .eh_frame CIE augmentation differences per arch.
• Parse ARM-specific DWARF extensions (if any vendor extensions present).

---

9. Link Planning (elf_link.c)

• Accept EM_ARM and EM_AARCH64 inputs.
• Reject class mismatches: ARM must be ELFCLASS32, AArch64 must be ELFCLASS64.
• Merge e_flags: take union of float ABI flags; error on conflict.
• Handle ARM/Thumb interwork symbol merging (symbol with T-bit → different treatment).
• .ARM.exidx section merging: sort entries by covered address range.
• .ARM.attributes merging: attribute compatibility checking per Build Attributes spec.
• Section group/COMDAT handling for ARM is identical to x86.
• AArch64 .note.gnu.property merging: AND of BTI/PAC bits across inputs.

---

10. ARM Build Attributes Parser

Per ARM EABI §2.2.3, .ARM.attributes contains vendor-specific attribute tags:

• Parse attribute section format: subsection headers, vendor name, tag-value pairs.
• Tag_CPU_name (4): CPU name string (e.g., "Cortex-A15").
• Tag_CPU_arch (6): architecture version (1=v4, 6=v6, 10=v7, 13=v7E-M, 14=v8).
• Tag_CPU_arch_profile (7): 'A' (Application), 'R' (Real-time), 'M' (Microcontroller).
• Tag_ARM_ISA_use (8): 0=no, 1=yes.
• Tag_THUMB_ISA_use (9): 0=no, 1=Thumb, 2=Thumb-2, 3=Armv8-M.baseline.
• Tag_FP_arch (10): 0=none, 1=VFPv1, 2=VFPv2, 3=VFPv3, 4=VFPv3-D16, 5=VFPv4, 6=VFPv4-D16.
• Tag_WMMX_arch (11): Wireless MMX.
• Tag_Advanced_SIMD_arch (12): 0=none, 1=NEONv1, 2=NEONv1+fused-MAC, 3=ARMv8 NEON.
• Tag_PCS_config (13): calling convention.
• Tag_ABI_PCS_R9_use (14): R9 usage.
• Tag_ABI_PCS_RW_data (15): RW data addressing.
• Tag_ABI_PCS_RO_data (16): RO data addressing.
• Tag_ABI_PCS_GOT_use (17): GOT addressing.
• Tag_ABI_PCS_wchar_t (18): wchar_t size.
• Tag_ABI_FP_rounding (19): rounding mode.
• Tag_ABI_FP_denormal (20): denormal handling.
• Tag_ABI_FP_exceptions (21): exception model.
• Tag_ABI_FP_user_exceptions (22): user-mode FP exceptions.
• Tag_ABI_FP_number_model (23): IEEE 754 conformance.
• Tag_ABI_align_needed (24): alignment requirements.
• Tag_ABI_align_preserved (25): alignment guarantees.
• Tag_ABI_enum_size (26): enum sizing.
• Tag_ABI_HardFP_use (27): hard-float VFP register usage.
• Tag_ABI_VFP_args (28): VFP argument passing convention.
• Tag_ABI_optimization_goals (30): optimization priorities.
• Tag_CPU_unaligned_access (34): unaligned access support.
• Tag_FP_HP_extension (36): half-precision extension.
• Tag_ABI_FP_16bit_format (38): FP16 format (IEEE754/alternative).
• Tag_MPExtension_use (42): multiprocessing extensions.
• Tag_DIV_use (44): integer divide instruction usage.
• Tag_DSP_extension (46): DSP extension usage.
• Tag_Virtualization_use (68): virtualization extensions.
• API: elf_arm_attribute_count(), elf_arm_attribute_tag_at(), elf_arm_attribute_value_at(), elf_arm_attribute_string_at().
• Validation: check compatibility of Tag_CPU_arch + Tag_FP_arch across link inputs.

---

11. Testing

11a. Relocation Backend Unit Tests

• For each ARM relocation type: known input (S, A, P, GOT) → expected output value.
• Overflow: ARM R_ARM_CALL with offset > ±32MB → error.
• Overflow: AArch64 R_AARCH64_JUMP26 with offset > ±128MB → error.
• Overflow: R_AARCH64_ADR_PREL_PG_HI21 with page delta > ±4GB → error.
• Alignment: R_AARCH64_LDST32_ABS_LO12_NC with non-4-byte-aligned → error.
• Thumb interwork: R_ARM_CALL to Thumb target → T bit set correctly.
• AArch64 ADRP+ADD pair: page calculation correct for page-aligned and non-aligned addresses.
• AArch64 MOVW_UABS_G0/G1/G2/G3: correct 16-bit slice extraction.
• ARM MOVW/MOVT: correct instruction field insertion for known bit patterns.
• Thumb BL encoding: J1/J2 bits encode correctly for positive and negative offsets.
• PC-relative classification: every PC-relative reloc returns true, every absolute returns false.
• TLS classification: every TLS reloc returns true, non-TLS returns false.
• All reloc sizes match expected values.

11b. Read/Write Round-Trip Tests

• Read ARM ELF32 object → inspect sections/symbols/relocs → write back → byte-compare.
• Read AArch64 ELF64 object → inspect → write back → byte-compare.
• Read ARM object with .ARM.exidx → section present with correct sh_link.
• Read ARM object with .ARM.attributes → parse attributes, verify tag values.
• Read AArch64 object with .note.gnu.property → BTI/PAC flags extracted.
• Create ARM object from scratch → write → readelf -a validates headers/sections/symbols/relocs.
• Create AArch64 object from scratch → write → readelf -a validates.
• Big-endian ARM object: read and write with correct byte order.

11c. Validation Tests

• ARM ELF with ELFCLASS64 → rejected.
• AArch64 ELF with ELFCLASS32 → rejected.
• ARM ELF with conflicting float ABI flags → diagnostic.
• ARM ELF with missing .ARM.exidx SHF_LINK_ORDER → diagnostic.
• AArch64 ELF with unknown e_flags → warning.
• Unrecognized relocation type → diagnostic.

11d. Link Planning Tests

• Merge two ARM objects → e_flags union is correct.
• Merge hard-float + soft-float ARM objects → error.
• Merge ARM + AArch64 objects → rejected (class mismatch).
• .ARM.attributes merge: compatible objects → merged, incompatible → error.
• AArch64 .note.gnu.property merge: BTI+PAC from both inputs → AND of features.

11e. Build Attributes Tests

• Parse .ARM.attributes from GCC-produced ARM object.
• All standard tags readable via API.
• Unknown vendor subsections skipped without error.
• Tag compatibility check across two inputs for Tag_CPU_arch, Tag_FP_arch, Tag_ABI_VFP_args.

11f. DWARF Tests

• ARM DWARF register numbers map correctly in .debug_frame / .eh_frame.
• AArch64 DWARF register numbers map correctly.
• CFA restoration rules work for ARM R11 frame pointer.
• CFA restoration rules work for AArch64 X29 frame pointer.

11g. Fuzz Tests

• Fuzz ARM ELF object parsing → crash-free.
• Fuzz AArch64 ELF object parsing → crash-free.
• Fuzz .ARM.attributes section parsing → crash-free.

---

12. Expanded x86 Relocation Backend

12a. i386 Backend Expansion

• R_386_COPY → no value (dynamic linker copies data)
• R_386_GLOB_DAT → S (GOT slot fill)
• R_386_JMP_SLOT → S (PLT GOT slot fill)
• R_386_RELATIVE → B(S) + A (base-relative)
• R_386_16 → S + A, check unsigned 16-bit
• R_386_PC16 → S + A − P, check signed 16-bit
• R_386_8 → S + A, check unsigned 8-bit
• R_386_PC8 → S + A − P, check signed 8-bit
• R_386_SIZE32 → Z + A (symbol size)
• R_386_GOT32X → GOT(S) + A − GOT_ORG (relaxable GOT reference)
• R_386_IRELATIVE → indirect function resolution
• R_386_TLS_DTPMOD32 → module ID for TLS
• R_386_TLS_DTPOFF32 → offset within TLS block
• R_386_TLS_LE_32 → negative TP-relative offset
• R_386_TLS_TPOFF32 → negative TP-relative offset (variant)
• Add i386_is_tls() for complete TLS classification: all R_386_TLS_* types

12b. x86-64 Backend Expansion

• R_X86_64_COPY → no value
• R_X86_64_GLOB_DAT → S
• R_X86_64_JUMP_SLOT → S
• R_X86_64_RELATIVE → B + A
• R_X86_64_16 → S + A, check unsigned 16-bit
• R_X86_64_PC16 → S + A − P, check signed 16-bit
• R_X86_64_8 → S + A, check unsigned 8-bit
• R_X86_64_PC8 → S + A − P, check signed 8-bit
• R_X86_64_PC64 → S + A − P (64-bit PC-relative)
• R_X86_64_GOTOFF64 → S + A − GOT_ORG
• R_X86_64_GOTPC32 → GOT_ORG + A − P
• R_X86_64_SIZE32 → Z + A (check 32-bit), R_X86_64_SIZE64 → Z + A
• R_X86_64_GOTPCRELX → GOT(S) + A − P (relaxable to LEA for non-preemptible)
• R_X86_64_REX_GOTPCRELX → same with REX prefix
• R_X86_64_IRELATIVE → indirect function resolution
• R_X86_64_DTPMOD64, R_X86_64_DTPOFF64, R_X86_64_TPOFF64 → TLS module/offset dynamic
• R_X86_64_TLSLD → Local Dynamic TLS
• R_X86_64_DTPOFF32 → 32-bit DTP offset
• R_X86_64_GOTPC32_TLSDESC → TLSDESC GOT-relative
• R_X86_64_TLSDESC_CALL → TLSDESC call relocation
• R_X86_64_TLSDESC → TLSDESC pair
• Add x64_is_tls() for complete TLS classification: all R_X86_64_TLS*, GOTTPOFF, TPOFF32, DTPMOD64, DTPOFF64, TPOFF64, DTPOFF32, GOTPC32_TLSDESC, TLSDESC_CALL, TLSDESC

12c. x86 Relocation Name Strings

• elf_reloc_name_for_machine(machine, type) → human-readable string (e.g., "R_X86_64_PC32")
• Complete name tables for all i386 and x86-64 relocation types.
• Complete name tables for all ARM and AArch64 relocation types.
• Complete name tables for all MIPS, RISC-V, LoongArch, M68K, VAX, Alpha, PPC, PPC64, and IA-64 relocation types.

---

13. x86-Specific Validation (elf_validate.c)

• Validate EM_386 with ELFCLASS32 only.
• Validate EM_X86_64 with ELFCLASS64 only.
• Both x86 variants: ELFDATA2LSB only (x86 is always little-endian).
• Validate .note.gnu.property structure for x86: NT_GNU_PROPERTY_TYPE_0, correct alignment (4-byte for ELF32, 8-byte for ELF64).
• Validate GNU_PROPERTY_X86_ISA_1_NEEDED bit values (only defined bits set).
• Validate GNU_PROPERTY_X86_FEATURE_1_AND bit values (only IBT/SHSTK).
• Warn on unknown GNU properties (forward compatibility).
• Validate SHT_REL used for i386, SHT_RELA for x86-64.
• Validate .eh_frame CIE return address register (8 for i386/RA, 16 for x86-64/RA).

---

14. GNU Property / Note API

• elf_note_count(obj) → number of notes across all note sections.
• elf_note_at(obj, index) → {name, type, desc_data, desc_size}.
• elf_gnu_property_count(obj) → number of GNU properties in .note.gnu.property.
• elf_gnu_property_at(obj, index) → {type, data, data_size}.
• elf_x86_isa_level(obj) → bitmask of GNU_PROPERTY_X86_ISA_1_NEEDED (0 if absent).
• elf_x86_feature_flags(obj) → bitmask of GNU_PROPERTY_X86_FEATURE_1_AND (0 if absent).
• elf_aarch64_feature_flags(obj) → bitmask of GNU_PROPERTY_AARCH64_FEATURE_1_AND (0 if absent).
• elf_add_gnu_property_x86(obj, isa_needed, isa_used, feature_1) → create/update .note.gnu.property.
• elf_add_gnu_property_aarch64(obj, feature_1) → create/update .note.gnu.property.
• elf_build_id(obj, out_data, out_size) → extract .note.gnu.build-id contents.

---

15. x86-Specific Tests

15a. Expanded i386 Relocation Tests

• R_386_16 and R_386_PC16: verify 16-bit relocations.
• R_386_8 and R_386_PC8: verify 8-bit relocations.
• R_386_SIZE32: verify symbol size relocation.
• R_386_GOT32X: verify relaxable GOT reference.
• R_386_IRELATIVE: verify indirect function.
• R_386_TLS_DTPMOD32/DTPOFF32: verify TLS relocations.
• All dynamic relocations (COPY/GLOB_DAT/JMP_SLOT/RELATIVE): verify.

15b. Expanded x86-64 Relocation Tests

• R_X86_64_PC64: verify 64-bit PC-relative.
• R_X86_64_GOTOFF64/GOTPC32: verify GOT-relative.
• R_X86_64_SIZE32/SIZE64: verify size relocations.
• R_X86_64_GOTPCRELX/REX_GOTPCRELX: verify relaxable GOT references.
• R_X86_64_IRELATIVE: verify indirect function.
• R_X86_64_TLSLD/DTPOFF32: verify Local Dynamic TLS.
• R_X86_64_GOTPC32_TLSDESC/TLSDESC_CALL/TLSDESC: verify TLSDESC relocations.
• All 16-bit and 8-bit relocations: verify.

15c. GNU Property Tests

• Read x86-64 object with .note.gnu.property → extract ISA level bits.
• Read AArch64 object → extract BTI/PAC flags.
• Create object → add GNU property → write → read back → verify.
• Property with ISA_1_V4 → elf_x86_isa_level() returns correct bitmask.
• Object without .note.gnu.property → elf_x86_isa_level() returns 0.
• Merge two objects with different ISA levels → OR result.
• Merge two objects with FEATURE_1_AND → AND result.

15d. Relocation Name Tests

• Every i386 relocation type → correct name string.
• Every x86-64 relocation type → correct name string.
• Every ARM relocation type → correct name string.
• Every AArch64 relocation type → correct name string.
• Unknown type → "UNKNOWN(N)" format.

15e. x86 Validation Tests

• EM_386 with ELFCLASS64 → rejected.
• EM_X86_64 with ELFCLASS32 → rejected.
• x86 with ELFDATA2MSB → rejected.
• .note.gnu.property with bad alignment → diagnostic.
• .note.gnu.property with unknown property type → warning (not error).

---

16. Documentation

• Update README.md with full multi-architecture support notes.
• Document all relocation backend registration APIs.
• Document ARM build attributes API.
• Document GNU property API.
• Document relocation name API.
• Update COMPATIBILITY_MATRIX.md with all architecture entries.
• Man page updates for elfobj.3 with per-arch API functions.

---

17. MIPS / MIPS64 Support

17a. Machine Types and Constants

• Define EM_MIPS (8).
• Define MIPS e_flags: EF_MIPS_NOREORDER, EF_MIPS_PIC, EF_MIPS_CPIC, EF_MIPS_ABI_O32, EF_MIPS_ABI_O64, EF_MIPS_ABI_EABI32, EF_MIPS_ABI_EABI64.
• Define MIPS ISA flags: EF_MIPS_ARCH_1 through EF_MIPS_ARCH_64R6.
• Define MIPS ASE flags: EF_MIPS_MIPS16, EF_MIPS_MICROMIPS, EF_MIPS_ARCH_ASE_MDMX, EF_MIPS_ARCH_ASE_M16, EF_MIPS_ARCH_ASE_DSP, EF_MIPS_ARCH_ASE_DSPR2, EF_MIPS_ARCH_ASE_MSA.
• Define MIPS FP mode: EF_MIPS_FP64 (FR=1).
• Define MIPS section types: SHT_MIPS_DWARF (0x7000001E), SHT_MIPS_ABIFLAGS (0x7000002A).
• Define MIPS segment types: PT_MIPS_ABIFLAGS (0x70000003), PT_MIPS_REGINFO (0x70000000).

17b. MIPS Relocation Type Constants

• R_MIPS_NONE (0), R_MIPS_16 (1), R_MIPS_32 (2), R_MIPS_REL32 (3)
• R_MIPS_26 (4), R_MIPS_HI16 (5), R_MIPS_LO16 (6)
• R_MIPS_GPREL16 (7), R_MIPS_LITERAL (8), R_MIPS_GOT16 (9)
• R_MIPS_PC16 (10), R_MIPS_CALL16 (11), R_MIPS_GPREL32 (12)
• R_MIPS_SHIFT5 (16), R_MIPS_SHIFT6 (17), R_MIPS_64 (18)
• R_MIPS_GOT_DISP (19), R_MIPS_GOT_PAGE (20), R_MIPS_GOT_OFST (21)
• R_MIPS_GOT_HI16 (22), R_MIPS_GOT_LO16 (23)
• R_MIPS_SUB (24), R_MIPS_INSERT_A (25), R_MIPS_INSERT_B (26), R_MIPS_DELETE (27)
• R_MIPS_HIGHER (28), R_MIPS_HIGHEST (29)
• R_MIPS_CALL_HI16 (30), R_MIPS_CALL_LO16 (31), R_MIPS_SCN_DISP (32)
• R_MIPS_REL16 (33), R_MIPS_ADD_IMMEDIATE (34)
• R_MIPS_PJUMP (35), R_MIPS_RELGOT (36)
• R_MIPS_JALR (37), R_MIPS_GLOB_DAT (51)
• R_MIPS_COPY (126), R_MIPS_JUMP_SLOT (127)
• TLS: R_MIPS_TLS_DTPMOD32 (38), R_MIPS_TLS_DTPREL32 (39), R_MIPS_TLS_DTPMOD64 (40), R_MIPS_TLS_DTPREL64 (41), R_MIPS_TLS_GD (42), R_MIPS_TLS_LDM (43), R_MIPS_TLS_DTPREL_HI16 (44), R_MIPS_TLS_DTPREL_LO16 (45), R_MIPS_TLS_GOTTPREL (46), R_MIPS_TLS_TPREL32 (47), R_MIPS_TLS_TPREL64 (48), R_MIPS_TLS_TPREL_HI16 (49), R_MIPS_TLS_TPREL_LO16 (50)
• MicroMIPS: R_MICROMIPS_26_S1 (133), R_MICROMIPS_HI16 (134), R_MICROMIPS_LO16 (135), R_MICROMIPS_GPREL16 (136), R_MICROMIPS_PC7_S1 (143), R_MICROMIPS_PC10_S1 (144), R_MICROMIPS_PC16_S1 (145), R_MICROMIPS_PC23_S2 (172)

17c. MIPS Relocation Backend

• mips_reloc_size() for all MIPS relocation types.
• mips_is_pc_relative(): PC-relative classification.
• mips_is_tls(): TLS classification.
• mips_apply(): HI16/LO16 paired relocation with AHL computation.
• mips_apply(): R_MIPS_26 with 256MB segment masking.
• mips_apply(): GP-relative relocations (GPREL16, LITERAL).
• mips_apply(): GOT16/CALL16 GOT slot references.
• mips_apply(): N64 compound relocations (up to 3 relocs per entry).
• mips_apply(): All TLS relocations.
• mips_apply(): MicroMIPS branch/jump encoding.
• Register under EM_MIPS in register_builtin_backends_locked().
• Relocation name strings for all MIPS types.

17d. MIPS ABIFLAGS Parser

• Parse .MIPS.abiflags structure: isa_level, isa_rev, gpr_size, cpr1_size, cpr2_size, fp_abi, isa_ext, ases, flags1, flags2.
• API: elf_mips_abiflags() returning parsed structure.
• Validate ABIFLAGS consistency with e_flags ISA level.
• ABIFLAGS merge rules across link inputs.

17e. MIPS Validation

• Accept EM_MIPS with ELFCLASS32 (O32/N32) or ELFCLASS64 (N64).
• Accept both ELFDATA2LSB (MIPSEL) and ELFDATA2MSB (MIPS).
• Validate e_flags ISA level and ABI fields.
• Validate .MIPS.abiflags section if present.
• Validate N64 compound relocation entries.

17f. MIPS ELF Read/Write/Create

• Recognize EM_MIPS as valid machine type.
• MIPS32/N32: parse/write REL relocations. MIPS64/N64: parse/write RELA with compound entries.
• Parse SHT_MIPS_ABIFLAGS, PT_MIPS_ABIFLAGS, PT_MIPS_REGINFO.
• elf_init_mips32(): ELF32/EM_MIPS/ELFDATA2LSB with O32 flags.
• elf_init_mips64(): ELF64/EM_MIPS/ELFDATA2LSB with N64 flags.
• Endian-correct output for big-endian MIPS.

17g. MIPS DWARF

• MIPS DWARF register mapping: $zero–$ra → 0–31, $f0–$f31 → 32–63, HI → 64, LO → 65.
• MIPS CFA: frame pointer $fp ($30) or $sp ($29).

17h. MIPS Testing

• Unit tests for all MIPS relocation types.
• HI16/LO16 pairing correctness.
• N64 compound relocation handling.
• ABIFLAGS parsing and merge tests.
• Round-trip read/write for MIPS32 and MIPS64 objects.
• Validation: class/endian checks.
• Fuzz MIPS ELF parsing → crash-free.

---

18. RISC-V Support (RV32 / RV64 / RV128)

18a. Machine Types and Constants

• Define EM_RISCV (243).
• Define RISC-V e_flags: EF_RISCV_RVC (0x0001), EF_RISCV_FLOAT_ABI_SOFT (0x0000), EF_RISCV_FLOAT_ABI_SINGLE (0x0002), EF_RISCV_FLOAT_ABI_DOUBLE (0x0004), EF_RISCV_FLOAT_ABI_QUAD (0x0006), EF_RISCV_RVE (0x0008), EF_RISCV_TSO (0x0010).
• Define RISC-V section types: SHT_RISCV_ATTRIBUTES (0x70000003).

18b. RISC-V Relocation Type Constants

• R_RISCV_NONE (0), R_RISCV_32 (1), R_RISCV_64 (2)
• R_RISCV_RELATIVE (3), R_RISCV_COPY (4), R_RISCV_JUMP_SLOT (5), R_RISCV_TLS_DTPMOD32 (6), R_RISCV_TLS_DTPMOD64 (7), R_RISCV_TLS_DTPREL32 (8), R_RISCV_TLS_DTPREL64 (9), R_RISCV_TLS_TPREL32 (10), R_RISCV_TLS_TPREL64 (11)
• R_RISCV_BRANCH (16), R_RISCV_JAL (17), R_RISCV_CALL (18), R_RISCV_CALL_PLT (19), R_RISCV_GOT_HI20 (20)
• R_RISCV_TLS_GOT_HI20 (21), R_RISCV_TLS_GD_HI20 (22), R_RISCV_PCREL_HI20 (23), R_RISCV_PCREL_LO12_I (24), R_RISCV_PCREL_LO12_S (25)
• R_RISCV_HI20 (26), R_RISCV_LO12_I (27), R_RISCV_LO12_S (28)
• R_RISCV_TPREL_HI20 (29), R_RISCV_TPREL_LO12_I (30), R_RISCV_TPREL_LO12_S (31), R_RISCV_TPREL_ADD (32)
• R_RISCV_ADD8 (33), R_RISCV_ADD16 (34), R_RISCV_ADD32 (35), R_RISCV_ADD64 (36)
• R_RISCV_SUB8 (37), R_RISCV_SUB16 (38), R_RISCV_SUB32 (39), R_RISCV_SUB64 (40)
• R_RISCV_ALIGN (43), R_RISCV_RVC_BRANCH (44), R_RISCV_RVC_JUMP (45), R_RISCV_RVC_LUI (46)
• R_RISCV_RELAX (51), R_RISCV_SUB6 (52), R_RISCV_SET6 (53), R_RISCV_SET8 (54), R_RISCV_SET16 (55), R_RISCV_SET32 (56)
• R_RISCV_32_PCREL (57), R_RISCV_IRELATIVE (58)
• RV128 (draft): R_RISCV_128 (TBD when standardized).
• Vendor: R_RISCV_VENDOR (reserved range).

18c. RISC-V Relocation Backend

• riscv_reloc_size() for all RISC-V relocation types.
• riscv_is_pc_relative(): BRANCH, JAL, CALL, CALL_PLT, PCREL_HI20, PCREL_LO12_I/S, RVC_BRANCH, RVC_JUMP, 32_PCREL.
• riscv_is_tls(): all TLS_* and TPREL_* types.
• riscv_apply(): U-type immediate insertion (HI20: bits[31:12]).
• riscv_apply(): I-type immediate insertion (LO12_I: bits[31:20]).
• riscv_apply(): S-type immediate insertion (LO12_S: bits[31:25]+bits[11:7]).
• riscv_apply(): B-type branch encoding (BRANCH: imm[12|10:5|4:1|11]).
• riscv_apply(): J-type jump encoding (JAL: imm[20|10:1|11|19:12]).
• riscv_apply(): CALL/CALL_PLT (AUIPC+JALR pair).
• riscv_apply(): RVC compressed branch/jump encoding.
• riscv_apply(): ADD/SUB content relocations for DWARF.
• riscv_apply(): RELAX marker handling (no-op, but must not error).
• Register under EM_RISCV.
• Relocation name strings for all RISC-V types.

18d. RISC-V Attributes Parser

• Parse .riscv.attributes (SHT_RISCV_ATTRIBUTES).
• Decode Tag_RISCV_arch ISA string (e.g., "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0").
• Decode Tag_RISCV_stack_align (stack alignment).
• Decode Tag_RISCV_unaligned_access (unaligned access).
• Decode Tag_RISCV_priv_spec / Tag_RISCV_priv_spec_minor / Tag_RISCV_priv_spec_revision.
• API: elf_riscv_attribute_count(), elf_riscv_attribute_tag_at(), elf_riscv_attribute_value_at().
• ISA string compatibility checking across link inputs.

18e. RISC-V Validation

• Accept EM_RISCV with ELFCLASS32 (RV32) or ELFCLASS64 (RV64/RV128).
• Reject ELFDATA2MSB (RISC-V is little-endian only).
• Validate e_flags float ABI, RVC, RVE, TSO flags.
• Validate .riscv.attributes section if present.
• Check for conflicting float ABI across link inputs.

18f. RISC-V ELF Read/Write/Create

• Recognize EM_RISCV as valid machine type.
• RV32: parse/write RELA relocations (ELF32). RV64: parse/write RELA relocations (ELF64).
• Parse SHT_RISCV_ATTRIBUTES sections.
• elf_init_riscv32(): ELF32/EM_RISCV/ELFDATA2LSB.
• elf_init_riscv64(): ELF64/EM_RISCV/ELFDATA2LSB.

18g. RISC-V DWARF

• RISC-V DWARF register mapping: x0–x31 → 0–31, f0–f31 → 32–63.
• RISC-V CFA: frame pointer x8 (s0/fp) or x2 (sp), return address x1 (ra).

18h. RISC-V Testing

• Unit tests for all RISC-V relocation types.
• B-type and J-type immediate encoding correctness.
• CALL/CALL_PLT AUIPC+JALR pair calculation.
• RVC branch/jump compressed encoding.
• ADD/SUB content relocations.
• .riscv.attributes parsing and ISA string decode.
• Round-trip read/write for RV32 and RV64 objects.
• Validation: class/endian checks, float ABI conflicts.
• Fuzz RISC-V ELF parsing → crash-free.

---

19. LoongArch Support (LA32 / LA64)

19a. Machine Types and Constants

• Define EM_LOONGARCH (258).
• Define LoongArch e_flags: EF_LARCH_ABI_MODIFIER_MASK, EF_LARCH_ABI_SOFT_FLOAT (0x1), EF_LARCH_ABI_SINGLE_FLOAT (0x2), EF_LARCH_ABI_DOUBLE_FLOAT (0x3), EF_LARCH_OBJABI_V1 (0x40).

19b. LoongArch Relocation Type Constants

• R_LARCH_NONE (0), R_LARCH_32 (1), R_LARCH_64 (2), R_LARCH_RELATIVE (3)
• R_LARCH_COPY (4), R_LARCH_JUMP_SLOT (5), R_LARCH_TLS_DTPMOD32 (6), R_LARCH_TLS_DTPMOD64 (7), R_LARCH_TLS_DTPREL32 (8), R_LARCH_TLS_DTPREL64 (9), R_LARCH_TLS_TPREL32 (10), R_LARCH_TLS_TPREL64 (11), R_LARCH_IRELATIVE (12)
• R_LARCH_MARK_LA (20), R_LARCH_MARK_PCREL (21), R_LARCH_SOP_PUSH_PCREL (22) through R_LARCH_SOP_POP_32_S_10_16_S2 (43)
• R_LARCH_B16 (64), R_LARCH_B21 (65), R_LARCH_B26 (66)
• R_LARCH_ABS_HI20 (67), R_LARCH_ABS_LO12 (68), R_LARCH_ABS64_LO20 (69), R_LARCH_ABS64_HI12 (70)
• R_LARCH_PCALA_HI20 (71), R_LARCH_PCALA_LO12 (72), R_LARCH_PCALA64_LO20 (73), R_LARCH_PCALA64_HI12 (74)
• R_LARCH_GOT_PC_HI20 (75), R_LARCH_GOT_PC_LO12 (76), R_LARCH_GOT64_PC_LO20 (77), R_LARCH_GOT64_PC_HI12 (78)
• TLS: R_LARCH_TLS_LE_HI20 (79), R_LARCH_TLS_LE_LO12 (80), R_LARCH_TLS_LE64_LO20 (81), R_LARCH_TLS_LE64_HI12 (82), R_LARCH_TLS_IE_PC_HI20 (83), R_LARCH_TLS_IE_PC_LO12 (84), R_LARCH_TLS_IE64_PC_LO20 (85), R_LARCH_TLS_IE64_PC_HI12 (86), R_LARCH_TLS_LD_PC_HI20 (87), R_LARCH_TLS_GD_PC_HI20 (98)
• TLSDESC: R_LARCH_TLS_DESC_PC_HI20 (99), R_LARCH_TLS_DESC_PC_LO12 (100), R_LARCH_TLS_DESC64_PC_LO20 (101), R_LARCH_TLS_DESC64_PC_HI12 (102), R_LARCH_TLS_DESC_HI20 (103), R_LARCH_TLS_DESC_LO12 (104), R_LARCH_TLS_DESC64_LO20 (105), R_LARCH_TLS_DESC64_HI12 (106), R_LARCH_TLS_DESC_LD (107), R_LARCH_TLS_DESC_CALL (108)
• R_LARCH_TLS_LE_HI20_R (109), R_LARCH_TLS_LE_ADD_R (110), R_LARCH_TLS_LE_LO12_R (111)
• Relaxation: R_LARCH_RELAX (100), R_LARCH_ALIGN (102)
• Content: R_LARCH_ADD6/8/16/32/64, R_LARCH_SUB6/8/16/32/64

19c. LoongArch Relocation Backend

• larch_reloc_size() for all LoongArch relocation types.
• larch_is_pc_relative(): B16/B21/B26, PCALA_HI20/LO12, GOT_PC_, TLS_IE_PC_, TLSDESC_PC_*.
• larch_is_tls(): all TLS_* and TLSDESC_* types.
• larch_apply(): 20-bit HI20 immediate insertion (bits[24:5]).
• larch_apply(): 12-bit LO12 immediate insertion (bits[21:10]).
• larch_apply(): Branch B16 (16-bit signed offset << 2), B21 (21-bit << 2), B26 (26-bit << 2).
• larch_apply(): PCALA page-aligned PC-relative pair.
• larch_apply(): ADD/SUB content relocations.
• Register under EM_LOONGARCH.
• Relocation name strings for all LoongArch types.

19d. LoongArch Validation

• Accept EM_LOONGARCH with ELFCLASS32 (LA32) or ELFCLASS64 (LA64).
• Reject ELFDATA2MSB (LoongArch is little-endian only).
• Validate e_flags ABI modifier and float ABI.

19e. LoongArch ELF Read/Write/Create

• Recognize EM_LOONGARCH as valid machine type.
• Parse/write RELA relocations.
• elf_init_loongarch32(): ELF32/EM_LOONGARCH/ELFDATA2LSB.
• elf_init_loongarch64(): ELF64/EM_LOONGARCH/ELFDATA2LSB.

19f. LoongArch DWARF

• LoongArch DWARF register mapping: $r0–$r31 → 0–31, $f0–$f31 → 32–63.
• LoongArch CFA: frame pointer $fp ($r22) or $sp ($r3), return address $ra ($r1).

19g. LoongArch Testing

• Unit tests for all LoongArch relocation types.
• HI20/LO12 pair calculation.
• Branch encoding (B16, B21, B26).
• TLS and TLSDESC relocation handling.
• Round-trip read/write for LA32 and LA64 objects.
• Validation: class/endian checks.
• Fuzz LoongArch ELF parsing → crash-free.

---

20. Motorola 68000 (M68K) Support

20a. Machine Types and Constants

• Define EM_68K (4).
• M68K has no mandatory e_flags; validate flags is 0 or recognized.

20b. M68K Relocation Type Constants

• R_68K_NONE (0), R_68K_32 (1), R_68K_16 (2), R_68K_8 (3)
• R_68K_PC32 (4), R_68K_PC16 (5), R_68K_PC8 (6)
• R_68K_GOT32 (7), R_68K_GOT16 (8), R_68K_GOT8 (9)
• R_68K_GOT32O (10), R_68K_GOT16O (11), R_68K_GOT8O (12)
• R_68K_PLT32 (13), R_68K_PLT16 (14), R_68K_PLT8 (15)
• R_68K_PLT32O (16), R_68K_PLT16O (17), R_68K_PLT8O (18)
• R_68K_COPY (19), R_68K_GLOB_DAT (20), R_68K_JMP_SLOT (21), R_68K_RELATIVE (22)
• TLS: R_68K_TLS_GD32 (25), R_68K_TLS_GD16 (26), R_68K_TLS_GD8 (27), R_68K_TLS_LDM32 (28), R_68K_TLS_LDM16 (29), R_68K_TLS_LDM8 (30), R_68K_TLS_LDO32 (31), R_68K_TLS_LDO16 (32), R_68K_TLS_LDO8 (33), R_68K_TLS_IE32 (34), R_68K_TLS_IE16 (35), R_68K_TLS_IE8 (36), R_68K_TLS_LE32 (37), R_68K_TLS_LE16 (38), R_68K_TLS_LE8 (39), R_68K_TLS_DTPMOD32 (40), R_68K_TLS_DTPREL32 (41), R_68K_TLS_TPREL32 (42)

20c. M68K Relocation Backend

• m68k_reloc_size() for all M68K relocation types.
• m68k_is_pc_relative(): PC32, PC16, PC8.
• m68k_is_tls(): all TLS_* types.
• m68k_apply(): S + A for absolute, S + A − P for PC-relative, with 8/16/32-bit overflow checks.
• m68k_apply(): GOT/PLT slot references.
• m68k_apply(): All TLS relocations.
• Register under EM_68K.
• Relocation name strings for all M68K types.

20d. M68K Validation

• Accept EM_68K with ELFCLASS32 only.
• Accept ELFDATA2MSB only (M68K is big-endian).
• Validate e_flags.

20e. M68K ELF Read/Write/Create

• Recognize EM_68K as valid machine type.
• Parse/write RELA relocations (M68K uses RELA).
• elf_init_m68k(): ELF32/EM_68K/ELFDATA2MSB.
• Big-endian read/write.

20f. M68K DWARF

• M68K DWARF register mapping: D0–D7 → 0–7, A0–A7 → 8–15, FP0–FP7 → 16–23.
• M68K CFA: frame pointer A6 (FP), return address on stack.

20g. M68K Testing

• Unit tests for all M68K relocation types (8/16/32-bit absolute and PC-relative).
• TLS relocation handling.
• Big-endian round-trip read/write.
• Validation: reject ELFCLASS64, reject ELFDATA2LSB.
• Fuzz M68K ELF parsing → crash-free.

---

21. VAX Support

21a. Machine Types and Constants

• Define EM_VAX (75).
• VAX has no mandatory e_flags; validate flags is 0.

21b. VAX Relocation Type Constants

• R_VAX_NONE (0), R_VAX_32 (1), R_VAX_16 (2), R_VAX_8 (3)
• R_VAX_PC32 (4), R_VAX_PC16 (5), R_VAX_PC8 (6)
• R_VAX_GOT32 (7), R_VAX_PLT32 (13)
• R_VAX_COPY (19), R_VAX_GLOB_DAT (20), R_VAX_JMP_SLOT (21), R_VAX_RELATIVE (22)

21c. VAX Relocation Backend

• vax_reloc_size() for all VAX relocation types.
• vax_is_pc_relative(): PC32, PC16, PC8.
• vax_apply(): S + A for absolute, S + A − P for PC-relative.
• Register under EM_VAX.
• Relocation name strings for all VAX types.

21d. VAX Validation

• Accept EM_VAX with ELFCLASS32 only.
• Accept ELFDATA2LSB only (VAX is little-endian).

21e. VAX ELF Read/Write/Create

• Recognize EM_VAX as valid machine type.
• Parse/write RELA relocations (VAX uses RELA).
• elf_init_vax(): ELF32/EM_VAX/ELFDATA2LSB.

21f. VAX DWARF

• VAX DWARF register mapping: R0–R15 → 0–15, AP → 12, FP → 13, SP → 14, PC → 15.

21g. VAX Testing

• Unit tests for all VAX relocation types.
• Round-trip read/write.
• Validation: reject ELFCLASS64, reject ELFDATA2MSB.
• Fuzz VAX ELF parsing → crash-free.

---

22. PowerPC / PowerPC64 Support

22a. Machine Types and Constants

• Define EM_PPC (20), EM_PPC64 (21).
• Define PPC32 e_flags: EF_PPC_EMB (0x80000000).
• Define PPC64 e_flags: EF_PPC64_ABI_V1 (1), EF_PPC64_ABI_V2 (2).
• Define PPC section types: SHT_PPC_TAGS (0x70000000), SHT_PPC64_OPD (for .opd function descriptors).
• Define PPC segment types: PT_PPC_GNU_MBIND variants if needed.

22b. PowerPC32 Relocation Type Constants

• R_PPC_NONE (0), R_PPC_ADDR32 (1), R_PPC_ADDR24 (2), R_PPC_ADDR16 (3)
• R_PPC_ADDR16_LO (4), R_PPC_ADDR16_HI (5), R_PPC_ADDR16_HA (6)
• R_PPC_ADDR14 (7), R_PPC_ADDR14_BRTAKEN (8), R_PPC_ADDR14_BRNTAKEN (9)
• R_PPC_REL24 (10), R_PPC_REL14 (11), R_PPC_REL14_BRTAKEN (12), R_PPC_REL14_BRNTAKEN (13)
• R_PPC_GOT16 (14), R_PPC_GOT16_LO (15), R_PPC_GOT16_HI (16), R_PPC_GOT16_HA (17)
• R_PPC_PLTREL24 (18), R_PPC_COPY (19), R_PPC_GLOB_DAT (20), R_PPC_JMP_SLOT (21), R_PPC_RELATIVE (22)
• R_PPC_LOCAL24PC (23), R_PPC_UADDR32 (24), R_PPC_UADDR16 (25), R_PPC_REL32 (26)
• R_PPC_PLT32 (27), R_PPC_PLTREL32 (28), R_PPC_PLT16_LO (29), R_PPC_PLT16_HI (30), R_PPC_PLT16_HA (31)
• R_PPC_SDAREL16 (32), R_PPC_SECTOFF (33), R_PPC_SECTOFF_LO (34), R_PPC_SECTOFF_HI (35), R_PPC_SECTOFF_HA (36)
• R_PPC_IRELATIVE (248)
• TLS: R_PPC_TLS (67), R_PPC_DTPMOD32 (68), R_PPC_TPREL16 (69), R_PPC_TPREL16_LO (70), R_PPC_TPREL16_HI (71), R_PPC_TPREL16_HA (72), R_PPC_TPREL32 (73), R_PPC_DTPREL16 (74), R_PPC_DTPREL16_LO (75), R_PPC_DTPREL16_HI (76), R_PPC_DTPREL16_HA (77), R_PPC_DTPREL32 (78), R_PPC_GOT_TLSGD16 (79), R_PPC_GOT_TLSGD16_LO (80), R_PPC_GOT_TLSGD16_HI (81), R_PPC_GOT_TLSGD16_HA (82), R_PPC_GOT_TLSLD16 (83), R_PPC_GOT_TLSLD16_LO (84), R_PPC_GOT_TLSLD16_HI (85), R_PPC_GOT_TLSLD16_HA (86), R_PPC_GOT_TPREL16 (87), R_PPC_GOT_TPREL16_LO (88), R_PPC_GOT_TPREL16_HI (89), R_PPC_GOT_TPREL16_HA (90)

22c. PowerPC64 Relocation Type Constants

• R_PPC64_ADDR64 (38), R_PPC64_ADDR16_HIGHER (39), R_PPC64_ADDR16_HIGHERA (40), R_PPC64_ADDR16_HIGHEST (41), R_PPC64_ADDR16_HIGHESTA (42)
• R_PPC64_UADDR64 (43), R_PPC64_REL64 (44), R_PPC64_PLT64 (45), R_PPC64_PLTREL64 (46)
• R_PPC64_TOC16 (47), R_PPC64_TOC16_LO (48), R_PPC64_TOC16_HI (49), R_PPC64_TOC16_HA (50), R_PPC64_TOC (51)
• R_PPC64_ADDR16_DS (56), R_PPC64_ADDR16_LO_DS (57), R_PPC64_GOT16_DS (58), R_PPC64_GOT16_LO_DS (59), R_PPC64_PLT16_LO_DS (60)
• R_PPC64_SECTOFF_DS (61), R_PPC64_SECTOFF_LO_DS (62), R_PPC64_TOC16_DS (63), R_PPC64_TOC16_LO_DS (64)
• R_PPC64_ENTRY (118), R_PPC64_PCREL34 (132), R_PPC64_GOT_PCREL34 (133), R_PPC64_PLT_PCREL34 (134)
• R_PPC64_IRELATIVE (248)
• TLS: R_PPC64_TLS, R_PPC64_DTPMOD64, R_PPC64_TPREL64, R_PPC64_DTPREL64, R_PPC64_TPREL16_DS, R_PPC64_TPREL16_LO_DS, R_PPC64_TPREL16_HIGHER, R_PPC64_TPREL16_HIGHERA, R_PPC64_TPREL16_HIGHEST, R_PPC64_TPREL16_HIGHESTA, R_PPC64_DTPREL16_DS, R_PPC64_DTPREL16_LO_DS, R_PPC64_DTPREL16_HIGHER, R_PPC64_DTPREL16_HIGHERA, R_PPC64_DTPREL16_HIGHEST, R_PPC64_DTPREL16_HIGHESTA, R_PPC64_GOT_TLSGD16{_LO/_HI/_HA}, R_PPC64_GOT_TLSLD16{_LO/_HI/_HA}, R_PPC64_GOT_TPREL16_DS, R_PPC64_GOT_TPREL16_LO_DS, R_PPC64_GOT_TPREL16_HI, R_PPC64_GOT_TPREL16_HA

22d. PowerPC Relocation Backend

• ppc_reloc_size() for all PPC32 relocation types.
• ppc64_reloc_size() for all PPC64 relocation types.
• ppc_is_pc_relative(): REL24, REL14, REL32, LOCAL24PC, PLTREL24, PLTREL32.
• ppc64_is_pc_relative(): above + REL64, PCREL34, GOT_PCREL34, PLT_PCREL34.
• ppc_is_tls() / ppc64_is_tls(): all TLS types.
• ppc_apply(): ADDR16_HI/HA with carry adjustment (((S + A + 0x8000) >> 16) & 0xFFFF for _HA).
• ppc_apply(): REL24 branch (26-bit signed offset in bits[25:2]).
• ppc_apply(): REL14 conditional branch (16-bit signed offset in bits[15:2]).
• ppc64_apply(): TOC16/TOC16_LO/HI/HA with TOC pointer base.
• ppc64_apply(): ADDR16_DS/LO_DS with 4-byte alignment check (low 2 bits must be 0).
• ppc64_apply(): PCREL34 (34-bit signed PC-relative, PCRel ABI).
• ppc64_apply(): ENTRY (local entry point offset).
• Register under EM_PPC and EM_PPC64.
• Relocation name strings for all PPC32 and PPC64 types.

22e. PowerPC64 OPD and TOC Handling

• Parse .opd section for ELFv1 function descriptors (3-word entries: address, TOC, environment).
• Handle ELFv2 local entry point offsets (encoded in st_other).
• TOC base calculation for ELFv2 linking.

22f. PowerPC Validation

• Accept EM_PPC with ELFCLASS32 only.
• Accept EM_PPC64 with ELFCLASS64 only.
• Accept both ELFDATA2LSB (PPC64LE) and ELFDATA2MSB (PPC/PPC64).
• Validate e_flags ELFv1/ELFv2 ABI version for PPC64.
• Validate .opd section structure for ELFv1.

22g. PowerPC ELF Read/Write/Create

• Recognize EM_PPC and EM_PPC64 as valid machine types.
• PPC32: parse/write RELA relocations (ELF32). PPC64: parse/write RELA relocations (ELF64).
• elf_init_ppc32(): ELF32/EM_PPC/ELFDATA2MSB.
• elf_init_ppc64(): ELF64/EM_PPC64/ELFDATA2LSB with ELFv2 flags.
• Endian-correct output for both LE and BE variants.

22h. PowerPC DWARF

• PPC32 DWARF register mapping: R0–R31 → 0–31, F0–F31 → 32–63, LR → 108, CTR → 109, CR → 68–75.
• PPC64 DWARF register mapping: same base + V0–V31 → 77–108 (VMX/AltiVec).
• PPC CFA: frame pointer R1 (SP), return address LR (R108).

22i. PowerPC Testing

• Unit tests for all PPC32 relocation types.
• Unit tests for all PPC64 relocation types.
• HA carry adjustment correctness.
• REL24 branch range checks.
• TOC16 DS-form alignment checks.
• PCREL34 encoding (PCRel ABI).
• .opd parsing for ELFv1 objects.
• ELFv2 local entry point offset decoding.
• Round-trip read/write for PPC32 (BE) and PPC64 (LE + BE) objects.
• Validation: class/endian checks, ELFv1/v2 flag validation.
• Fuzz PPC32 and PPC64 ELF parsing → crash-free.

---

23. Alpha Support

23a. Machine Types and Constants

• Define EM_ALPHA (0x9026).
• Alpha has no mandatory e_flags; validate flags is 0.

23b. Alpha Relocation Type Constants

• R_ALPHA_NONE (0), R_ALPHA_REFLONG (1), R_ALPHA_REFQUAD (2)
• R_ALPHA_GPREL32 (3), R_ALPHA_LITERAL (4), R_ALPHA_LITUSE (5)
• R_ALPHA_GPDISP (6), R_ALPHA_BRADDR (7), R_ALPHA_HINT (8)
• R_ALPHA_SREL16 (9), R_ALPHA_SREL32 (10), R_ALPHA_SREL64 (11)
• R_ALPHA_GPRELHIGH (17), R_ALPHA_GPRELLOW (18), R_ALPHA_GPREL16 (19)
• R_ALPHA_COPY (24), R_ALPHA_GLOB_DAT (25), R_ALPHA_JMP_SLOT (26), R_ALPHA_RELATIVE (27)
• TLS: R_ALPHA_TLSGD (25), R_ALPHA_TLSLDM (26), R_ALPHA_DTPMOD64 (27), R_ALPHA_GOTDTPREL (28), R_ALPHA_DTPREL64 (29), R_ALPHA_DTPRELHI (30), R_ALPHA_DTPRELLO (31), R_ALPHA_DTPREL16 (32), R_ALPHA_GOTTPREL (33), R_ALPHA_TPREL64 (34), R_ALPHA_TPRELHI (35), R_ALPHA_TPRELLO (36), R_ALPHA_TPREL16 (37)

23c. Alpha Relocation Backend

• alpha_reloc_size() for all Alpha relocation types.
• alpha_is_pc_relative(): BRADDR, HINT, SREL16/32/64.
• alpha_is_tls(): all TLS types.
• alpha_apply(): REFLONG (S + A, 32-bit), REFQUAD (S + A, 64-bit).
• alpha_apply(): BRADDR (21-bit signed PC-relative branch, bits[20:0]).
• alpha_apply(): HINT (14-bit hint for JMP/JSR).
• alpha_apply(): GPREL32 (S + A − GP).
• alpha_apply(): LITERAL/LITUSE (GOT slot + optimization hints).
• alpha_apply(): GPDISP (GP displacement pair).
• alpha_apply(): SREL16/32/64 (S + A − P).
• alpha_apply(): All TLS relocations.
• Register under EM_ALPHA.
• Relocation name strings for all Alpha types.

23d. Alpha Validation

• Accept EM_ALPHA with ELFCLASS64 only.
• Accept ELFDATA2LSB only (Alpha is little-endian).
• Validate e_flags.

23e. Alpha ELF Read/Write/Create

• Recognize EM_ALPHA as valid machine type.
• Parse/write RELA relocations (Alpha uses RELA).
• elf_init_alpha(): ELF64/EM_ALPHA/ELFDATA2LSB.

23f. Alpha DWARF

• Alpha DWARF register mapping: $0–$30 → 0–30, $f0–$f30 → 32–62, $sp → 30, $ra → 26.
• Alpha CFA: frame pointer $15 (FP) or $30 (SP), return address $26 (RA).

23g. Alpha Testing

• Unit tests for all Alpha relocation types.
• BRADDR range check (±4MB).
• GPREL/LITERAL/GPDISP GP-displacement correctness.
• TLS relocation handling.
• Round-trip read/write for Alpha ELF64 objects.
• Validation: reject ELFCLASS32, reject ELFDATA2MSB.
• Fuzz Alpha ELF parsing → crash-free.

---

24. IA-64 (Itanium) Support

24a. Machine Types and Constants

• Define EM_IA_64 (50).
• Define IA-64 e_flags: EF_IA_64_ABI64 (0x10), EF_IA_64_ARCH (0xFF000000).

24b. IA-64 Relocation Type Constants

• R_IA64_NONE (0)
• R_IA64_IMM14 (0x21), R_IA64_IMM22 (0x22), R_IA64_IMM64 (0x23)
• R_IA64_DIR32MSB (0x24), R_IA64_DIR32LSB (0x25), R_IA64_DIR64MSB (0x26), R_IA64_DIR64LSB (0x27)
• R_IA64_GPREL22 (0x2A), R_IA64_GPREL64I (0x2B), R_IA64_GPREL32MSB (0x2C), R_IA64_GPREL32LSB (0x2D), R_IA64_GPREL64MSB (0x2E), R_IA64_GPREL64LSB (0x2F)
• R_IA64_LTOFF22 (0x32), R_IA64_LTOFF64I (0x33)
• R_IA64_PLTOFF22 (0x3A), R_IA64_PLTOFF64I (0x3B), R_IA64_PLTOFF64MSB (0x3E), R_IA64_PLTOFF64LSB (0x3F)
• R_IA64_FPTR64I (0x43), R_IA64_FPTR32MSB (0x44), R_IA64_FPTR32LSB (0x45), R_IA64_FPTR64MSB (0x46), R_IA64_FPTR64LSB (0x47)
• R_IA64_PCREL21B (0x49), R_IA64_PCREL21M (0x4A), R_IA64_PCREL21F (0x4B), R_IA64_PCREL32MSB (0x4C), R_IA64_PCREL32LSB (0x4D), R_IA64_PCREL64MSB (0x4E), R_IA64_PCREL64LSB (0x4F)
• R_IA64_LTOFF_FPTR22 (0x52), R_IA64_LTOFF_FPTR64I (0x53), R_IA64_LTOFF_FPTR32MSB (0x54), R_IA64_LTOFF_FPTR32LSB (0x55), R_IA64_LTOFF_FPTR64MSB (0x56), R_IA64_LTOFF_FPTR64LSB (0x57)
• R_IA64_SEGREL32MSB (0x5C), R_IA64_SEGREL32LSB (0x5D), R_IA64_SEGREL64MSB (0x5E), R_IA64_SEGREL64LSB (0x5F)
• R_IA64_SECREL32MSB (0x64), R_IA64_SECREL32LSB (0x65), R_IA64_SECREL64MSB (0x66), R_IA64_SECREL64LSB (0x67)
• R_IA64_REL32MSB (0x6C), R_IA64_REL32LSB (0x6D), R_IA64_REL64MSB (0x6E), R_IA64_REL64LSB (0x6F)
• Dynamic: R_IA64_IPLTMSB (0x80), R_IA64_IPLTLSB (0x81), R_IA64_COPY (0x84), R_IA64_SUB (0x85)
• TLS: R_IA64_LTOFF_DTPMOD22 (0xAA), R_IA64_DTPMOD64MSB (0xAE), R_IA64_DTPMOD64LSB (0xAF), R_IA64_LTOFF_DTPREL22 (0xB2), R_IA64_DTPREL14 (0xB1), R_IA64_DTPREL22 (0xB2), R_IA64_DTPREL64I (0xB3), R_IA64_DTPREL32MSB (0xB4), R_IA64_DTPREL32LSB (0xB5), R_IA64_DTPREL64MSB (0xB6), R_IA64_DTPREL64LSB (0xB7), R_IA64_LTOFF_TPREL22 (0xBA), R_IA64_TPREL14 (0xC1), R_IA64_TPREL22 (0xC2), R_IA64_TPREL64I (0xC3), R_IA64_TPREL64MSB (0xC6), R_IA64_TPREL64LSB (0xC7)

24c. IA-64 Relocation Backend

• ia64_reloc_size() for all IA-64 relocation types.
• ia64_is_pc_relative(): PCREL21B/M/F, PCREL32MSB/LSB, PCREL64MSB/LSB.
• ia64_is_tls(): all TLS types.
• ia64_apply(): DIR32/64 MSB/LSB (S + A, 32/64-bit, both endiannesses).
• ia64_apply(): PCREL21B (21-bit signed PC-relative branch in bundle slot).
• ia64_apply(): PCREL21M/F (slot-specific PC-relative).
• ia64_apply(): IMM22 (22-bit immediate in instruction slot).
• ia64_apply(): IMM64 (64-bit immediate spread across MOVL bundle).
• ia64_apply(): IMM14 (14-bit immediate in instruction slot).
• ia64_apply(): GPREL22/64I/32/64 (GP-relative).
• ia64_apply(): LTOFF22/64I (linkage table offset, GOT-relative).
• ia64_apply(): FPTR (function pointer descriptor).
• ia64_apply(): SEGREL/SECREL (segment/section relative).
• Bundle slot decoding: extract template byte, identify slot positions, decode/encode instruction immediates.
• Register under EM_IA_64.
• Relocation name strings for all IA-64 types.

24d. IA-64 Validation

• Accept EM_IA_64 with ELFCLASS64 only.
• Accept both ELFDATA2LSB and ELFDATA2MSB.
• Validate e_flags EF_IA_64_ABI64 and EF_IA_64_ARCH.

24e. IA-64 ELF Read/Write/Create

• Recognize EM_IA_64 as valid machine type.
• Parse/write RELA relocations (IA-64 uses RELA).
• elf_init_ia64(): ELF64/EM_IA_64/ELFDATA2LSB.
• Endian-correct output for big-endian IA-64 (HP-UX).

24f. IA-64 DWARF

• IA-64 DWARF register mapping: GR0–GR127 → 0–127, FR0–FR127 → 128–255, BR0–BR7 → 320–327, PR0–PR63 → 256–319.
• IA-64 CFA: frame pointer GR12 (SP), return address BR0 (RP).

24g. IA-64 Testing

• Unit tests for all IA-64 relocation types.
• Bundle slot encoding/decoding correctness.
• IMM22/IMM64/IMM14 immediate insertion.
• PCREL21B branch range checks.
• GP-relative and LTOFF relocations.
• FPTR function descriptor handling.
• Round-trip read/write for IA-64 ELF64 objects.
• Validation: reject ELFCLASS32, e_flags checks.
• Fuzz IA-64 ELF parsing → crash-free.