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Colorlight 5A-75B v7.0 with two Ethernet Phys?
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| #============================================================================= | |
| self.submodules.ethphy0 = LiteEthPHYRGMII( | |
| clock_pads = self.platform.request("eth_clocks", 0), | |
| pads = self.platform.request("eth", 0), | |
| tx_delay=0e-9, | |
| ) | |
| self.add_etherbone(phy=self.ethphy0, ip_address=eth_ip, phy_cd="ethphy0_eth") | |
| self.submodules.ethphy1 = LiteEthPHYRGMII( | |
| clock_pads = self.platform.request("eth_clocks", 1), | |
| pads = self.platform.request("eth", 1), | |
| tx_delay=0e-9, | |
| ) | |
| self.add_ethernet(phy=self.ethphy1, phy_cd="ethphy1_eth") | |
| #============================================================================= | |
| ERROR: Cell 'TRELLIS_IO' cannot be bound to bel 'X0/Y38/PIOD' since it is already bound to cell 'TRELLIS_IO_1' | |
| #============================================================================= | |
| self.submodules.ethphy0 = LiteEthPHYRGMII( | |
| clock_pads = self.platform.request("eth_clocks", 0), | |
| pads = self.platform.request("eth", 0), | |
| tx_delay=0e-9, | |
| ) | |
| self.add_etherbone(phy=self.ethphy0, ip_address=eth_ip) | |
| self.submodules.ethphy1 = LiteEthPHYRGMII( | |
| clock_pads = self.platform.request("eth_clocks", 1), | |
| pads = self.platform.request("eth", 1), | |
| tx_delay=0e-9, | |
| ) | |
| self.add_ethernet(phy=self.ethphy1) | |
| #============================================================================= | |
| Exception: Unresolved clock domain eth_rx, availables: | |
| - etherbone | |
| - sys | |
| - sys_ps | |
| - ethphy0_eth_rx | |
| - ethphy0_eth_tx | |
| - ethphy1_eth_rx | |
| - ethphy1_eth_tx | |
| #============================================================================= | |
| the_clock_pads = self.platform.request("eth_clocks", 0) | |
| self.submodules.ethphy0 = LiteEthPHYRGMII( | |
| clock_pads =the_clock_pads, | |
| pads = self.platform.request("eth", 0), | |
| tx_delay=0e-9, | |
| ) | |
| self.add_etherbone(phy=self.ethphy0, ip_address=eth_ip, phy_cd="ethphy0_eth") | |
| self.submodules.ethphy1 = LiteEthPHYRGMII( | |
| clock_pads = the_clock_pads, | |
| pads = self.platform.request("eth", 1), | |
| tx_delay=0e-9, | |
| ) | |
| self.add_ethernet(phy=self.ethphy1, phy_cd="ethphy1_eth") | |
| #============================================================================= | |
| Warning: multiple conflicting drivers for colorlight_5a_75b.\eth_clocks0_tx: | |
| port Z[0] of cell DELAYG (DELAYG) | |
| port Z[0] of cell DELAYG_11 (DELAYG) | |
| found and reported 648 problems. | |
| ERROR: Net 'eth_clocks0_tx' is multiply driven by cell ports DELAYG.Z and DELAYG_11.Z |
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