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barebox
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| barebox@riscv-virtio,qemu:/ drvinfo | |
| Driver Device(s) | |
| -------------------- | |
| syscon | |
| riscv-timer | |
| riscv-timer | |
| riscv | |
| cpus:cpu@0.of | |
| cpus:cpu@1.of | |
| cpus:cpu@2.of | |
| cpus:cpu@3.of | |
| cpus:cpu@4.of | |
| cpus:cpu@5.of | |
| cpus:cpu@6.of | |
| cpus:cpu@7.of | |
| ns16550_serial | |
| 10000000.uart@10000000.of | |
| basic-mmio-gpio | |
| syscon-reboot-mode | |
| syscon-reboot | |
| soc:reboot.of | |
| syscon-poweroff | |
| soc:poweroff.of | |
| ext4 | |
| ramfs | |
| ramfs0 | |
| devfs | |
| devfs0 | |
| uimagefs | |
| pstore | |
| pstore0 | |
| fat | |
| virtio_blk | |
| virtio0 | |
| virtio_console | |
| cfi_flash | |
| 20000000.flash@20000000.of | |
| m25p80 | |
| gpio-spi | |
| i2c-gpio | |
| simple-framebuffer | |
| at24 | |
| mem | |
| mem0 | |
| mem1 | |
| virtio-rng | |
| virtio-mmio | |
| 10008000.virtio_mmio@10008000.of | |
| squashfs | |
| board-riscvemu | |
| Use 'devinfo DEVICE' for more information |
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| source riscv64-env.sh | |
| make clean | |
| make --silent --keep-going --jobs=12 O=/home/smalinux/.cache/tuxmake/builds/current ARCH=riscv CROSS_COMPILE=riscv64-linux- virt64_defconfig | |
| make ARCH=riscv virt64_defconfig | |
| make -j12 | |
| curl -L -o opensbi-riscv64-generic-fw_dynamic.bin https://github.com/qemu/qemu/blob/v5.2.0/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin?raw=true |
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| sohaib@barebox\<3 git log --oneline -20 | |
| bd28677a6 (HEAD -> master) common: boards: qemu-virt: genericize to support non-ARM architectures | |
| 5776022fc ARM: qemu: move board code to central location | |
| 801869d22 ARM: qemu: enable deep probe support | |
| c31c8479f of: overlay: rescan aliases calling of_overlay_apply_tree on live tree | |
| 45f6263b0 state: make first boot less verbose | |
| 1ff8315f7 state: mark state init errors specially | |
| f9e320b6f (origin/master, origin/HEAD) usb: dwc2: host: Do not map buffer on zero len packet | |
| 9d90cd027 Documentation/boards/riscv.rst: fix code blocks | |
| 81ceab953 Merge branch 'for-next/spdx' | |
| 0f89a1c65 Merge branch 'for-next/skov-imx6' | |
| 64f85586d Merge branch 'for-next/scripts-common-library' | |
| 0fdbd47ac Merge branch 'for-next/rockchip' | |
| 42cdd1452 Merge branch 'for-next/misc' | |
| 71f347dad Merge branch 'for-next/imx' | |
| 9525a9d93 Merge branch 'for-next/dts' | |
| e2c198488 (tag: v2021.11.0) Release v2021.11.0 | |
| 7a448cc54 efi: efi-iomem: fix erroneous use of IS_ENABLED() | |
| c0d1dd7c0 efi: efi-iomem: don't add EFI loader code/data as memory banks | |
| 462f3ca86 pci: efi: skip driver model fixup for non-EFI PCI busses | |
| d80921c93 dts: update to v5.15 |
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| barebox@riscv-virtio,qemu:/ of_dump / | |
| { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| compatible = "riscv-virtio"; | |
| model = "riscv-virtio,qemu"; | |
| reserved-memory { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| mmode_pmp0@80000000 { | |
| reg = <0x0 0x80000000 0x0 0x40000>; | |
| }; | |
| }; | |
| fw-cfg@10100000 { | |
| dma-coherent; | |
| reg = <0x0 0x10100000 0x0 0x18>; | |
| compatible = "qemu,fw-cfg-mmio"; | |
| }; | |
| chosen { | |
| bootargs = ""; | |
| stdout-path = "/soc/uart@10000000"; | |
| }; | |
| memory@80000000 { | |
| device_type = "memory"; | |
| reg = <0x0 0x80000000 0x0 0x80000000>; | |
| }; | |
| cpus { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| timebase-frequency = <0x989680>; | |
| cpu@0 { | |
| phandle = <0xf>; | |
| device_type = "cpu"; | |
| reg = <0x0>; | |
| status = "okay"; | |
| compatible = "riscv"; | |
| riscv,isa = "rv64imafdcsu"; | |
| mmu-type = "riscv,sv48"; | |
| interrupt-controller { | |
| #interrupt-cells = <0x1>; | |
| interrupt-controller; | |
| compatible = "riscv,cpu-intc"; | |
| phandle = <0x10>; | |
| }; | |
| }; | |
| cpu@1 { | |
| phandle = <0xd>; | |
| device_type = "cpu"; | |
| reg = <0x1>; | |
| status = "okay"; | |
| compatible = "riscv"; | |
| riscv,isa = "rv64imafdcsu"; | |
| mmu-type = "riscv,sv48"; | |
| interrupt-controller { | |
| #interrupt-cells = <0x1>; | |
| interrupt-controller; | |
| compatible = "riscv,cpu-intc"; | |
| phandle = <0xe>; | |
| }; | |
| }; | |
| cpu@2 { | |
| phandle = <0xb>; | |
| device_type = "cpu"; | |
| reg = <0x2>; | |
| status = "okay"; | |
| compatible = "riscv"; | |
| riscv,isa = "rv64imafdcsu"; | |
| mmu-type = "riscv,sv48"; | |
| interrupt-controller { | |
| #interrupt-cells = <0x1>; | |
| interrupt-controller; | |
| compatible = "riscv,cpu-intc"; | |
| phandle = <0xc>; | |
| }; | |
| }; | |
| cpu@3 { | |
| phandle = <0x9>; | |
| device_type = "cpu"; | |
| reg = <0x3>; | |
| status = "okay"; | |
| compatible = "riscv"; | |
| riscv,isa = "rv64imafdcsu"; | |
| mmu-type = "riscv,sv48"; | |
| interrupt-controller { | |
| #interrupt-cells = <0x1>; | |
| interrupt-controller; | |
| compatible = "riscv,cpu-intc"; | |
| phandle = <0xa>; | |
| }; | |
| }; | |
| cpu@4 { | |
| phandle = <0x7>; | |
| device_type = "cpu"; | |
| reg = <0x4>; | |
| status = "okay"; | |
| compatible = "riscv"; | |
| riscv,isa = "rv64imafdcsu"; | |
| mmu-type = "riscv,sv48"; | |
| interrupt-controller { | |
| #interrupt-cells = <0x1>; | |
| interrupt-controller; | |
| compatible = "riscv,cpu-intc"; | |
| phandle = <0x8>; | |
| }; | |
| }; | |
| cpu@5 { | |
| phandle = <0x5>; | |
| device_type = "cpu"; | |
| reg = <0x5>; | |
| status = "okay"; | |
| compatible = "riscv"; | |
| riscv,isa = "rv64imafdcsu"; | |
| mmu-type = "riscv,sv48"; | |
| interrupt-controller { | |
| #interrupt-cells = <0x1>; | |
| interrupt-controller; | |
| compatible = "riscv,cpu-intc"; | |
| phandle = <0x6>; | |
| }; | |
| }; | |
| cpu@6 { | |
| phandle = <0x3>; | |
| device_type = "cpu"; | |
| reg = <0x6>; | |
| status = "okay"; | |
| compatible = "riscv"; | |
| riscv,isa = "rv64imafdcsu"; | |
| mmu-type = "riscv,sv48"; | |
| interrupt-controller { | |
| #interrupt-cells = <0x1>; | |
| interrupt-controller; | |
| compatible = "riscv,cpu-intc"; | |
| phandle = <0x4>; | |
| }; | |
| }; | |
| cpu@7 { | |
| phandle = <0x1>; | |
| device_type = "cpu"; | |
| reg = <0x7>; | |
| status = "okay"; | |
| compatible = "riscv"; | |
| riscv,isa = "rv64imafdcsu"; | |
| mmu-type = "riscv,sv48"; | |
| interrupt-controller { | |
| #interrupt-cells = <0x1>; | |
| interrupt-controller; | |
| compatible = "riscv,cpu-intc"; | |
| phandle = <0x2>; | |
| }; | |
| }; | |
| cpu-map { | |
| cluster0 { | |
| core0 { | |
| cpu = <0xf>; | |
| }; | |
| core1 { | |
| cpu = <0xd>; | |
| }; | |
| core2 { | |
| cpu = <0xb>; | |
| }; | |
| core3 { | |
| cpu = <0x9>; | |
| }; | |
| core4 { | |
| cpu = <0x7>; | |
| }; | |
| core5 { | |
| cpu = <0x5>; | |
| }; | |
| core6 { | |
| cpu = <0x3>; | |
| }; | |
| core7 { | |
| cpu = <0x1>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| soc { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| compatible = "simple-bus"; | |
| ranges; | |
| flash@20000000 { | |
| bank-width = <0x4>; | |
| reg = <0x0 0x20000000 0x0 0x2000000 0x0 0x22000000 0x0 0x2000000>; | |
| compatible = "cfi-flash"; | |
| }; | |
| rtc@101000 { | |
| interrupts = <0xb>; | |
| interrupt-parent = <0x11>; | |
| reg = <0x0 0x101000 0x0 0x1000>; | |
| compatible = "google,goldfish-rtc"; | |
| }; | |
| uart@10000000 { | |
| interrupts = <0xa>; | |
| interrupt-parent = <0x11>; | |
| clock-frequency = "", "8@"; | |
| reg = <0x0 0x10000000 0x0 0x100>; | |
| compatible = "ns16550a"; | |
| }; | |
| poweroff { | |
| value = <0x5555>; | |
| offset = <0x0>; | |
| regmap = <0x12>; | |
| compatible = "syscon-poweroff"; | |
| }; | |
| reboot { | |
| value = <0x7777>; | |
| offset = <0x0>; | |
| regmap = <0x12>; | |
| compatible = "syscon-reboot"; | |
| }; | |
| test@100000 { | |
| phandle = <0x12>; | |
| reg = <0x0 0x100000 0x0 0x1000>; | |
| compatible = "sifive,test1", "sifive,test0", "syscon"; | |
| }; | |
| pci@30000000 { | |
| interrupt-map-mask = <0x1800 0x0 0x0 0x7>; | |
| interrupt-map = <0x0 0x0 0x0 0x1 0x11 0x20 0x0 0x0 0x0 0x2 0x11 0x21 0x0 0x0 0x0 0x3 0x11 0x22 0x0 0x0 0x0 0x4 0x11 0x23 0x800 0x0 0x0 0x1 0x11 0x21 0x800 0x0 0x0 0x2 0x11 0x22 0x800 0x0 0x0 0x3 0x11 0x23 0x800 0x0 0x0 0x4 0x11 0x20 0x1000 0x0 0x0 0x1 0x11 0x22 0x1000 0x0 0x0 0x2 0x11 0x23 0x1000 0x0 0x0 0x3 0x11 0x20 0x1000 0x0 0x0 0x4 0x11 0x21 0x1800 0x0 0x0 0x1 0x11 0x23 0x1800 0x0 0x0 0x2 0x11 0x20 0x1800 0x0 0x0 0x3 0x11 0x21 0x1800 0x0 0x0 0x4 0x11 0x22>; | |
| ranges = <0x1000000 0x0 0x0 0x0 0x3000000 0x0 0x10000 0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000 0x3000000 0x4 0x0 0x4 0x0 0x4 0x0>; | |
| reg = <0x0 0x30000000 0x0 0x10000000>; | |
| dma-coherent; | |
| bus-range = <0x0 0xff>; | |
| linux,pci-domain = <0x0>; | |
| device_type = "pci"; | |
| compatible = "pci-host-ecam-generic"; | |
| #size-cells = <0x2>; | |
| #interrupt-cells = <0x1>; | |
| #address-cells = <0x3>; | |
| }; | |
| virtio_mmio@10008000 { | |
| interrupts = <0x8>; | |
| interrupt-parent = <0x11>; | |
| reg = <0x0 0x10008000 0x0 0x1000>; | |
| compatible = "virtio,mmio"; | |
| }; | |
| virtio_mmio@10007000 { | |
| interrupts = <0x7>; | |
| interrupt-parent = <0x11>; | |
| reg = <0x0 0x10007000 0x0 0x1000>; | |
| compatible = "virtio,mmio"; | |
| }; | |
| virtio_mmio@10006000 { | |
| interrupts = <0x6>; | |
| interrupt-parent = <0x11>; | |
| reg = <0x0 0x10006000 0x0 0x1000>; | |
| compatible = "virtio,mmio"; | |
| }; | |
| virtio_mmio@10005000 { | |
| interrupts = <0x5>; | |
| interrupt-parent = <0x11>; | |
| reg = <0x0 0x10005000 0x0 0x1000>; | |
| compatible = "virtio,mmio"; | |
| }; | |
| virtio_mmio@10004000 { | |
| interrupts = <0x4>; | |
| interrupt-parent = <0x11>; | |
| reg = <0x0 0x10004000 0x0 0x1000>; | |
| compatible = "virtio,mmio"; | |
| }; | |
| virtio_mmio@10003000 { | |
| interrupts = <0x3>; | |
| interrupt-parent = <0x11>; | |
| reg = <0x0 0x10003000 0x0 0x1000>; | |
| compatible = "virtio,mmio"; | |
| }; | |
| virtio_mmio@10002000 { | |
| interrupts = <0x2>; | |
| interrupt-parent = <0x11>; | |
| reg = <0x0 0x10002000 0x0 0x1000>; | |
| compatible = "virtio,mmio"; | |
| }; | |
| virtio_mmio@10001000 { | |
| interrupts = <0x1>; | |
| interrupt-parent = <0x11>; | |
| reg = <0x0 0x10001000 0x0 0x1000>; | |
| compatible = "virtio,mmio"; | |
| }; | |
| plic@c000000 { | |
| phandle = <0x11>; | |
| riscv,ndev = <0x35>; | |
| reg = <0x0 0xc000000 0x0 0x210000>; | |
| interrupts-extended = <0x10 0xffffffff 0x10 0x9 0xe 0xffffffff 0xe 0x9 0xc 0xffffffff 0xc 0x9 0xa 0xffffffff 0xa 0x9 0x8 0xffffffff 0x8 0x9 0x6 0xffffffff 0x6 0x9 0x4 0xffffffff 0x4 0x9 0x2 0xffffffff 0x2 0x9>; | |
| interrupt-controller; | |
| compatible = "sifive,plic-1.0.0", "riscv,plic0"; | |
| #interrupt-cells = <0x1>; | |
| #address-cells = <0x0>; | |
| }; | |
| clint@2000000 { | |
| interrupts-extended = <0x10 0x3 0x10 0x7 0xe 0x3 0xe 0x7 0xc 0x3 0xc 0x7 0xa 0x3 0xa 0x7 0x8 0x3 0x8 0x7 0x6 0x3 0x6 0x7 0x4 0x3 0x4 0x7 0x2 0x3 0x2 0x7>; | |
| reg = <0x0 0x2000000 0x0 0x10000>; | |
| compatible = "sifive,clint0", "riscv,clint0"; | |
| }; | |
| }; | |
| }; |
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| #!/bin/bash | |
| export PATH=$HOME/repos/riscv/toolchain/riscv64-buildroot-linux-musl_sdk-buildroot/bin:$PATH | |
| export export ARCH=riscv | |
| export CROSS_COMPILE=riscv64-linux- |
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| qemu-system-riscv64 -M virt \ | |
| -cpu rv64 \ | |
| -smp 8 \ | |
| -m 2G \ | |
| -nographic \ | |
| -kernel barebox/images/barebox-dt-2nd.img \ | |
| -bios opensbi-riscv64-generic-fw_dynamic.bin \ | |
| -serial mon:stdio \ | |
| -drive id=hd0,format=raw,file=disk.img \ | |
| -device virtio-blk-device,drive=hd0 \ |
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