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stnolting/neorv32_cfs.vhd

Last active Mar 3, 2021
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WS2812 hardware interface for the NEORV32 processor (for HW version up to v1.5.2.0)
-- #################################################################################################
-- # << NEORV32 - Custom Functions Subsystem (CFS) >> #
-- # ********************************************************************************************* #
-- # WS2812-compatible hardware interface module. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_cfs is
generic (
CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000" -- custom CFS configuration conduit generic
);
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rstn_i : in std_ulogic; -- global reset line, low-active, use as async
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- word write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
-- CPU state --
sleep_i : in std_ulogic; -- set if cpu is in sleep mode
-- interrupt --
irq_o : out std_ulogic; -- interrupt request
irq_ack_i : in std_ulogic; -- interrupt acknowledge
-- custom io (conduits) --
cfs_in_i : in std_ulogic_vector(31 downto 0); -- custom inputs
cfs_out_o : out std_ulogic_vector(31 downto 0) -- custom outputs
);
end neorv32_cfs;
architecture neorv32_cfs_rtl of neorv32_cfs is
-- IO space: module base address (DO NOT MODIFY!) --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(cfs_size_c); -- low address boundary bit
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(31 downto 0); -- access address
signal wren : std_ulogic; -- word write enable
signal rden : std_ulogic; -- read enable
-- Control register bits --
constant ctrl_enable_c : natural := 0; -- r/w: module enable
constant ctrl_mode_c : natural := 1; -- r/w: 0 = 24-bit RGB mode, 1 = 32-bit RGBW mode
constant ctrl_clksel0_c : natural := 2; -- r/w: prescaler select bit 0
constant ctrl_clksel1_c : natural := 3; -- r/w: prescaler select bit 1
constant ctrl_clksel2_c : natural := 4; -- r/w: prescaler select bit 2
constant ctrl_ch_mask0_c : natural := 5; -- r/w: output channel enable mask bit 0
constant ctrl_ch_mask1_c : natural := 6; -- r/w: output channel enable mask bit 1
constant ctrl_ch_mask2_c : natural := 7; -- r/w: output channel enable mask bit 2
constant ctrl_ch_mask3_c : natural := 8; -- r/w: output channel enable mask bit 3
--
constant ctrl_t_tot_0_c : natural := 10; -- r/w: pulse-clock ticks per total period bit 0
constant ctrl_t_tot_1_c : natural := 11; -- r/w: pulse-clock ticks per total period bit 1
constant ctrl_t_tot_2_c : natural := 12; -- r/w: pulse-clock ticks per total period bit 2
constant ctrl_t_tot_3_c : natural := 13; -- r/w: pulse-clock ticks per total period bit 3
constant ctrl_t_tot_4_c : natural := 14; -- r/w: pulse-clock ticks per total period bit 4
--
constant ctrl_t_0h_0_c : natural := 15; -- r/w: pulse-clock ticks per ONE high-time bit 0
constant ctrl_t_0h_1_c : natural := 16; -- r/w: pulse-clock ticks per ONE high-time bit 1
constant ctrl_t_0h_2_c : natural := 17; -- r/w: pulse-clock ticks per ONE high-time bit 2
constant ctrl_t_0h_3_c : natural := 18; -- r/w: pulse-clock ticks per ONE high-time bit 3
constant ctrl_t_0h_4_c : natural := 19; -- r/w: pulse-clock ticks per ONE high-time bit 4
--
constant ctrl_t_1h_0_c : natural := 20; -- r/w: pulse-clock ticks per ZERO high-time bit 0
constant ctrl_t_1h_1_c : natural := 21; -- r/w: pulse-clock ticks per ZERO high-time bit 1
constant ctrl_t_1h_2_c : natural := 22; -- r/w: pulse-clock ticks per ZERO high-time bit 2
constant ctrl_t_1h_3_c : natural := 23; -- r/w: pulse-clock ticks per ZERO high-time bit 3
constant ctrl_t_1h_4_c : natural := 24; -- r/w: pulse-clock ticks per ZERO high-time bit 4
--
constant ctrl_busy_c : natural := 31; -- r/-: transmission in progress
-- control register --
type ctrl_t is record
enable : std_ulogic;
mode : std_ulogic;
clk_prsc : std_ulogic_vector(2 downto 0);
ch_mask : std_ulogic_vector(3 downto 0);
-- pulse config --
t_total : std_ulogic_vector(4 downto 0);
t0_high : std_ulogic_vector(4 downto 0);
t1_high : std_ulogic_vector(4 downto 0);
end record;
signal ctrl : ctrl_t;
-- serial engine --
type serial_t is record
-- state control --
busy : std_ulogic; -- unit is busy/idle
state : std_ulogic; -- state of pulse transmission
bit_cnt : std_ulogic_vector(5 downto 0);
-- shift register --
sreg : std_ulogic_vector(31 downto 0);
next_bit : std_ulogic; -- next bit to send
-- pulse generator --
pulse_clk : std_ulogic; -- pulse cycle "clock"
pulse_cnt : std_ulogic_vector(4 downto 0);
t_high : std_ulogic_vector(4 downto 0);
output : std_ulogic;
end record;
signal serial : serial_t;
begin
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfs_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= cfs_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
wren <= acc_en and wren_i;
rden <= acc_en and rden_i;
-- Read/Write Access ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
rw_access: process(clk_i)
begin
if rising_edge(clk_i) then
-- access acknowledge --
ack_o <= wren or rden;
-- write access: control register --
if (wren = '1') and (addr = cfs_reg0_addr_c) then
ctrl.enable <= data_i(ctrl_enable_c);
ctrl.mode <= data_i(ctrl_mode_c);
ctrl.clk_prsc <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
ctrl.ch_mask <= data_i(ctrl_ch_mask3_c downto ctrl_ch_mask0_c);
ctrl.t_total <= data_i(ctrl_t_tot_4_c downto ctrl_t_tot_0_c);
ctrl.t0_high <= data_i(ctrl_t_0h_4_c downto ctrl_t_0h_0_c);
ctrl.t1_high <= data_i(ctrl_t_1h_4_c downto ctrl_t_1h_0_c);
end if;
-- read access: control register --
data_o <= (others => '0');
if (rden = '1') and (addr = cfs_reg0_addr_c) then
data_o(ctrl_enable_c) <= ctrl.enable;
data_o(ctrl_mode_c) <= ctrl.mode;
data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl.clk_prsc;
data_o(ctrl_ch_mask3_c downto ctrl_ch_mask0_c) <= ctrl.ch_mask;
data_o(ctrl_t_tot_4_c downto ctrl_t_tot_0_c) <= ctrl.t_total;
data_o(ctrl_t_0h_4_c downto ctrl_t_0h_0_c) <= ctrl.t0_high;
data_o(ctrl_t_1h_4_c downto ctrl_t_1h_0_c) <= ctrl.t1_high;
data_o(ctrl_busy_c) <= serial.busy;
end if;
end if;
end process rw_access;
-- enable external clock generator --
clkgen_en_o <= ctrl.enable;
-- Serial TX Engine -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
serial_engine: process(clk_i)
begin
if rising_edge(clk_i) then
-- defaults --
serial.pulse_clk <= clkgen_i(to_integer(unsigned(ctrl.clk_prsc)));
-- idle or disabled --
if (serial.busy = '0') or (ctrl.enable = '0') then -- idle or disabled
serial.output <= '0';
serial.busy <= '0';
serial.state <= '0';
serial.pulse_cnt <= (others => '0');
if (ctrl.mode = '0') then -- "RGB" mode
serial.bit_cnt <= "011000"; -- total number of bits to send: 3x8=24
else -- "RGBW" mode
serial.bit_cnt <= "100000"; -- total number of bits to send: 4x8=32
end if;
if (ctrl.enable = '0') then
serial.busy <= '0';
elsif (wren = '1') and (addr = cfs_reg1_addr_c) then
serial.sreg <= data_i;
serial.busy <= '1';
end if;
else
-- get next TX bit --
if (serial.state = '0') then
serial.sreg <= serial.sreg(serial.sreg'left-1 downto 0) & '0'; -- shift left by one position (MSB-first)
serial.bit_cnt <= std_ulogic_vector(unsigned(serial.bit_cnt) - 1);
serial.pulse_cnt <= (others => '0');
if (serial.bit_cnt = "000000") then -- all done?
serial.busy <= '0';
else -- check current data MSB
if (serial.next_bit = '0') then -- send zero-bit
serial.t_high <= ctrl.t0_high;
else -- send one-bit
serial.t_high <= ctrl.t1_high;
end if;
serial.state <= '1'; -- transmit single pulse
serial.output <= '1';
end if;
-- send pulse with specific duty cycle --
-- total pulse length = ctrl.t_total
-- pulse high time = serial.t_high
else
if (serial.pulse_clk = '1') then
serial.pulse_cnt <= std_ulogic_vector(unsigned(serial.pulse_cnt) + 1);
-- T_high reached? --
if (serial.pulse_cnt = serial.t_high) then
serial.output <= '0';
end if;
-- T_total reached? --
if (serial.pulse_cnt = ctrl.t_total) then
serial.state <= '0'; -- get next bit to send
end if;
end if;
end if;
end if;
end if;
end process serial_engine;
-- SREG's TX data: bit 23 for RGB mode, bit 31 for RGBW mode --
serial.next_bit <= serial.sreg(23) when (ctrl.mode = '0') else serial.sreg(31);
irq_o <= '0'; -- FIXME
-- Channel Select -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
channel_sel: process(clk_i)
begin
if rising_edge(clk_i) then
cfs_out_o <= (others => '0');
for i in 0 to 3 loop
cfs_out_o(i) <= serial.output and ctrl.ch_mask(i);
end loop; -- i
end if;
end process channel_sel;
end neorv32_cfs_rtl;
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