the6p4c

You don't actually have to download the entire (now over 100 GiB) unified installer.

The self-extracting web installer (~300 MiB) can create a customised bundle identical to the unified installer - thus only downloading the components you require. Here's what I did to install Vivado and support for Artix 7 only, so no guarantees that this works in general. Keep in mind that version numbers and dates may have changed.

1. Download the “AMD Unified Installer for FPGAs & Adaptive SoCs 2023.2: Linux Self Extracting Web Installer”
   • This is a binary with a name like FPGAs_AdaptiveSoCs_Unified_2023.2_1013_2256_Lin64.bin
2. Create the archive
   1. Run the installer (chmod +x the binary and launch it from a shell)
      • Flags to the installer binary must be provider after -- so as to not pass them to the makeself wrapper

• Passing the --xdebug flag to the installer

the6p4c

from enum import Enum
from nmigen import *
from nmigen.asserts import *
from nmigen.sim import pysim

class Opcodes(Enum):
    NOPO = 0x0
    LD = 0x1
    LDC = 0x2
    AND = 0x3

the6p4c

#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#include <sys/io.h>
#include <sys/mman.h>
#include "elf.h"

the6p4c

import sys

def main():
    input_file = sys.argv[1]
    output_file = sys.argv[2]

    with open(input_file, 'rb') as f_in, open(output_file, 'wb') as f_out:
        decompressed_length = int.from_bytes(f_in.read(4), 'little')
        bytes_written = 0

the6p4c

`default_nettype none

module top(input CLK, output PIN_24);
	wire tx_buf_empty;
	reg tx_data_ready;
	reg [7:0] tx_data;

	uart_tx #(
		.BAUD_DIVISOR(16000000 / 115200)
	) uart_tx_inst (

the6p4c

// Build with gcc -o bug bug.c
//
// Prints non-NULL address of y when executed outside of valgrind, and a NULL
// (rendered as "(nil)" by printf) when executed inside valgrind.
#include <stdio.h>
#include <stdlib.h>
#include <sys/ipc.h>
#include <sys/shm.h>
#include <sys/stat.h>
#include <sys/types.h>

the6p4c

/* !heavily! work in progress */
MEMORY {
	ram (rwx) : org = 0x00000000, l = 64K
	user (rx) : org = 0xFFF80000, l = 512K
}

SECTIONS {
	.text : {
		*(.text)
		*(.text*)

the6p4c

from nmigen import *
from nmigen.cli import main

class Test:
    def __init__(self):
        self.out = Signal(8)

    def get_fragment(self, platform):
        data = list(range(10))
        arr = Array(data)

the6p4c

LAI x (01XX)
	load accumulator immediate
	acc = x
LAM x (02XX)
	load accumulator memory
	acc = mem[x]
LAI x (0300)
	load accumulator memory indirect
	acc = mem[mem[0]]
SAM x (04XX)

the6p4c

def generate_stacks(n):
	if n == 1:
		yield (True,)
		yield (False,)
	else:
		for stack in generate_stacks(n - 1):
			yield stack + (True,)
			yield stack + (False,)

def stack_flip(stack, n):