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Modified ramintfc_jtag.vhd file to use the MySdramCntl.vhd
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---------------------------------------------------------------------------------- | |
-- This program is free software; you can redistribute it and/or | |
-- modify it under the terms of the GNU General Public License | |
-- as published by the Free Software Foundation; either version 2 | |
-- of the License, or (at your option) any later version. | |
-- | |
-- This program is distributed in the hope that it will be useful, | |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
-- GNU General Public License for more details. | |
-- | |
-- You should have received a copy of the GNU General Public License | |
-- along with this program; if not, write to the Free Software | |
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA | |
-- 02111-1307, USA. | |
-- | |
-- 1997-2012 - X Engineering Software Systems Corp. (www.xess.com) | |
---------------------------------------------------------------------------------- | |
---------------------------------------------------------------------------------- | |
-- SDRAM/RAM upload/download via JTAG. | |
-- See userinstr_jtag.vhd for details of operation. | |
-------------------------------------------------------------------- | |
library IEEE, XESS; | |
use IEEE.STD_LOGIC_1164.all; | |
use IEEE.numeric_std.all; | |
use XESS.CommonPckg.all; | |
use XESS.HostIoPckg.all; | |
use XESS.SdramCntlPckg.all; | |
use XESS.ClkgenPckg.all; | |
use XESS.SyncToClockPckg.all; | |
use work.XessBoardPckg.all; | |
use work.pck_myhdl_10.all; | |
use work.all; | |
entity ramintfc_jtag is | |
generic( | |
ID_G : std_logic_vector := "00000011"; -- The ID this module responds to. | |
BASE_FREQ_G : real := BASE_FREQ_C; | |
CLK_MUL_G : natural := 25; -- Multiplier for base frequency. | |
CLK_DIV_G : natural := 3; -- Divider for base frequency. | |
PIPE_EN_G : boolean := true | |
); | |
port( | |
fpgaClk_i : in std_logic; -- Main clock input from external clock source. | |
sdClk_o : out std_logic; -- Clock to SDRAM. | |
sdClkFb_i : in std_logic; -- SDRAM clock comes back in. | |
sdCke_o : out std_logic; -- Clock-enable to SDRAM. | |
sdCe_bo : out std_logic; -- Chip-select to SDRAM. | |
sdRas_bo : out std_logic; -- SDRAM row address strobe. | |
sdCas_bo : out std_logic; -- SDRAM column address strobe. | |
sdWe_bo : out std_logic; -- SDRAM write enable. | |
sdBs_o : out std_logic_vector(1 downto 0); -- SDRAM bank address. | |
sdAddr_o : out std_logic_vector(SDRAM_SADDR_WIDTH_C-1 downto 0); -- SDRAM row/column address. | |
sdData_io : inout unsigned(15 downto 0); -- Data to/from SDRAM. | |
sdDqmh_o : out std_logic; -- Enable upper-byte of SDRAM databus if true. | |
sdDqml_o : out std_logic -- Enable lower-byte of SDRAM databus if true. | |
); | |
end entity; | |
architecture arch of ramintfc_jtag is | |
constant FREQ_G : real := (BASE_FREQ_C * real(CLK_MUL_G)) / real(CLK_DIV_G); | |
signal clk_s : std_logic; | |
signal reset_s : std_logic := YES; | |
component MySdramCntl | |
port ( | |
clk_i: in std_logic; | |
sd_intf_cke: out std_logic; | |
sd_intf_we: out std_logic; | |
sd_intf_addr: out unsigned(12 downto 0); | |
sd_intf_dqml: out std_logic; | |
sd_intf_cas: out std_logic; | |
sd_intf_dqmh: out std_logic; | |
sd_intf_ras: out std_logic; | |
sd_intf_bs: out unsigned(1 downto 0); | |
sd_intf_cs: out std_logic; | |
sd_intf_dq: inout unsigned(15 downto 0); | |
host_intf_wr_i: in std_logic; | |
host_intf_done_o: out std_logic; | |
host_intf_rdPending_o: out std_logic; | |
host_intf_rst_i: in std_logic; | |
host_intf_data_i: in unsigned(15 downto 0); | |
host_intf_data_o: out unsigned(15 downto 0); | |
host_intf_rd_i: in std_logic; | |
host_intf_addr_i: in unsigned(23 downto 0) | |
); | |
end component; | |
-- signals to/from the SDRAM controller | |
signal rd_s : std_logic; -- host read enable | |
signal wr_s : std_logic; -- host write enable | |
signal opBegun_s : std_logic; -- true when current read/write has begun. | |
signal done_s : std_logic; -- true when current read/write is done | |
signal addr_s : std_logic_vector(SDRAM_HADDR_WIDTH_C-1 downto 0); -- host address | |
signal dataToRam_s : std_logic_vector(SDRAM_DATA_WIDTH_C-1 downto 0); -- data input from host | |
signal dataFromRam_s : std_logic_vector(SDRAM_DATA_WIDTH_C-1 downto 0); -- host data output to host | |
signal my_addr_s : unsigned(SDRAM_HADDR_WIDTH_C-1 downto 0); -- host address | |
signal my_dataToRam_s : unsigned(SDRAM_DATA_WIDTH_C-1 downto 0); -- data input from host | |
signal my_dataFromRam_s : unsigned(SDRAM_DATA_WIDTH_C-1 downto 0); -- host data output to host | |
signal my_sdBs_o : unsigned(1 downto 0); -- SDRAM bank address. | |
signal my_sdAddr_o : unsigned(SDRAM_SADDR_WIDTH_C-1 downto 0); -- SDRAM row/column address. | |
signal my_sdData_io : unsigned(SDRAM_DATA_WIDTH_C-1 downto 0); | |
begin | |
-- Generate a 100 MHz clock from the 12 MHz input clock. | |
u0 : Clkgen | |
generic map (BASE_FREQ_G => BASE_FREQ_G, CLK_MUL_G => CLK_MUL_G, CLK_DIV_G => CLK_DIV_G) | |
port map(I => fpgaClk_i, clkToLogic_o => sdClk_o); | |
clk_s <= sdClkFb_i; -- Main clock is SDRAM clock fed back into FPGA. | |
-- Generate reset signal for SDRAM controller. | |
process(clk_s) | |
variable resetCnt_v : natural range 0 to 15 := 10; | |
begin | |
if rising_edge(clk_s) then | |
reset_s <= YES; | |
if resetCnt_v = 0 then | |
reset_s <= NO; | |
else | |
resetCnt_v := resetCnt_v - 1; | |
end if; | |
end if; | |
end process; | |
u3 : HostIoToRam | |
generic map( | |
ID_G => ID_G, -- The ID this module responds to. | |
SIMPLE_G => true, -- If true, include BscanToHostIo module in this module. | |
SYNC_G => true -- If true, sync this module with the FPGA app. logic clock domain. | |
) | |
port map( | |
reset_i => reset_s, -- Active-high reset signal. | |
-- Interface to the memory. | |
clk_i => clk_s, -- Clock from FPGA application logic. | |
addr_o => addr_s, -- Address to memory. | |
wr_o => wr_s, -- Write data to memory when high. | |
dataFromHost_o => dataToRam_s, -- Data written to memory. | |
rd_o => rd_s, -- Read data from memory when high. | |
dataToHost_i => dataFromRam_s, -- Data read from memory. | |
opBegun_i => opBegun_s, -- True when R/W operation has initiated. | |
done_i => done_s -- True when memory read/write operation is done. | |
); | |
-- SDRAM controller | |
u4 : MySdramCntl | |
port map( | |
clk_i => clk_s, -- master clock from external clock source (unbuffered) | |
--lock_i => YES, -- no DLLs, so frequency is always locked | |
host_intf_rst_i => reset_s, -- reset | |
host_intf_rd_i => rd_s, -- host-side SDRAM read control from memory tester | |
host_intf_wr_i => wr_s, -- host-side SDRAM write control from memory tester | |
--opBegun_o => opBegun_s, -- SDRAM memory read/write begun indicator | |
host_intf_done_o => done_s, -- SDRAM memory read/write done indicator | |
host_intf_addr_i => my_addr_s, -- host-side address from memory tester to SDRAM | |
host_intf_data_i => my_dataToRam_s, -- test data pattern from memory tester to SDRAM | |
host_intf_data_o => my_dataFromRam_s, -- SDRAM data output to memory tester | |
sd_intf_cke => sdCke_o, | |
sd_intf_cs => sdCe_bo, | |
sd_intf_ras => sdRas_bo, -- SDRAM RAS | |
sd_intf_cas => sdCas_bo, -- SDRAM CAS | |
sd_intf_we => sdWe_bo, -- SDRAM write-enable | |
sd_intf_bs => my_sdBs_o, -- SDRAM bank address | |
sd_intf_addr => my_sdAddr_o, -- SDRAM address | |
sd_intf_dq => sdData_io, -- data to/from SDRAM | |
sd_intf_dqmh => sdDqmh_o, -- upper-byte enable for SDRAM data bus. | |
sd_intf_dqml => sdDqml_o -- lower-byte enable for SDRAM data bus. | |
); | |
my_addr_s <= unsigned(addr_s); | |
my_dataToRam_s <= unsigned(dataToRam_s); | |
dataFromRam_s <= std_logic_vector(my_dataFromRam_s); | |
sdBs_o <= std_logic_vector(my_sdBs_o); | |
sdAddr_o <= std_logic_vector(my_sdAddr_o); | |
--my_sdData_io <= unsigned(sdData_io); | |
end architecture; |
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