Skip to content

Instantly share code, notes, and snippets.

@uenoku

uenoku/fpu.sv

Created December 10, 2021 16:47
Show Gist options
  • Star 1 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save uenoku/949bc54690506fbdd9dfa5aecf21083f to your computer and use it in GitHub Desktop.
Save uenoku/949bc54690506fbdd9dfa5aecf21083f to your computer and use it in GitHub Desktop.
Download ZIP
Raw
fpu.sv
// Standard header to adapt well known macros to our needs.
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM {$random}
`endif
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif
`else
`define INIT_RANDOM_PROLOG_
`endif
module FIRRTLMem_3_2_0_65_32_0_1_1_0_1_aa( // FPU.scala:547:20
input [4:0] R0_addr,
input R0_en, R0_clk,
input [4:0] R1_addr,
input R1_en, R1_clk,
input [4:0] R2_addr,
input R2_en, R2_clk,
input [4:0] W0_addr,
input W0_en, W0_clk,
input [64:0] W0_data,
input W0_mask,
input [4:0] W1_addr,
input W1_en, W1_clk,
input [64:0] W1_data,
input W1_mask,
output [64:0] R0_data, R1_data, R2_data);
reg [64:0] Memory[0:31];
always @(posedge W0_clk) begin
if (W0_en & W0_mask)
Memory[W0_addr] <= W0_data;
if (W1_en & W1_mask)
Memory[W1_addr] <= W1_data;
end // always @(posedge)
assign R0_data = R0_en ? Memory[R0_addr] : 65'bx; // FPU.scala:547:20
assign R1_data = R1_en ? Memory[R1_addr] : 65'bx; // FPU.scala:547:20
assign R2_data = R2_en ? Memory[R2_addr] : 65'bx; // FPU.scala:547:20
endmodule
module FPU( // ../perf/regress/FPU.fir:3:10
input clock,
input reset,
input [31:0] io_inst,
input [63:0] io_fromint_data,
input [2:0] io_fcsr_rm,
input io_dmem_resp_val,
input [2:0] io_dmem_resp_type,
input [4:0] io_dmem_resp_tag,
input [63:0] io_dmem_resp_data,
input io_valid,
input io_killx,
input io_killm,
input io_cp_req_valid,
input struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } io_cp_req_bits,
input io_cp_resp_ready,
output struct packed {logic valid; logic [4:0] bits; } io_fcsr_flags,
output [63:0] io_store_data,
output [63:0] io_toint_data,
output io_fcsr_rdy,
output io_nack_mem,
output io_illegal_rm,
output struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; } io_dec,
output io_sboard_set,
output io_sboard_clr,
output [4:0] io_sboard_clra,
output io_cp_req_ready,
output io_cp_resp_valid,
output struct packed {logic [64:0] data; logic [4:0] exc; } io_cp_resp_bits);
wire [4:0] _T; // FPU.scala:750:43
wire [64:0] _T_0; // FPU.scala:749:25
wire _T_1; // FPU.scala:723:27
wire [32:0] RecFNToRecFN_io_out; // FPU.scala:746:34
wire [4:0] RecFNToRecFN_io_exceptionFlags; // FPU.scala:746:34
wire DivSqrtRecF64_io_inReady_div; // FPU.scala:722:25
wire DivSqrtRecF64_io_inReady_sqrt; // FPU.scala:722:25
wire DivSqrtRecF64_io_outValid_div; // FPU.scala:722:25
wire DivSqrtRecF64_io_outValid_sqrt; // FPU.scala:722:25
wire [64:0] DivSqrtRecF64_io_out; // FPU.scala:722:25
wire [4:0] DivSqrtRecF64_io_exceptionFlags; // FPU.scala:722:25
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } FPUFMAPipe_io_out; // FPU.scala:624:28
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } fpmu_io_out; // FPU.scala:603:20
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } ifpu_io_out; // FPU.scala:598:20
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } fpiu_io_as_double; // FPU.scala:588:20
wire struct packed {logic valid; struct packed {logic lt; logic [63:0] store; logic [63:0] toint; logic [4:0] exc; } bits; } fpiu_io_out; // FPU.scala:588:20
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } sfma_io_out; // FPU.scala:584:20
wire [64:0] regfile_R0_data; // FPU.scala:547:20
wire [64:0] regfile_R1_data; // FPU.scala:547:20
wire [64:0] regfile_R2_data; // FPU.scala:547:20
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; } fp_decoder_io_sigs; // FPU.scala:520:26
wire struct packed {logic valid; logic [4:0] bits; } _io_fcsr_flags_output; // ../perf/regress/FPU.fir:3:10
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; } _io_dec_output; // ../perf/regress/FPU.fir:3:10
wire struct packed {logic [64:0] data; logic [4:0] exc; } _io_cp_resp_bits_output; // ../perf/regress/FPU.fir:3:10
reg ex_reg_valid; // FPU.scala:509:25
reg [31:0] ex_reg_inst; // Reg.scala:34:16
reg mem_reg_valid; // FPU.scala:513:26
reg [31:0] mem_reg_inst; // Reg.scala:34:16
reg mem_cp_valid; // FPU.scala:515:25
reg wb_reg_valid; // FPU.scala:517:25
reg wb_cp_valid; // FPU.scala:518:24
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; } cp_ctrl; // FPU.scala:523:21
struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; } _T_2_20; // Reg.scala:34:16
struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; } mem_ctrl; // Reg.scala:34:16
struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; } wb_ctrl; // Reg.scala:34:16
reg load_wb; // FPU.scala:534:20
reg load_wb_single; // Reg.scala:34:16
reg [63:0] load_wb_data; // Reg.scala:34:16
reg [4:0] load_wb_tag; // Reg.scala:34:16
reg [4:0] ex_ra1; // FPU.scala:554:53
reg [4:0] ex_ra2; // FPU.scala:554:53
reg [4:0] ex_ra3; // FPU.scala:554:53
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } req; // FPU.scala:569:17
wire struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } _io_in_wire; // FPU.scala:584:20
wire struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } _io_in_wire_3; // FPU.scala:588:20
wire struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } _io_in_wire_4; // FPU.scala:598:20
wire struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } _io_in_wire_5; // FPU.scala:603:20
reg divSqrt_wen; // FPU.scala:608:24
reg [4:0] divSqrt_waddr; // FPU.scala:610:26
reg divSqrt_single; // FPU.scala:611:27
reg divSqrt_in_flight; // FPU.scala:614:30
reg divSqrt_killed; // FPU.scala:615:27
wire struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } _io_in_wire_6; // FPU.scala:624:28
reg [2:0] wen; // FPU.scala:645:16
struct packed {logic [4:0] rd; logic single; logic cp; logic [1:0] pipeid; }[2:0] wbInfo; // FPU.scala:646:19
reg write_port_busy; // Reg.scala:34:16
reg [4:0] wb_toint_exc; // Reg.scala:34:16
reg _T_7_179; // FPU.scala:708:55
reg [1:0] _T_8_180; // FPU.scala:718:25
reg [4:0] _T_9_181; // FPU.scala:719:35
reg [64:0] _T_10_182; // FPU.scala:720:35
assign _io_cp_resp_bits_output.exc = 5'h0; // ../perf/regress/FPU.fir:8:8, :9:8
wire _T_2 = ex_reg_valid | io_cp_req_valid; // FPU.scala:510:32
wire _T_3 = ~ex_reg_valid & io_cp_req_valid; // Decoupled.scala:30:37, FPU.scala:510:32, :693:22
wire [4:0] _T_4 = io_cp_req_bits.cmd; // FPU.scala:524:11
assign cp_ctrl.cmd = _T_4; // FPU.scala:524:11
wire _T_5 = io_cp_req_bits.ldst; // FPU.scala:524:11
assign cp_ctrl.ldst = _T_5; // FPU.scala:524:11
wire _T_6 = io_cp_req_bits.wen; // FPU.scala:524:11
assign cp_ctrl.wen = _T_6; // FPU.scala:524:11
wire _T_7 = io_cp_req_bits.ren1; // FPU.scala:524:11
assign cp_ctrl.ren1 = _T_7; // FPU.scala:524:11
wire _T_8 = io_cp_req_bits.ren2; // FPU.scala:524:11
assign cp_ctrl.ren2 = _T_8; // FPU.scala:524:11
wire _T_9 = io_cp_req_bits.ren3; // FPU.scala:524:11
assign cp_ctrl.ren3 = _T_9; // FPU.scala:524:11
wire _T_10 = io_cp_req_bits.swap12; // FPU.scala:524:11
assign cp_ctrl.swap12 = _T_10; // FPU.scala:524:11
wire _T_11 = io_cp_req_bits.swap23; // FPU.scala:524:11
assign cp_ctrl.swap23 = _T_11; // FPU.scala:524:11
wire _T_12 = io_cp_req_bits.single; // FPU.scala:524:11
assign cp_ctrl.single = _T_12; // FPU.scala:524:11
wire _T_13 = io_cp_req_bits.fromint; // FPU.scala:524:11
assign cp_ctrl.fromint = _T_13; // FPU.scala:524:11
wire _T_14 = io_cp_req_bits.toint; // FPU.scala:524:11
assign cp_ctrl.toint = _T_14; // FPU.scala:524:11
wire _T_15 = io_cp_req_bits.fastpipe; // FPU.scala:524:11
assign cp_ctrl.fastpipe = _T_15; // FPU.scala:524:11
wire _T_16 = io_cp_req_bits.fma; // FPU.scala:524:11
assign cp_ctrl.fma = _T_16; // FPU.scala:524:11
wire _T_17 = io_cp_req_bits.div; // FPU.scala:524:11
assign cp_ctrl.div = _T_17; // FPU.scala:524:11
wire _T_18 = io_cp_req_bits.sqrt; // FPU.scala:524:11
assign cp_ctrl.sqrt = _T_18; // FPU.scala:524:11
wire _T_19 = io_cp_req_bits.wflags; // FPU.scala:524:11
assign cp_ctrl.wflags = _T_19; // FPU.scala:524:11
wire [4:0] _T_21 = _T_2_20.cmd; // Reg.scala:34:16
wire _T_22 = _T_2_20.ldst; // Reg.scala:34:16
wire _T_23 = _T_2_20.wen; // Reg.scala:34:16
wire _T_24 = _T_2_20.ren1; // Reg.scala:34:16
wire _T_25 = _T_2_20.ren2; // Reg.scala:34:16
wire _T_26 = _T_2_20.ren3; // Reg.scala:34:16
wire _T_27 = _T_2_20.swap12; // Reg.scala:34:16
wire _T_28 = _T_2_20.swap23; // Reg.scala:34:16
wire _T_29 = _T_2_20.single; // Reg.scala:34:16
wire _T_30 = _T_2_20.fromint; // Reg.scala:34:16
wire _T_31 = _T_2_20.toint; // Reg.scala:34:16
wire _T_32 = _T_2_20.fastpipe; // Reg.scala:34:16
wire _T_33 = _T_2_20.fma; // Reg.scala:34:16
wire _T_34 = _T_2_20.div; // Reg.scala:34:16
wire _T_35 = _T_2_20.sqrt; // Reg.scala:34:16
wire _T_36 = _T_2_20.wflags; // Reg.scala:34:16
wire [4:0] _T_37 = fp_decoder_io_sigs.cmd; // FPU.scala:520:26, Reg.scala:35:23
assign _T_21 = io_valid ? _T_37 : _T_21; // Reg.scala:35:23
wire _T_38 = fp_decoder_io_sigs.ldst; // FPU.scala:520:26, Reg.scala:35:23
assign _T_22 = io_valid ? _T_38 : _T_22; // Reg.scala:35:23
wire _T_39 = fp_decoder_io_sigs.wen; // FPU.scala:520:26, Reg.scala:35:23
assign _T_23 = io_valid ? _T_39 : _T_23; // Reg.scala:35:23
wire _T_40 = fp_decoder_io_sigs.ren1; // FPU.scala:520:26, Reg.scala:35:23
assign _T_24 = io_valid ? _T_40 : _T_24; // Reg.scala:35:23
wire _T_41 = fp_decoder_io_sigs.ren2; // FPU.scala:520:26, Reg.scala:35:23
assign _T_25 = io_valid ? _T_41 : _T_25; // Reg.scala:35:23
wire _T_42 = fp_decoder_io_sigs.ren3; // FPU.scala:520:26, Reg.scala:35:23
assign _T_26 = io_valid ? _T_42 : _T_26; // Reg.scala:35:23
wire _T_43 = fp_decoder_io_sigs.swap12; // FPU.scala:520:26, Reg.scala:35:23
assign _T_27 = io_valid ? _T_43 : _T_27; // Reg.scala:35:23
wire _T_44 = fp_decoder_io_sigs.swap23; // FPU.scala:520:26, Reg.scala:35:23
assign _T_28 = io_valid ? _T_44 : _T_28; // Reg.scala:35:23
wire _T_45 = fp_decoder_io_sigs.single; // FPU.scala:520:26, Reg.scala:35:23
assign _T_29 = io_valid ? _T_45 : _T_29; // Reg.scala:35:23
wire _T_46 = fp_decoder_io_sigs.fromint; // FPU.scala:520:26, Reg.scala:35:23
assign _T_30 = io_valid ? _T_46 : _T_30; // Reg.scala:35:23
wire _T_47 = fp_decoder_io_sigs.toint; // FPU.scala:520:26, Reg.scala:35:23
assign _T_31 = io_valid ? _T_47 : _T_31; // Reg.scala:35:23
wire _T_48 = fp_decoder_io_sigs.fastpipe; // FPU.scala:520:26, Reg.scala:35:23
assign _T_32 = io_valid ? _T_48 : _T_32; // Reg.scala:35:23
wire _T_49 = fp_decoder_io_sigs.fma; // FPU.scala:520:26, Reg.scala:35:23
assign _T_33 = io_valid ? _T_49 : _T_33; // Reg.scala:35:23
wire _T_50 = fp_decoder_io_sigs.div; // FPU.scala:520:26, Reg.scala:35:23
assign _T_34 = io_valid ? _T_50 : _T_34; // Reg.scala:35:23
wire _T_51 = fp_decoder_io_sigs.sqrt; // FPU.scala:520:26, Reg.scala:35:23
assign _T_35 = io_valid ? _T_51 : _T_35; // Reg.scala:35:23
wire _T_52 = fp_decoder_io_sigs.wflags; // FPU.scala:520:26, Reg.scala:35:23
assign _T_36 = io_valid ? _T_52 : _T_36; // Reg.scala:35:23
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; } _T_53 = _T_3 ? cp_ctrl : _T_2_20; // FPU.scala:529:20
wire [4:0] _T_54 = mem_ctrl.cmd; // Reg.scala:34:16
wire _T_55 = mem_ctrl.ldst; // Reg.scala:34:16
wire _T_56 = mem_ctrl.wen; // Reg.scala:34:16
wire _T_57 = mem_ctrl.ren1; // Reg.scala:34:16
wire _T_58 = mem_ctrl.ren2; // Reg.scala:34:16
wire _T_59 = mem_ctrl.ren3; // Reg.scala:34:16
wire _T_60 = mem_ctrl.swap12; // Reg.scala:34:16
wire _T_61 = mem_ctrl.swap23; // Reg.scala:34:16
wire _T_62 = mem_ctrl.single; // Reg.scala:34:16
wire _T_63 = mem_ctrl.fromint; // Reg.scala:34:16
wire _T_64 = mem_ctrl.toint; // Reg.scala:34:16
wire _T_65 = mem_ctrl.fastpipe; // Reg.scala:34:16
wire _T_66 = mem_ctrl.fma; // Reg.scala:34:16
wire _T_67 = mem_ctrl.div; // Reg.scala:34:16
wire _T_68 = mem_ctrl.sqrt; // Reg.scala:34:16
wire _T_69 = mem_ctrl.wflags; // Reg.scala:34:16
wire [4:0] _T_70 = _T_53.cmd; // Reg.scala:35:23
assign _T_54 = _T_2 ? _T_70 : _T_54; // Reg.scala:35:23
wire _T_71 = _T_53.ldst; // Reg.scala:35:23
assign _T_55 = _T_2 ? _T_71 : _T_55; // Reg.scala:35:23
wire _T_72 = _T_53.wen; // Reg.scala:35:23
assign _T_56 = _T_2 ? _T_72 : _T_56; // Reg.scala:35:23
wire _T_73 = _T_53.ren1; // Reg.scala:35:23
assign _T_57 = _T_2 ? _T_73 : _T_57; // Reg.scala:35:23
wire _T_74 = _T_53.ren2; // Reg.scala:35:23
assign _T_58 = _T_2 ? _T_74 : _T_58; // Reg.scala:35:23
wire _T_75 = _T_53.ren3; // Reg.scala:35:23
assign _T_59 = _T_2 ? _T_75 : _T_59; // Reg.scala:35:23
wire _T_76 = _T_53.swap12; // Reg.scala:35:23
assign _T_60 = _T_2 ? _T_76 : _T_60; // Reg.scala:35:23
wire _T_77 = _T_53.swap23; // Reg.scala:35:23
assign _T_61 = _T_2 ? _T_77 : _T_61; // Reg.scala:35:23
wire _T_78 = _T_53.single; // Reg.scala:35:23
assign _T_62 = _T_2 ? _T_78 : _T_62; // Reg.scala:35:23
wire _T_79 = _T_53.fromint; // Reg.scala:35:23
assign _T_63 = _T_2 ? _T_79 : _T_63; // Reg.scala:35:23
wire _T_80 = _T_53.toint; // Reg.scala:35:23
assign _T_64 = _T_2 ? _T_80 : _T_64; // Reg.scala:35:23
wire _T_81 = _T_53.fastpipe; // Reg.scala:35:23
assign _T_65 = _T_2 ? _T_81 : _T_65; // Reg.scala:35:23
wire _T_82 = _T_53.fma; // Reg.scala:35:23
assign _T_66 = _T_2 ? _T_82 : _T_66; // Reg.scala:35:23
wire _T_83 = _T_53.div; // Reg.scala:35:23
assign _T_67 = _T_2 ? _T_83 : _T_67; // Reg.scala:35:23
wire _T_84 = _T_53.sqrt; // Reg.scala:35:23
assign _T_68 = _T_2 ? _T_84 : _T_68; // Reg.scala:35:23
wire _T_85 = _T_53.wflags; // Reg.scala:35:23
assign _T_69 = _T_2 ? _T_85 : _T_69; // Reg.scala:35:23
wire [4:0] _T_86 = wb_ctrl.cmd; // Reg.scala:34:16
wire _T_87 = wb_ctrl.ldst; // Reg.scala:34:16
wire _T_88 = wb_ctrl.wen; // Reg.scala:34:16
wire _T_89 = wb_ctrl.ren1; // Reg.scala:34:16
wire _T_90 = wb_ctrl.ren2; // Reg.scala:34:16
wire _T_91 = wb_ctrl.ren3; // Reg.scala:34:16
wire _T_92 = wb_ctrl.swap12; // Reg.scala:34:16
wire _T_93 = wb_ctrl.swap23; // Reg.scala:34:16
wire _T_94 = wb_ctrl.single; // Reg.scala:34:16
wire _T_95 = wb_ctrl.fromint; // Reg.scala:34:16
wire _T_96 = wb_ctrl.toint; // Reg.scala:34:16
wire _T_97 = wb_ctrl.fastpipe; // Reg.scala:34:16
wire _T_98 = wb_ctrl.fma; // Reg.scala:34:16
wire _T_99 = wb_ctrl.div; // Reg.scala:34:16
wire _T_100 = wb_ctrl.sqrt; // Reg.scala:34:16
wire _T_101 = wb_ctrl.wflags; // Reg.scala:34:16
assign _T_86 = mem_reg_valid ? _T_54 : _T_86; // FPU.scala:517:45, Reg.scala:35:23
assign _T_87 = mem_reg_valid ? _T_55 : _T_87; // FPU.scala:517:45, Reg.scala:35:23
assign _T_88 = mem_reg_valid ? _T_56 : _T_88; // FPU.scala:517:45, Reg.scala:35:23
assign _T_89 = mem_reg_valid ? _T_57 : _T_89; // FPU.scala:517:45, Reg.scala:35:23
assign _T_90 = mem_reg_valid ? _T_58 : _T_90; // FPU.scala:517:45, Reg.scala:35:23
assign _T_91 = mem_reg_valid ? _T_59 : _T_91; // FPU.scala:517:45, Reg.scala:35:23
assign _T_92 = mem_reg_valid ? _T_60 : _T_92; // FPU.scala:517:45, Reg.scala:35:23
assign _T_93 = mem_reg_valid ? _T_61 : _T_93; // FPU.scala:517:45, Reg.scala:35:23
assign _T_94 = mem_reg_valid ? _T_62 : _T_94; // FPU.scala:517:45, Reg.scala:35:23
assign _T_95 = mem_reg_valid ? _T_63 : _T_95; // FPU.scala:517:45, Reg.scala:35:23
assign _T_96 = mem_reg_valid ? _T_64 : _T_96; // FPU.scala:517:45, Reg.scala:35:23
assign _T_97 = mem_reg_valid ? _T_65 : _T_97; // FPU.scala:517:45, Reg.scala:35:23
assign _T_98 = mem_reg_valid ? _T_66 : _T_98; // FPU.scala:517:45, Reg.scala:35:23
assign _T_99 = mem_reg_valid ? _T_67 : _T_99; // FPU.scala:517:45, Reg.scala:35:23
assign _T_100 = mem_reg_valid ? _T_68 : _T_100; // FPU.scala:517:45, Reg.scala:35:23
assign _T_101 = mem_reg_valid ? _T_69 : _T_101; // FPU.scala:517:45, Reg.scala:35:23
wire [7:0] _load_wb_data_30to23 = load_wb_data[30:23]; // Reg.scala:35:23, recFNFromFN.scala:48:23
wire [22:0] _load_wb_data_22to0 = load_wb_data[22:0]; // Reg.scala:35:23, recFNFromFN.scala:49:25
wire _T_102 = _load_wb_data_30to23 == 8'h0; // recFNFromFN.scala:51:34
wire [15:0] _load_wb_data_22to7 = load_wb_data[22:7]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [7:0] _load_wb_data_22to15 = load_wb_data[22:15]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_22to19 = load_wb_data[22:19]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_14to11 = load_wb_data[14:11]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [6:0] _load_wb_data_6to0 = load_wb_data[6:0]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_6to3 = load_wb_data[6:3]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _T_103 = |_load_wb_data_22to7 ? {|_load_wb_data_22to15, |_load_wb_data_22to15 ?
{|_load_wb_data_22to19, |_load_wb_data_22to19 ? (load_wb_data[22] ? 2'h3 : load_wb_data[21]
? 2'h2 : {1'h0, load_wb_data[20]}) : load_wb_data[18] ? 2'h3 : load_wb_data[17] ? 2'h2 :
{1'h0, load_wb_data[16]}} : {|_load_wb_data_14to11, |_load_wb_data_14to11 ?
(load_wb_data[14] ? 2'h3 : load_wb_data[13] ? 2'h2 : {1'h0, load_wb_data[12]}) :
load_wb_data[10] ? 2'h3 : load_wb_data[9] ? 2'h2 : {1'h0, load_wb_data[8]}}} :
{|_load_wb_data_6to0, |_load_wb_data_6to0 ? {|_load_wb_data_6to3, |_load_wb_data_6to3 ?
(load_wb_data[6] ? 2'h3 : load_wb_data[5] ? 2'h2 : {1'h0, load_wb_data[4]}) :
load_wb_data[2] ? 2'h3 : load_wb_data[1] ? 2'h2 : {1'h0, load_wb_data[0]}} : 3'h0}; // Bitwise.scala:71:12, Cat.scala:30:58, CircuitMath.scala:30:8, :32:{10,12}, :37:22, :38:21, FPU.scala:509:25, Reg.scala:35:23
wire [53:0] _T_104 = {31'h0, _load_wb_data_22to0} << ~{|_load_wb_data_22to7, _T_103}; // Cat.scala:30:58, CircuitMath.scala:37:22, recFNFromFN.scala:56:13, :58:25
wire [8:0] _T_105 = (_T_102 ? {4'hF, |_load_wb_data_22to7, _T_103} : {1'h0, _load_wb_data_30to23}) + {7'h20,
_T_102 ? 2'h2 : 2'h1}; // CircuitMath.scala:32:10, :37:22, FPU.scala:509:25, recFNFromFN.scala:61:16, :62:27, :64:{15,47}
wire [10:0] _load_wb_data_62to52 = load_wb_data[62:52]; // Reg.scala:35:23, recFNFromFN.scala:48:23
wire [51:0] _load_wb_data_51to0 = load_wb_data[51:0]; // Reg.scala:35:23, recFNFromFN.scala:49:25
wire _T_106 = _load_wb_data_62to52 == 11'h0; // recFNFromFN.scala:51:34
wire [31:0] _load_wb_data_51to20 = load_wb_data[51:20]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [15:0] _load_wb_data_51to36 = load_wb_data[51:36]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [7:0] _load_wb_data_51to44 = load_wb_data[51:44]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_51to48 = load_wb_data[51:48]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_43to40 = load_wb_data[43:40]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [7:0] _load_wb_data_35to28 = load_wb_data[35:28]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_35to32 = load_wb_data[35:32]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_27to24 = load_wb_data[27:24]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [15:0] _load_wb_data_19to4 = load_wb_data[19:4]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [7:0] _load_wb_data_19to12 = load_wb_data[19:12]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_19to16 = load_wb_data[19:16]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_11to8 = load_wb_data[11:8]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_3to0 = load_wb_data[3:0]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [3:0] _load_wb_data_3to0_107 = load_wb_data[3:0]; // CircuitMath.scala:35:17, Reg.scala:35:23
wire [4:0] _T_108 = |_load_wb_data_51to20 ? {|_load_wb_data_51to36, |_load_wb_data_51to36 ?
{|_load_wb_data_51to44, |_load_wb_data_51to44 ? {|_load_wb_data_51to48,
|_load_wb_data_51to48 ? (load_wb_data[51] ? 2'h3 : load_wb_data[50] ? 2'h2 : {1'h0,
load_wb_data[49]}) : load_wb_data[47] ? 2'h3 : load_wb_data[46] ? 2'h2 : {1'h0,
load_wb_data[45]}} : {|_load_wb_data_43to40, |_load_wb_data_43to40 ? (load_wb_data[43] ?
2'h3 : load_wb_data[42] ? 2'h2 : {1'h0, load_wb_data[41]}) : load_wb_data[39] ? 2'h3 :
load_wb_data[38] ? 2'h2 : {1'h0, load_wb_data[37]}}} : {|_load_wb_data_35to28,
|_load_wb_data_35to28 ? {|_load_wb_data_35to32, |_load_wb_data_35to32 ? (load_wb_data[35] ?
2'h3 : load_wb_data[34] ? 2'h2 : {1'h0, load_wb_data[33]}) : load_wb_data[31] ? 2'h3 :
load_wb_data[30] ? 2'h2 : {1'h0, load_wb_data[29]}} : {|_load_wb_data_27to24,
|_load_wb_data_27to24 ? (load_wb_data[27] ? 2'h3 : load_wb_data[26] ? 2'h2 : {1'h0,
load_wb_data[25]}) : load_wb_data[23] ? 2'h3 : load_wb_data[22] ? 2'h2 : {1'h0,
load_wb_data[21]}}}} : {|_load_wb_data_19to4, |_load_wb_data_19to4 ?
{|_load_wb_data_19to12, |_load_wb_data_19to12 ? {|_load_wb_data_19to16,
|_load_wb_data_19to16 ? (load_wb_data[19] ? 2'h3 : load_wb_data[18] ? 2'h2 : {1'h0,
load_wb_data[17]}) : load_wb_data[15] ? 2'h3 : load_wb_data[14] ? 2'h2 : {1'h0,
load_wb_data[13]}} : {|_load_wb_data_11to8, |_load_wb_data_11to8 ? (load_wb_data[11] ? 2'h3
: load_wb_data[10] ? 2'h2 : {1'h0, load_wb_data[9]}) : load_wb_data[7] ? 2'h3 :
load_wb_data[6] ? 2'h2 : {1'h0, load_wb_data[5]}}} : {|_load_wb_data_3to0,
|_load_wb_data_3to0 ? {|_load_wb_data_3to0_107, |_load_wb_data_3to0_107 ? (load_wb_data[3]
? 2'h3 : load_wb_data[2] ? 2'h2 : {1'h0, load_wb_data[1]}) : 2'h0} : 3'h0}}; // Bitwise.scala:71:12, Cat.scala:30:58, CircuitMath.scala:30:8, :32:{10,12}, :37:22, :38:21, FPU.scala:509:25, :631:23, Reg.scala:35:23
wire [114:0] _T_109 = {63'h0, _load_wb_data_51to0} << ~{|_load_wb_data_51to20, _T_108}; // Cat.scala:30:58, CircuitMath.scala:37:22, recFNFromFN.scala:56:13, :58:25
wire [11:0] _T_110 = (_T_106 ? {6'h3F, |_load_wb_data_51to20, _T_108} : {1'h0, _load_wb_data_62to52}) +
{10'h100, _T_106 ? 2'h2 : 2'h1}; // CircuitMath.scala:32:10, :37:22, FPU.scala:509:25, recFNFromFN.scala:56:13, :61:16, :62:27, :64:{15,47}
wire [2:0] _ex_reg_inst_14to12 = ex_reg_inst[14:12]; // FPU.scala:567:30, Reg.scala:35:23
wire [64:0] _T_111 = req.in2; // FPU.scala:569:17
wire [64:0] _T_112 = req.in3; // FPU.scala:569:17
wire [4:0] _T_113 = req.cmd; // FPU.scala:577:9
assign _T_113 = _T_3 ? _T_4 : _T_70; // FPU.scala:577:9
wire _T_114 = req.ldst; // FPU.scala:577:9
assign _T_114 = _T_3 ? _T_5 : _T_71; // FPU.scala:577:9
wire _T_115 = req.wen; // FPU.scala:577:9
assign _T_115 = _T_3 ? _T_6 : _T_72; // FPU.scala:577:9
wire _T_116 = req.ren1; // FPU.scala:577:9
assign _T_116 = _T_3 ? _T_7 : _T_73; // FPU.scala:577:9
wire _T_117 = req.ren2; // FPU.scala:577:9
assign _T_117 = _T_3 ? _T_8 : _T_74; // FPU.scala:577:9
wire _T_118 = req.ren3; // FPU.scala:577:9
assign _T_118 = _T_3 ? _T_9 : _T_75; // FPU.scala:577:9
wire _T_119 = req.swap12; // FPU.scala:577:9
assign _T_119 = _T_3 ? _T_10 : _T_76; // FPU.scala:577:9
wire _T_120 = req.swap23; // FPU.scala:577:9
assign _T_120 = _T_3 ? _T_11 : _T_77; // FPU.scala:577:9
wire _T_121 = req.single; // FPU.scala:577:9
assign _T_121 = _T_3 ? _T_12 : _T_78; // FPU.scala:577:9
wire _T_122 = req.fromint; // FPU.scala:577:9
assign _T_122 = _T_3 ? _T_13 : _T_79; // FPU.scala:577:9
wire _T_123 = req.toint; // FPU.scala:577:9
assign _T_123 = _T_3 ? _T_14 : _T_80; // FPU.scala:577:9
wire _T_124 = req.fastpipe; // FPU.scala:577:9
assign _T_124 = _T_3 ? _T_15 : _T_81; // FPU.scala:577:9
wire _T_125 = req.fma; // FPU.scala:577:9
assign _T_125 = _T_3 ? _T_16 : _T_82; // FPU.scala:577:9
wire _T_126 = req.div; // FPU.scala:577:9
assign _T_126 = _T_3 ? _T_17 : _T_83; // FPU.scala:577:9
wire _T_127 = req.sqrt; // FPU.scala:577:9
assign _T_127 = _T_3 ? _T_18 : _T_84; // FPU.scala:577:9
wire _T_128 = req.wflags; // FPU.scala:577:9
assign _T_128 = _T_3 ? _T_19 : _T_85; // FPU.scala:577:9
wire [2:0] _T_129 = req.rm; // FPU.scala:577:9
assign _T_129 = _T_3 ? io_cp_req_bits.rm : &_ex_reg_inst_14to12 ? io_fcsr_rm : _ex_reg_inst_14to12; // FPU.scala:567:{18,38}, :577:9
wire [1:0] _T_130 = req.typ; // FPU.scala:577:9
assign _T_130 = _T_3 ? io_cp_req_bits.typ : ex_reg_inst[21:20]; // FPU.scala:575:25, :577:9, Reg.scala:35:23
wire [64:0] _T_131 = io_cp_req_bits.in1; // FPU.scala:577:9
wire [64:0] _T_132 = req.in1; // FPU.scala:577:9
assign _T_132 = _T_3 ? _T_131 : regfile_R0_data; // FPU.scala:547:20, :577:9
wire [64:0] _T_133 = io_cp_req_bits.in2; // FPU.scala:577:9
wire [64:0] _T_134 = io_cp_req_bits.in3; // FPU.scala:577:9
assign _T_111 = _T_3 ? (_T_11 ? _T_134 : _T_133) : regfile_R1_data; // FPU.scala:547:20, :579:15
assign _T_112 = _T_3 ? (_T_11 ? _T_133 : _T_134) : regfile_R2_data; // FPU.scala:547:20, :580:15
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T_135 = _io_in_wire.bits; // ../perf/regress/FPU.fir:446:13
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_136 = sfma_io_out.bits; // ../perf/regress/FPU.fir:446:13, FPU.scala:584:20
wire _T_137 = _T_2 & _T_82; // FPU.scala:585:33
assign _io_in_wire.valid = _T_137 & _T_78; // ../perf/regress/FPU.fir:446:13, FPU.scala:585:{20,48}
assign _T_135.cmd = _T_113; // FPU.scala:586:19
assign _T_135.ldst = _T_114; // FPU.scala:586:19
assign _T_135.wen = _T_115; // FPU.scala:586:19
assign _T_135.ren1 = _T_116; // FPU.scala:586:19
assign _T_135.ren2 = _T_117; // FPU.scala:586:19
assign _T_135.ren3 = _T_118; // FPU.scala:586:19
assign _T_135.swap12 = _T_119; // FPU.scala:586:19
assign _T_135.swap23 = _T_120; // FPU.scala:586:19
assign _T_135.single = _T_121; // FPU.scala:586:19
assign _T_135.fromint = _T_122; // FPU.scala:586:19
assign _T_135.toint = _T_123; // FPU.scala:586:19
assign _T_135.fastpipe = _T_124; // FPU.scala:586:19
assign _T_135.fma = _T_125; // FPU.scala:586:19
assign _T_135.div = _T_126; // FPU.scala:586:19
assign _T_135.sqrt = _T_127; // FPU.scala:586:19
assign _T_135.wflags = _T_128; // FPU.scala:586:19
assign _T_135.rm = _T_129; // FPU.scala:586:19
assign _T_135.typ = _T_130; // FPU.scala:586:19
assign _T_135.in1 = _T_132; // FPU.scala:586:19
assign _T_135.in2 = _T_111; // FPU.scala:586:19
assign _T_135.in3 = _T_112; // FPU.scala:586:19
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T_138 = _io_in_wire_3.bits; // ../perf/regress/FPU.fir:454:13
wire struct packed {logic lt; logic [63:0] store; logic [63:0] toint; logic [4:0] exc; } _T_139 = fpiu_io_out.bits; // ../perf/regress/FPU.fir:454:13, FPU.scala:588:20
assign _io_in_wire_3.valid = _T_2 & (_T_80 | _T_83 | _T_84 | {_T_70[3:2], _T_70[0]} == 3'h3); // ../perf/regress/FPU.fir:454:13, FPU.scala:589:{20,33,82,97}
assign _T_138.cmd = _T_113; // FPU.scala:586:19, :590:19
assign _T_138.ldst = _T_114; // FPU.scala:586:19, :590:19
assign _T_138.wen = _T_115; // FPU.scala:586:19, :590:19
assign _T_138.ren1 = _T_116; // FPU.scala:586:19, :590:19
assign _T_138.ren2 = _T_117; // FPU.scala:586:19, :590:19
assign _T_138.ren3 = _T_118; // FPU.scala:586:19, :590:19
assign _T_138.swap12 = _T_119; // FPU.scala:586:19, :590:19
assign _T_138.swap23 = _T_120; // FPU.scala:586:19, :590:19
assign _T_138.single = _T_121; // FPU.scala:586:19, :590:19
assign _T_138.fromint = _T_122; // FPU.scala:586:19, :590:19
assign _T_138.toint = _T_123; // FPU.scala:586:19, :590:19
assign _T_138.fastpipe = _T_124; // FPU.scala:586:19, :590:19
assign _T_138.fma = _T_125; // FPU.scala:586:19, :590:19
assign _T_138.div = _T_126; // FPU.scala:586:19, :590:19
assign _T_138.sqrt = _T_127; // FPU.scala:586:19, :590:19
assign _T_138.wflags = _T_128; // FPU.scala:586:19, :590:19
assign _T_138.rm = _T_129; // FPU.scala:586:19, :590:19
assign _T_138.typ = _T_130; // FPU.scala:586:19, :590:19
assign _T_138.in1 = _T_132; // FPU.scala:586:19, :590:19
assign _T_138.in2 = _T_111; // FPU.scala:586:19, :590:19
assign _T_138.in3 = _T_112; // FPU.scala:586:19, :590:19
wire [63:0] _T_140 = _T_139.toint; // FPU.scala:592:17
wire _T_141 = fpiu_io_out.valid & mem_cp_valid & _T_64; // FPU.scala:516:44, :588:20, :593:{26,42}, Reg.scala:35:23
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T_142 = _io_in_wire_4.bits; // ../perf/regress/FPU.fir:474:13
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_143 = ifpu_io_out.bits; // ../perf/regress/FPU.fir:474:13, FPU.scala:598:20
assign _io_in_wire_4.valid = _T_2 & _T_79; // ../perf/regress/FPU.fir:474:13, FPU.scala:599:{20,33}
assign _T_142.cmd = _T_113; // FPU.scala:586:19, :600:19
assign _T_142.ldst = _T_114; // FPU.scala:586:19, :600:19
assign _T_142.wen = _T_115; // FPU.scala:586:19, :600:19
assign _T_142.ren1 = _T_116; // FPU.scala:586:19, :600:19
assign _T_142.ren2 = _T_117; // FPU.scala:586:19, :600:19
assign _T_142.ren3 = _T_118; // FPU.scala:586:19, :600:19
assign _T_142.swap12 = _T_119; // FPU.scala:586:19, :600:19
assign _T_142.swap23 = _T_120; // FPU.scala:586:19, :600:19
assign _T_142.single = _T_121; // FPU.scala:586:19, :600:19
assign _T_142.fromint = _T_122; // FPU.scala:586:19, :600:19
assign _T_142.toint = _T_123; // FPU.scala:586:19, :600:19
assign _T_142.fastpipe = _T_124; // FPU.scala:586:19, :600:19
assign _T_142.fma = _T_125; // FPU.scala:586:19, :600:19
assign _T_142.div = _T_126; // FPU.scala:586:19, :600:19
assign _T_142.sqrt = _T_127; // FPU.scala:586:19, :600:19
assign _T_142.wflags = _T_128; // FPU.scala:586:19, :600:19
assign _T_142.rm = _T_129; // FPU.scala:586:19, :600:19
assign _T_142.typ = _T_130; // FPU.scala:586:19, :600:19
assign _T_142.in2 = _T_111; // FPU.scala:586:19, :600:19
assign _T_142.in3 = _T_112; // FPU.scala:586:19, :600:19
assign _T_142.in1 = _T_3 ? _T_131 : {1'h0, io_fromint_data}; // ../perf/regress/FPU.fir:474:13, FPU.scala:509:25, :601:{23,29}
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T_144 = _io_in_wire_5.bits; // ../perf/regress/FPU.fir:483:13
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_145 = fpmu_io_out.bits; // ../perf/regress/FPU.fir:483:13, FPU.scala:603:20
assign _io_in_wire_5.valid = _T_2 & _T_81; // ../perf/regress/FPU.fir:483:13, FPU.scala:604:{20,33}
assign _T_144.cmd = _T_113; // FPU.scala:586:19, :605:19
assign _T_144.ldst = _T_114; // FPU.scala:586:19, :605:19
assign _T_144.wen = _T_115; // FPU.scala:586:19, :605:19
assign _T_144.ren1 = _T_116; // FPU.scala:586:19, :605:19
assign _T_144.ren2 = _T_117; // FPU.scala:586:19, :605:19
assign _T_144.ren3 = _T_118; // FPU.scala:586:19, :605:19
assign _T_144.swap12 = _T_119; // FPU.scala:586:19, :605:19
assign _T_144.swap23 = _T_120; // FPU.scala:586:19, :605:19
assign _T_144.single = _T_121; // FPU.scala:586:19, :605:19
assign _T_144.fromint = _T_122; // FPU.scala:586:19, :605:19
assign _T_144.toint = _T_123; // FPU.scala:586:19, :605:19
assign _T_144.fastpipe = _T_124; // FPU.scala:586:19, :605:19
assign _T_144.fma = _T_125; // FPU.scala:586:19, :605:19
assign _T_144.div = _T_126; // FPU.scala:586:19, :605:19
assign _T_144.sqrt = _T_127; // FPU.scala:586:19, :605:19
assign _T_144.wflags = _T_128; // FPU.scala:586:19, :605:19
assign _T_144.rm = _T_129; // FPU.scala:586:19, :605:19
assign _T_144.typ = _T_130; // FPU.scala:586:19, :605:19
assign _T_144.in1 = _T_132; // FPU.scala:586:19, :605:19
assign _T_144.in2 = _T_111; // FPU.scala:586:19, :605:19
assign _T_144.in3 = _T_112; // FPU.scala:586:19, :605:19
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T_146 = _io_in_wire_6.bits; // ../perf/regress/FPU.fir:504:19
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_147 = FPUFMAPipe_io_out.bits; // ../perf/regress/FPU.fir:504:19, FPU.scala:624:28
assign _io_in_wire_6.valid = _T_137 & ~_T_78; // ../perf/regress/FPU.fir:504:19, FPU.scala:625:{28,56,59}
assign _T_146.cmd = _T_113; // FPU.scala:586:19, :626:27
assign _T_146.ldst = _T_114; // FPU.scala:586:19, :626:27
assign _T_146.wen = _T_115; // FPU.scala:586:19, :626:27
assign _T_146.ren1 = _T_116; // FPU.scala:586:19, :626:27
assign _T_146.ren2 = _T_117; // FPU.scala:586:19, :626:27
assign _T_146.ren3 = _T_118; // FPU.scala:586:19, :626:27
assign _T_146.swap12 = _T_119; // FPU.scala:586:19, :626:27
assign _T_146.swap23 = _T_120; // FPU.scala:586:19, :626:27
assign _T_146.single = _T_121; // FPU.scala:586:19, :626:27
assign _T_146.fromint = _T_122; // FPU.scala:586:19, :626:27
assign _T_146.toint = _T_123; // FPU.scala:586:19, :626:27
assign _T_146.fastpipe = _T_124; // FPU.scala:586:19, :626:27
assign _T_146.fma = _T_125; // FPU.scala:586:19, :626:27
assign _T_146.div = _T_126; // FPU.scala:586:19, :626:27
assign _T_146.sqrt = _T_127; // FPU.scala:586:19, :626:27
assign _T_146.wflags = _T_128; // FPU.scala:586:19, :626:27
assign _T_146.rm = _T_129; // FPU.scala:586:19, :626:27
assign _T_146.typ = _T_130; // FPU.scala:586:19, :626:27
assign _T_146.in1 = _T_132; // FPU.scala:586:19, :626:27
assign _T_146.in2 = _T_111; // FPU.scala:586:19, :626:27
assign _T_146.in3 = _T_112; // FPU.scala:586:19, :626:27
wire _T_148 = _T_66 & _T_62; // FPU.scala:622:56, Reg.scala:35:23
wire _T_149 = _T_66 & ~_T_62; // FPU.scala:627:{62,65}, Reg.scala:35:23
wire _T_150 = _T_65 | _T_63; // FPU.scala:631:78, Reg.scala:35:23
wire [4:0] _T_151 = wbInfo[2'h0].rd; // FPU.scala:631:23, :646:19
wire _T_152 = wbInfo[2'h0].single; // FPU.scala:631:23, :646:19
wire _T_153 = wbInfo[2'h0].cp; // FPU.scala:631:23, :646:19
wire [1:0] _T_154 = wbInfo[2'h0].pipeid; // FPU.scala:631:23, :646:19
wire [4:0] _T_155 = wbInfo[2'h1].rd; // FPU.scala:646:19, recFNFromFN.scala:64:47
wire _T_156 = wbInfo[2'h1].single; // FPU.scala:646:19, recFNFromFN.scala:64:47
wire _T_157 = wbInfo[2'h1].cp; // FPU.scala:646:19, recFNFromFN.scala:64:47
wire [1:0] _T_158 = wbInfo[2'h1].pipeid; // FPU.scala:646:19, recFNFromFN.scala:64:47
wire [4:0] _T_159 = wbInfo[2'h2].rd; // CircuitMath.scala:32:10, FPU.scala:646:19
wire _T_160 = wbInfo[2'h2].single; // CircuitMath.scala:32:10, FPU.scala:646:19
wire _T_161 = wbInfo[2'h2].cp; // CircuitMath.scala:32:10, FPU.scala:646:19
wire [1:0] _T_162 = wbInfo[2'h2].pipeid; // CircuitMath.scala:32:10, FPU.scala:646:19
wire _T_163 = mem_reg_valid & (_T_66 | _T_65 | _T_63); // FPU.scala:517:45, :647:{31,69}, Reg.scala:35:23
wire _wen_1 = wen[1]; // FPU.scala:648:101, :651:14
wire _wen_2 = wen[2]; // FPU.scala:648:101, :651:14
wire _T_164 = ~write_port_busy & _T_150; // FPU.scala:659:{13,30}, Reg.scala:35:23
assign _T_153 = _T_163 & _T_164 ? mem_cp_valid : _wen_1 ? _T_157 : _T_153; // FPU.scala:516:44, :651:33, :660:22
assign _T_152 = _T_163 & _T_164 ? _T_62 : _wen_1 ? _T_156 : _T_152; // FPU.scala:651:33, :661:26, Reg.scala:35:23
wire [1:0] _T_165 = {_T_148, _T_63} | {2{_T_149}}; // FPU.scala:633:{63,108}, Reg.scala:35:23
assign _T_154 = _T_163 & _T_164 ? _T_165 : _wen_1 ? _T_158 : _T_154; // FPU.scala:651:33, :662:26
wire [4:0] _mem_reg_inst_11to7 = mem_reg_inst[11:7]; // FPU.scala:663:37, Reg.scala:35:23
assign _T_151 = _T_163 & _T_164 ? _mem_reg_inst_11to7 : _wen_1 ? _T_155 : _T_151; // FPU.scala:651:33, :663:22
wire _T_166 = ~write_port_busy & _T_148; // FPU.scala:659:{13,30}, Reg.scala:35:23
assign _T_157 = _T_163 & _T_166 ? mem_cp_valid : _wen_2 ? _T_161 : _T_157; // FPU.scala:516:44, :651:33, :660:22
assign _T_156 = _T_163 & _T_166 ? _T_62 : _wen_2 ? _T_160 : _T_156; // FPU.scala:651:33, :661:26, Reg.scala:35:23
assign _T_158 = _T_163 & _T_166 ? _T_165 : _wen_2 ? _T_162 : _T_158; // FPU.scala:651:33, :662:26
assign _T_155 = _T_163 & _T_166 ? _mem_reg_inst_11to7 : _wen_2 ? _T_159 : _T_155; // FPU.scala:651:33, :663:22
wire _T_167 = ~write_port_busy & _T_149; // FPU.scala:659:{13,30}, Reg.scala:35:23
assign _T_161 = _T_163 & _T_167 ? mem_cp_valid : _T_161; // FPU.scala:516:44, :660:22
assign _T_160 = _T_163 & _T_167 ? _T_62 : _T_160; // FPU.scala:661:26, Reg.scala:35:23
assign _T_162 = _T_163 & _T_167 ? _T_165 : _T_162; // FPU.scala:662:26
assign _T_159 = _T_163 & _T_167 ? _mem_reg_inst_11to7 : _T_159; // FPU.scala:663:22
wire [4:0] _T_168 = divSqrt_wen ? divSqrt_waddr : _T_151; // FPU.scala:651:33, :668:18
wire [1:0] _T_169 = _T_154; // FPU.scala:651:33
wire _T_170 = _T_169[0]; // Package.scala:18:26
wire [1:0] _T_171 = _T_154; // FPU.scala:651:33
wire _T_172 = _T_171[1]; // Package.scala:19:17
wire [64:0] _T_173 = divSqrt_wen ? _T_0 : _T_172 ? (_T_170 ? _T_147.data : _T_136.data) : _T_170 ? _T_143.data :
_T_145.data; // FPU.scala:668:18, :669:19, :749:25, Package.scala:19:12
wire [64:0] _T_174 = (divSqrt_wen ? divSqrt_single : _T_152) ? {32'h70020000, _T_173[32:0]} : _T_173; // FPU.scala:543:33, :651:33, :668:18, :670:20, :673:{19,36,44}
wire _wen_0 = wen[0]; // FPU.scala:648:101, :676:30
wire _T_175 = _T_153 & _wen_0; // FPU.scala:651:33, :689:22
assign _io_cp_resp_bits_output.data = _T_175 ? _T_174 : {1'h0, _T_141 ? _T_140 : 64'h0}; // ../perf/regress/FPU.fir:8:8, FPU.scala:509:25, :594:26, :690:26
wire _T_176 = wb_reg_valid & _T_96; // FPU.scala:695:37, Reg.scala:35:23
assign _io_fcsr_flags_output.valid = _T_176 | divSqrt_wen | _wen_0; // ../perf/regress/FPU.fir:8:8, FPU.scala:668:18, :697:{23,56}
assign _io_fcsr_flags_output.bits = (_T_176 ? wb_toint_exc : 5'h0) | (divSqrt_wen ? _T : 5'h0) | (_wen_0 ? (_T_172 ? (_T_170 ?
_T_147.exc : _T_136.exc) : _T_170 ? _T_143.exc : _T_145.exc) : 5'h0); // ../perf/regress/FPU.fir:8:8, FPU.scala:668:18, :698:22, :699:8, :700:{8,46}, :701:8, :750:43, Package.scala:19:12, Reg.scala:35:23
wire _T_177 = mem_reg_valid & (_T_67 | _T_68); // FPU.scala:517:45, :703:{34,51}, Reg.scala:35:23
wire _T_178 = _T_177 & (~_T_1 | |wen) | write_port_busy | divSqrt_in_flight; // FPU.scala:648:101, :703:{69,73,90,97}, :704:131, :705:48, :723:27, Reg.scala:35:23
assign _io_dec_output.cmd = _T_37; // FPU.scala:706:10
assign _io_dec_output.ldst = _T_38; // FPU.scala:706:10
assign _io_dec_output.wen = _T_39; // FPU.scala:706:10
assign _io_dec_output.ren1 = _T_40; // FPU.scala:706:10
assign _io_dec_output.ren2 = _T_41; // FPU.scala:706:10
assign _io_dec_output.ren3 = _T_42; // FPU.scala:706:10
assign _io_dec_output.swap12 = _T_43; // FPU.scala:706:10
assign _io_dec_output.swap23 = _T_44; // FPU.scala:706:10
assign _io_dec_output.single = _T_45; // FPU.scala:706:10
assign _io_dec_output.fromint = _T_46; // FPU.scala:706:10
assign _io_dec_output.toint = _T_47; // FPU.scala:706:10
assign _io_dec_output.fastpipe = _T_48; // FPU.scala:706:10
assign _io_dec_output.fma = _T_49; // FPU.scala:706:10
assign _io_dec_output.div = _T_50; // FPU.scala:706:10
assign _io_dec_output.sqrt = _T_51; // FPU.scala:706:10
assign _io_dec_output.wflags = _T_52; // FPU.scala:706:10
`ifndef SYNTHESIS // FPU.scala:509:25
initial begin // FPU.scala:509:25
automatic logic [31:0] _RANDOM; // FPU.scala:509:25
automatic logic [31:0] _RANDOM_186; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_187; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_188; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_189; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_190; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_191; // FPU.scala:645:16
automatic logic [31:0] _RANDOM_192; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_193; // FPU.scala:720:35
`INIT_RANDOM_PROLOG_ // FPU.scala:509:25
`ifdef RANDOMIZE_REG_INIT // FPU.scala:509:25
_RANDOM = `RANDOM; // FPU.scala:509:25
ex_reg_valid = _RANDOM[0]; // FPU.scala:509:25
_RANDOM_186 = `RANDOM; // Reg.scala:34:16
ex_reg_inst = {_RANDOM[31:1], _RANDOM_186[0]}; // Reg.scala:34:16
mem_reg_valid = _RANDOM_186[1]; // FPU.scala:513:26
_RANDOM_187 = `RANDOM; // Reg.scala:34:16
mem_reg_inst = {_RANDOM_186[31:2], _RANDOM_187[1:0]}; // Reg.scala:34:16
mem_cp_valid = _RANDOM_187[2]; // FPU.scala:515:25
wb_reg_valid = _RANDOM_187[3]; // FPU.scala:517:25
wb_cp_valid = _RANDOM_187[4]; // FPU.scala:518:24
_T_21 = _RANDOM_187[9:5]; // Reg.scala:34:16
_T_22 = _RANDOM_187[10]; // Reg.scala:34:16
_T_23 = _RANDOM_187[11]; // Reg.scala:34:16
_T_24 = _RANDOM_187[12]; // Reg.scala:34:16
_T_25 = _RANDOM_187[13]; // Reg.scala:34:16
_T_26 = _RANDOM_187[14]; // Reg.scala:34:16
_T_27 = _RANDOM_187[15]; // Reg.scala:34:16
_T_28 = _RANDOM_187[16]; // Reg.scala:34:16
_T_29 = _RANDOM_187[17]; // Reg.scala:34:16
_T_30 = _RANDOM_187[18]; // Reg.scala:34:16
_T_31 = _RANDOM_187[19]; // Reg.scala:34:16
_T_32 = _RANDOM_187[20]; // Reg.scala:34:16
_T_33 = _RANDOM_187[21]; // Reg.scala:34:16
_T_34 = _RANDOM_187[22]; // Reg.scala:34:16
_T_35 = _RANDOM_187[23]; // Reg.scala:34:16
_T_36 = _RANDOM_187[24]; // Reg.scala:34:16
_T_54 = _RANDOM_187[29:25]; // Reg.scala:34:16
_T_55 = _RANDOM_187[30]; // Reg.scala:34:16
_T_56 = _RANDOM_187[31]; // Reg.scala:34:16
_RANDOM_188 = `RANDOM; // Reg.scala:34:16
_T_57 = _RANDOM_188[0]; // Reg.scala:34:16
_T_58 = _RANDOM_188[1]; // Reg.scala:34:16
_T_59 = _RANDOM_188[2]; // Reg.scala:34:16
_T_60 = _RANDOM_188[3]; // Reg.scala:34:16
_T_61 = _RANDOM_188[4]; // Reg.scala:34:16
_T_62 = _RANDOM_188[5]; // Reg.scala:34:16
_T_63 = _RANDOM_188[6]; // Reg.scala:34:16
_T_64 = _RANDOM_188[7]; // Reg.scala:34:16
_T_65 = _RANDOM_188[8]; // Reg.scala:34:16
_T_66 = _RANDOM_188[9]; // Reg.scala:34:16
_T_67 = _RANDOM_188[10]; // Reg.scala:34:16
_T_68 = _RANDOM_188[11]; // Reg.scala:34:16
_T_69 = _RANDOM_188[12]; // Reg.scala:34:16
_T_86 = _RANDOM_188[17:13]; // Reg.scala:34:16
_T_87 = _RANDOM_188[18]; // Reg.scala:34:16
_T_88 = _RANDOM_188[19]; // Reg.scala:34:16
_T_89 = _RANDOM_188[20]; // Reg.scala:34:16
_T_90 = _RANDOM_188[21]; // Reg.scala:34:16
_T_91 = _RANDOM_188[22]; // Reg.scala:34:16
_T_92 = _RANDOM_188[23]; // Reg.scala:34:16
_T_93 = _RANDOM_188[24]; // Reg.scala:34:16
_T_94 = _RANDOM_188[25]; // Reg.scala:34:16
_T_95 = _RANDOM_188[26]; // Reg.scala:34:16
_T_96 = _RANDOM_188[27]; // Reg.scala:34:16
_T_97 = _RANDOM_188[28]; // Reg.scala:34:16
_T_98 = _RANDOM_188[29]; // Reg.scala:34:16
_T_99 = _RANDOM_188[30]; // Reg.scala:34:16
_T_100 = _RANDOM_188[31]; // Reg.scala:34:16
_RANDOM_189 = `RANDOM; // Reg.scala:34:16
_T_101 = _RANDOM_189[0]; // Reg.scala:34:16
load_wb = _RANDOM_189[1]; // FPU.scala:534:20
load_wb_single = _RANDOM_189[2]; // Reg.scala:34:16
_RANDOM_190 = `RANDOM; // Reg.scala:34:16
load_wb_data = {_RANDOM_189[31:3], `RANDOM, _RANDOM_190[2:0]}; // Reg.scala:34:16
load_wb_tag = _RANDOM_190[7:3]; // Reg.scala:34:16
ex_ra1 = _RANDOM_190[12:8]; // FPU.scala:554:53
ex_ra2 = _RANDOM_190[17:13]; // FPU.scala:554:53
ex_ra3 = _RANDOM_190[22:18]; // FPU.scala:554:53
divSqrt_wen = _RANDOM_190[23]; // FPU.scala:608:24
divSqrt_waddr = _RANDOM_190[28:24]; // FPU.scala:610:26
divSqrt_single = _RANDOM_190[29]; // FPU.scala:611:27
divSqrt_in_flight = _RANDOM_190[30]; // FPU.scala:614:30
divSqrt_killed = _RANDOM_190[31]; // FPU.scala:615:27
_RANDOM_191 = `RANDOM; // FPU.scala:645:16
wen = _RANDOM_191[2:0]; // FPU.scala:645:16
_T_151 = _RANDOM_191[7:3]; // FPU.scala:646:19
_T_152 = _RANDOM_191[8]; // FPU.scala:646:19
_T_153 = _RANDOM_191[9]; // FPU.scala:646:19
_T_154 = _RANDOM_191[11:10]; // FPU.scala:646:19
_T_155 = _RANDOM_191[16:12]; // FPU.scala:646:19
_T_156 = _RANDOM_191[17]; // FPU.scala:646:19
_T_157 = _RANDOM_191[18]; // FPU.scala:646:19
_T_158 = _RANDOM_191[20:19]; // FPU.scala:646:19
_T_159 = _RANDOM_191[25:21]; // FPU.scala:646:19
_T_160 = _RANDOM_191[26]; // FPU.scala:646:19
_T_161 = _RANDOM_191[27]; // FPU.scala:646:19
_T_162 = _RANDOM_191[29:28]; // FPU.scala:646:19
write_port_busy = _RANDOM_191[30]; // Reg.scala:34:16
_RANDOM_192 = `RANDOM; // Reg.scala:34:16
wb_toint_exc = {_RANDOM_191[31], _RANDOM_192[3:0]}; // Reg.scala:34:16
_T_7_179 = _RANDOM_192[4]; // FPU.scala:708:55
_T_8_180 = _RANDOM_192[6:5]; // FPU.scala:718:25
_T_9_181 = _RANDOM_192[11:7]; // FPU.scala:719:35
_RANDOM_193 = `RANDOM; // FPU.scala:720:35
_T_10_182 = {_RANDOM_192[31:12], `RANDOM, _RANDOM_193[12:0]}; // FPU.scala:720:35
`endif
end // initial
`endif
assign _T_1 = _T_68 ? DivSqrtRecF64_io_inReady_sqrt : DivSqrtRecF64_io_inReady_div; // FPU.scala:722:25, :723:27, Reg.scala:35:23
wire _T_183 = _T_177 & ~divSqrt_in_flight; // FPU.scala:704:131, :725:{76,79}
wire [2:0] _T_184 = fpiu_io_as_double.rm; // FPU.scala:588:20, :729:29
wire [1:0] _T_185 = _T_184[1:0]; // FPU.scala:729:29
always @(posedge clock) begin // Reg.scala:35:23
automatic logic _T_194 = (io_killm | _T_178) & ~mem_cp_valid; // FPU.scala:516:{25,41,44}
automatic logic [4:0] _io_inst_19to15 = io_inst[19:15]; // FPU.scala:557:49
automatic logic [4:0] _io_inst_24to20 = io_inst[24:20]; // FPU.scala:561:48
automatic logic _T_195 = DivSqrtRecF64_io_outValid_div | DivSqrtRecF64_io_outValid_sqrt; // FPU.scala:722:25, :724:52
automatic logic _T_196 = _T_183 & _T_1; // FPU.scala:723:27, :731:30
if (reset) begin // FPU.scala:509:25
ex_reg_valid <= 1'h0; // FPU.scala:509:25
mem_reg_valid <= 1'h0; // FPU.scala:509:25, :513:26
mem_cp_valid <= 1'h0; // FPU.scala:509:25, :515:25
wb_reg_valid <= 1'h0; // FPU.scala:509:25, :517:25
wb_cp_valid <= 1'h0; // FPU.scala:509:25, :518:24
divSqrt_in_flight <= 1'h0; // FPU.scala:509:25, :614:30
wen <= 3'h0; // Bitwise.scala:71:12, FPU.scala:645:16
end
else begin // FPU.scala:509:25
ex_reg_valid <= io_valid; // FPU.scala:509:25
mem_reg_valid <= ex_reg_valid & ~io_killx | _T_3; // FPU.scala:510:32, :513:{26,45,48,58}
mem_cp_valid <= _T_3; // FPU.scala:515:25
wb_reg_valid <= mem_reg_valid & (~_T_194 | mem_cp_valid); // FPU.scala:516:44, :517:{25,45,49,56}
wb_cp_valid <= mem_cp_valid; // FPU.scala:516:44, :518:24
wen <= ~_T_163 | _T_194 ? {1'h0, wen[2:1]} : {_T_149, wen[2] | _T_148, wen[1] | _T_150}; // FPU.scala:509:25, :648:101, :653:14, :656:{11,23}
divSqrt_in_flight <= ~_T_195 & (_T_196 | divSqrt_in_flight); // FPU.scala:704:131, :732:25, :742:25
end
ex_reg_inst <= io_valid ? io_inst : ex_reg_inst; // Reg.scala:35:23
mem_reg_inst <= ex_reg_valid ? ex_reg_inst : mem_reg_inst; // FPU.scala:510:32, Reg.scala:35:23
load_wb <= io_dmem_resp_val; // FPU.scala:534:20
load_wb_single <= io_dmem_resp_val ? ~(io_dmem_resp_type[0]) : load_wb_single; // FPU.scala:535:{34,52}, Reg.scala:35:23
load_wb_data <= io_dmem_resp_val ? io_dmem_resp_data : load_wb_data; // Reg.scala:35:23
load_wb_tag <= io_dmem_resp_val ? io_dmem_resp_tag : load_wb_tag; // Reg.scala:35:23
ex_ra1 <= io_valid ? (_T_41 & _T_43 ? _io_inst_24to20 : ~_T_40 | _T_43 ? ex_ra1 : _io_inst_19to15) :
ex_ra1; // FPU.scala:557:39, :561:38
ex_ra2 <= io_valid ? (~_T_41 | _T_43 | _T_44 ? (_T_40 & _T_43 ? _io_inst_19to15 : ex_ra2) :
_io_inst_24to20) : ex_ra2; // FPU.scala:558:38, :563:58
ex_ra3 <= io_valid ? (_T_42 ? io_inst[31:27] : _T_41 & _T_44 ? _io_inst_24to20 : ex_ra3) : ex_ra3; // FPU.scala:562:38, :565:{34,44}
write_port_busy <= _T_2 ? _T_163 & |({_T_149, _T_148} & {_T_82 & _T_78, _T_81 | _T_79}) | wen[2] & (_T_81 |
_T_79) : write_port_busy; // FPU.scala:622:56, :631:78, :648:{43,62,89,93,101}, Reg.scala:35:23
wb_toint_exc <= _T_64 ? _T_139.exc : wb_toint_exc; // Reg.scala:35:23
_T_7_179 <= _T_149 | _T_67 | _T_68; // FPU.scala:708:{55,112}, Reg.scala:35:23
divSqrt_killed <= _T_196 ? _T_194 : divSqrt_killed; // FPU.scala:733:22
divSqrt_single <= _T_196 ? _T_62 : divSqrt_single; // FPU.scala:670:20, :734:22, Reg.scala:35:23
divSqrt_waddr <= _T_196 ? _mem_reg_inst_11to7 : divSqrt_waddr; // FPU.scala:668:18, :735:21
_T_8_180 <= _T_196 ? _T_185 : _T_8_180; // FPU.scala:736:18
divSqrt_wen <= _T_195 & ~divSqrt_killed; // FPU.scala:733:22, :740:{19,22}
_T_10_182 <= _T_195 ? DivSqrtRecF64_io_out : _T_10_182; // FPU.scala:722:25, :741:28
_T_9_181 <= _T_195 ? DivSqrtRecF64_io_exceptionFlags : _T_9_181; // FPU.scala:722:25, :743:28
end // always @(posedge)
assign _T_0 = divSqrt_single ? {32'h0, RecFNToRecFN_io_out} : _T_10_182; // CircuitMath.scala:37:22, FPU.scala:670:20, :741:28, :746:34, :749:25
assign _T = _T_9_181 | (divSqrt_single ? RecFNToRecFN_io_exceptionFlags : 5'h0); // ../perf/regress/FPU.fir:8:8, FPU.scala:670:20, :743:28, :746:34, :750:{43,48}
FPUDecoder fp_decoder ( // FPU.scala:520:26
.clock (clock),
.reset (reset),
.io_inst (io_inst),
.io_sigs (fp_decoder_io_sigs)
);
FIRRTLMem_3_2_0_65_32_0_1_1_0_1_aa regfile ( // FPU.scala:547:20
.R0_addr (ex_ra1), // FPU.scala:557:39
.R0_en (1'h1), // ../perf/regress/FPU.fir:3:10
.R0_clk (clock),
.R1_addr (ex_ra2), // FPU.scala:558:38
.R1_en (1'h1), // ../perf/regress/FPU.fir:3:10
.R1_clk (clock),
.R2_addr (ex_ra3), // FPU.scala:562:38
.R2_en (1'h1), // ../perf/regress/FPU.fir:3:10
.R2_clk (clock),
.W0_addr (_T_168),
.W0_en (~_T_153 & _wen_0 | divSqrt_wen), // FPU.scala:651:33, :668:18, :676:{10,24,35}
.W0_clk (clock),
.W0_data (_T_174),
.W0_mask (1'h1), // ../perf/regress/FPU.fir:3:10
.W1_addr (load_wb_tag), // Reg.scala:35:23
.W1_en (load_wb), // ../perf/regress/FPU.fir:376:7
.W1_clk (clock),
.W1_data (load_wb_single ? {32'h70020000, load_wb_data[31], _T_105 & {~{3{_T_102 &
~(|_load_wb_data_22to0)}}, 6'h3F} | {2'h0, &(_T_105[8:7]) & |_load_wb_data_22to0, 6'h0},
_T_102 ? {_T_104[21:0], 1'h0} : _load_wb_data_22to0} : {load_wb_data[63], _T_110 &
{~{3{_T_106 & ~(|_load_wb_data_51to0)}}, 9'h1FF} | {2'h0, &(_T_110[11:10]) &
|_load_wb_data_51to0, 9'h0}, _T_106 ? {_T_109[50:0], 1'h0} : _load_wb_data_51to0}), // Bitwise.scala:71:12, Cat.scala:30:58, FPU.scala:509:25, :543:{10,33}, :631:23, Reg.scala:35:23, recFNFromFN.scala:47:22, :52:38, :53:34, :56:{13,26}, :58:37, :64:42, :67:{25,50,63}, :71:{26,28,45,64}, :73:27
.W1_mask (1'h1), // ../perf/regress/FPU.fir:3:10
.R0_data (regfile_R0_data),
.R1_data (regfile_R1_data),
.R2_data (regfile_R2_data)
);
FPUFMAPipe sfma ( // FPU.scala:584:20
.clock (clock),
.reset (reset),
.io_in (_io_in_wire), // FPU.scala:584:20
.io_out (sfma_io_out)
);
FPToInt fpiu ( // FPU.scala:588:20
.clock (clock),
.reset (reset),
.io_in (_io_in_wire_3), // FPU.scala:588:20
.io_as_double (fpiu_io_as_double),
.io_out (fpiu_io_out)
);
IntToFP ifpu ( // FPU.scala:598:20
.clock (clock),
.reset (reset),
.io_in (_io_in_wire_4), // FPU.scala:598:20
.io_out (ifpu_io_out)
);
FPToFP fpmu ( // FPU.scala:603:20
.clock (clock),
.reset (reset),
.io_in (_io_in_wire_5), // FPU.scala:603:20
.io_lt (_T_139.lt), // FPU.scala:606:14
.io_out (fpmu_io_out)
);
FPUFMAPipe_1 FPUFMAPipe ( // FPU.scala:624:28
.clock (clock),
.reset (reset),
.io_in (_io_in_wire_6), // FPU.scala:624:28
.io_out (FPUFMAPipe_io_out)
);
DivSqrtRecF64 DivSqrtRecF64 ( // FPU.scala:722:25
.clock (clock),
.reset (reset),
.io_inValid (_T_183),
.io_sqrtOp (_T_68), // Reg.scala:35:23
.io_a (fpiu_io_as_double.in1), // FPU.scala:588:20, :727:18
.io_b (fpiu_io_as_double.in2), // FPU.scala:588:20, :728:18
.io_roundingMode (_T_185),
.io_inReady_div (DivSqrtRecF64_io_inReady_div),
.io_inReady_sqrt (DivSqrtRecF64_io_inReady_sqrt),
.io_outValid_div (DivSqrtRecF64_io_outValid_div),
.io_outValid_sqrt (DivSqrtRecF64_io_outValid_sqrt),
.io_out (DivSqrtRecF64_io_out),
.io_exceptionFlags (DivSqrtRecF64_io_exceptionFlags)
);
RecFNToRecFN_2 RecFNToRecFN ( // FPU.scala:746:34
.clock (clock),
.reset (reset),
.io_in (_T_10_182), // FPU.scala:741:28
.io_roundingMode (_T_8_180), // FPU.scala:736:18
.io_out (RecFNToRecFN_io_out),
.io_exceptionFlags (RecFNToRecFN_io_exceptionFlags)
);
assign io_fcsr_flags = _io_fcsr_flags_output; // ../perf/regress/FPU.fir:3:10
assign io_store_data = _T_139.store; // ../perf/regress/FPU.fir:3:10, FPU.scala:591:17
assign io_toint_data = _T_140; // ../perf/regress/FPU.fir:3:10
assign io_fcsr_rdy = ~(ex_reg_valid & _T_85 | mem_reg_valid & _T_69 | _T_176 | |wen | divSqrt_in_flight); // ../perf/regress/FPU.fir:3:10, FPU.scala:510:32, :517:45, :648:101, :703:97, :704:{18,33,68,131}, Reg.scala:35:23
assign io_nack_mem = _T_178; // ../perf/regress/FPU.fir:3:10
assign io_illegal_rm = io_inst[14] & (io_inst[13:12] != 2'h3 | io_fcsr_rm[2]); // ../perf/regress/FPU.fir:3:10, CircuitMath.scala:32:10, FPU.scala:712:{27,32,43,51,55,69}
assign io_dec = _io_dec_output; // ../perf/regress/FPU.fir:3:10
assign io_sboard_set = wb_reg_valid & ~wb_cp_valid & _T_7_179; // ../perf/regress/FPU.fir:3:10, FPU.scala:695:37, :708:{36,49}
assign io_sboard_clr = ~wb_cp_valid & (divSqrt_wen | _wen_0 & &_T_154); // ../perf/regress/FPU.fir:3:10, FPU.scala:651:33, :668:18, :708:36, :709:{33,49,60,99}
assign io_sboard_clra = _T_168; // ../perf/regress/FPU.fir:3:10
assign io_cp_req_ready = ~ex_reg_valid; // ../perf/regress/FPU.fir:3:10, FPU.scala:510:32, :693:22
assign io_cp_resp_valid = _T_175 | _T_141; // ../perf/regress/FPU.fir:3:10, FPU.scala:691:22
assign io_cp_resp_bits = _io_cp_resp_bits_output; // ../perf/regress/FPU.fir:3:10
endmodule
module FPUDecoder( // ../perf/regress/FPU.fir:787:10
input clock,
input reset,
input [31:0] io_inst,
output struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; } io_sigs);
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; } _io_sigs_output; // ../perf/regress/FPU.fir:787:10
wire _io_inst_6 = io_inst[6]; // Decode.scala:13:65
wire _T = {io_inst[6], io_inst[4]} == 2'h2; // Decode.scala:13:{65,121}
wire _io_inst_5 = io_inst[5]; // Decode.scala:13:65
assign _io_sigs_output.cmd = {~(io_inst[4]), ~_io_inst_6 | io_inst[30], ~_io_inst_6 | io_inst[29], io_inst[3] |
&{io_inst[28], io_inst[4]}, io_inst[2] | &{io_inst[27], io_inst[4]}}; // ../perf/regress/FPU.fir:792:8, Cat.scala:30:58, Decode.scala:13:{65,121}, :14:30, FPU.scala:149:40
assign _io_sigs_output.ldst = ~_io_inst_6; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:121, FPU.scala:149:40
assign _io_sigs_output.wen = {io_inst[31], io_inst[5]} == 2'h0 | io_inst[5:4] == 2'h0 | {io_inst[28], io_inst[5]} ==
2'h2; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, :14:30, FPU.scala:149:40
assign _io_sigs_output.ren1 = {io_inst[31], io_inst[2]} == 2'h0 | {io_inst[28], io_inst[2]} == 2'h0 | _T; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, :14:30, FPU.scala:149:40
assign _io_sigs_output.ren2 = {io_inst[30], io_inst[2]} == 2'h0 | _io_inst_5 | _T; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, :14:30, FPU.scala:149:40
assign _io_sigs_output.ren3 = _T; // ../perf/regress/FPU.fir:792:8, FPU.scala:149:40
assign _io_sigs_output.swap12 = ~_io_inst_6 | &{io_inst[30], io_inst[28], io_inst[4]}; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, :14:30, FPU.scala:149:40
assign _io_sigs_output.swap23 = {io_inst[29:28], io_inst[4]} == 3'h1; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, FPU.scala:149:40
assign _io_sigs_output.single = {io_inst[12], io_inst[6]} == 2'h0 | {io_inst[25], io_inst[6]} == 2'h1; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, :14:30, FPU.scala:149:40
assign _io_sigs_output.fromint = &{io_inst[31], io_inst[28], io_inst[4]}; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, FPU.scala:149:40
assign _io_sigs_output.toint = _io_inst_5 | {io_inst[31], io_inst[28], io_inst[4]} == 3'h5; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, :14:30, FPU.scala:149:40
assign _io_sigs_output.fastpipe = {io_inst[31], io_inst[29], io_inst[4]} == 3'h3 | {io_inst[31:30], io_inst[28], io_inst[4]}
== 4'h5; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, :14:30, FPU.scala:149:40
assign _io_sigs_output.fma = {io_inst[30:28], io_inst[2]} == 4'h0 | {io_inst[30:29], io_inst[27], io_inst[2]} == 4'h0 |
_T; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, :14:30, FPU.scala:149:40
assign _io_sigs_output.div = {io_inst[30], io_inst[28:27], io_inst[4]} == 4'h7; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, FPU.scala:149:40
assign _io_sigs_output.sqrt = {io_inst[31:30], io_inst[28], io_inst[4]} == 4'h7; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, FPU.scala:149:40
assign _io_sigs_output.wflags = {io_inst[29], io_inst[2]} == 2'h0 | _T | {io_inst[27], io_inst[13]} == 2'h2 |
{io_inst[31:30], io_inst[2]} == 3'h4; // ../perf/regress/FPU.fir:792:8, Decode.scala:13:{65,121}, :14:30, FPU.scala:149:40
assign io_sigs = _io_sigs_output; // ../perf/regress/FPU.fir:787:10
endmodule
module FPUFMAPipe( // ../perf/regress/FPU.fir:916:10
input clock,
input reset,
input struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } io_in,
output struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } io_out);
wire [32:0] fma_io_out; // FPU.scala:493:19
wire [4:0] fma_io_exceptionFlags; // FPU.scala:493:19
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } _io_out_output; // ../perf/regress/FPU.fir:916:10
reg valid; // FPU.scala:482:18
struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } in; // FPU.scala:483:15
wire struct packed {logic [64:0] data; logic [4:0] exc; } res; // FPU.scala:500:17
reg _T_35; // Valid.scala:47:18
struct packed {logic [64:0] data; logic [4:0] exc; } _T_0_36; // Reg.scala:34:16
reg _T_1_39; // Valid.scala:47:18
struct packed {logic [64:0] data; logic [4:0] exc; } _T_2_40; // Reg.scala:34:16
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } _T_3_43; // Valid.scala:42:21
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T = io_in.bits; // ../perf/regress/FPU.fir:921:8
wire [64:0] _T_0 = _T.in1; // FPU.scala:480:29
wire [64:0] _T_1 = _T.in2; // FPU.scala:480:53
wire _T_2 = io_in.valid; // FPU.scala:482:18
wire [4:0] _T_3 = in.cmd; // FPU.scala:483:15
wire _T_4 = in.ldst; // FPU.scala:483:15
wire _T_5 = in.wen; // FPU.scala:483:15
wire _T_6 = in.ren1; // FPU.scala:483:15
wire _T_7 = in.ren2; // FPU.scala:483:15
wire _T_8 = in.ren3; // FPU.scala:483:15
wire _T_9 = in.swap12; // FPU.scala:483:15
wire _T_10 = in.swap23; // FPU.scala:483:15
wire _T_11 = in.single; // FPU.scala:483:15
wire _T_12 = in.fromint; // FPU.scala:483:15
wire _T_13 = in.toint; // FPU.scala:483:15
wire _T_14 = in.fastpipe; // FPU.scala:483:15
wire _T_15 = in.fma; // FPU.scala:483:15
wire _T_16 = in.div; // FPU.scala:483:15
wire _T_17 = in.sqrt; // FPU.scala:483:15
wire _T_18 = in.wflags; // FPU.scala:483:15
wire [2:0] _T_19 = in.rm; // FPU.scala:483:15
wire [1:0] _T_20 = in.typ; // FPU.scala:483:15
wire [64:0] _T_21 = in.in1; // FPU.scala:483:15
wire [64:0] _T_22 = in.in2; // FPU.scala:483:15
wire [64:0] _T_23 = in.in3; // FPU.scala:483:15
assign _T_4 = _T_2 ? _T.ldst : _T_4; // FPU.scala:485:8
assign _T_5 = _T_2 ? _T.wen : _T_5; // FPU.scala:485:8
assign _T_6 = _T_2 ? _T.ren1 : _T_6; // FPU.scala:485:8
assign _T_7 = _T_2 ? _T.ren2 : _T_7; // FPU.scala:485:8
wire _T_24 = _T.ren3; // FPU.scala:485:8
assign _T_8 = _T_2 ? _T_24 : _T_8; // FPU.scala:485:8
assign _T_9 = _T_2 ? _T.swap12 : _T_9; // FPU.scala:485:8
wire _T_25 = _T.swap23; // FPU.scala:485:8
assign _T_10 = _T_2 ? _T_25 : _T_10; // FPU.scala:485:8
assign _T_11 = _T_2 ? _T.single : _T_11; // FPU.scala:485:8
assign _T_12 = _T_2 ? _T.fromint : _T_12; // FPU.scala:485:8
assign _T_13 = _T_2 ? _T.toint : _T_13; // FPU.scala:485:8
assign _T_14 = _T_2 ? _T.fastpipe : _T_14; // FPU.scala:485:8
assign _T_15 = _T_2 ? _T.fma : _T_15; // FPU.scala:485:8
assign _T_16 = _T_2 ? _T.div : _T_16; // FPU.scala:485:8
assign _T_17 = _T_2 ? _T.sqrt : _T_17; // FPU.scala:485:8
assign _T_18 = _T_2 ? _T.wflags : _T_18; // FPU.scala:485:8
assign _T_19 = _T_2 ? _T.rm : _T_19; // FPU.scala:485:8
assign _T_20 = _T_2 ? _T.typ : _T_20; // FPU.scala:485:8
assign _T_21 = _T_2 ? _T_0 : _T_21; // FPU.scala:485:8
wire [4:0] _T_26 = _T.cmd; // FPU.scala:488:33
wire _T_27 = _T_24 | _T_25; // FPU.scala:488:48
assign _T_3 = _T_2 ? {3'h0, _T_26[1] & _T_27, _T_26[0]} : _T_3; // FPU.scala:488:{12,33,37,78}
assign _T_22 = _T_2 ? (_T_25 ? 65'h80000000 : _T_1) : _T_22; // FPU.scala:489:32
assign _T_23 = _T_2 ? (_T_27 ? _T.in3 : {32'h0, _T_0[32] ^ _T_1[32], 32'h0}) : _T_23; // FPU.scala:480:{29,37,53,62}, :485:8, :490:45
wire [4:0] _T_28 = _T_3; // FPU.scala:488:12
wire [2:0] _T_29 = _T_19; // FPU.scala:485:8
wire [64:0] _T_30 = _T_21; // FPU.scala:485:8
wire [64:0] _T_31 = _T_22; // FPU.scala:489:32
wire [64:0] _T_32 = _T_23; // FPU.scala:490:45
wire [64:0] _T_33 = res.data; // FPU.scala:500:17
wire [4:0] _T_34 = res.exc; // FPU.scala:500:17
assign _T_33 = {32'h0, fma_io_out}; // FPU.scala:480:62, :493:19, :501:12
assign _T_34 = fma_io_exceptionFlags; // FPU.scala:493:19, :502:11
wire [64:0] _T_37 = _T_0_36.data; // Reg.scala:34:16
wire [4:0] _T_38 = _T_0_36.exc; // Reg.scala:34:16
assign _T_37 = valid ? _T_33 : _T_37; // Reg.scala:35:23, Valid.scala:47:18
assign _T_38 = valid ? _T_34 : _T_38; // Reg.scala:35:23, Valid.scala:47:18
always @(posedge clock) begin // Valid.scala:47:18
valid <= _T_2; // FPU.scala:482:18
if (reset) begin // Valid.scala:47:18
_T_35 <= 1'h0; // Conditional.scala:19:11, Valid.scala:47:18
_T_1_39 <= 1'h0; // Conditional.scala:19:11, Valid.scala:47:18
end
else begin // Valid.scala:47:18
_T_35 <= valid; // Valid.scala:47:18
_T_1_39 <= _T_35; // Valid.scala:47:18
end
end // always @(posedge)
`ifndef SYNTHESIS // FPU.scala:482:18
initial begin // FPU.scala:482:18
automatic logic [31:0] _RANDOM; // FPU.scala:482:18
automatic logic [31:0] _RANDOM_49; // FPU.scala:483:15
automatic logic [31:0] _RANDOM_50; // FPU.scala:483:15
automatic logic [31:0] _RANDOM_51; // FPU.scala:483:15
automatic logic [31:0] _RANDOM_52; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_53; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_54; // Reg.scala:34:16
`INIT_RANDOM_PROLOG_ // FPU.scala:482:18
`ifdef RANDOMIZE_REG_INIT // FPU.scala:482:18
_RANDOM = `RANDOM; // FPU.scala:482:18
valid = _RANDOM[0]; // FPU.scala:482:18
_T_3 = _RANDOM[5:1]; // FPU.scala:483:15
_T_4 = _RANDOM[6]; // FPU.scala:483:15
_T_5 = _RANDOM[7]; // FPU.scala:483:15
_T_6 = _RANDOM[8]; // FPU.scala:483:15
_T_7 = _RANDOM[9]; // FPU.scala:483:15
_T_8 = _RANDOM[10]; // FPU.scala:483:15
_T_9 = _RANDOM[11]; // FPU.scala:483:15
_T_10 = _RANDOM[12]; // FPU.scala:483:15
_T_11 = _RANDOM[13]; // FPU.scala:483:15
_T_12 = _RANDOM[14]; // FPU.scala:483:15
_T_13 = _RANDOM[15]; // FPU.scala:483:15
_T_14 = _RANDOM[16]; // FPU.scala:483:15
_T_15 = _RANDOM[17]; // FPU.scala:483:15
_T_16 = _RANDOM[18]; // FPU.scala:483:15
_T_17 = _RANDOM[19]; // FPU.scala:483:15
_T_18 = _RANDOM[20]; // FPU.scala:483:15
_T_19 = _RANDOM[23:21]; // FPU.scala:483:15
_T_20 = _RANDOM[25:24]; // FPU.scala:483:15
_RANDOM_49 = `RANDOM; // FPU.scala:483:15
_T_21 = {_RANDOM[31:26], `RANDOM, _RANDOM_49[26:0]}; // FPU.scala:483:15
_RANDOM_50 = `RANDOM; // FPU.scala:483:15
_T_22 = {_RANDOM_49[31:27], `RANDOM, _RANDOM_50[27:0]}; // FPU.scala:483:15
_RANDOM_51 = `RANDOM; // FPU.scala:483:15
_T_23 = {_RANDOM_50[31:28], `RANDOM, _RANDOM_51[28:0]}; // FPU.scala:483:15
_T_35 = _RANDOM_51[29]; // Valid.scala:47:18
_RANDOM_52 = `RANDOM; // Reg.scala:34:16
_T_37 = {_RANDOM_51[31:30], `RANDOM, _RANDOM_52[30:0]}; // Reg.scala:34:16
_RANDOM_53 = `RANDOM; // Reg.scala:34:16
_T_38 = {_RANDOM_52[31], _RANDOM_53[3:0]}; // Reg.scala:34:16
_T_1_39 = _RANDOM_53[4]; // Valid.scala:47:18
_RANDOM_54 = `RANDOM; // Reg.scala:34:16
_T_2_40.data = {_RANDOM_53[31:5], `RANDOM, _RANDOM_54[5:0]}; // Reg.scala:34:16
_T_2_40.exc = _RANDOM_54[10:6]; // Reg.scala:34:16
`endif
end // initial
`endif
wire [64:0] _T_41 = _T_2_40.data; // Reg.scala:34:16
wire [4:0] _T_42 = _T_2_40.exc; // Reg.scala:34:16
assign _T_41 = _T_35 ? _T_37 : _T_41; // Reg.scala:35:23, Valid.scala:47:18
assign _T_42 = _T_35 ? _T_38 : _T_42; // Reg.scala:35:23, Valid.scala:47:18
wire _T_44 = _T_3_43.valid; // Valid.scala:42:21
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_45 = _T_3_43.bits; // Valid.scala:42:21
assign _T_44 = _T_1_39; // Valid.scala:43:17
wire [64:0] _T_46 = _T_45.data; // Valid.scala:44:16
assign _T_46 = _T_41; // Reg.scala:35:23, Valid.scala:44:16
wire [4:0] _T_47 = _T_45.exc; // Valid.scala:44:16
assign _T_47 = _T_42; // Reg.scala:35:23, Valid.scala:44:16
assign _io_out_output.valid = _T_44; // FPU.scala:503:10
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_48 = _io_out_output.bits; // FPU.scala:503:10
assign _T_48.data = _T_46; // FPU.scala:503:10
assign _T_48.exc = _T_47; // FPU.scala:503:10
MulAddRecFN fma ( // FPU.scala:493:19
.clock (clock),
.reset (reset),
.io_op (_T_28[1:0]), // FPU.scala:494:13
.io_a (_T_30[32:0]), // FPU.scala:496:12
.io_b (_T_31[32:0]), // FPU.scala:497:12
.io_c (_T_32[32:0]), // FPU.scala:498:12
.io_roundingMode (_T_29[1:0]), // FPU.scala:495:23
.io_out (fma_io_out),
.io_exceptionFlags (fma_io_exceptionFlags)
);
assign io_out = _io_out_output; // ../perf/regress/FPU.fir:916:10
endmodule
module FPToInt( // ../perf/regress/FPU.fir:979:10
input clock,
input reset,
input struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } io_in,
output struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } io_as_double,
output struct packed {logic valid; struct packed {logic lt; logic [63:0] store; logic [63:0] toint; logic [4:0] exc; } bits; } io_out);
wire _T; // FPU.scala:339:35
wire [63:0] RecFNToIN_1_io_out; // FPU.scala:336:24
wire [2:0] RecFNToIN_1_io_intExceptionFlags; // FPU.scala:336:24
wire [31:0] RecFNToIN_io_out; // FPU.scala:336:24
wire [2:0] RecFNToIN_io_intExceptionFlags; // FPU.scala:336:24
wire dcmp_io_lt; // FPU.scala:319:20
wire dcmp_io_eq; // FPU.scala:319:20
wire dcmp_io_gt; // FPU.scala:319:20
wire [4:0] dcmp_io_exceptionFlags; // FPU.scala:319:20
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _io_as_double_output; // ../perf/regress/FPU.fir:979:10
wire struct packed {logic valid; struct packed {logic lt; logic [63:0] store; logic [63:0] toint; logic [4:0] exc; } bits; } _io_out_output; // ../perf/regress/FPU.fir:979:10
struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } in; // FPU.scala:286:15
reg valid; // FPU.scala:287:18
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T_0 = io_in.bits; // ../perf/regress/FPU.fir:984:8
wire struct packed {logic lt; logic [63:0] store; logic [63:0] toint; logic [4:0] exc; } _T_1 = _io_out_output.bits; // ../perf/regress/FPU.fir:984:8
wire [4:0] _T_2 = in.cmd; // FPU.scala:286:15
wire _T_3 = in.ldst; // FPU.scala:286:15
wire _T_4 = in.wen; // FPU.scala:286:15
wire _T_5 = in.ren1; // FPU.scala:286:15
wire _T_6 = in.ren2; // FPU.scala:286:15
wire _T_7 = in.ren3; // FPU.scala:286:15
wire _T_8 = in.swap12; // FPU.scala:286:15
wire _T_9 = in.swap23; // FPU.scala:286:15
wire _T_10 = in.single; // FPU.scala:286:15
wire _T_11 = in.fromint; // FPU.scala:286:15
wire _T_12 = in.toint; // FPU.scala:286:15
wire _T_13 = in.fastpipe; // FPU.scala:286:15
wire _T_14 = in.fma; // FPU.scala:286:15
wire _T_15 = in.div; // FPU.scala:286:15
wire _T_16 = in.sqrt; // FPU.scala:286:15
wire _T_17 = in.wflags; // FPU.scala:286:15
wire [2:0] _T_18 = in.rm; // FPU.scala:286:15
wire [1:0] _T_19 = in.typ; // FPU.scala:286:15
wire [64:0] _T_20 = in.in1; // FPU.scala:286:15
wire [64:0] _T_21 = in.in2; // FPU.scala:286:15
wire [64:0] _T_22 = in.in3; // FPU.scala:286:15
`ifndef SYNTHESIS // FPU.scala:286:15
initial begin // FPU.scala:286:15
automatic logic [31:0] _RANDOM; // FPU.scala:286:15
automatic logic [31:0] _RANDOM_91; // FPU.scala:286:15
automatic logic [31:0] _RANDOM_92; // FPU.scala:286:15
automatic logic [31:0] _RANDOM_93; // FPU.scala:286:15
`INIT_RANDOM_PROLOG_ // FPU.scala:286:15
`ifdef RANDOMIZE_REG_INIT // FPU.scala:286:15
_RANDOM = `RANDOM; // FPU.scala:286:15
_T_2 = _RANDOM[4:0]; // FPU.scala:286:15
_T_3 = _RANDOM[5]; // FPU.scala:286:15
_T_4 = _RANDOM[6]; // FPU.scala:286:15
_T_5 = _RANDOM[7]; // FPU.scala:286:15
_T_6 = _RANDOM[8]; // FPU.scala:286:15
_T_7 = _RANDOM[9]; // FPU.scala:286:15
_T_8 = _RANDOM[10]; // FPU.scala:286:15
_T_9 = _RANDOM[11]; // FPU.scala:286:15
_T_10 = _RANDOM[12]; // FPU.scala:286:15
_T_11 = _RANDOM[13]; // FPU.scala:286:15
_T_12 = _RANDOM[14]; // FPU.scala:286:15
_T_13 = _RANDOM[15]; // FPU.scala:286:15
_T_14 = _RANDOM[16]; // FPU.scala:286:15
_T_15 = _RANDOM[17]; // FPU.scala:286:15
_T_16 = _RANDOM[18]; // FPU.scala:286:15
_T_17 = _RANDOM[19]; // FPU.scala:286:15
_T_18 = _RANDOM[22:20]; // FPU.scala:286:15
_T_19 = _RANDOM[24:23]; // FPU.scala:286:15
_RANDOM_91 = `RANDOM; // FPU.scala:286:15
_T_20 = {_RANDOM[31:25], `RANDOM, _RANDOM_91[25:0]}; // FPU.scala:286:15
_RANDOM_92 = `RANDOM; // FPU.scala:286:15
_T_21 = {_RANDOM_91[31:26], `RANDOM, _RANDOM_92[26:0]}; // FPU.scala:286:15
_RANDOM_93 = `RANDOM; // FPU.scala:286:15
_T_22 = {_RANDOM_92[31:27], `RANDOM, _RANDOM_93[27:0]}; // FPU.scala:286:15
valid = _RANDOM_93[28]; // FPU.scala:287:18
`endif
end // initial
`endif
wire _T_23 = io_in.valid; // FPU.scala:287:18
always @(posedge clock) // FPU.scala:287:18
valid <= _T_23; // FPU.scala:287:18
wire [4:0] _T_24 = _T_0.cmd; // FPU.scala:292:8
assign _T_2 = _T_23 ? _T_24 : _T_2; // FPU.scala:292:8
wire _T_25 = _T_0.ldst; // FPU.scala:292:8
assign _T_3 = _T_23 ? _T_25 : _T_3; // FPU.scala:292:8
assign _T_4 = _T_23 ? _T_0.wen : _T_4; // FPU.scala:292:8
assign _T_5 = _T_23 ? _T_0.ren1 : _T_5; // FPU.scala:292:8
assign _T_6 = _T_23 ? _T_0.ren2 : _T_6; // FPU.scala:292:8
assign _T_7 = _T_23 ? _T_0.ren3 : _T_7; // FPU.scala:292:8
assign _T_8 = _T_23 ? _T_0.swap12 : _T_8; // FPU.scala:292:8
assign _T_9 = _T_23 ? _T_0.swap23 : _T_9; // FPU.scala:292:8
wire _T_26 = _T_0.single; // FPU.scala:292:8
assign _T_10 = _T_23 ? _T_26 : _T_10; // FPU.scala:292:8
assign _T_11 = _T_23 ? _T_0.fromint : _T_11; // FPU.scala:292:8
assign _T_12 = _T_23 ? _T_0.toint : _T_12; // FPU.scala:292:8
assign _T_13 = _T_23 ? _T_0.fastpipe : _T_13; // FPU.scala:292:8
assign _T_14 = _T_23 ? _T_0.fma : _T_14; // FPU.scala:292:8
assign _T_15 = _T_23 ? _T_0.div : _T_15; // FPU.scala:292:8
assign _T_16 = _T_23 ? _T_0.sqrt : _T_16; // FPU.scala:292:8
assign _T_17 = _T_23 ? _T_0.wflags : _T_17; // FPU.scala:292:8
assign _T_18 = _T_23 ? _T_0.rm : _T_18; // FPU.scala:292:8
assign _T_19 = _T_23 ? _T_0.typ : _T_19; // FPU.scala:292:8
wire [64:0] _T_27 = _T_0.in1; // FPU.scala:292:8
wire [64:0] _T_28 = _T_0.in2; // FPU.scala:292:8
assign _T_22 = _T_23 ? _T_0.in3 : _T_22; // FPU.scala:292:8
wire _T_29 = _T_26 & ~_T_25 & _T_24[3:2] != 2'h3; // FPU.scala:293:{47,64,82}, fNFromRecFN.scala:58:55
wire [2:0] _T_30 = _T_27[31:29]; // FPU.scala:242:26
wire [11:0] _T_31 = {3'h0, _T_27[31:23]} + 12'h700; // Cat.scala:30:58, FPU.scala:239:19, :243:{31,53}
assign _T_20 = _T_23 ? (_T_29 ? {_T_27[32], _T_30 == 3'h0 | _T_30 > 3'h5 ? {_T_30, _T_31[8:0]} : _T_31,
_T_27[22:0], 29'h0} : _T_27) : _T_20; // Cat.scala:30:58, FPU.scala:237:18, :238:21, :240:43, :244:{10,19,25,36,65}, :294:14
wire [2:0] _T_32 = _T_28[31:29]; // FPU.scala:242:26
wire [11:0] _T_33 = {3'h0, _T_28[31:23]} + 12'h700; // Cat.scala:30:58, FPU.scala:239:19, :243:{31,53}
assign _T_21 = _T_23 ? (_T_29 ? {_T_28[32], _T_32 == 3'h0 | _T_32 > 3'h5 ? {_T_32, _T_33[8:0]} : _T_33,
_T_28[22:0], 29'h0} : _T_28) : _T_21; // Cat.scala:30:58, FPU.scala:237:18, :238:21, :240:43, :244:{10,19,25,36,65}, :295:14
wire [64:0] _T_34 = _T_20; // FPU.scala:294:14
wire _T_35 = _T_34[32]; // fNFromRecFN.scala:45:22
wire [64:0] _T_36 = _T_20; // FPU.scala:294:14
wire [22:0] _T_37 = _T_36[22:0]; // fNFromRecFN.scala:47:25
wire [64:0] _T_38 = _T_20; // FPU.scala:294:14
wire _T_39 = _T_38[29:23] < 7'h2; // fNFromRecFN.scala:49:{39,57}
wire [64:0] _T_40 = _T_20; // FPU.scala:294:14
wire [2:0] _T_41 = _T_40[31:29]; // fNFromRecFN.scala:51:19
wire [64:0] _T_42 = _T_20; // FPU.scala:294:14
wire [1:0] _T_43 = _T_42[31:30]; // fNFromRecFN.scala:52:24
wire _T_44 = _T_43 == 2'h1; // fNFromRecFN.scala:52:49
wire _T_45 = _T_41 == 3'h1 | _T_44 & _T_39; // fNFromRecFN.scala:51:{44,57}, :52:62
wire _T_46 = _T_44 & ~_T_39 | _T_43 == 2'h2; // fNFromRecFN.scala:49:57, :55:58, :56:{18,39}, :57:48
wire [64:0] _T_47 = _T_20; // FPU.scala:294:14
wire _T_48 = _T_47[29]; // fNFromRecFN.scala:59:39
wire [64:0] _T_49 = _T_20; // FPU.scala:294:14
wire [23:0] _T_50 = {1'h1, _T_37} >> 5'h2 - _T_49[27:23]; // Cat.scala:30:58, fNFromRecFN.scala:51:44, :61:{39,46}, :63:35
wire [64:0] _T_51 = _T_20; // FPU.scala:294:14
wire [64:0] _T_52 = _T_20; // FPU.scala:294:14
wire _T_53 = _T_52[64]; // fNFromRecFN.scala:45:22
wire [64:0] _T_54 = _T_20; // FPU.scala:294:14
wire [51:0] _T_55 = _T_54[51:0]; // fNFromRecFN.scala:47:25
wire [64:0] _T_56 = _T_20; // FPU.scala:294:14
wire _T_57 = _T_56[61:52] < 10'h2; // fNFromRecFN.scala:49:{39,57}
wire [64:0] _T_58 = _T_20; // FPU.scala:294:14
wire [2:0] _T_59 = _T_58[63:61]; // fNFromRecFN.scala:51:19
wire [64:0] _T_60 = _T_20; // FPU.scala:294:14
wire [1:0] _T_61 = _T_60[63:62]; // fNFromRecFN.scala:52:24
wire _T_62 = _T_61 == 2'h1; // fNFromRecFN.scala:52:49
wire _T_63 = _T_59 == 3'h1 | _T_62 & _T_57; // fNFromRecFN.scala:51:{44,57}, :52:62
wire _T_64 = _T_62 & ~_T_57 | _T_61 == 2'h2; // fNFromRecFN.scala:49:57, :55:58, :56:{18,39}, :57:48
wire [64:0] _T_65 = _T_20; // FPU.scala:294:14
wire _T_66 = _T_65[61]; // fNFromRecFN.scala:59:39
wire [64:0] _T_67 = _T_20; // FPU.scala:294:14
wire [52:0] _T_68 = {1'h1, _T_55} >> 6'h2 - _T_67[57:52]; // Cat.scala:30:58, fNFromRecFN.scala:51:44, :61:{39,46}, :63:35
wire [64:0] _T_69 = _T_20; // FPU.scala:294:14
wire [63:0] _T_70 = _T_10 ? {{33{_T_35}}, _T_46 ? _T_51[30:23] + 8'h7F : {8{&_T_43}}, _T_46 | &_T_43 & _T_48 ?
_T_37 : _T_45 ? _T_50[22:0] : 23'h0} : {_T_53, _T_64 ? _T_69[62:52] + 11'h3FF :
{11{&_T_61}}, _T_64 | &_T_61 & _T_66 ? _T_55 : _T_63 ? _T_68[51:0] : 52'h0}; // Bitwise.scala:71:12, Cat.scala:30:58, FPU.scala:292:8, :304:10, fNFromRecFN.scala:58:55, :59:31, :63:53, :65:{18,36}, :68:16, :70:{16,26}, :72:20
wire _T_71 = _T_41 == 3'h0; // Cat.scala:30:58, FPU.scala:212:23
wire _T_72 = &_T_43 & ~_T_48; // FPU.scala:213:{27,30}, fNFromRecFN.scala:58:55
wire [64:0] _T_73 = _T_20; // FPU.scala:294:14
wire _T_74 = _T_73[22]; // FPU.scala:215:31
wire _T_75 = _T_59 == 3'h0; // Cat.scala:30:58, FPU.scala:212:23
wire _T_76 = &_T_61 & ~_T_66; // FPU.scala:213:{27,30}, fNFromRecFN.scala:58:55
wire [64:0] _T_77 = _T_20; // FPU.scala:294:14
wire _T_78 = _T_77[51]; // FPU.scala:215:31
wire [2:0] _T_79 = _T_18; // FPU.scala:292:8
wire [2:0] _T_80 = _T_18; // FPU.scala:292:8
assign _T_1.store = _T_70; // ../perf/regress/FPU.fir:984:8, FPU.scala:325:21
wire [4:0] _T_81 = _T_2; // FPU.scala:292:8
wire [4:0] _T_82 = _T_2; // FPU.scala:292:8
wire _T_83 = _T_82[3:2] == 2'h1; // FPU.scala:328:16, fNFromRecFN.scala:52:49
wire [2:0] _T_84 = _T_18; // FPU.scala:292:8
wire _T_85 = _T_81[3:2] == 2'h2; // FPU.scala:328:16, :332:16, fNFromRecFN.scala:49:57
wire [2:0] _T_86 = _T_18; // FPU.scala:292:8
wire [1:0] _T_87 = _T_86[1:0]; // FPU.scala:338:28
wire [1:0] _T_88 = _T_19; // FPU.scala:292:8
assign _T = _T_88[0]; // FPU.scala:339:35
wire [1:0] _T_89 = _T_19; // FPU.scala:292:8
wire _T_90 = _T_89[1]; // Package.scala:44:13
assign _T_1.toint = _T_85 ? (_T_90 ? RecFNToIN_1_io_out : {{32{RecFNToIN_io_out[31]}}, RecFNToIN_io_out}) :
_T_83 ? {63'h0, |(~(_T_84[1:0]) & {dcmp_io_lt, dcmp_io_eq})} : _T_80[0] ? {54'h0, _T_10 ?
{&_T_41 & _T_74, &_T_41 & ~_T_74, _T_72 & ~_T_35, _T_46 & ~_T_35, _T_45 & ~_T_35, _T_71 &
~_T_35, _T_71 & _T_35, _T_45 & _T_35, _T_46 & _T_35, _T_72 & _T_35} : {&_T_59 & _T_78,
&_T_59 & ~_T_78, _T_76 & ~_T_53, _T_64 & ~_T_53, _T_63 & ~_T_53, _T_75 & ~_T_53, _T_75 &
_T_53, _T_63 & _T_53, _T_64 & _T_53, _T_76 & _T_53}} : _T_70; // ../perf/regress/FPU.fir:984:8, Bitwise.scala:71:12, Cat.scala:30:58, FPU.scala:214:22, :215:{24,27}, :216:24, :218:{31,34,50}, :219:{21,38,55}, :220:{21,39,54}, :292:8, :316:10, :319:20, :324:{27,33}, :329:{23,27,34,65}, :336:24, :341:27, Package.scala:40:38
assign _T_1.exc = _T_85 ? (_T_90 ? {|(RecFNToIN_1_io_intExceptionFlags[2:1]), 3'h0,
RecFNToIN_1_io_intExceptionFlags[0]} : {|(RecFNToIN_io_intExceptionFlags[2:1]), 3'h0,
RecFNToIN_io_intExceptionFlags[0]}) : _T_83 ? dcmp_io_exceptionFlags : 5'h0; // ../perf/regress/FPU.fir:984:8, Cat.scala:30:58, FPU.scala:319:20, :330:21, :336:24, :342:{25,57,64,106}
assign _io_out_output.valid = valid; // ../perf/regress/FPU.fir:984:8, FPU.scala:347:16
assign _T_1.lt = dcmp_io_lt; // ../perf/regress/FPU.fir:984:8, FPU.scala:319:20, :348:18
assign _io_as_double_output.cmd = _T_2; // FPU.scala:292:8, :349:16
assign _io_as_double_output.ldst = _T_3; // FPU.scala:292:8, :349:16
assign _io_as_double_output.wen = _T_4; // FPU.scala:292:8, :349:16
assign _io_as_double_output.ren1 = _T_5; // FPU.scala:292:8, :349:16
assign _io_as_double_output.ren2 = _T_6; // FPU.scala:292:8, :349:16
assign _io_as_double_output.ren3 = _T_7; // FPU.scala:292:8, :349:16
assign _io_as_double_output.swap12 = _T_8; // FPU.scala:292:8, :349:16
assign _io_as_double_output.swap23 = _T_9; // FPU.scala:292:8, :349:16
assign _io_as_double_output.single = _T_10; // FPU.scala:292:8, :349:16
assign _io_as_double_output.fromint = _T_11; // FPU.scala:292:8, :349:16
assign _io_as_double_output.toint = _T_12; // FPU.scala:292:8, :349:16
assign _io_as_double_output.fastpipe = _T_13; // FPU.scala:292:8, :349:16
assign _io_as_double_output.fma = _T_14; // FPU.scala:292:8, :349:16
assign _io_as_double_output.div = _T_15; // FPU.scala:292:8, :349:16
assign _io_as_double_output.sqrt = _T_16; // FPU.scala:292:8, :349:16
assign _io_as_double_output.wflags = _T_17; // FPU.scala:292:8, :349:16
assign _io_as_double_output.rm = _T_18; // FPU.scala:292:8, :349:16
assign _io_as_double_output.typ = _T_19; // FPU.scala:292:8, :349:16
assign _io_as_double_output.in1 = _T_20; // FPU.scala:294:14, :349:16
assign _io_as_double_output.in2 = _T_21; // FPU.scala:295:14, :349:16
assign _io_as_double_output.in3 = _T_22; // FPU.scala:292:8, :349:16
CompareRecFN dcmp ( // FPU.scala:319:20
.clock (clock),
.reset (reset),
.io_a (_T_20), // FPU.scala:294:14
.io_b (_T_21), // FPU.scala:295:14
.io_signaling (~(_T_79[1])), // FPU.scala:322:{24,30}
.io_lt (dcmp_io_lt),
.io_eq (dcmp_io_eq),
.io_gt (dcmp_io_gt),
.io_exceptionFlags (dcmp_io_exceptionFlags)
);
RecFNToIN RecFNToIN ( // FPU.scala:336:24
.clock (clock),
.reset (reset),
.io_in (_T_20), // FPU.scala:294:14
.io_roundingMode (_T_87),
.io_signedOut (~_T), // FPU.scala:339:{28,35}
.io_out (RecFNToIN_io_out),
.io_intExceptionFlags (RecFNToIN_io_intExceptionFlags)
);
RecFNToIN_1 RecFNToIN_1 ( // FPU.scala:336:24
.clock (clock),
.reset (reset),
.io_in (_T_20), // FPU.scala:294:14
.io_roundingMode (_T_87),
.io_signedOut (~_T), // FPU.scala:339:{28,35}
.io_out (RecFNToIN_1_io_out),
.io_intExceptionFlags (RecFNToIN_1_io_intExceptionFlags)
);
assign io_as_double = _io_as_double_output; // ../perf/regress/FPU.fir:979:10
assign io_out = _io_out_output; // ../perf/regress/FPU.fir:979:10
endmodule
module IntToFP( // ../perf/regress/FPU.fir:1304:10
input clock,
input reset,
input struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } io_in,
output struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } io_out);
wire [64:0] INToRecFN_1_io_out; // FPU.scala:391:25
wire [4:0] INToRecFN_1_io_exceptionFlags; // FPU.scala:391:25
wire [32:0] INToRecFN_io_out; // FPU.scala:381:21
wire [4:0] INToRecFN_io_exceptionFlags; // FPU.scala:381:21
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } _io_out_output; // ../perf/regress/FPU.fir:1304:10
reg _T_0; // Valid.scala:47:18
struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T_0_2; // Reg.scala:34:16
wire struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } in; // Valid.scala:42:21
wire struct packed {logic [64:0] data; logic [4:0] exc; } mux; // FPU.scala:360:17
reg _T_1_159; // Valid.scala:47:18
struct packed {logic [64:0] data; logic [4:0] exc; } _T_2; // Reg.scala:34:16
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } _T_3_162; // Valid.scala:42:21
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T = io_in.bits; // ../perf/regress/FPU.fir:1309:8
wire _T_1 = io_in.valid; // Valid.scala:47:18
wire [4:0] _T_3 = _T_0_2.cmd; // Reg.scala:34:16
wire _T_4 = _T_0_2.ldst; // Reg.scala:34:16
wire _T_5 = _T_0_2.wen; // Reg.scala:34:16
wire _T_6 = _T_0_2.ren1; // Reg.scala:34:16
wire _T_7 = _T_0_2.ren2; // Reg.scala:34:16
wire _T_8 = _T_0_2.ren3; // Reg.scala:34:16
wire _T_9 = _T_0_2.swap12; // Reg.scala:34:16
wire _T_10 = _T_0_2.swap23; // Reg.scala:34:16
wire _T_11 = _T_0_2.single; // Reg.scala:34:16
wire _T_12 = _T_0_2.fromint; // Reg.scala:34:16
wire _T_13 = _T_0_2.toint; // Reg.scala:34:16
wire _T_14 = _T_0_2.fastpipe; // Reg.scala:34:16
wire _T_15 = _T_0_2.fma; // Reg.scala:34:16
wire _T_16 = _T_0_2.div; // Reg.scala:34:16
wire _T_17 = _T_0_2.sqrt; // Reg.scala:34:16
wire _T_18 = _T_0_2.wflags; // Reg.scala:34:16
wire [2:0] _T_19 = _T_0_2.rm; // Reg.scala:34:16
wire [1:0] _T_20 = _T_0_2.typ; // Reg.scala:34:16
wire [64:0] _T_21 = _T_0_2.in1; // Reg.scala:34:16
wire [64:0] _T_22 = _T_0_2.in2; // Reg.scala:34:16
wire [64:0] _T_23 = _T_0_2.in3; // Reg.scala:34:16
assign _T_3 = _T_1 ? _T.cmd : _T_3; // Reg.scala:35:23
assign _T_4 = _T_1 ? _T.ldst : _T_4; // Reg.scala:35:23
assign _T_5 = _T_1 ? _T.wen : _T_5; // Reg.scala:35:23
assign _T_6 = _T_1 ? _T.ren1 : _T_6; // Reg.scala:35:23
assign _T_7 = _T_1 ? _T.ren2 : _T_7; // Reg.scala:35:23
assign _T_8 = _T_1 ? _T.ren3 : _T_8; // Reg.scala:35:23
assign _T_9 = _T_1 ? _T.swap12 : _T_9; // Reg.scala:35:23
assign _T_10 = _T_1 ? _T.swap23 : _T_10; // Reg.scala:35:23
assign _T_11 = _T_1 ? _T.single : _T_11; // Reg.scala:35:23
assign _T_12 = _T_1 ? _T.fromint : _T_12; // Reg.scala:35:23
assign _T_13 = _T_1 ? _T.toint : _T_13; // Reg.scala:35:23
assign _T_14 = _T_1 ? _T.fastpipe : _T_14; // Reg.scala:35:23
assign _T_15 = _T_1 ? _T.fma : _T_15; // Reg.scala:35:23
assign _T_16 = _T_1 ? _T.div : _T_16; // Reg.scala:35:23
assign _T_17 = _T_1 ? _T.sqrt : _T_17; // Reg.scala:35:23
assign _T_18 = _T_1 ? _T.wflags : _T_18; // Reg.scala:35:23
assign _T_19 = _T_1 ? _T.rm : _T_19; // Reg.scala:35:23
assign _T_20 = _T_1 ? _T.typ : _T_20; // Reg.scala:35:23
assign _T_21 = _T_1 ? _T.in1 : _T_21; // Reg.scala:35:23
assign _T_22 = _T_1 ? _T.in2 : _T_22; // Reg.scala:35:23
assign _T_23 = _T_1 ? _T.in3 : _T_23; // Reg.scala:35:23
wire _T_24 = in.valid; // Valid.scala:42:21
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T_25 = in.bits; // Valid.scala:42:21
wire [4:0] _T_26 = _T_25.cmd; // Valid.scala:42:21
wire [4:0] _T_27 = _T_26; // FPU.scala:380:21
wire _T_28 = _T_25.single; // Valid.scala:42:21
wire [2:0] _T_29 = _T_25.rm; // Valid.scala:42:21
wire [2:0] _T_30 = _T_29; // FPU.scala:384:25
wire [1:0] _T_31 = _T_25.typ; // Valid.scala:42:21
wire [1:0] _T_32 = _T_31; // Package.scala:44:13
wire [64:0] _T_33 = _T_25.in1; // Valid.scala:42:21
wire [64:0] _T_34 = _T_33; // recFNFromFN.scala:47:22
assign _T_24 = _T_0; // Valid.scala:43:17
assign _T_26 = _T_3; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.ldst = _T_4; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.wen = _T_5; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.ren1 = _T_6; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.ren2 = _T_7; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.ren3 = _T_8; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.swap12 = _T_9; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.swap23 = _T_10; // Reg.scala:35:23, Valid.scala:44:16
assign _T_28 = _T_11; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.fromint = _T_12; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.toint = _T_13; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.fastpipe = _T_14; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.fma = _T_15; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.div = _T_16; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.sqrt = _T_17; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.wflags = _T_18; // Reg.scala:35:23, Valid.scala:44:16
assign _T_29 = _T_19; // Reg.scala:35:23, Valid.scala:44:16
assign _T_31 = _T_20; // Reg.scala:35:23, Valid.scala:44:16
assign _T_33 = _T_21; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.in2 = _T_22; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.in3 = _T_23; // Reg.scala:35:23, Valid.scala:44:16
wire [64:0] _T_35 = mux.data; // FPU.scala:360:17
wire [4:0] _T_36 = mux.exc; // FPU.scala:360:17
wire [64:0] _T_37 = _T_33; // recFNFromFN.scala:47:22
wire [7:0] _T_38 = _T_37[30:23]; // recFNFromFN.scala:48:23
wire [64:0] _T_39 = _T_33; // recFNFromFN.scala:47:22
wire [22:0] _T_40 = _T_39[22:0]; // recFNFromFN.scala:49:25
wire _T_41 = _T_38 == 8'h0; // recFNFromFN.scala:51:34
wire [64:0] _T_42 = _T_33; // recFNFromFN.scala:47:22
wire [15:0] _T_43 = _T_42[22:7]; // CircuitMath.scala:35:17
wire [64:0] _T_44 = _T_33; // recFNFromFN.scala:47:22
wire [7:0] _T_45 = _T_44[22:15]; // CircuitMath.scala:35:17
wire [64:0] _T_46 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_47 = _T_46[22:19]; // CircuitMath.scala:35:17
wire [64:0] _T_48 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_49 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_50 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_51 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_52 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_53 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_54 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_55 = _T_54[14:11]; // CircuitMath.scala:35:17
wire [64:0] _T_56 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_57 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_58 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_59 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_60 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_61 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_62 = _T_33; // recFNFromFN.scala:47:22
wire [6:0] _T_63 = _T_62[6:0]; // CircuitMath.scala:35:17
wire [64:0] _T_64 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_65 = _T_64[6:3]; // CircuitMath.scala:35:17
wire [64:0] _T_66 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_67 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_68 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_69 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_70 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_71 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_72 = |_T_43 ? {|_T_45, |_T_45 ? {|_T_47, |_T_47 ? (_T_48[22] ? 2'h3 : _T_49[21] ? 2'h2 : {1'h0,
_T_50[20]}) : _T_51[18] ? 2'h3 : _T_52[17] ? 2'h2 : {1'h0, _T_53[16]}} : {|_T_55, |_T_55 ?
(_T_56[14] ? 2'h3 : _T_57[13] ? 2'h2 : {1'h0, _T_58[12]}) : _T_59[10] ? 2'h3 : _T_60[9] ?
2'h2 : {1'h0, _T_61[8]}}} : {|_T_63, |_T_63 ? {|_T_65, |_T_65 ? (_T_66[6] ? 2'h3 : _T_67[5]
? 2'h2 : {1'h0, _T_68[4]}) : _T_69[2] ? 2'h3 : _T_70[1] ? 2'h2 : {1'h0, _T_71[0]}} : 3'h0}; // Bitwise.scala:71:12, Cat.scala:30:58, CircuitMath.scala:30:8, :32:{10,12}, :37:22, :38:21, Valid.scala:47:18
wire [53:0] _T_73 = {31'h0, _T_40} << ~{|_T_43, _T_72}; // Cat.scala:30:58, CircuitMath.scala:37:22, recFNFromFN.scala:56:13, :58:25
wire [8:0] _T_74 = (_T_41 ? {4'hF, |_T_43, _T_72} : {1'h0, _T_38}) + {7'h20, _T_41 ? 2'h2 : 2'h1}; // CircuitMath.scala:32:10, :37:22, Valid.scala:47:18, recFNFromFN.scala:61:16, :62:27, :64:{15,47}
wire [64:0] _T_75 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_76 = _T_33; // recFNFromFN.scala:47:22
wire [10:0] _T_77 = _T_76[62:52]; // recFNFromFN.scala:48:23
wire [64:0] _T_78 = _T_33; // recFNFromFN.scala:47:22
wire [51:0] _T_79 = _T_78[51:0]; // recFNFromFN.scala:49:25
wire _T_80 = _T_77 == 11'h0; // recFNFromFN.scala:51:34
wire [64:0] _T_81 = _T_33; // recFNFromFN.scala:47:22
wire [31:0] _T_82 = _T_81[51:20]; // CircuitMath.scala:35:17
wire [64:0] _T_83 = _T_33; // recFNFromFN.scala:47:22
wire [15:0] _T_84 = _T_83[51:36]; // CircuitMath.scala:35:17
wire [64:0] _T_85 = _T_33; // recFNFromFN.scala:47:22
wire [7:0] _T_86 = _T_85[51:44]; // CircuitMath.scala:35:17
wire [64:0] _T_87 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_88 = _T_87[51:48]; // CircuitMath.scala:35:17
wire [64:0] _T_89 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_90 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_91 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_92 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_93 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_94 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_95 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_96 = _T_95[43:40]; // CircuitMath.scala:35:17
wire [64:0] _T_97 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_98 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_99 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_100 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_101 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_102 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_103 = _T_33; // recFNFromFN.scala:47:22
wire [7:0] _T_104 = _T_103[35:28]; // CircuitMath.scala:35:17
wire [64:0] _T_105 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_106 = _T_105[35:32]; // CircuitMath.scala:35:17
wire [64:0] _T_107 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_108 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_109 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_110 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_111 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_112 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_113 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_114 = _T_113[27:24]; // CircuitMath.scala:35:17
wire [64:0] _T_115 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_116 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_117 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_118 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_119 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_120 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_121 = _T_33; // recFNFromFN.scala:47:22
wire [15:0] _T_122 = _T_121[19:4]; // CircuitMath.scala:35:17
wire [64:0] _T_123 = _T_33; // recFNFromFN.scala:47:22
wire [7:0] _T_124 = _T_123[19:12]; // CircuitMath.scala:35:17
wire [64:0] _T_125 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_126 = _T_125[19:16]; // CircuitMath.scala:35:17
wire [64:0] _T_127 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_128 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_129 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_130 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_131 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_132 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_133 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_134 = _T_133[11:8]; // CircuitMath.scala:35:17
wire [64:0] _T_135 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_136 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_137 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_138 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_139 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_140 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_141 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_142 = _T_141[3:0]; // CircuitMath.scala:35:17
wire [64:0] _T_143 = _T_33; // recFNFromFN.scala:47:22
wire [3:0] _T_144 = _T_143[3:0]; // CircuitMath.scala:35:17
wire [64:0] _T_145 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_146 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_147 = _T_33; // recFNFromFN.scala:47:22
wire [4:0] _T_148 = |_T_82 ? {|_T_84, |_T_84 ? {|_T_86, |_T_86 ? {|_T_88, |_T_88 ? (_T_89[51] ? 2'h3 :
_T_90[50] ? 2'h2 : {1'h0, _T_91[49]}) : _T_92[47] ? 2'h3 : _T_93[46] ? 2'h2 : {1'h0,
_T_94[45]}} : {|_T_96, |_T_96 ? (_T_97[43] ? 2'h3 : _T_98[42] ? 2'h2 : {1'h0, _T_99[41]}) :
_T_100[39] ? 2'h3 : _T_101[38] ? 2'h2 : {1'h0, _T_102[37]}}} : {|_T_104, |_T_104 ?
{|_T_106, |_T_106 ? (_T_107[35] ? 2'h3 : _T_108[34] ? 2'h2 : {1'h0, _T_109[33]}) :
_T_110[31] ? 2'h3 : _T_111[30] ? 2'h2 : {1'h0, _T_112[29]}} : {|_T_114, |_T_114 ?
(_T_115[27] ? 2'h3 : _T_116[26] ? 2'h2 : {1'h0, _T_117[25]}) : _T_118[23] ? 2'h3 :
_T_119[22] ? 2'h2 : {1'h0, _T_120[21]}}}} : {|_T_122, |_T_122 ? {|_T_124, |_T_124 ?
{|_T_126, |_T_126 ? (_T_127[19] ? 2'h3 : _T_128[18] ? 2'h2 : {1'h0, _T_129[17]}) :
_T_130[15] ? 2'h3 : _T_131[14] ? 2'h2 : {1'h0, _T_132[13]}} : {|_T_134, |_T_134 ?
(_T_135[11] ? 2'h3 : _T_136[10] ? 2'h2 : {1'h0, _T_137[9]}) : _T_138[7] ? 2'h3 : _T_139[6]
? 2'h2 : {1'h0, _T_140[5]}}} : {|_T_142, |_T_142 ? {|_T_144, |_T_144 ? (_T_145[3] ? 2'h3 :
_T_146[2] ? 2'h2 : {1'h0, _T_147[1]}) : 2'h0} : 3'h0}}; // Bitwise.scala:71:12, Cat.scala:30:58, CircuitMath.scala:30:8, :32:{10,12}, :37:22, :38:21, Valid.scala:47:18, recFNFromFN.scala:64:15
wire [114:0] _T_149 = {63'h0, _T_79} << ~{|_T_82, _T_148}; // Cat.scala:30:58, CircuitMath.scala:37:22, recFNFromFN.scala:56:13, :58:25
wire [11:0] _T_150 = (_T_80 ? {6'h3F, |_T_82, _T_148} : {1'h0, _T_77}) + {10'h100, _T_80 ? 2'h2 : 2'h1}; // CircuitMath.scala:32:10, :37:22, Valid.scala:47:18, recFNFromFN.scala:56:13, :61:16, :62:27, :64:{15,47}
wire [64:0] _T_151 = _T_33; // recFNFromFN.scala:47:22
wire [1:0] _T_152 = _T_31; // Package.scala:44:13
wire _T_153 = _T_152[0]; // FPU.scala:374:31
wire [64:0] _T_154 = _T_33; // recFNFromFN.scala:47:22
wire [64:0] _T_155 = _T_33; // recFNFromFN.scala:47:22
wire [63:0] _T_156 = _T_32[1] ? _T_155[63:0] : {{32{~_T_153 & _T_154[31]}}, _T_151[31:0]}; // FPU.scala:372:33, :374:{13,19}, Package.scala:44:13
wire _T_157 = _T_27[2]; // FPU.scala:380:21
wire [1:0] _T_158 = _T_30[1:0]; // FPU.scala:384:25
assign _T_35 = _T_157 ? (_T_28 ? {32'h0, _T_34[31], _T_74 & {~{3{_T_41 & ~(|_T_40)}}, 6'h3F} | {2'h0,
&(_T_74[8:7]) & |_T_40, 6'h0}, _T_41 ? {_T_73[21:0], 1'h0} : _T_40} : {_T_75[63], _T_150 &
{~{3{_T_80 & ~(|_T_79)}}, 9'h1FF} | {2'h0, &(_T_150[11:10]) & |_T_79, 9'h0}, _T_80 ?
{_T_149[50:0], 1'h0} : _T_79}) : _T_28 ? {INToRecFN_1_io_out[64:33], INToRecFN_io_out} :
INToRecFN_1_io_out; // Bitwise.scala:71:12, Cat.scala:30:58, CircuitMath.scala:37:22, FPU.scala:363:24, :364:14, :381:21, :391:25, :396:36, :399:20, Valid.scala:47:18, recFNFromFN.scala:47:22, :52:38, :53:34, :56:{13,26}, :58:37, :64:{15,42}, :67:{25,50,63}, :71:{26,28,45,64}, :73:27
assign _T_36 = _T_157 ? 5'h0 : _T_28 ? INToRecFN_io_exceptionFlags : INToRecFN_1_io_exceptionFlags; // FPU.scala:363:24, :381:21, :391:25, :400:19
always @(posedge clock) begin // Valid.scala:47:18
if (reset) begin // Valid.scala:47:18
_T_0 <= 1'h0; // Valid.scala:47:18
_T_1_159 <= 1'h0; // Valid.scala:47:18
end
else begin // Valid.scala:47:18
_T_0 <= _T_1; // Valid.scala:47:18
_T_1_159 <= _T_24; // Valid.scala:47:18
end
end // always @(posedge)
`ifndef SYNTHESIS // Valid.scala:47:18
initial begin // Valid.scala:47:18
automatic logic [31:0] _RANDOM; // Valid.scala:47:18
automatic logic [31:0] _RANDOM_168; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_169; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_170; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_171; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_172; // Reg.scala:34:16
`INIT_RANDOM_PROLOG_ // Valid.scala:47:18
`ifdef RANDOMIZE_REG_INIT // Valid.scala:47:18
_RANDOM = `RANDOM; // Valid.scala:47:18
_T_0 = _RANDOM[0]; // Valid.scala:47:18
_T_3 = _RANDOM[5:1]; // Reg.scala:34:16
_T_4 = _RANDOM[6]; // Reg.scala:34:16
_T_5 = _RANDOM[7]; // Reg.scala:34:16
_T_6 = _RANDOM[8]; // Reg.scala:34:16
_T_7 = _RANDOM[9]; // Reg.scala:34:16
_T_8 = _RANDOM[10]; // Reg.scala:34:16
_T_9 = _RANDOM[11]; // Reg.scala:34:16
_T_10 = _RANDOM[12]; // Reg.scala:34:16
_T_11 = _RANDOM[13]; // Reg.scala:34:16
_T_12 = _RANDOM[14]; // Reg.scala:34:16
_T_13 = _RANDOM[15]; // Reg.scala:34:16
_T_14 = _RANDOM[16]; // Reg.scala:34:16
_T_15 = _RANDOM[17]; // Reg.scala:34:16
_T_16 = _RANDOM[18]; // Reg.scala:34:16
_T_17 = _RANDOM[19]; // Reg.scala:34:16
_T_18 = _RANDOM[20]; // Reg.scala:34:16
_T_19 = _RANDOM[23:21]; // Reg.scala:34:16
_T_20 = _RANDOM[25:24]; // Reg.scala:34:16
_RANDOM_168 = `RANDOM; // Reg.scala:34:16
_T_21 = {_RANDOM[31:26], `RANDOM, _RANDOM_168[26:0]}; // Reg.scala:34:16
_RANDOM_169 = `RANDOM; // Reg.scala:34:16
_T_22 = {_RANDOM_168[31:27], `RANDOM, _RANDOM_169[27:0]}; // Reg.scala:34:16
_RANDOM_170 = `RANDOM; // Reg.scala:34:16
_T_23 = {_RANDOM_169[31:28], `RANDOM, _RANDOM_170[28:0]}; // Reg.scala:34:16
_T_1_159 = _RANDOM_170[29]; // Valid.scala:47:18
_RANDOM_171 = `RANDOM; // Reg.scala:34:16
_T_2.data = {_RANDOM_170[31:30], `RANDOM, _RANDOM_171[30:0]}; // Reg.scala:34:16
_RANDOM_172 = `RANDOM; // Reg.scala:34:16
_T_2.exc = {_RANDOM_171[31], _RANDOM_172[3:0]}; // Reg.scala:34:16
`endif
end // initial
`endif
wire [64:0] _T_160 = _T_2.data; // Reg.scala:34:16
wire [4:0] _T_161 = _T_2.exc; // Reg.scala:34:16
assign _T_160 = _T_24 ? _T_35 : _T_160; // Reg.scala:35:23, Valid.scala:47:18
assign _T_161 = _T_24 ? _T_36 : _T_161; // Reg.scala:35:23, Valid.scala:47:18
wire _T_163 = _T_3_162.valid; // Valid.scala:42:21
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_164 = _T_3_162.bits; // Valid.scala:42:21
assign _T_163 = _T_1_159; // Valid.scala:43:17
wire [64:0] _T_165 = _T_164.data; // Valid.scala:44:16
assign _T_165 = _T_160; // Reg.scala:35:23, Valid.scala:44:16
wire [4:0] _T_166 = _T_164.exc; // Valid.scala:44:16
assign _T_166 = _T_161; // Reg.scala:35:23, Valid.scala:44:16
assign _io_out_output.valid = _T_163; // FPU.scala:405:12
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_167 = _io_out_output.bits; // FPU.scala:405:12
assign _T_167.data = _T_165; // FPU.scala:405:12
assign _T_167.exc = _T_166; // FPU.scala:405:12
INToRecFN INToRecFN ( // FPU.scala:381:21
.clock (clock),
.reset (reset),
.io_signedIn (~_T_153), // FPU.scala:382:24
.io_in (_T_156),
.io_roundingMode (_T_158),
.io_out (INToRecFN_io_out),
.io_exceptionFlags (INToRecFN_io_exceptionFlags)
);
INToRecFN_1 INToRecFN_1 ( // FPU.scala:391:25
.clock (clock),
.reset (reset),
.io_signedIn (~_T_153), // FPU.scala:382:24
.io_in (_T_156),
.io_roundingMode (_T_158),
.io_out (INToRecFN_1_io_out),
.io_exceptionFlags (INToRecFN_1_io_exceptionFlags)
);
assign io_out = _io_out_output; // ../perf/regress/FPU.fir:1304:10
endmodule
module FPToFP( // ../perf/regress/FPU.fir:1681:10
input clock,
input reset,
input struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } io_in,
input io_lt,
output struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } io_out);
wire [64:0] RecFNToRecFN_1_io_out; // FPU.scala:455:25
wire [4:0] RecFNToRecFN_1_io_exceptionFlags; // FPU.scala:455:25
wire [32:0] RecFNToRecFN_io_out; // FPU.scala:451:25
wire [4:0] RecFNToRecFN_io_exceptionFlags; // FPU.scala:451:25
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } _io_out_output; // ../perf/regress/FPU.fir:1681:10
reg _T_0; // Valid.scala:47:18
struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T_0_2; // Reg.scala:34:16
wire struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } in; // Valid.scala:42:21
wire struct packed {logic [64:0] data; logic [4:0] exc; } mux; // FPU.scala:424:19
reg _T_1_66; // Valid.scala:47:18
struct packed {logic [64:0] data; logic [4:0] exc; } _T_2; // Reg.scala:34:16
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } _T_3_69; // Valid.scala:42:21
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T = io_in.bits; // ../perf/regress/FPU.fir:1686:8
wire _T_1 = io_in.valid; // Valid.scala:47:18
wire [4:0] _T_3 = _T_0_2.cmd; // Reg.scala:34:16
wire _T_4 = _T_0_2.ldst; // Reg.scala:34:16
wire _T_5 = _T_0_2.wen; // Reg.scala:34:16
wire _T_6 = _T_0_2.ren1; // Reg.scala:34:16
wire _T_7 = _T_0_2.ren2; // Reg.scala:34:16
wire _T_8 = _T_0_2.ren3; // Reg.scala:34:16
wire _T_9 = _T_0_2.swap12; // Reg.scala:34:16
wire _T_10 = _T_0_2.swap23; // Reg.scala:34:16
wire _T_11 = _T_0_2.single; // Reg.scala:34:16
wire _T_12 = _T_0_2.fromint; // Reg.scala:34:16
wire _T_13 = _T_0_2.toint; // Reg.scala:34:16
wire _T_14 = _T_0_2.fastpipe; // Reg.scala:34:16
wire _T_15 = _T_0_2.fma; // Reg.scala:34:16
wire _T_16 = _T_0_2.div; // Reg.scala:34:16
wire _T_17 = _T_0_2.sqrt; // Reg.scala:34:16
wire _T_18 = _T_0_2.wflags; // Reg.scala:34:16
wire [2:0] _T_19 = _T_0_2.rm; // Reg.scala:34:16
wire [1:0] _T_20 = _T_0_2.typ; // Reg.scala:34:16
wire [64:0] _T_21 = _T_0_2.in1; // Reg.scala:34:16
wire [64:0] _T_22 = _T_0_2.in2; // Reg.scala:34:16
wire [64:0] _T_23 = _T_0_2.in3; // Reg.scala:34:16
assign _T_3 = _T_1 ? _T.cmd : _T_3; // Reg.scala:35:23
assign _T_4 = _T_1 ? _T.ldst : _T_4; // Reg.scala:35:23
assign _T_5 = _T_1 ? _T.wen : _T_5; // Reg.scala:35:23
assign _T_6 = _T_1 ? _T.ren1 : _T_6; // Reg.scala:35:23
assign _T_7 = _T_1 ? _T.ren2 : _T_7; // Reg.scala:35:23
assign _T_8 = _T_1 ? _T.ren3 : _T_8; // Reg.scala:35:23
assign _T_9 = _T_1 ? _T.swap12 : _T_9; // Reg.scala:35:23
assign _T_10 = _T_1 ? _T.swap23 : _T_10; // Reg.scala:35:23
assign _T_11 = _T_1 ? _T.single : _T_11; // Reg.scala:35:23
assign _T_12 = _T_1 ? _T.fromint : _T_12; // Reg.scala:35:23
assign _T_13 = _T_1 ? _T.toint : _T_13; // Reg.scala:35:23
assign _T_14 = _T_1 ? _T.fastpipe : _T_14; // Reg.scala:35:23
assign _T_15 = _T_1 ? _T.fma : _T_15; // Reg.scala:35:23
assign _T_16 = _T_1 ? _T.div : _T_16; // Reg.scala:35:23
assign _T_17 = _T_1 ? _T.sqrt : _T_17; // Reg.scala:35:23
assign _T_18 = _T_1 ? _T.wflags : _T_18; // Reg.scala:35:23
assign _T_19 = _T_1 ? _T.rm : _T_19; // Reg.scala:35:23
assign _T_20 = _T_1 ? _T.typ : _T_20; // Reg.scala:35:23
assign _T_21 = _T_1 ? _T.in1 : _T_21; // Reg.scala:35:23
assign _T_22 = _T_1 ? _T.in2 : _T_22; // Reg.scala:35:23
assign _T_23 = _T_1 ? _T.in3 : _T_23; // Reg.scala:35:23
wire _T_24 = in.valid; // Valid.scala:42:21
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T_25 = in.bits; // Valid.scala:42:21
wire [4:0] _T_26 = _T_25.cmd; // Valid.scala:42:21
wire [4:0] _T_27 = _T_26; // FPU.scala:428:23
wire _T_28 = _T_25.single; // Valid.scala:42:21
wire [2:0] _T_29 = _T_25.rm; // Valid.scala:42:21
wire [2:0] _T_30 = _T_29; // FPU.scala:417:33
wire [64:0] _T_31 = _T_25.in1; // Valid.scala:42:21
wire [64:0] _T_32 = _T_31; // FPU.scala:417:50
wire [64:0] _T_33 = _T_25.in2; // Valid.scala:42:21
wire [64:0] _T_34 = _T_33; // FPU.scala:417:50
assign _T_24 = _T_0; // Valid.scala:43:17
assign _T_26 = _T_3; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.ldst = _T_4; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.wen = _T_5; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.ren1 = _T_6; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.ren2 = _T_7; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.ren3 = _T_8; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.swap12 = _T_9; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.swap23 = _T_10; // Reg.scala:35:23, Valid.scala:44:16
assign _T_28 = _T_11; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.fromint = _T_12; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.toint = _T_13; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.fastpipe = _T_14; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.fma = _T_15; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.div = _T_16; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.sqrt = _T_17; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.wflags = _T_18; // Reg.scala:35:23, Valid.scala:44:16
assign _T_29 = _T_19; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.typ = _T_20; // Reg.scala:35:23, Valid.scala:44:16
assign _T_31 = _T_21; // Reg.scala:35:23, Valid.scala:44:16
assign _T_33 = _T_22; // Reg.scala:35:23, Valid.scala:44:16
assign _T_25.in3 = _T_23; // Reg.scala:35:23, Valid.scala:44:16
wire [64:0] _T_35 = _T_31; // FPU.scala:417:50
wire [64:0] _T_36 = _T_33; // FPU.scala:417:50
wire [2:0] _T_37 = _T_29; // FPU.scala:417:33
wire _T_38 = _T_37[0]; // FPU.scala:417:79
wire [64:0] _T_39 = _T_33; // FPU.scala:417:50
wire [32:0] _T_40 = _T_30[1] ? _T_35[64:32] ^ _T_36[64:32] : {33{_T_38}} ^ _T_39[64:32]; // FPU.scala:417:{22,33,50,68}
wire [64:0] _T_41 = _T_31; // FPU.scala:417:50
wire [64:0] _T_42 = _T_31; // FPU.scala:417:50
wire [64:0] _T_43 = mux.data; // FPU.scala:424:19
wire [4:0] _T_44 = mux.exc; // FPU.scala:424:19
wire [4:0] _T_45 = _T_26; // FPU.scala:428:23
wire [4:0] _T_46 = _T_26; // FPU.scala:428:23
wire _T_47 = {_T_46[3:2], _T_45[0]} == 3'h3; // FPU.scala:428:23
wire [64:0] _T_48 = _T_31; // FPU.scala:417:50
wire _T_49 = _T_48[31:29] != 3'h7; // FPU.scala:226:{7,58}
wire [2:0] _T_50 = _T_34[31:29]; // FPU.scala:226:7
wire [64:0] _T_51 = _T_31; // FPU.scala:417:50
wire [64:0] _T_52 = _T_33; // FPU.scala:417:50
wire _T_53 = ~_T_49 & ~(_T_51[22]) | &_T_50 & ~(_T_52[22]); // FPU.scala:226:58, :231:{40,43,46}, :434:31
wire _T_54 = _T_38 != io_lt; // FPU.scala:437:34
wire [64:0] _T_55 = _T_31; // FPU.scala:417:50
wire _T_56 = _T_55[63:61] != 3'h7; // FPU.scala:226:{7,58}
wire [64:0] _T_57 = _T_33; // FPU.scala:417:50
wire [2:0] _T_58 = _T_57[63:61]; // FPU.scala:226:7
wire [64:0] _T_59 = _T_31; // FPU.scala:417:50
wire [64:0] _T_60 = _T_33; // FPU.scala:417:50
wire _T_61 = ~_T_56 & ~(_T_59[51]) | &_T_58 & ~(_T_60[51]); // FPU.scala:226:58, :231:{40,43,46}, :434:31
wire _T_62 = _T_27[2]; // FPU.scala:450:25
wire [2:0] _T_63 = _T_29; // FPU.scala:417:33
wire [1:0] _T_64 = _T_63[1:0]; // FPU.scala:453:29
wire [64:0] _T_65 = _T_31; // FPU.scala:417:50
assign _T_43 = _T_62 ? (_T_47 ? ((_T_28 ? _T_53 | ~_T_49 & &_T_50 : _T_61 | ~_T_56 & &_T_58) ? (_T_28 ?
65'hE0080000E0400000 : 65'hE008000000000000) : (_T_28 ? &_T_50 | _T_54 & _T_49 : &_T_58 |
_T_54 & _T_56) ? _T_31 : _T_33) : _T_28 ? {_T_41[64:33], _T_40[0], _T_32[31:0]} :
{_T_40[32], _T_42[63:0]}) : _T_28 ? {RecFNToRecFN_1_io_out[64:33], RecFNToRecFN_io_out} :
RecFNToRecFN_1_io_out; // Cat.scala:30:58, FPU.scala:226:58, :417:50, :418:{30,47}, :421:{21,54}, :422:{49,66}, :435:{32,43}, :436:100, :437:{17,44}, :444:{16,22,42}, :451:25, :455:25, :460:38, :463:20, Misc.scala:42:{9,63,90}
assign _T_44 = _T_62 ? (_T_47 ? {_T_28 ? _T_53 : _T_61, 4'h0} : 5'h0) : _T_28 ?
RecFNToRecFN_io_exceptionFlags : RecFNToRecFN_1_io_exceptionFlags; // FPU.scala:421:21, :443:{15,28}, :451:25, :455:25, :464:19, Misc.scala:42:36
always @(posedge clock) begin // Valid.scala:47:18
if (reset) begin // Valid.scala:47:18
_T_0 <= 1'h0; // Valid.scala:47:18
_T_1_66 <= 1'h0; // Valid.scala:47:18
end
else begin // Valid.scala:47:18
_T_0 <= _T_1; // Valid.scala:47:18
_T_1_66 <= _T_24; // Valid.scala:47:18
end
end // always @(posedge)
`ifndef SYNTHESIS // Valid.scala:47:18
initial begin // Valid.scala:47:18
automatic logic [31:0] _RANDOM; // Valid.scala:47:18
automatic logic [31:0] _RANDOM_75; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_76; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_77; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_78; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_79; // Reg.scala:34:16
`INIT_RANDOM_PROLOG_ // Valid.scala:47:18
`ifdef RANDOMIZE_REG_INIT // Valid.scala:47:18
_RANDOM = `RANDOM; // Valid.scala:47:18
_T_0 = _RANDOM[0]; // Valid.scala:47:18
_T_3 = _RANDOM[5:1]; // Reg.scala:34:16
_T_4 = _RANDOM[6]; // Reg.scala:34:16
_T_5 = _RANDOM[7]; // Reg.scala:34:16
_T_6 = _RANDOM[8]; // Reg.scala:34:16
_T_7 = _RANDOM[9]; // Reg.scala:34:16
_T_8 = _RANDOM[10]; // Reg.scala:34:16
_T_9 = _RANDOM[11]; // Reg.scala:34:16
_T_10 = _RANDOM[12]; // Reg.scala:34:16
_T_11 = _RANDOM[13]; // Reg.scala:34:16
_T_12 = _RANDOM[14]; // Reg.scala:34:16
_T_13 = _RANDOM[15]; // Reg.scala:34:16
_T_14 = _RANDOM[16]; // Reg.scala:34:16
_T_15 = _RANDOM[17]; // Reg.scala:34:16
_T_16 = _RANDOM[18]; // Reg.scala:34:16
_T_17 = _RANDOM[19]; // Reg.scala:34:16
_T_18 = _RANDOM[20]; // Reg.scala:34:16
_T_19 = _RANDOM[23:21]; // Reg.scala:34:16
_T_20 = _RANDOM[25:24]; // Reg.scala:34:16
_RANDOM_75 = `RANDOM; // Reg.scala:34:16
_T_21 = {_RANDOM[31:26], `RANDOM, _RANDOM_75[26:0]}; // Reg.scala:34:16
_RANDOM_76 = `RANDOM; // Reg.scala:34:16
_T_22 = {_RANDOM_75[31:27], `RANDOM, _RANDOM_76[27:0]}; // Reg.scala:34:16
_RANDOM_77 = `RANDOM; // Reg.scala:34:16
_T_23 = {_RANDOM_76[31:28], `RANDOM, _RANDOM_77[28:0]}; // Reg.scala:34:16
_T_1_66 = _RANDOM_77[29]; // Valid.scala:47:18
_RANDOM_78 = `RANDOM; // Reg.scala:34:16
_T_2.data = {_RANDOM_77[31:30], `RANDOM, _RANDOM_78[30:0]}; // Reg.scala:34:16
_RANDOM_79 = `RANDOM; // Reg.scala:34:16
_T_2.exc = {_RANDOM_78[31], _RANDOM_79[3:0]}; // Reg.scala:34:16
`endif
end // initial
`endif
wire [64:0] _T_67 = _T_2.data; // Reg.scala:34:16
wire [4:0] _T_68 = _T_2.exc; // Reg.scala:34:16
assign _T_67 = _T_24 ? _T_43 : _T_67; // Reg.scala:35:23, Valid.scala:47:18
assign _T_68 = _T_24 ? _T_44 : _T_68; // Reg.scala:35:23, Valid.scala:47:18
wire _T_70 = _T_3_69.valid; // Valid.scala:42:21
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_71 = _T_3_69.bits; // Valid.scala:42:21
assign _T_70 = _T_1_66; // Valid.scala:43:17
wire [64:0] _T_72 = _T_71.data; // Valid.scala:44:16
assign _T_72 = _T_67; // Reg.scala:35:23, Valid.scala:44:16
wire [4:0] _T_73 = _T_71.exc; // Valid.scala:44:16
assign _T_73 = _T_68; // Reg.scala:35:23, Valid.scala:44:16
assign _io_out_output.valid = _T_70; // FPU.scala:469:10
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_74 = _io_out_output.bits; // FPU.scala:469:10
assign _T_74.data = _T_72; // FPU.scala:469:10
assign _T_74.exc = _T_73; // FPU.scala:469:10
RecFNToRecFN RecFNToRecFN ( // FPU.scala:451:25
.clock (clock),
.reset (reset),
.io_in (_T_31), // FPU.scala:417:50
.io_roundingMode (_T_64),
.io_out (RecFNToRecFN_io_out),
.io_exceptionFlags (RecFNToRecFN_io_exceptionFlags)
);
RecFNToRecFN_1 RecFNToRecFN_1 ( // FPU.scala:455:25
.clock (clock),
.reset (reset),
.io_in (_T_65[32:0]), // FPU.scala:456:19
.io_roundingMode (_T_64),
.io_out (RecFNToRecFN_1_io_out),
.io_exceptionFlags (RecFNToRecFN_1_io_exceptionFlags)
);
assign io_out = _io_out_output; // ../perf/regress/FPU.fir:1681:10
endmodule
module FPUFMAPipe_1( // ../perf/regress/FPU.fir:1823:10
input clock,
input reset,
input struct packed {logic valid; struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } bits; } io_in,
output struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } io_out);
wire [64:0] fma_io_out; // FPU.scala:493:19
wire [4:0] fma_io_exceptionFlags; // FPU.scala:493:19
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } _io_out_output; // ../perf/regress/FPU.fir:1823:10
reg valid; // FPU.scala:482:18
struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } in; // FPU.scala:483:15
wire struct packed {logic [64:0] data; logic [4:0] exc; } res; // FPU.scala:500:17
reg _T_32; // Valid.scala:47:18
struct packed {logic [64:0] data; logic [4:0] exc; } _T_0_33; // Reg.scala:34:16
reg _T_1_36; // Valid.scala:47:18
struct packed {logic [64:0] data; logic [4:0] exc; } _T_2_37; // Reg.scala:34:16
reg _T_3_40; // Valid.scala:47:18
struct packed {logic [64:0] data; logic [4:0] exc; } _T_4_41; // Reg.scala:34:16
wire struct packed {logic valid; struct packed {logic [64:0] data; logic [4:0] exc; } bits; } _T_5_44; // Valid.scala:42:21
wire struct packed {logic [4:0] cmd; logic ldst; logic wen; logic ren1; logic ren2; logic ren3; logic swap12; logic swap23; logic single; logic fromint; logic toint; logic fastpipe; logic fma; logic div; logic sqrt; logic wflags; logic [2:0] rm; logic [1:0] typ; logic [64:0] in1; logic [64:0] in2; logic [64:0] in3; } _T = io_in.bits; // ../perf/regress/FPU.fir:1828:8
wire [64:0] _T_0 = _T.in1; // FPU.scala:480:29
wire [64:0] _T_1 = _T.in2; // FPU.scala:480:53
wire _T_2 = io_in.valid; // FPU.scala:482:18
wire [4:0] _T_3 = in.cmd; // FPU.scala:483:15
wire _T_4 = in.ldst; // FPU.scala:483:15
wire _T_5 = in.wen; // FPU.scala:483:15
wire _T_6 = in.ren1; // FPU.scala:483:15
wire _T_7 = in.ren2; // FPU.scala:483:15
wire _T_8 = in.ren3; // FPU.scala:483:15
wire _T_9 = in.swap12; // FPU.scala:483:15
wire _T_10 = in.swap23; // FPU.scala:483:15
wire _T_11 = in.single; // FPU.scala:483:15
wire _T_12 = in.fromint; // FPU.scala:483:15
wire _T_13 = in.toint; // FPU.scala:483:15
wire _T_14 = in.fastpipe; // FPU.scala:483:15
wire _T_15 = in.fma; // FPU.scala:483:15
wire _T_16 = in.div; // FPU.scala:483:15
wire _T_17 = in.sqrt; // FPU.scala:483:15
wire _T_18 = in.wflags; // FPU.scala:483:15
wire [2:0] _T_19 = in.rm; // FPU.scala:483:15
wire [1:0] _T_20 = in.typ; // FPU.scala:483:15
wire [64:0] _T_21 = in.in1; // FPU.scala:483:15
wire [64:0] _T_22 = in.in2; // FPU.scala:483:15
wire [64:0] _T_23 = in.in3; // FPU.scala:483:15
assign _T_4 = _T_2 ? _T.ldst : _T_4; // FPU.scala:485:8
assign _T_5 = _T_2 ? _T.wen : _T_5; // FPU.scala:485:8
assign _T_6 = _T_2 ? _T.ren1 : _T_6; // FPU.scala:485:8
assign _T_7 = _T_2 ? _T.ren2 : _T_7; // FPU.scala:485:8
wire _T_24 = _T.ren3; // FPU.scala:485:8
assign _T_8 = _T_2 ? _T_24 : _T_8; // FPU.scala:485:8
assign _T_9 = _T_2 ? _T.swap12 : _T_9; // FPU.scala:485:8
wire _T_25 = _T.swap23; // FPU.scala:485:8
assign _T_10 = _T_2 ? _T_25 : _T_10; // FPU.scala:485:8
assign _T_11 = _T_2 ? _T.single : _T_11; // FPU.scala:485:8
assign _T_12 = _T_2 ? _T.fromint : _T_12; // FPU.scala:485:8
assign _T_13 = _T_2 ? _T.toint : _T_13; // FPU.scala:485:8
assign _T_14 = _T_2 ? _T.fastpipe : _T_14; // FPU.scala:485:8
assign _T_15 = _T_2 ? _T.fma : _T_15; // FPU.scala:485:8
assign _T_16 = _T_2 ? _T.div : _T_16; // FPU.scala:485:8
assign _T_17 = _T_2 ? _T.sqrt : _T_17; // FPU.scala:485:8
assign _T_18 = _T_2 ? _T.wflags : _T_18; // FPU.scala:485:8
assign _T_19 = _T_2 ? _T.rm : _T_19; // FPU.scala:485:8
assign _T_20 = _T_2 ? _T.typ : _T_20; // FPU.scala:485:8
assign _T_21 = _T_2 ? _T_0 : _T_21; // FPU.scala:485:8
wire [4:0] _T_26 = _T.cmd; // FPU.scala:488:33
wire _T_27 = _T_24 | _T_25; // FPU.scala:488:48
assign _T_3 = _T_2 ? {3'h0, _T_26[1] & _T_27, _T_26[0]} : _T_3; // FPU.scala:488:{12,33,37,78}
assign _T_22 = _T_2 ? (_T_25 ? 65'h8000000000000000 : _T_1) : _T_22; // FPU.scala:489:32
assign _T_23 = _T_2 ? (_T_27 ? _T.in3 : {_T_0[64] ^ _T_1[64], 64'h0}) : _T_23; // FPU.scala:480:{29,37,53,62}, :485:8, :490:45
wire [4:0] _T_28 = _T_3; // FPU.scala:488:12
wire [2:0] _T_29 = _T_19; // FPU.scala:485:8
wire [64:0] _T_30 = res.data; // FPU.scala:500:17
wire [4:0] _T_31 = res.exc; // FPU.scala:500:17
assign _T_30 = fma_io_out; // FPU.scala:493:19, :501:12
assign _T_31 = fma_io_exceptionFlags; // FPU.scala:493:19, :502:11
wire [64:0] _T_34 = _T_0_33.data; // Reg.scala:34:16
wire [4:0] _T_35 = _T_0_33.exc; // Reg.scala:34:16
assign _T_34 = valid ? _T_30 : _T_34; // Reg.scala:35:23, Valid.scala:47:18
assign _T_35 = valid ? _T_31 : _T_35; // Reg.scala:35:23, Valid.scala:47:18
wire [64:0] _T_38 = _T_2_37.data; // Reg.scala:34:16
wire [4:0] _T_39 = _T_2_37.exc; // Reg.scala:34:16
assign _T_38 = _T_32 ? _T_34 : _T_38; // Reg.scala:35:23, Valid.scala:47:18
assign _T_39 = _T_32 ? _T_35 : _T_39; // Reg.scala:35:23, Valid.scala:47:18
always @(posedge clock) begin // Valid.scala:47:18
valid <= _T_2; // FPU.scala:482:18
if (reset) begin // Valid.scala:47:18
_T_32 <= 1'h0; // Conditional.scala:19:11, Valid.scala:47:18
_T_1_36 <= 1'h0; // Conditional.scala:19:11, Valid.scala:47:18
_T_3_40 <= 1'h0; // Conditional.scala:19:11, Valid.scala:47:18
end
else begin // Valid.scala:47:18
_T_32 <= valid; // Valid.scala:47:18
_T_1_36 <= _T_32; // Valid.scala:47:18
_T_3_40 <= _T_1_36; // Valid.scala:47:18
end
end // always @(posedge)
`ifndef SYNTHESIS // FPU.scala:482:18
initial begin // FPU.scala:482:18
automatic logic [31:0] _RANDOM; // FPU.scala:482:18
automatic logic [31:0] _RANDOM_50; // FPU.scala:483:15
automatic logic [31:0] _RANDOM_51; // FPU.scala:483:15
automatic logic [31:0] _RANDOM_52; // FPU.scala:483:15
automatic logic [31:0] _RANDOM_53; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_54; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_55; // Reg.scala:34:16
automatic logic [31:0] _RANDOM_56; // Reg.scala:34:16
`INIT_RANDOM_PROLOG_ // FPU.scala:482:18
`ifdef RANDOMIZE_REG_INIT // FPU.scala:482:18
_RANDOM = `RANDOM; // FPU.scala:482:18
valid = _RANDOM[0]; // FPU.scala:482:18
_T_3 = _RANDOM[5:1]; // FPU.scala:483:15
_T_4 = _RANDOM[6]; // FPU.scala:483:15
_T_5 = _RANDOM[7]; // FPU.scala:483:15
_T_6 = _RANDOM[8]; // FPU.scala:483:15
_T_7 = _RANDOM[9]; // FPU.scala:483:15
_T_8 = _RANDOM[10]; // FPU.scala:483:15
_T_9 = _RANDOM[11]; // FPU.scala:483:15
_T_10 = _RANDOM[12]; // FPU.scala:483:15
_T_11 = _RANDOM[13]; // FPU.scala:483:15
_T_12 = _RANDOM[14]; // FPU.scala:483:15
_T_13 = _RANDOM[15]; // FPU.scala:483:15
_T_14 = _RANDOM[16]; // FPU.scala:483:15
_T_15 = _RANDOM[17]; // FPU.scala:483:15
_T_16 = _RANDOM[18]; // FPU.scala:483:15
_T_17 = _RANDOM[19]; // FPU.scala:483:15
_T_18 = _RANDOM[20]; // FPU.scala:483:15
_T_19 = _RANDOM[23:21]; // FPU.scala:483:15
_T_20 = _RANDOM[25:24]; // FPU.scala:483:15
_RANDOM_50 = `RANDOM; // FPU.scala:483:15
_T_21 = {_RANDOM[31:26], `RANDOM, _RANDOM_50[26:0]}; // FPU.scala:483:15
_RANDOM_51 = `RANDOM; // FPU.scala:483:15
_T_22 = {_RANDOM_50[31:27], `RANDOM, _RANDOM_51[27:0]}; // FPU.scala:483:15
_RANDOM_52 = `RANDOM; // FPU.scala:483:15
_T_23 = {_RANDOM_51[31:28], `RANDOM, _RANDOM_52[28:0]}; // FPU.scala:483:15
_T_32 = _RANDOM_52[29]; // Valid.scala:47:18
_RANDOM_53 = `RANDOM; // Reg.scala:34:16
_T_34 = {_RANDOM_52[31:30], `RANDOM, _RANDOM_53[30:0]}; // Reg.scala:34:16
_RANDOM_54 = `RANDOM; // Reg.scala:34:16
_T_35 = {_RANDOM_53[31], _RANDOM_54[3:0]}; // Reg.scala:34:16
_T_1_36 = _RANDOM_54[4]; // Valid.scala:47:18
_RANDOM_55 = `RANDOM; // Reg.scala:34:16
_T_38 = {_RANDOM_54[31:5], `RANDOM, _RANDOM_55[5:0]}; // Reg.scala:34:16
_T_39 = _RANDOM_55[10:6]; // Reg.scala:34:16
_T_3_40 = _RANDOM_55[11]; // Valid.scala:47:18
_RANDOM_56 = `RANDOM; // Reg.scala:34:16
_T_4_41.data = {_RANDOM_55[31:12], `RANDOM, _RANDOM_56[12:0]}; // Reg.scala:34:16
_T_4_41.exc = _RANDOM_56[17:13]; // Reg.scala:34:16
`endif
end // initial
`endif
wire [64:0] _T_42 = _T_4_41.data; // Reg.scala:34:16
wire [4:0] _T_43 = _T_4_41.exc; // Reg.scala:34:16
assign _T_42 = _T_1_36 ? _T_38 : _T_42; // Reg.scala:35:23, Valid.scala:47:18
assign _T_43 = _T_1_36 ? _T_39 : _T_43; // Reg.scala:35:23, Valid.scala:47:18
wire _T_45 = _T_5_44.valid; // Valid.scala:42:21
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_46 = _T_5_44.bits; // Valid.scala:42:21
assign _T_45 = _T_3_40; // Valid.scala:43:17
wire [64:0] _T_47 = _T_46.data; // Valid.scala:44:16
assign _T_47 = _T_42; // Reg.scala:35:23, Valid.scala:44:16
wire [4:0] _T_48 = _T_46.exc; // Valid.scala:44:16
assign _T_48 = _T_43; // Reg.scala:35:23, Valid.scala:44:16
assign _io_out_output.valid = _T_45; // FPU.scala:503:10
wire struct packed {logic [64:0] data; logic [4:0] exc; } _T_49 = _io_out_output.bits; // FPU.scala:503:10
assign _T_49.data = _T_47; // FPU.scala:503:10
assign _T_49.exc = _T_48; // FPU.scala:503:10
MulAddRecFN_1 fma ( // FPU.scala:493:19
.clock (clock),
.reset (reset),
.io_op (_T_28[1:0]), // FPU.scala:494:13
.io_a (_T_21), // FPU.scala:485:8
.io_b (_T_22), // FPU.scala:489:32
.io_c (_T_23), // FPU.scala:490:45
.io_roundingMode (_T_29[1:0]), // FPU.scala:495:23
.io_out (fma_io_out),
.io_exceptionFlags (fma_io_exceptionFlags)
);
assign io_out = _io_out_output; // ../perf/regress/FPU.fir:1823:10
endmodule
module DivSqrtRecF64( // ../perf/regress/FPU.fir:1892:10
input clock, reset, io_inValid, io_sqrtOp,
input [64:0] io_a, io_b,
input [1:0] io_roundingMode,
output io_inReady_div, io_inReady_sqrt, io_outValid_div, io_outValid_sqrt,
output [64:0] io_out,
output [4:0] io_exceptionFlags);
wire [104:0] mul_io_result_s3; // DivSqrtRecF64.scala:73:21
wire [3:0] ds_io_usingMulAdd; // DivSqrtRecF64.scala:59:20
wire ds_io_latchMulAddA_0; // DivSqrtRecF64.scala:59:20
wire [53:0] ds_io_mulAddA_0; // DivSqrtRecF64.scala:59:20
wire ds_io_latchMulAddB_0; // DivSqrtRecF64.scala:59:20
wire [53:0] ds_io_mulAddB_0; // DivSqrtRecF64.scala:59:20
wire [104:0] ds_io_mulAddC_2; // DivSqrtRecF64.scala:59:20
DivSqrtRecF64_mulAddZ31 ds ( // DivSqrtRecF64.scala:59:20
.clock (clock),
.reset (reset),
.io_inValid (io_inValid),
.io_sqrtOp (io_sqrtOp),
.io_a (io_a),
.io_b (io_b),
.io_roundingMode (io_roundingMode),
.io_mulAddResult_3 (mul_io_result_s3), // DivSqrtRecF64.scala:73:21
.io_inReady_div (io_inReady_div),
.io_inReady_sqrt (io_inReady_sqrt),
.io_outValid_div (io_outValid_div),
.io_outValid_sqrt (io_outValid_sqrt),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags),
.io_usingMulAdd (ds_io_usingMulAdd),
.io_latchMulAddA_0 (ds_io_latchMulAddA_0),
.io_mulAddA_0 (ds_io_mulAddA_0),
.io_latchMulAddB_0 (ds_io_latchMulAddB_0),
.io_mulAddB_0 (ds_io_mulAddB_0),
.io_mulAddC_2 (ds_io_mulAddC_2)
);
Mul54 mul ( // DivSqrtRecF64.scala:73:21
.clock (clock),
.reset (reset),
.io_val_s0 (ds_io_usingMulAdd[0]), // DivSqrtRecF64.scala:59:20, :75:39
.io_latch_a_s0 (ds_io_latchMulAddA_0), // DivSqrtRecF64.scala:59:20
.io_a_s0 (ds_io_mulAddA_0), // DivSqrtRecF64.scala:59:20
.io_latch_b_s0 (ds_io_latchMulAddB_0), // DivSqrtRecF64.scala:59:20
.io_b_s0 (ds_io_mulAddB_0), // DivSqrtRecF64.scala:59:20
.io_c_s2 (ds_io_mulAddC_2), // DivSqrtRecF64.scala:59:20
.io_result_s3 (mul_io_result_s3)
);
endmodule
module RecFNToRecFN_2( // ../perf/regress/FPU.fir:1927:10
input clock, reset,
input [64:0] io_in,
input [1:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags);
wire struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [12:0] sExp; logic [55:0] sig; } _T; // rawFNFromRecFN.scala:54:23
wire struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [9:0] sExp; logic [26:0] sig; } outRawFloat; // resizeRawFN.scala:51:23
wire struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [9:0] sExp; logic [26:0] sig; } _io_in_wire; // RecFNToRecFN.scala:102:19
wire [2:0] _io_in_63to61 = io_in[63:61]; // rawFNFromRecFN.scala:51:29
wire [1:0] _io_in_63to62 = io_in[63:62]; // rawFNFromRecFN.scala:52:29
wire _T_0 = _T.sign; // rawFNFromRecFN.scala:54:23
wire _T_1 = _T.isNaN; // rawFNFromRecFN.scala:54:23
wire _T_2 = _T.isInf; // rawFNFromRecFN.scala:54:23
wire _T_3 = _T.isZero; // rawFNFromRecFN.scala:54:23
wire [12:0] _T_4 = _T.sExp; // rawFNFromRecFN.scala:54:23
wire [12:0] _T_5 = _T_4; // resizeRawFN.scala:49:31
wire [55:0] _T_6 = _T.sig; // rawFNFromRecFN.scala:54:23
wire [55:0] _T_7 = _T_6; // resizeRawFN.scala:71:28
assign _T_0 = io_in[64]; // rawFNFromRecFN.scala:55:{18,23}
wire _io_in_61 = io_in[61]; // rawFNFromRecFN.scala:56:40
assign _T_1 = &_io_in_63to62 & _io_in_61; // rawFNFromRecFN.scala:52:54, :56:{19,32}
assign _T_2 = &_io_in_63to62 & ~_io_in_61; // rawFNFromRecFN.scala:52:54, :57:{19,32,35}
assign _T_3 = ~(|_io_in_63to61); // rawFNFromRecFN.scala:51:54, :58:20
assign _T_4 = {1'h0, io_in[63:52]}; // rawFNFromRecFN.scala:50:21, :51:54, :59:{18,25}
assign _T_6 = {1'h0, |_io_in_63to61, io_in[51:0], 2'h0}; // Cat.scala:30:58, rawFNFromRecFN.scala:51:54, :60:{17,48}
wire [13:0] _T_8 = {_T_5[12], _T_4} - 14'h700; // resizeRawFN.scala:49:31
wire _T_9 = outRawFloat.sign; // resizeRawFN.scala:51:23
wire _T_10 = outRawFloat.isNaN; // resizeRawFN.scala:51:23
wire _T_11 = outRawFloat.isInf; // resizeRawFN.scala:51:23
wire _T_12 = outRawFloat.isZero; // resizeRawFN.scala:51:23
wire [9:0] _T_13 = outRawFloat.sExp; // resizeRawFN.scala:51:23
wire [26:0] _T_14 = outRawFloat.sig; // resizeRawFN.scala:51:23
wire [26:0] _T_15 = _T_14; // RoundRawFNToRecFN.scala:61:57
assign _T_9 = _T_0; // resizeRawFN.scala:52:20
assign _T_10 = _T_1; // resizeRawFN.scala:53:20
assign _T_11 = _T_2; // resizeRawFN.scala:54:20
assign _T_12 = _T_3; // resizeRawFN.scala:55:20
assign _T_13 = {$signed(_T_8) < 14'sh0, |(_T_8[12:9]) ? 9'h1FC : _T_8[8:0]}; // Cat.scala:30:58, resizeRawFN.scala:56:18, :60:31, :61:{25,33,65}, :63:33
wire [55:0] _T_16 = _T_6; // resizeRawFN.scala:71:28
assign _T_14 = {_T_7[55:30], |(_T_16[29:0])}; // Cat.scala:30:58, resizeRawFN.scala:67:17, :71:28, :72:{28,56}
assign _io_in_wire.sign = _T_9; // RecFNToRecFN.scala:105:33
assign _io_in_wire.isNaN = _T_10; // RecFNToRecFN.scala:105:33, RoundRawFNToRecFN.scala:61:46
assign _io_in_wire.isInf = _T_11; // RecFNToRecFN.scala:105:33
assign _io_in_wire.isZero = _T_12; // RecFNToRecFN.scala:105:33
assign _io_in_wire.sExp = _T_13; // RecFNToRecFN.scala:105:33
assign _io_in_wire.sig = _T_14; // RecFNToRecFN.scala:105:33, RoundRawFNToRecFN.scala:61:57
RoundRawFNToRecFN_1 RoundRawFNToRecFN ( // RecFNToRecFN.scala:102:19
.clock (clock),
.reset (reset),
.io_invalidExc (_T_10 & ~(_T_15[24])), // RoundRawFNToRecFN.scala:61:{46,49,57}
.io_infiniteExc (1'h0), // rawFNFromRecFN.scala:51:54
.io_in (_io_in_wire), // RecFNToRecFN.scala:102:19
.io_roundingMode (io_roundingMode),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule
module MulAddRecFN( // ../perf/regress/FPU.fir:1995:10
input clock, reset,
input [1:0] io_op,
input [32:0] io_a, io_b, io_c,
input [1:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags);
wire [23:0] mulAddRecFN_preMul_io_mulAddA; // MulAddRecFN.scala:598:15
wire [23:0] mulAddRecFN_preMul_io_mulAddB; // MulAddRecFN.scala:598:15
wire [47:0] mulAddRecFN_preMul_io_mulAddC; // MulAddRecFN.scala:598:15
wire struct packed {logic [2:0] highExpA; logic isNaN_isQuietNaNA; logic [2:0] highExpB; logic isNaN_isQuietNaNB; logic signProd; logic isZeroProd; logic opSignC; logic [2:0] highExpC; logic isNaN_isQuietNaNC; logic isCDominant; logic CAlignDist_0; logic [6:0] CAlignDist; logic bit0AlignedNegSigC; logic [25:0] highAlignedNegSigC; logic [10:0] sExpSum; logic [1:0] roundingMode; } mulAddRecFN_preMul_io_toPostMul; // MulAddRecFN.scala:598:15
wire struct packed {logic [2:0] highExpA; logic isNaN_isQuietNaNA; logic [2:0] highExpB; logic isNaN_isQuietNaNB; logic signProd; logic isZeroProd; logic opSignC; logic [2:0] highExpC; logic isNaN_isQuietNaNC; logic isCDominant; logic CAlignDist_0; logic [6:0] CAlignDist; logic bit0AlignedNegSigC; logic [25:0] highAlignedNegSigC; logic [10:0] sExpSum; logic [1:0] roundingMode; } _io_fromPreMul_wire; // MulAddRecFN.scala:600:15
assign _io_fromPreMul_wire.highExpA = mulAddRecFN_preMul_io_toPostMul.highExpA; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.isNaN_isQuietNaNA = mulAddRecFN_preMul_io_toPostMul.isNaN_isQuietNaNA; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.highExpB = mulAddRecFN_preMul_io_toPostMul.highExpB; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.isNaN_isQuietNaNB = mulAddRecFN_preMul_io_toPostMul.isNaN_isQuietNaNB; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.signProd = mulAddRecFN_preMul_io_toPostMul.signProd; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.isZeroProd = mulAddRecFN_preMul_io_toPostMul.isZeroProd; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.opSignC = mulAddRecFN_preMul_io_toPostMul.opSignC; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.highExpC = mulAddRecFN_preMul_io_toPostMul.highExpC; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.isNaN_isQuietNaNC = mulAddRecFN_preMul_io_toPostMul.isNaN_isQuietNaNC; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.isCDominant = mulAddRecFN_preMul_io_toPostMul.isCDominant; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.CAlignDist_0 = mulAddRecFN_preMul_io_toPostMul.CAlignDist_0; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.CAlignDist = mulAddRecFN_preMul_io_toPostMul.CAlignDist; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.bit0AlignedNegSigC = mulAddRecFN_preMul_io_toPostMul.bit0AlignedNegSigC; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.highAlignedNegSigC = mulAddRecFN_preMul_io_toPostMul.highAlignedNegSigC; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.sExpSum = mulAddRecFN_preMul_io_toPostMul.sExpSum; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.roundingMode = mulAddRecFN_preMul_io_toPostMul.roundingMode; // MulAddRecFN.scala:598:15, :608:39
MulAddRecFN_preMul mulAddRecFN_preMul ( // MulAddRecFN.scala:598:15
.clock (clock),
.reset (reset),
.io_op (io_op),
.io_a (io_a),
.io_b (io_b),
.io_c (io_c),
.io_roundingMode (io_roundingMode),
.io_mulAddA (mulAddRecFN_preMul_io_mulAddA),
.io_mulAddB (mulAddRecFN_preMul_io_mulAddB),
.io_mulAddC (mulAddRecFN_preMul_io_mulAddC),
.io_toPostMul (mulAddRecFN_preMul_io_toPostMul)
);
MulAddRecFN_postMul mulAddRecFN_postMul ( // MulAddRecFN.scala:600:15
.clock (clock),
.reset (reset),
.io_fromPreMul (_io_fromPreMul_wire), // MulAddRecFN.scala:600:15
.io_mulAddResult ({1'h0, {24'h0, mulAddRecFN_preMul_io_mulAddA} * {24'h0, mulAddRecFN_preMul_io_mulAddB}} +
{1'h0, mulAddRecFN_preMul_io_mulAddC}), // Cat.scala:30:58, MulAddRecFN.scala:598:15, :610:{39,71}
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule
module CompareRecFN( // ../perf/regress/FPU.fir:2024:10
input clock, reset,
input [64:0] io_a, io_b,
input io_signaling,
output io_lt, io_eq, io_gt,
output [4:0] io_exceptionFlags);
wire struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [12:0] sExp; logic [55:0] sig; } rawA; // rawFNFromRecFN.scala:54:23
wire struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [12:0] sExp; logic [55:0] sig; } rawB; // rawFNFromRecFN.scala:54:23
wire [2:0] _io_a_63to61 = io_a[63:61]; // rawFNFromRecFN.scala:51:29
wire [1:0] _io_a_63to62 = io_a[63:62]; // rawFNFromRecFN.scala:52:29
wire _T = rawA.sign; // rawFNFromRecFN.scala:54:23
wire _T_0 = rawA.isNaN; // rawFNFromRecFN.scala:54:23
wire _T_1 = rawA.isInf; // rawFNFromRecFN.scala:54:23
wire _T_2 = rawA.isZero; // rawFNFromRecFN.scala:54:23
wire [12:0] _T_3 = rawA.sExp; // rawFNFromRecFN.scala:54:23
wire [55:0] _T_4 = rawA.sig; // rawFNFromRecFN.scala:54:23
assign _T = io_a[64]; // rawFNFromRecFN.scala:55:{18,23}
wire _io_a_61 = io_a[61]; // rawFNFromRecFN.scala:56:40
assign _T_0 = &_io_a_63to62 & _io_a_61; // rawFNFromRecFN.scala:52:54, :56:{19,32}
assign _T_1 = &_io_a_63to62 & ~_io_a_61; // rawFNFromRecFN.scala:52:54, :57:{19,32,35}
assign _T_2 = ~(|_io_a_63to61); // rawFNFromRecFN.scala:51:54, :58:20
assign _T_3 = {1'h0, io_a[63:52]}; // rawFNFromRecFN.scala:50:21, :51:54, :59:{18,25}
assign _T_4 = {1'h0, |_io_a_63to61, io_a[51:0], 2'h0}; // Cat.scala:30:58, rawFNFromRecFN.scala:51:54, :60:{17,48}
wire [2:0] _io_b_63to61 = io_b[63:61]; // rawFNFromRecFN.scala:51:29
wire [1:0] _io_b_63to62 = io_b[63:62]; // rawFNFromRecFN.scala:52:29
wire _T_5 = rawB.sign; // rawFNFromRecFN.scala:54:23
wire _T_6 = rawB.isNaN; // rawFNFromRecFN.scala:54:23
wire _T_7 = rawB.isInf; // rawFNFromRecFN.scala:54:23
wire _T_8 = rawB.isZero; // rawFNFromRecFN.scala:54:23
wire [12:0] _T_9 = rawB.sExp; // rawFNFromRecFN.scala:54:23
wire [55:0] _T_10 = rawB.sig; // rawFNFromRecFN.scala:54:23
assign _T_5 = io_b[64]; // rawFNFromRecFN.scala:55:{18,23}
wire _io_b_61 = io_b[61]; // rawFNFromRecFN.scala:56:40
assign _T_6 = &_io_b_63to62 & _io_b_61; // rawFNFromRecFN.scala:52:54, :56:{19,32}
assign _T_7 = &_io_b_63to62 & ~_io_b_61; // rawFNFromRecFN.scala:52:54, :57:{19,32,35}
assign _T_8 = ~(|_io_b_63to61); // rawFNFromRecFN.scala:51:54, :58:20
assign _T_9 = {1'h0, io_b[63:52]}; // rawFNFromRecFN.scala:50:21, :51:54, :59:{18,25}
assign _T_10 = {1'h0, |_io_b_63to61, io_b[51:0], 2'h0}; // Cat.scala:30:58, rawFNFromRecFN.scala:51:54, :60:{17,48}
wire _T_11 = ~_T_0 & ~_T_6; // CompareRecFN.scala:57:{19,32,35}
wire _T_12 = _T_1 & _T_7; // CompareRecFN.scala:58:33
wire _T_13 = _T_2 & _T_8; // CompareRecFN.scala:59:33
wire _T_14 = _T_3 == _T_9; // CompareRecFN.scala:60:29
wire _T_15 = $signed(_T_3) < $signed(_T_9) | _T_14 & _T_4 < _T_10; // CompareRecFN.scala:60:29, :62:{20,33,44,57}
wire _T_16 = _T_14 & _T_4 == _T_10; // CompareRecFN.scala:62:57, :63:{32,45}
wire _T_17 = ~_T_13 & (_T & ~_T_5 | ~_T_12 & (_T & ~_T_15 & ~_T_16 | ~_T_5 & _T_15)); // CompareRecFN.scala:66:{9,21}, :67:{25,28,41}, :68:{19,30}, :69:{38,54,57,74}, :70:41
wire _T_18 = _T_13 | _T == _T_5 & (_T_12 | _T_16); // CompareRecFN.scala:67:{25,28}, :72:{19,34,49,62}
wire [55:0] _T_19 = _T_4; // CompareRecFN.scala:62:57
wire [55:0] _T_20 = _T_10; // CompareRecFN.scala:62:57
assign io_lt = _T_11 & _T_17; // ../perf/regress/FPU.fir:2024:10, CompareRecFN.scala:78:22
assign io_eq = _T_11 & _T_18; // ../perf/regress/FPU.fir:2024:10, CompareRecFN.scala:79:22
assign io_gt = _T_11 & ~_T_17 & ~_T_18; // ../perf/regress/FPU.fir:2024:10, CompareRecFN.scala:80:{25,38,41}
assign io_exceptionFlags = {_T_0 & ~(_T_19[53]) | _T_6 & ~(_T_20[53]) | io_signaling & ~_T_11, 4'h0}; // ../perf/regress/FPU.fir:2024:10, Cat.scala:30:58, CompareRecFN.scala:57:{19,35}, :75:52, :76:{27,30}, RoundRawFNToRecFN.scala:61:{46,49,57}
endmodule
module RecFNToIN( // ../perf/regress/FPU.fir:2133:10
input clock, reset,
input [64:0] io_in,
input [1:0] io_roundingMode,
input io_signedOut,
output [31:0] io_out,
output [2:0] io_intExceptionFlags);
wire _io_in_64 = io_in[64]; // RecFNToIN.scala:54:21
wire [1:0] _io_in_63to62 = io_in[63:62]; // RecFNToIN.scala:59:25
wire _io_in_63 = io_in[63]; // RecFNToIN.scala:61:34
wire [83:0] _T = {31'h0, _io_in_63, io_in[51:0]} << (_io_in_63 ? io_in[56:52] : 5'h0); // RecFNToIN.scala:56:22, :72:40, :73:16, :74:20, :127:12
wire [1:0] _T_0 = {_T[51], |(_T[50:0])}; // RecFNToIN.scala:86:{23,41}, :88:58
wire _T_1 = _io_in_63 ? |_T_0 : |(io_in[63:61]); // RecFNToIN.scala:58:{22,47}, :88:{27,65}
wire [10:0] _io_in_62to52 = io_in[62:52]; // RecFNToIN.scala:92:20
wire _T_2 = io_roundingMode == 2'h0 & (_io_in_63 ? &(_T[52:51]) | &_T_0 : &_io_in_62to52 & |_T_0) |
io_roundingMode == 2'h2 & _io_in_64 & _T_1 | &io_roundingMode & ~_io_in_64 & _T_1; // RecFNToIN.scala:85:23, :88:65, :90:12, :91:{29,34,53}, :92:{16,38}, :95:{27,51}, :96:{27,49,78}, :97:{27,49,53}
wire [31:0] _T_3 = {32{_io_in_64}} ^ _T[83:52]; // RecFNToIN.scala:82:24, :98:32
wire _T_4 = &(_T[81:52]) & _T_2; // RecFNToIN.scala:103:{38,56,61}
wire [5:0] _io_in_62to57 = io_in[62:57]; // RecFNToIN.scala:108:21
wire _T_5 = _io_in_62to52 == 11'h1F; // RecFNToIN.scala:109:26
wire _T_6 = io_signedOut ? _io_in_63 & (|_io_in_62to57 | _T_5 & (~_io_in_64 | |(_T[82:52]) | _T_2) |
~_io_in_64 & _io_in_62to52 == 11'h1E & _T_4) : _io_in_63 ? _io_in_64 | |_io_in_62to57 |
_T_5 & _T[82] & _T_4 : _io_in_64 & _T_2; // RecFNToIN.scala:97:53, :107:12, :108:21, :109:50, :110:{45,63}, :111:{27,42}, :112:{36,60}, :116:12, :117:48, :119:{34,49}, :120:18, :122:23
wire _T_7 = _io_in_64 & ~(&_io_in_63to62 & io_in[61]); // RecFNToIN.scala:59:50, :60:{27,33}, :124:{24,27}
assign io_out = &_io_in_63to62 | _T_6 ? {io_signedOut & _T_7, {31{io_signedOut & ~_T_7}}} |
{32{~io_signedOut & ~_T_7}} : _T_2 ^ _io_in_64 ? _T_3 + 32'h1 : _T_3; // ../perf/regress/FPU.fir:2133:10, RecFNToIN.scala:59:50, :100:{12,23,49}, :126:{26,72}, :127:{12,26,29}, :130:11, :131:{12,13,28}, :137:{18,27}
assign io_intExceptionFlags = {&_io_in_63to62, _T_6, _T_1 & ~(&_io_in_63to62) & ~_T_6}; // ../perf/regress/FPU.fir:2133:10, Cat.scala:30:58, RecFNToIN.scala:59:50, :135:{35,45,48}
endmodule
module RecFNToIN_1( // ../perf/regress/FPU.fir:2249:10
input clock, reset,
input [64:0] io_in,
input [1:0] io_roundingMode,
input io_signedOut,
output [63:0] io_out,
output [2:0] io_intExceptionFlags);
wire _io_in_64 = io_in[64]; // RecFNToIN.scala:54:21
wire [1:0] _io_in_63to62 = io_in[63:62]; // RecFNToIN.scala:59:25
wire _io_in_63 = io_in[63]; // RecFNToIN.scala:61:34
wire [115:0] _T = {63'h0, _io_in_63, io_in[51:0]} << (_io_in_63 ? io_in[57:52] : 6'h0); // RecFNToIN.scala:56:22, :72:40, :73:16, :74:20, :127:12
wire [1:0] _T_0 = {_T[51], |(_T[50:0])}; // RecFNToIN.scala:86:{23,41}, :88:58
wire _T_1 = _io_in_63 ? |_T_0 : |(io_in[63:61]); // RecFNToIN.scala:58:{22,47}, :88:{27,65}
wire [10:0] _io_in_62to52 = io_in[62:52]; // RecFNToIN.scala:92:20
wire _T_2 = io_roundingMode == 2'h0 & (_io_in_63 ? &(_T[52:51]) | &_T_0 : &_io_in_62to52 & |_T_0) |
io_roundingMode == 2'h2 & _io_in_64 & _T_1 | &io_roundingMode & ~_io_in_64 & _T_1; // RecFNToIN.scala:85:23, :88:65, :90:12, :91:{29,34,53}, :92:{16,38}, :95:{27,51}, :96:{27,49,78}, :97:{27,49,53}
wire [63:0] _T_3 = {64{_io_in_64}} ^ _T[115:52]; // RecFNToIN.scala:82:24, :98:32
wire _T_4 = &(_T[113:52]) & _T_2; // RecFNToIN.scala:103:{38,56,61}
wire [4:0] _io_in_62to58 = io_in[62:58]; // RecFNToIN.scala:108:21
wire _T_5 = _io_in_62to52 == 11'h3F; // RecFNToIN.scala:109:26
wire _T_6 = io_signedOut ? _io_in_63 & (|_io_in_62to58 | _T_5 & (~_io_in_64 | |(_T[114:52]) | _T_2) |
~_io_in_64 & _io_in_62to52 == 11'h3E & _T_4) : _io_in_63 ? _io_in_64 | |_io_in_62to58 |
_T_5 & _T[114] & _T_4 : _io_in_64 & _T_2; // RecFNToIN.scala:97:53, :107:12, :108:21, :109:50, :110:{45,63}, :111:{27,42}, :112:{36,60}, :116:12, :117:48, :119:{34,49}, :120:18, :122:23
wire _T_7 = _io_in_64 & ~(&_io_in_63to62 & io_in[61]); // RecFNToIN.scala:59:50, :60:{27,33}, :124:{24,27}
assign io_out = &_io_in_63to62 | _T_6 ? {io_signedOut & _T_7, {63{io_signedOut & ~_T_7}}} |
{64{~io_signedOut & ~_T_7}} : _T_2 ^ _io_in_64 ? _T_3 + 64'h1 : _T_3; // ../perf/regress/FPU.fir:2249:10, RecFNToIN.scala:59:50, :100:{12,23,49}, :126:{26,72}, :127:{12,26,29}, :130:11, :131:{12,13,28}, :137:{18,27}
assign io_intExceptionFlags = {&_io_in_63to62, _T_6, _T_1 & ~(&_io_in_63to62) & ~_T_6}; // ../perf/regress/FPU.fir:2249:10, Cat.scala:30:58, RecFNToIN.scala:59:50, :135:{35,45,48}
endmodule
module INToRecFN( // ../perf/regress/FPU.fir:2365:10
input clock, reset, io_signedIn,
input [63:0] io_in,
input [1:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags);
wire _T = io_signedIn & io_in[63]; // INToRecFN.scala:55:{28,36}
wire [63:0] _T_0 = _T ? 64'h0 - io_in : io_in; // INToRecFN.scala:56:{20,27}
wire [31:0] _T_1 = _T_0[63:32]; // CircuitMath.scala:35:17
wire [15:0] _T_2 = _T_0[63:48]; // CircuitMath.scala:35:17
wire [7:0] _T_3 = _T_0[63:56]; // CircuitMath.scala:35:17
wire [3:0] _T_4 = _T_0[63:60]; // CircuitMath.scala:35:17
wire [3:0] _T_5 = _T_0[55:52]; // CircuitMath.scala:35:17
wire [7:0] _T_6 = _T_0[47:40]; // CircuitMath.scala:35:17
wire [3:0] _T_7 = _T_0[47:44]; // CircuitMath.scala:35:17
wire [3:0] _T_8 = _T_0[39:36]; // CircuitMath.scala:35:17
wire [15:0] _T_9 = _T_0[31:16]; // CircuitMath.scala:35:17
wire [7:0] _T_10 = _T_0[31:24]; // CircuitMath.scala:35:17
wire [3:0] _T_11 = _T_0[31:28]; // CircuitMath.scala:35:17
wire [3:0] _T_12 = _T_0[23:20]; // CircuitMath.scala:35:17
wire [7:0] _T_13 = _T_0[15:8]; // CircuitMath.scala:35:17
wire [3:0] _T_14 = _T_0[15:12]; // CircuitMath.scala:35:17
wire [3:0] _T_15 = _T_0[7:4]; // CircuitMath.scala:35:17
wire [4:0] _T_16 = |_T_1 ? {|_T_2, |_T_2 ? {|_T_3, |_T_3 ? {|_T_4, |_T_4 ? (_T_0[63] ? 2'h3 : _T_0[62] ? 2'h2
: {1'h0, _T_0[61]}) : _T_0[59] ? 2'h3 : _T_0[58] ? 2'h2 : {1'h0, _T_0[57]}} : {|_T_5, |_T_5
? (_T_0[55] ? 2'h3 : _T_0[54] ? 2'h2 : {1'h0, _T_0[53]}) : _T_0[51] ? 2'h3 : _T_0[50] ?
2'h2 : {1'h0, _T_0[49]}}} : {|_T_6, |_T_6 ? {|_T_7, |_T_7 ? (_T_0[47] ? 2'h3 : _T_0[46] ?
2'h2 : {1'h0, _T_0[45]}) : _T_0[43] ? 2'h3 : _T_0[42] ? 2'h2 : {1'h0, _T_0[41]}} : {|_T_8,
|_T_8 ? (_T_0[39] ? 2'h3 : _T_0[38] ? 2'h2 : {1'h0, _T_0[37]}) : _T_0[35] ? 2'h3 : _T_0[34]
? 2'h2 : {1'h0, _T_0[33]}}}} : {|_T_9, |_T_9 ? {|_T_10, |_T_10 ? {|_T_11, |_T_11 ?
(_T_0[31] ? 2'h3 : _T_0[30] ? 2'h2 : {1'h0, _T_0[29]}) : _T_0[27] ? 2'h3 : _T_0[26] ? 2'h2
: {1'h0, _T_0[25]}} : {|_T_12, |_T_12 ? (_T_0[23] ? 2'h3 : _T_0[22] ? 2'h2 : {1'h0,
_T_0[21]}) : _T_0[19] ? 2'h3 : _T_0[18] ? 2'h2 : {1'h0, _T_0[17]}}} : {|_T_13, |_T_13 ?
{|_T_14, |_T_14 ? (_T_0[15] ? 2'h3 : _T_0[14] ? 2'h2 : {1'h0, _T_0[13]}) : _T_0[11] ? 2'h3
: _T_0[10] ? 2'h2 : {1'h0, _T_0[9]}} : {|_T_15, |_T_15 ? (_T_0[7] ? 2'h3 : _T_0[6] ? 2'h2 :
{1'h0, _T_0[5]}) : _T_0[3] ? 2'h3 : _T_0[2] ? 2'h2 : {1'h0, _T_0[1]}}}}; // Cat.scala:30:58, CircuitMath.scala:30:8, :32:{10,12}, :37:22, :38:21, INToRecFN.scala:56:27
wire [126:0] _T_17 = {63'h0, _T_0} << ~{|_T_1, _T_16}; // Cat.scala:30:58, CircuitMath.scala:37:22, INToRecFN.scala:57:21, :58:27
wire [1:0] _T_18 = {_T_17[39], |(_T_17[38:0])}; // INToRecFN.scala:64:{26,55}, :72:33
wire [23:0] _T_19 = _T_17[63:40]; // INToRecFN.scala:89:34
wire [24:0] _T_20 = io_roundingMode == 2'h0 & (&(_T_17[40:39]) | &_T_18) | io_roundingMode == 2'h2 & _T &
|_T_18 | &io_roundingMode & ~_T & |_T_18 ? {1'h0, _T_19} + 25'h1 : {1'h0, _T_19}; // Cat.scala:30:58, CircuitMath.scala:32:10, INToRecFN.scala:56:27, :63:26, :72:40, :74:{12,30}, :75:{29,34,53}, :78:{12,30}, :81:11, :82:{12,30}, :83:13, :94:{26,48}
assign io_out = {_T, _T_17[63], {2'h0, |_T_1, _T_16} + {7'h0, _T_20[24]}, _T_20[22:0]}; // ../perf/regress/FPU.fir:2365:10, Cat.scala:30:58, CircuitMath.scala:37:22, INToRecFN.scala:72:40, :106:{52,65}, :112:22, :122:44
assign io_exceptionFlags = {4'h0, |_T_18}; // ../perf/regress/FPU.fir:2365:10, Cat.scala:30:58, CircuitMath.scala:37:22, INToRecFN.scala:72:40
endmodule
module INToRecFN_1( // ../perf/regress/FPU.fir:2587:10
input clock, reset, io_signedIn,
input [63:0] io_in,
input [1:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags);
wire _T = io_signedIn & io_in[63]; // INToRecFN.scala:55:{28,36}
wire [63:0] _T_0 = _T ? 64'h0 - io_in : io_in; // INToRecFN.scala:56:{20,27}
wire [31:0] _T_1 = _T_0[63:32]; // CircuitMath.scala:35:17
wire [15:0] _T_2 = _T_0[63:48]; // CircuitMath.scala:35:17
wire [7:0] _T_3 = _T_0[63:56]; // CircuitMath.scala:35:17
wire [3:0] _T_4 = _T_0[63:60]; // CircuitMath.scala:35:17
wire [3:0] _T_5 = _T_0[55:52]; // CircuitMath.scala:35:17
wire [7:0] _T_6 = _T_0[47:40]; // CircuitMath.scala:35:17
wire [3:0] _T_7 = _T_0[47:44]; // CircuitMath.scala:35:17
wire [3:0] _T_8 = _T_0[39:36]; // CircuitMath.scala:35:17
wire [15:0] _T_9 = _T_0[31:16]; // CircuitMath.scala:35:17
wire [7:0] _T_10 = _T_0[31:24]; // CircuitMath.scala:35:17
wire [3:0] _T_11 = _T_0[31:28]; // CircuitMath.scala:35:17
wire [3:0] _T_12 = _T_0[23:20]; // CircuitMath.scala:35:17
wire [7:0] _T_13 = _T_0[15:8]; // CircuitMath.scala:35:17
wire [3:0] _T_14 = _T_0[15:12]; // CircuitMath.scala:35:17
wire [3:0] _T_15 = _T_0[7:4]; // CircuitMath.scala:35:17
wire [4:0] _T_16 = |_T_1 ? {|_T_2, |_T_2 ? {|_T_3, |_T_3 ? {|_T_4, |_T_4 ? (_T_0[63] ? 2'h3 : _T_0[62] ? 2'h2
: {1'h0, _T_0[61]}) : _T_0[59] ? 2'h3 : _T_0[58] ? 2'h2 : {1'h0, _T_0[57]}} : {|_T_5, |_T_5
? (_T_0[55] ? 2'h3 : _T_0[54] ? 2'h2 : {1'h0, _T_0[53]}) : _T_0[51] ? 2'h3 : _T_0[50] ?
2'h2 : {1'h0, _T_0[49]}}} : {|_T_6, |_T_6 ? {|_T_7, |_T_7 ? (_T_0[47] ? 2'h3 : _T_0[46] ?
2'h2 : {1'h0, _T_0[45]}) : _T_0[43] ? 2'h3 : _T_0[42] ? 2'h2 : {1'h0, _T_0[41]}} : {|_T_8,
|_T_8 ? (_T_0[39] ? 2'h3 : _T_0[38] ? 2'h2 : {1'h0, _T_0[37]}) : _T_0[35] ? 2'h3 : _T_0[34]
? 2'h2 : {1'h0, _T_0[33]}}}} : {|_T_9, |_T_9 ? {|_T_10, |_T_10 ? {|_T_11, |_T_11 ?
(_T_0[31] ? 2'h3 : _T_0[30] ? 2'h2 : {1'h0, _T_0[29]}) : _T_0[27] ? 2'h3 : _T_0[26] ? 2'h2
: {1'h0, _T_0[25]}} : {|_T_12, |_T_12 ? (_T_0[23] ? 2'h3 : _T_0[22] ? 2'h2 : {1'h0,
_T_0[21]}) : _T_0[19] ? 2'h3 : _T_0[18] ? 2'h2 : {1'h0, _T_0[17]}}} : {|_T_13, |_T_13 ?
{|_T_14, |_T_14 ? (_T_0[15] ? 2'h3 : _T_0[14] ? 2'h2 : {1'h0, _T_0[13]}) : _T_0[11] ? 2'h3
: _T_0[10] ? 2'h2 : {1'h0, _T_0[9]}} : {|_T_15, |_T_15 ? (_T_0[7] ? 2'h3 : _T_0[6] ? 2'h2 :
{1'h0, _T_0[5]}) : _T_0[3] ? 2'h3 : _T_0[2] ? 2'h2 : {1'h0, _T_0[1]}}}}; // Cat.scala:30:58, CircuitMath.scala:30:8, :32:{10,12}, :37:22, :38:21, INToRecFN.scala:56:27
wire [126:0] _T_17 = {63'h0, _T_0} << ~{|_T_1, _T_16}; // Cat.scala:30:58, CircuitMath.scala:37:22, INToRecFN.scala:57:21, :58:27
wire [1:0] _T_18 = {_T_17[10], |(_T_17[9:0])}; // INToRecFN.scala:64:{26,55}, :72:33
wire [52:0] _T_19 = _T_17[63:11]; // INToRecFN.scala:89:34
wire [53:0] _T_20 = io_roundingMode == 2'h0 & (&(_T_17[11:10]) | &_T_18) | io_roundingMode == 2'h2 & _T &
|_T_18 | &io_roundingMode & ~_T & |_T_18 ? {1'h0, _T_19} + 54'h1 : {1'h0, _T_19}; // Cat.scala:30:58, CircuitMath.scala:32:10, INToRecFN.scala:56:27, :63:26, :72:40, :74:{12,30}, :75:{29,34,53}, :78:{12,30}, :81:11, :82:{12,30}, :83:13, :94:{26,48}
assign io_out = {_T, _T_17[63], {5'h0, |_T_1, _T_16} + {10'h0, _T_20[53]}, _T_20[51:0]}; // ../perf/regress/FPU.fir:2587:10, Cat.scala:30:58, CircuitMath.scala:37:22, INToRecFN.scala:64:55, :106:{52,65}, :112:22, :122:44
assign io_exceptionFlags = {4'h0, |_T_18}; // ../perf/regress/FPU.fir:2587:10, Cat.scala:30:58, INToRecFN.scala:72:40
endmodule
module RecFNToRecFN( // ../perf/regress/FPU.fir:2809:10
input clock, reset,
input [64:0] io_in,
input [1:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags);
wire struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [12:0] sExp; logic [55:0] sig; } _T; // rawFNFromRecFN.scala:54:23
wire struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [9:0] sExp; logic [26:0] sig; } outRawFloat; // resizeRawFN.scala:51:23
wire struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [9:0] sExp; logic [26:0] sig; } _io_in_wire; // RecFNToRecFN.scala:102:19
wire [2:0] _io_in_63to61 = io_in[63:61]; // rawFNFromRecFN.scala:51:29
wire [1:0] _io_in_63to62 = io_in[63:62]; // rawFNFromRecFN.scala:52:29
wire _T_0 = _T.sign; // rawFNFromRecFN.scala:54:23
wire _T_1 = _T.isNaN; // rawFNFromRecFN.scala:54:23
wire _T_2 = _T.isInf; // rawFNFromRecFN.scala:54:23
wire _T_3 = _T.isZero; // rawFNFromRecFN.scala:54:23
wire [12:0] _T_4 = _T.sExp; // rawFNFromRecFN.scala:54:23
wire [12:0] _T_5 = _T_4; // resizeRawFN.scala:49:31
wire [55:0] _T_6 = _T.sig; // rawFNFromRecFN.scala:54:23
wire [55:0] _T_7 = _T_6; // resizeRawFN.scala:71:28
assign _T_0 = io_in[64]; // rawFNFromRecFN.scala:55:{18,23}
wire _io_in_61 = io_in[61]; // rawFNFromRecFN.scala:56:40
assign _T_1 = &_io_in_63to62 & _io_in_61; // rawFNFromRecFN.scala:52:54, :56:{19,32}
assign _T_2 = &_io_in_63to62 & ~_io_in_61; // rawFNFromRecFN.scala:52:54, :57:{19,32,35}
assign _T_3 = ~(|_io_in_63to61); // rawFNFromRecFN.scala:51:54, :58:20
assign _T_4 = {1'h0, io_in[63:52]}; // rawFNFromRecFN.scala:50:21, :51:54, :59:{18,25}
assign _T_6 = {1'h0, |_io_in_63to61, io_in[51:0], 2'h0}; // Cat.scala:30:58, rawFNFromRecFN.scala:51:54, :60:{17,48}
wire [13:0] _T_8 = {_T_5[12], _T_4} - 14'h700; // resizeRawFN.scala:49:31
wire _T_9 = outRawFloat.sign; // resizeRawFN.scala:51:23
wire _T_10 = outRawFloat.isNaN; // resizeRawFN.scala:51:23
wire _T_11 = outRawFloat.isInf; // resizeRawFN.scala:51:23
wire _T_12 = outRawFloat.isZero; // resizeRawFN.scala:51:23
wire [9:0] _T_13 = outRawFloat.sExp; // resizeRawFN.scala:51:23
wire [26:0] _T_14 = outRawFloat.sig; // resizeRawFN.scala:51:23
wire [26:0] _T_15 = _T_14; // RoundRawFNToRecFN.scala:61:57
assign _T_9 = _T_0; // resizeRawFN.scala:52:20
assign _T_10 = _T_1; // resizeRawFN.scala:53:20
assign _T_11 = _T_2; // resizeRawFN.scala:54:20
assign _T_12 = _T_3; // resizeRawFN.scala:55:20
assign _T_13 = {$signed(_T_8) < 14'sh0, |(_T_8[12:9]) ? 9'h1FC : _T_8[8:0]}; // Cat.scala:30:58, resizeRawFN.scala:56:18, :60:31, :61:{25,33,65}, :63:33
wire [55:0] _T_16 = _T_6; // resizeRawFN.scala:71:28
assign _T_14 = {_T_7[55:30], |(_T_16[29:0])}; // Cat.scala:30:58, resizeRawFN.scala:67:17, :71:28, :72:{28,56}
assign _io_in_wire.sign = _T_9; // RecFNToRecFN.scala:105:33
assign _io_in_wire.isNaN = _T_10; // RecFNToRecFN.scala:105:33, RoundRawFNToRecFN.scala:61:46
assign _io_in_wire.isInf = _T_11; // RecFNToRecFN.scala:105:33
assign _io_in_wire.isZero = _T_12; // RecFNToRecFN.scala:105:33
assign _io_in_wire.sExp = _T_13; // RecFNToRecFN.scala:105:33
assign _io_in_wire.sig = _T_14; // RecFNToRecFN.scala:105:33, RoundRawFNToRecFN.scala:61:57
RoundRawFNToRecFN RoundRawFNToRecFN ( // RecFNToRecFN.scala:102:19
.clock (clock),
.reset (reset),
.io_invalidExc (_T_10 & ~(_T_15[24])), // RoundRawFNToRecFN.scala:61:{46,49,57}
.io_infiniteExc (1'h0), // rawFNFromRecFN.scala:51:54
.io_in (_io_in_wire), // RecFNToRecFN.scala:102:19
.io_roundingMode (io_roundingMode),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule
module RecFNToRecFN_1( // ../perf/regress/FPU.fir:2877:10
input clock, reset,
input [32:0] io_in,
input [1:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags);
wire struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [9:0] sExp; logic [26:0] sig; } _T; // rawFNFromRecFN.scala:54:23
wire struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [12:0] sExp; logic [55:0] sig; } outRawFloat; // resizeRawFN.scala:51:23
wire [2:0] _io_in_31to29 = io_in[31:29]; // rawFNFromRecFN.scala:51:29
wire [1:0] _io_in_31to30 = io_in[31:30]; // rawFNFromRecFN.scala:52:29
wire _T_0 = _T.sign; // rawFNFromRecFN.scala:54:23
wire _T_1 = _T.isNaN; // rawFNFromRecFN.scala:54:23
wire _T_2 = _T.isInf; // rawFNFromRecFN.scala:54:23
wire _T_3 = _T.isZero; // rawFNFromRecFN.scala:54:23
wire [9:0] _T_4 = _T.sExp; // rawFNFromRecFN.scala:54:23
wire [9:0] _T_5 = _T_4; // resizeRawFN.scala:49:31
wire [26:0] _T_6 = _T.sig; // rawFNFromRecFN.scala:54:23
assign _T_0 = io_in[32]; // rawFNFromRecFN.scala:55:{18,23}
wire _io_in_29 = io_in[29]; // rawFNFromRecFN.scala:56:40
assign _T_1 = &_io_in_31to30 & _io_in_29; // rawFNFromRecFN.scala:52:54, :56:{19,32}
assign _T_2 = &_io_in_31to30 & ~_io_in_29; // rawFNFromRecFN.scala:52:54, :57:{19,32,35}
assign _T_3 = ~(|_io_in_31to29); // rawFNFromRecFN.scala:51:54, :58:20
assign _T_4 = {1'h0, io_in[31:23]}; // rawFNFromRecFN.scala:50:21, :51:54, :59:{18,25}
assign _T_6 = {1'h0, |_io_in_31to29, io_in[22:0], 2'h0}; // Cat.scala:30:58, rawFNFromRecFN.scala:51:54, :60:{17,48}
wire _T_7 = outRawFloat.sign; // resizeRawFN.scala:51:23
wire _T_8 = outRawFloat.isNaN; // resizeRawFN.scala:51:23
wire _T_9 = outRawFloat.isInf; // resizeRawFN.scala:51:23
wire _T_10 = outRawFloat.isZero; // resizeRawFN.scala:51:23
wire [12:0] _T_11 = outRawFloat.sExp; // resizeRawFN.scala:51:23
wire [12:0] _T_12 = _T_11; // RecFNToRecFN.scala:71:30
wire [55:0] _T_13 = outRawFloat.sig; // resizeRawFN.scala:51:23
wire [55:0] _T_14 = _T_13; // RoundRawFNToRecFN.scala:61:57
assign _T_7 = _T_0; // resizeRawFN.scala:52:20
assign _T_8 = _T_1; // resizeRawFN.scala:53:20
assign _T_9 = _T_2; // resizeRawFN.scala:54:20
assign _T_10 = _T_3; // resizeRawFN.scala:55:20
assign _T_11 = {{3{_T_5[9]}}, _T_4} + 13'h700; // resizeRawFN.scala:49:31, :56:18
assign _T_13 = {_T_6, 29'h0}; // resizeRawFN.scala:67:17, :69:24
wire [55:0] _T_15 = _T_13; // RoundRawFNToRecFN.scala:61:57
assign io_out = {_T_7 & ~_T_8, _T_12[11:0] & ~(_T_10 ? 12'hC00 : 12'h0) & {2'h3, ~(_T_10 | _T_9), 9'h1FF} |
(_T_9 ? 12'hC00 : 12'h0) | (_T_8 ? 12'hE00 : 12'h0), _T_8 ? 52'h8000000000000 :
_T_15[53:2]}; // ../perf/regress/FPU.fir:2877:10, Cat.scala:30:58, RecFNToRecFN.scala:69:{37,40}, :71:30, :72:{18,22}, :75:21, :76:{18,22,42}, :80:20, :83:19, :84:20, :89:16, :90:24, :91:32, RoundRawFNToRecFN.scala:61:46, rawFNFromRecFN.scala:52:54
assign io_exceptionFlags = {_T_8 & ~(_T_14[53]), 4'h0}; // ../perf/regress/FPU.fir:2877:10, Cat.scala:30:58, RoundRawFNToRecFN.scala:61:{46,49,57}
endmodule
module MulAddRecFN_1( // ../perf/regress/FPU.fir:2945:10
input clock, reset,
input [1:0] io_op,
input [64:0] io_a, io_b, io_c,
input [1:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags);
wire [52:0] mulAddRecFN_preMul_io_mulAddA; // MulAddRecFN.scala:598:15
wire [52:0] mulAddRecFN_preMul_io_mulAddB; // MulAddRecFN.scala:598:15
wire [105:0] mulAddRecFN_preMul_io_mulAddC; // MulAddRecFN.scala:598:15
wire struct packed {logic [2:0] highExpA; logic isNaN_isQuietNaNA; logic [2:0] highExpB; logic isNaN_isQuietNaNB; logic signProd; logic isZeroProd; logic opSignC; logic [2:0] highExpC; logic isNaN_isQuietNaNC; logic isCDominant; logic CAlignDist_0; logic [7:0] CAlignDist; logic bit0AlignedNegSigC; logic [54:0] highAlignedNegSigC; logic [13:0] sExpSum; logic [1:0] roundingMode; } mulAddRecFN_preMul_io_toPostMul; // MulAddRecFN.scala:598:15
wire struct packed {logic [2:0] highExpA; logic isNaN_isQuietNaNA; logic [2:0] highExpB; logic isNaN_isQuietNaNB; logic signProd; logic isZeroProd; logic opSignC; logic [2:0] highExpC; logic isNaN_isQuietNaNC; logic isCDominant; logic CAlignDist_0; logic [7:0] CAlignDist; logic bit0AlignedNegSigC; logic [54:0] highAlignedNegSigC; logic [13:0] sExpSum; logic [1:0] roundingMode; } _io_fromPreMul_wire; // MulAddRecFN.scala:600:15
assign _io_fromPreMul_wire.highExpA = mulAddRecFN_preMul_io_toPostMul.highExpA; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.isNaN_isQuietNaNA = mulAddRecFN_preMul_io_toPostMul.isNaN_isQuietNaNA; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.highExpB = mulAddRecFN_preMul_io_toPostMul.highExpB; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.isNaN_isQuietNaNB = mulAddRecFN_preMul_io_toPostMul.isNaN_isQuietNaNB; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.signProd = mulAddRecFN_preMul_io_toPostMul.signProd; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.isZeroProd = mulAddRecFN_preMul_io_toPostMul.isZeroProd; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.opSignC = mulAddRecFN_preMul_io_toPostMul.opSignC; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.highExpC = mulAddRecFN_preMul_io_toPostMul.highExpC; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.isNaN_isQuietNaNC = mulAddRecFN_preMul_io_toPostMul.isNaN_isQuietNaNC; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.isCDominant = mulAddRecFN_preMul_io_toPostMul.isCDominant; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.CAlignDist_0 = mulAddRecFN_preMul_io_toPostMul.CAlignDist_0; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.CAlignDist = mulAddRecFN_preMul_io_toPostMul.CAlignDist; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.bit0AlignedNegSigC = mulAddRecFN_preMul_io_toPostMul.bit0AlignedNegSigC; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.highAlignedNegSigC = mulAddRecFN_preMul_io_toPostMul.highAlignedNegSigC; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.sExpSum = mulAddRecFN_preMul_io_toPostMul.sExpSum; // MulAddRecFN.scala:598:15, :608:39
assign _io_fromPreMul_wire.roundingMode = mulAddRecFN_preMul_io_toPostMul.roundingMode; // MulAddRecFN.scala:598:15, :608:39
MulAddRecFN_preMul_1 mulAddRecFN_preMul ( // MulAddRecFN.scala:598:15
.clock (clock),
.reset (reset),
.io_op (io_op),
.io_a (io_a),
.io_b (io_b),
.io_c (io_c),
.io_roundingMode (io_roundingMode),
.io_mulAddA (mulAddRecFN_preMul_io_mulAddA),
.io_mulAddB (mulAddRecFN_preMul_io_mulAddB),
.io_mulAddC (mulAddRecFN_preMul_io_mulAddC),
.io_toPostMul (mulAddRecFN_preMul_io_toPostMul)
);
MulAddRecFN_postMul_1 mulAddRecFN_postMul ( // MulAddRecFN.scala:600:15
.clock (clock),
.reset (reset),
.io_fromPreMul (_io_fromPreMul_wire), // MulAddRecFN.scala:600:15
.io_mulAddResult ({1'h0, {53'h0, mulAddRecFN_preMul_io_mulAddA} * {53'h0, mulAddRecFN_preMul_io_mulAddB}} +
{1'h0, mulAddRecFN_preMul_io_mulAddC}), // Cat.scala:30:58, MulAddRecFN.scala:598:15, :610:{39,71}
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule
module DivSqrtRecF64_mulAddZ31( // ../perf/regress/FPU.fir:2974:10
input clock, reset, io_inValid, io_sqrtOp,
input [64:0] io_a, io_b,
input [1:0] io_roundingMode,
input [104:0] io_mulAddResult_3,
output io_inReady_div, io_inReady_sqrt, io_outValid_div, io_outValid_sqrt,
output [64:0] io_out,
output [4:0] io_exceptionFlags,
output [3:0] io_usingMulAdd,
output io_latchMulAddA_0,
output [53:0] io_mulAddA_0,
output io_latchMulAddB_0,
output [53:0] io_mulAddB_0,
output [104:0] io_mulAddC_2);
wire [53:0] _T; // DivSqrtRecF64_mulAddZ31.scala:716:12
wire [53:0] _T_0; // DivSqrtRecF64_mulAddZ31.scala:710:11
wire [45:0] _T_1; // DivSqrtRecF64_mulAddZ31.scala:702:22
wire _T_2; // DivSqrtRecF64_mulAddZ31.scala:481:27
wire _T_3; // DivSqrtRecF64_mulAddZ31.scala:458:27
wire _T_4; // DivSqrtRecF64_mulAddZ31.scala:457:27
wire _T_5; // DivSqrtRecF64_mulAddZ31.scala:456:27
wire _T_6; // DivSqrtRecF64_mulAddZ31.scala:447:27
wire _T_7; // DivSqrtRecF64_mulAddZ31.scala:444:39
wire _T_8; // DivSqrtRecF64_mulAddZ31.scala:443:39
wire _T_9; // DivSqrtRecF64_mulAddZ31.scala:442:39
wire _T_10; // DivSqrtRecF64_mulAddZ31.scala:439:26
wire _T_11; // DivSqrtRecF64_mulAddZ31.scala:437:38
wire _T_12; // DivSqrtRecF64_mulAddZ31.scala:432:27
wire _T_13; // DivSqrtRecF64_mulAddZ31.scala:431:27
wire _T_14; // DivSqrtRecF64_mulAddZ31.scala:426:33
wire _T_15; // DivSqrtRecF64_mulAddZ31.scala:382:28
wire _T_16; // DivSqrtRecF64_mulAddZ31.scala:322:28
wire _T_17; // DivSqrtRecF64_mulAddZ31.scala:284:28
reg valid_PA; // DivSqrtRecF64_mulAddZ31.scala:78:30
reg sqrtOp_PA; // DivSqrtRecF64_mulAddZ31.scala:79:30
reg sign_PA; // DivSqrtRecF64_mulAddZ31.scala:80:30
reg [2:0] specialCodeB_PA; // DivSqrtRecF64_mulAddZ31.scala:82:30
reg fractB_51_PA; // DivSqrtRecF64_mulAddZ31.scala:83:30
reg [1:0] roundingMode_PA; // DivSqrtRecF64_mulAddZ31.scala:84:30
reg [2:0] specialCodeA_PA; // DivSqrtRecF64_mulAddZ31.scala:85:30
reg fractA_51_PA; // DivSqrtRecF64_mulAddZ31.scala:86:30
reg [13:0] exp_PA; // DivSqrtRecF64_mulAddZ31.scala:87:30
reg [50:0] fractB_other_PA; // DivSqrtRecF64_mulAddZ31.scala:88:30
reg [50:0] fractA_other_PA; // DivSqrtRecF64_mulAddZ31.scala:89:30
reg valid_PB; // DivSqrtRecF64_mulAddZ31.scala:91:30
reg sqrtOp_PB; // DivSqrtRecF64_mulAddZ31.scala:92:30
reg sign_PB; // DivSqrtRecF64_mulAddZ31.scala:93:30
reg [2:0] specialCodeA_PB; // DivSqrtRecF64_mulAddZ31.scala:95:30
reg fractA_51_PB; // DivSqrtRecF64_mulAddZ31.scala:96:30
reg [2:0] specialCodeB_PB; // DivSqrtRecF64_mulAddZ31.scala:97:30
reg fractB_51_PB; // DivSqrtRecF64_mulAddZ31.scala:98:30
reg [1:0] roundingMode_PB; // DivSqrtRecF64_mulAddZ31.scala:99:30
reg [13:0] exp_PB; // DivSqrtRecF64_mulAddZ31.scala:100:30
reg fractA_0_PB; // DivSqrtRecF64_mulAddZ31.scala:101:30
reg [50:0] fractB_other_PB; // DivSqrtRecF64_mulAddZ31.scala:102:30
reg valid_PC; // DivSqrtRecF64_mulAddZ31.scala:104:30
reg sqrtOp_PC; // DivSqrtRecF64_mulAddZ31.scala:105:30
reg sign_PC; // DivSqrtRecF64_mulAddZ31.scala:106:30
reg [2:0] specialCodeA_PC; // DivSqrtRecF64_mulAddZ31.scala:108:30
reg fractA_51_PC; // DivSqrtRecF64_mulAddZ31.scala:109:30
reg [2:0] specialCodeB_PC; // DivSqrtRecF64_mulAddZ31.scala:110:30
reg fractB_51_PC; // DivSqrtRecF64_mulAddZ31.scala:111:30
reg [1:0] roundingMode_PC; // DivSqrtRecF64_mulAddZ31.scala:112:30
reg [13:0] exp_PC; // DivSqrtRecF64_mulAddZ31.scala:113:30
reg fractA_0_PC; // DivSqrtRecF64_mulAddZ31.scala:114:30
reg [50:0] fractB_other_PC; // DivSqrtRecF64_mulAddZ31.scala:115:30
reg [2:0] cycleNum_A; // DivSqrtRecF64_mulAddZ31.scala:117:30
reg [3:0] cycleNum_B; // DivSqrtRecF64_mulAddZ31.scala:118:30
reg [2:0] cycleNum_C; // DivSqrtRecF64_mulAddZ31.scala:119:30
reg [2:0] cycleNum_E; // DivSqrtRecF64_mulAddZ31.scala:120:30
reg [8:0] fractR0_A; // DivSqrtRecF64_mulAddZ31.scala:122:30
reg [9:0] hiSqrR0_A_sqrt; // DivSqrtRecF64_mulAddZ31.scala:124:30
reg [20:0] partNegSigma0_A; // DivSqrtRecF64_mulAddZ31.scala:125:30
reg [8:0] nextMulAdd9A_A; // DivSqrtRecF64_mulAddZ31.scala:126:30
reg [8:0] nextMulAdd9B_A; // DivSqrtRecF64_mulAddZ31.scala:127:30
reg [16:0] ER1_B_sqrt; // DivSqrtRecF64_mulAddZ31.scala:128:30
reg [31:0] ESqrR1_B_sqrt; // DivSqrtRecF64_mulAddZ31.scala:130:30
reg [57:0] sigX1_B; // DivSqrtRecF64_mulAddZ31.scala:131:30
reg [32:0] sqrSigma1_C; // DivSqrtRecF64_mulAddZ31.scala:132:30
reg [57:0] sigXN_C; // DivSqrtRecF64_mulAddZ31.scala:133:30
reg [30:0] u_C_sqrt; // DivSqrtRecF64_mulAddZ31.scala:134:30
reg E_E_div; // DivSqrtRecF64_mulAddZ31.scala:135:30
reg [52:0] sigT_E; // DivSqrtRecF64_mulAddZ31.scala:136:30
reg extraT_E; // DivSqrtRecF64_mulAddZ31.scala:137:30
reg isNegRemT_E; // DivSqrtRecF64_mulAddZ31.scala:138:30
reg isZeroRemT_E; // DivSqrtRecF64_mulAddZ31.scala:139:30
`ifndef SYNTHESIS // DivSqrtRecF64_mulAddZ31.scala:78:30
initial begin // DivSqrtRecF64_mulAddZ31.scala:78:30
automatic logic [31:0] _RANDOM; // DivSqrtRecF64_mulAddZ31.scala:78:30
automatic logic [31:0] _RANDOM_147; // DivSqrtRecF64_mulAddZ31.scala:88:30
automatic logic [31:0] _RANDOM_148; // DivSqrtRecF64_mulAddZ31.scala:89:30
automatic logic [31:0] _RANDOM_149; // DivSqrtRecF64_mulAddZ31.scala:102:30
automatic logic [31:0] _RANDOM_150; // DivSqrtRecF64_mulAddZ31.scala:113:30
automatic logic [31:0] _RANDOM_151; // DivSqrtRecF64_mulAddZ31.scala:115:30
automatic logic [31:0] _RANDOM_152; // DivSqrtRecF64_mulAddZ31.scala:117:30
automatic logic [31:0] _RANDOM_153; // DivSqrtRecF64_mulAddZ31.scala:125:30
automatic logic [31:0] _RANDOM_154; // DivSqrtRecF64_mulAddZ31.scala:127:30
automatic logic [31:0] _RANDOM_155; // DivSqrtRecF64_mulAddZ31.scala:130:30
automatic logic [31:0] _RANDOM_156; // DivSqrtRecF64_mulAddZ31.scala:131:30
automatic logic [31:0] _RANDOM_157; // DivSqrtRecF64_mulAddZ31.scala:132:30
automatic logic [31:0] _RANDOM_158; // DivSqrtRecF64_mulAddZ31.scala:133:30
automatic logic [31:0] _RANDOM_159; // DivSqrtRecF64_mulAddZ31.scala:134:30
automatic logic [31:0] _RANDOM_160; // DivSqrtRecF64_mulAddZ31.scala:136:30
`INIT_RANDOM_PROLOG_ // DivSqrtRecF64_mulAddZ31.scala:78:30
`ifdef RANDOMIZE_REG_INIT // DivSqrtRecF64_mulAddZ31.scala:78:30
_RANDOM = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:78:30
valid_PA = _RANDOM[0]; // DivSqrtRecF64_mulAddZ31.scala:78:30
sqrtOp_PA = _RANDOM[1]; // DivSqrtRecF64_mulAddZ31.scala:79:30
sign_PA = _RANDOM[2]; // DivSqrtRecF64_mulAddZ31.scala:80:30
specialCodeB_PA = _RANDOM[5:3]; // DivSqrtRecF64_mulAddZ31.scala:82:30
fractB_51_PA = _RANDOM[6]; // DivSqrtRecF64_mulAddZ31.scala:83:30
roundingMode_PA = _RANDOM[8:7]; // DivSqrtRecF64_mulAddZ31.scala:84:30
specialCodeA_PA = _RANDOM[11:9]; // DivSqrtRecF64_mulAddZ31.scala:85:30
fractA_51_PA = _RANDOM[12]; // DivSqrtRecF64_mulAddZ31.scala:86:30
exp_PA = _RANDOM[26:13]; // DivSqrtRecF64_mulAddZ31.scala:87:30
_RANDOM_147 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:88:30
fractB_other_PA = {_RANDOM[31:27], `RANDOM, _RANDOM_147[13:0]}; // DivSqrtRecF64_mulAddZ31.scala:88:30
_RANDOM_148 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:89:30
fractA_other_PA = {_RANDOM_147[31:14], `RANDOM, _RANDOM_148[0]}; // DivSqrtRecF64_mulAddZ31.scala:89:30
valid_PB = _RANDOM_148[1]; // DivSqrtRecF64_mulAddZ31.scala:91:30
sqrtOp_PB = _RANDOM_148[2]; // DivSqrtRecF64_mulAddZ31.scala:92:30
sign_PB = _RANDOM_148[3]; // DivSqrtRecF64_mulAddZ31.scala:93:30
specialCodeA_PB = _RANDOM_148[6:4]; // DivSqrtRecF64_mulAddZ31.scala:95:30
fractA_51_PB = _RANDOM_148[7]; // DivSqrtRecF64_mulAddZ31.scala:96:30
specialCodeB_PB = _RANDOM_148[10:8]; // DivSqrtRecF64_mulAddZ31.scala:97:30
fractB_51_PB = _RANDOM_148[11]; // DivSqrtRecF64_mulAddZ31.scala:98:30
roundingMode_PB = _RANDOM_148[13:12]; // DivSqrtRecF64_mulAddZ31.scala:99:30
exp_PB = _RANDOM_148[27:14]; // DivSqrtRecF64_mulAddZ31.scala:100:30
fractA_0_PB = _RANDOM_148[28]; // DivSqrtRecF64_mulAddZ31.scala:101:30
_RANDOM_149 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:102:30
fractB_other_PB = {_RANDOM_148[31:29], `RANDOM, _RANDOM_149[15:0]}; // DivSqrtRecF64_mulAddZ31.scala:102:30
valid_PC = _RANDOM_149[16]; // DivSqrtRecF64_mulAddZ31.scala:104:30
sqrtOp_PC = _RANDOM_149[17]; // DivSqrtRecF64_mulAddZ31.scala:105:30
sign_PC = _RANDOM_149[18]; // DivSqrtRecF64_mulAddZ31.scala:106:30
specialCodeA_PC = _RANDOM_149[21:19]; // DivSqrtRecF64_mulAddZ31.scala:108:30
fractA_51_PC = _RANDOM_149[22]; // DivSqrtRecF64_mulAddZ31.scala:109:30
specialCodeB_PC = _RANDOM_149[25:23]; // DivSqrtRecF64_mulAddZ31.scala:110:30
fractB_51_PC = _RANDOM_149[26]; // DivSqrtRecF64_mulAddZ31.scala:111:30
roundingMode_PC = _RANDOM_149[28:27]; // DivSqrtRecF64_mulAddZ31.scala:112:30
_RANDOM_150 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:113:30
exp_PC = {_RANDOM_149[31:29], _RANDOM_150[10:0]}; // DivSqrtRecF64_mulAddZ31.scala:113:30
fractA_0_PC = _RANDOM_150[11]; // DivSqrtRecF64_mulAddZ31.scala:114:30
_RANDOM_151 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:115:30
fractB_other_PC = {_RANDOM_150[31:12], _RANDOM_151[30:0]}; // DivSqrtRecF64_mulAddZ31.scala:115:30
_RANDOM_152 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:117:30
cycleNum_A = {_RANDOM_151[31], _RANDOM_152[1:0]}; // DivSqrtRecF64_mulAddZ31.scala:117:30
cycleNum_B = _RANDOM_152[5:2]; // DivSqrtRecF64_mulAddZ31.scala:118:30
cycleNum_C = _RANDOM_152[8:6]; // DivSqrtRecF64_mulAddZ31.scala:119:30
cycleNum_E = _RANDOM_152[11:9]; // DivSqrtRecF64_mulAddZ31.scala:120:30
fractR0_A = _RANDOM_152[20:12]; // DivSqrtRecF64_mulAddZ31.scala:122:30
hiSqrR0_A_sqrt = _RANDOM_152[30:21]; // DivSqrtRecF64_mulAddZ31.scala:124:30
_RANDOM_153 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:125:30
partNegSigma0_A = {_RANDOM_152[31], _RANDOM_153[19:0]}; // DivSqrtRecF64_mulAddZ31.scala:125:30
nextMulAdd9A_A = _RANDOM_153[28:20]; // DivSqrtRecF64_mulAddZ31.scala:126:30
_RANDOM_154 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:127:30
nextMulAdd9B_A = {_RANDOM_153[31:29], _RANDOM_154[5:0]}; // DivSqrtRecF64_mulAddZ31.scala:127:30
ER1_B_sqrt = _RANDOM_154[22:6]; // DivSqrtRecF64_mulAddZ31.scala:128:30
_RANDOM_155 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:130:30
ESqrR1_B_sqrt = {_RANDOM_154[31:23], _RANDOM_155[22:0]}; // DivSqrtRecF64_mulAddZ31.scala:130:30
_RANDOM_156 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:131:30
sigX1_B = {_RANDOM_155[31:23], `RANDOM, _RANDOM_156[16:0]}; // DivSqrtRecF64_mulAddZ31.scala:131:30
_RANDOM_157 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:132:30
sqrSigma1_C = {_RANDOM_156[31:17], _RANDOM_157[17:0]}; // DivSqrtRecF64_mulAddZ31.scala:132:30
_RANDOM_158 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:133:30
sigXN_C = {_RANDOM_157[31:18], `RANDOM, _RANDOM_158[11:0]}; // DivSqrtRecF64_mulAddZ31.scala:133:30
_RANDOM_159 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:134:30
u_C_sqrt = {_RANDOM_158[31:12], _RANDOM_159[10:0]}; // DivSqrtRecF64_mulAddZ31.scala:134:30
E_E_div = _RANDOM_159[11]; // DivSqrtRecF64_mulAddZ31.scala:135:30
_RANDOM_160 = `RANDOM; // DivSqrtRecF64_mulAddZ31.scala:136:30
sigT_E = {_RANDOM_159[31:12], `RANDOM, _RANDOM_160[0]}; // DivSqrtRecF64_mulAddZ31.scala:136:30
extraT_E = _RANDOM_160[1]; // DivSqrtRecF64_mulAddZ31.scala:137:30
isNegRemT_E = _RANDOM_160[2]; // DivSqrtRecF64_mulAddZ31.scala:138:30
isZeroRemT_E = _RANDOM_160[3]; // DivSqrtRecF64_mulAddZ31.scala:139:30
`endif
end // initial
`endif
wire _T_18 = _T_17 & ~_T_14 & ~_T_9 & ~_T_8 & ~_T_7 & ~_T_13 & ~_T_12 & ~_T_6 & ~_T_5 & ~_T_4; // DivSqrtRecF64_mulAddZ31.scala:197:{21,38,55}, :198:{13,30,42,54}, :199:{13,22,25}, :284:28, :426:33, :431:27, :432:27, :442:39, :443:39, :444:39, :447:27, :456:27, :457:27
wire _T_19 = _T_17 & ~_T_9 & ~_T_8 & ~_T_7 & ~_T_10 & ~_T_6; // DivSqrtRecF64_mulAddZ31.scala:197:{38,55}, :198:{13,54}, :202:{13,26}, :284:28, :439:26, :442:39, :443:39, :444:39, :447:27
wire _T_20 = _T_18 & io_inValid & ~io_sqrtOp; // DivSqrtRecF64_mulAddZ31.scala:203:{52,55}
wire _T_21 = _T_19 & io_inValid & io_sqrtOp; // DivSqrtRecF64_mulAddZ31.scala:204:52
wire _T_22 = _T_20 | _T_21; // DivSqrtRecF64_mulAddZ31.scala:205:27
wire [2:0] _io_a_63to61 = io_a[63:61]; // DivSqrtRecF64_mulAddZ31.scala:210:32
wire _io_b_64 = io_b[64]; // DivSqrtRecF64_mulAddZ31.scala:214:24
wire [2:0] _io_b_63to61 = io_b[63:61]; // DivSqrtRecF64_mulAddZ31.scala:217:32
wire _T_23 = io_b[63:62] != 2'h3; // DivSqrtRecF64_mulAddZ31.scala:212:46, :219:{39,46}
wire _T_24 = io_a[63:62] != 2'h3 & _T_23 & |_io_a_63to61 & |_io_b_63to61; // DivSqrtRecF64_mulAddZ31.scala:211:40, :212:{39,46}, :218:40, :224:57
wire _T_25 = _T_23 & |_io_b_63to61 & ~_io_b_64; // DivSqrtRecF64_mulAddZ31.scala:218:40, :225:{59,62}
wire _T_26 = _T_20 & _T_24; // DivSqrtRecF64_mulAddZ31.scala:228:50
wire _T_27 = _T_21 & _T_25; // DivSqrtRecF64_mulAddZ31.scala:229:50
wire _io_b_51 = io_b[51]; // DivSqrtRecF64_mulAddZ31.scala:247:36
wire _T_28 = specialCodeB_PA[2:1] != 2'h3; // DivSqrtRecF64_mulAddZ31.scala:212:46, :246:25, :271:{41,48}
wire _T_29 = sqrtOp_PA ? _T_28 & |specialCodeB_PA & ~sign_PA : specialCodeA_PA[2:1] != 2'h3 & _T_28 &
|specialCodeA_PA & |specialCodeB_PA; // DivSqrtRecF64_mulAddZ31.scala:212:46, :244:25, :245:25, :246:25, :251:25, :266:42, :267:{41,48}, :270:42, :275:12, :276:{45,48}, :277:64
wire _T_30 = _T_11 | _T_14; // DivSqrtRecF64_mulAddZ31.scala:280:50, :426:33, :437:38
wire _T_31 = _T_29 ? _T_30 : _T_16; // DivSqrtRecF64_mulAddZ31.scala:282:12, :322:28
wire _T_32 = valid_PA & _T_31; // DivSqrtRecF64_mulAddZ31.scala:233:55, :283:28
assign _T_17 = ~valid_PA | _T_31; // DivSqrtRecF64_mulAddZ31.scala:233:55, :235:36, :284:28
wire _T_33 = specialCodeB_PB[2:1] != 2'h3; // DivSqrtRecF64_mulAddZ31.scala:212:46, :298:25, :311:{41,48}
wire _T_34 = sqrtOp_PB ? _T_33 & |specialCodeB_PB & ~sign_PB : specialCodeA_PB[2:1] != 2'h3 & _T_33 &
|specialCodeA_PB & |specialCodeB_PB; // DivSqrtRecF64_mulAddZ31.scala:212:46, :294:25, :295:25, :296:25, :298:25, :308:42, :309:{41,48}, :310:42, :313:12, :314:{45,48}, :315:64
wire _T_35 = _T_34 ? _T_3 : _T_15; // DivSqrtRecF64_mulAddZ31.scala:320:12, :382:28, :458:27
wire _T_36 = valid_PB & _T_35; // DivSqrtRecF64_mulAddZ31.scala:236:29, :321:28
assign _T_16 = ~valid_PB | _T_35; // DivSqrtRecF64_mulAddZ31.scala:236:29, :322:28
wire [1:0] _specialCodeA_PC_2to1 = specialCodeA_PC[2:1]; // DivSqrtRecF64_mulAddZ31.scala:334:25, :347:41
wire _specialCodeA_PC_0 = specialCodeA_PC[0]; // DivSqrtRecF64_mulAddZ31.scala:334:25, :348:59
wire _T_37 = &_specialCodeA_PC_2to1 & ~_specialCodeA_PC_0; // DivSqrtRecF64_mulAddZ31.scala:347:48, :348:{39,42}
wire _T_38 = &_specialCodeA_PC_2to1 & _specialCodeA_PC_0; // DivSqrtRecF64_mulAddZ31.scala:347:48, :349:39
wire [1:0] _specialCodeB_PC_2to1 = specialCodeB_PC[2:1]; // DivSqrtRecF64_mulAddZ31.scala:336:25, :353:41
wire _specialCodeB_PC_0 = specialCodeB_PC[0]; // DivSqrtRecF64_mulAddZ31.scala:336:25, :354:59
wire _T_39 = &_specialCodeB_PC_2to1 & ~_specialCodeB_PC_0; // DivSqrtRecF64_mulAddZ31.scala:353:48, :354:{39,42}
wire _T_40 = &_specialCodeB_PC_2to1 & _specialCodeB_PC_0; // DivSqrtRecF64_mulAddZ31.scala:353:48, :355:39
wire _T_41 = sqrtOp_PC ? ~(&_specialCodeB_PC_2to1) & |specialCodeB_PC & ~sign_PC :
~(&_specialCodeA_PC_2to1) & ~(&_specialCodeB_PC_2to1) & |specialCodeA_PC & |specialCodeB_PC; // DivSqrtRecF64_mulAddZ31.scala:332:25, :333:25, :334:25, :336:25, :346:42, :347:48, :352:42, :353:48, :360:{12,24,56,59}, :361:{13,64}
wire [13:0] _T_42 = exp_PC + 14'h2; // DivSqrtRecF64_mulAddZ31.scala:341:25, :363:27
wire _exp_PC_0 = exp_PC[0]; // DivSqrtRecF64_mulAddZ31.scala:341:25, :365:19
wire [12:0] _T_43 = _T_42[13:1]; // DivSqrtRecF64_mulAddZ31.scala:366:25
wire [12:0] _exp_PC_13to1 = exp_PC[13:1]; // DivSqrtRecF64_mulAddZ31.scala:341:25, :367:23
wire [13:0] _T_44 = _exp_PC_0 ? {_T_43, 1'h0} : {_exp_PC_13to1, 1'h1}; // Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:78:30, :365:12
wire _T_45 = sign_PC ? roundingMode_PC == 2'h2 : &roundingMode_PC; // DivSqrtRecF64_mulAddZ31.scala:333:25, :338:25, :363:27, :372:54, :373:54, :376:12
wire _T_46 = ~(|roundingMode_PC) | _T_45; // DivSqrtRecF64_mulAddZ31.scala:338:25, :370:54, :377:61
wire _T_47 = ~_T_41 | _T_2; // DivSqrtRecF64_mulAddZ31.scala:380:{28,44}, :481:27
wire _T_48 = valid_PC & _T_47; // DivSqrtRecF64_mulAddZ31.scala:329:18, :381:28
assign _T_15 = ~valid_PC | _T_47; // DivSqrtRecF64_mulAddZ31.scala:329:18, :382:{17,28}
wire _T_49 = cycleNum_A == 3'h6; // DivSqrtRecF64_mulAddZ31.scala:388:49, :391:16, :396:35
wire _T_50 = cycleNum_A == 3'h5; // DivSqrtRecF64_mulAddZ31.scala:388:49, :397:35
wire _T_51 = cycleNum_A == 3'h4; // DivSqrtRecF64_mulAddZ31.scala:388:49, :398:35
wire _T_52 = _T_51 | _T_26; // DivSqrtRecF64_mulAddZ31.scala:402:30
wire _T_53 = cycleNum_A == 3'h3; // DivSqrtRecF64_mulAddZ31.scala:388:49, :403:30, :827:59
wire _T_54 = cycleNum_A == 3'h2; // DivSqrtRecF64_mulAddZ31.scala:388:49, :404:30
wire _T_55 = cycleNum_A == 3'h1; // DivSqrtRecF64_mulAddZ31.scala:388:49, :405:30
wire _T_56 = _T_53 & ~sqrtOp_PA; // DivSqrtRecF64_mulAddZ31.scala:244:25, :407:{29,32}
wire _T_57 = _T_55 & ~sqrtOp_PA; // DivSqrtRecF64_mulAddZ31.scala:244:25, :407:32, :409:29
wire _T_58 = _T_55 & sqrtOp_PA; // DivSqrtRecF64_mulAddZ31.scala:244:25, :413:30
wire _T_59 = cycleNum_B == 4'h9; // DivSqrtRecF64_mulAddZ31.scala:415:33, :424:33
wire _T_60 = cycleNum_B == 4'h8; // DivSqrtRecF64_mulAddZ31.scala:415:33, :425:33
assign _T_14 = cycleNum_B == 4'h7; // DivSqrtRecF64_mulAddZ31.scala:415:33, :426:33
wire _T_61 = cycleNum_B == 4'h6; // DivSqrtRecF64_mulAddZ31.scala:415:33, :418:20, :428:27
wire _T_62 = cycleNum_B == 4'h5; // DivSqrtRecF64_mulAddZ31.scala:415:33, :429:27
wire _T_63 = cycleNum_B == 4'h4; // DivSqrtRecF64_mulAddZ31.scala:415:33, :430:27
assign _T_13 = cycleNum_B == 4'h3; // DivSqrtRecF64_mulAddZ31.scala:415:33, :431:27
assign _T_12 = cycleNum_B == 4'h2; // DivSqrtRecF64_mulAddZ31.scala:415:33, :432:27
wire _T_64 = cycleNum_B == 4'h1; // DivSqrtRecF64_mulAddZ31.scala:392:54, :415:33, :433:27
wire _T_65 = _T_61 & valid_PA & ~sqrtOp_PA; // DivSqrtRecF64_mulAddZ31.scala:233:55, :244:25, :407:32, :435:38
assign _T_11 = _T_63 & valid_PA & ~sqrtOp_PA; // DivSqrtRecF64_mulAddZ31.scala:233:55, :244:25, :407:32, :437:38
assign _T_10 = _T_12 & ~sqrtOp_PB; // DivSqrtRecF64_mulAddZ31.scala:294:25, :432:27, :438:29, :439:26
assign _T_9 = _T_61 & valid_PB & sqrtOp_PB; // DivSqrtRecF64_mulAddZ31.scala:236:29, :294:25, :442:39
assign _T_8 = _T_62 & valid_PB & sqrtOp_PB; // DivSqrtRecF64_mulAddZ31.scala:236:29, :294:25, :443:39
assign _T_7 = _T_63 & valid_PB & sqrtOp_PB; // DivSqrtRecF64_mulAddZ31.scala:236:29, :294:25, :444:39
wire _T_66 = _T_13 & sqrtOp_PB; // DivSqrtRecF64_mulAddZ31.scala:294:25, :431:27, :445:27
wire _T_67 = _T_12 & sqrtOp_PB; // DivSqrtRecF64_mulAddZ31.scala:294:25, :432:27, :446:27
assign _T_6 = _T_64 & sqrtOp_PB; // DivSqrtRecF64_mulAddZ31.scala:294:25, :447:27
wire _T_68 = cycleNum_C == 3'h6; // DivSqrtRecF64_mulAddZ31.scala:391:16, :449:33, :454:35
assign _T_5 = cycleNum_C == 3'h5; // DivSqrtRecF64_mulAddZ31.scala:397:35, :449:33, :456:27
assign _T_4 = cycleNum_C == 3'h4; // DivSqrtRecF64_mulAddZ31.scala:398:35, :449:33, :457:27
assign _T_3 = cycleNum_C == 3'h3; // DivSqrtRecF64_mulAddZ31.scala:449:33, :458:27, :827:59
wire _T_69 = cycleNum_C == 3'h2; // DivSqrtRecF64_mulAddZ31.scala:404:30, :449:33, :459:27
wire _T_70 = cycleNum_C == 3'h1; // DivSqrtRecF64_mulAddZ31.scala:405:30, :449:33, :460:27
wire _T_71 = _T_70 & ~sqrtOp_PC; // DivSqrtRecF64_mulAddZ31.scala:332:25, :383:39, :466:29
wire _T_72 = _T_4 & sqrtOp_PB; // DivSqrtRecF64_mulAddZ31.scala:294:25, :457:27, :469:30
wire _T_73 = _T_70 & sqrtOp_PC; // DivSqrtRecF64_mulAddZ31.scala:332:25, :472:30
wire _T_74 = cycleNum_E == 3'h3; // DivSqrtRecF64_mulAddZ31.scala:474:33, :479:27, :827:59
assign _T_2 = cycleNum_E == 3'h1; // DivSqrtRecF64_mulAddZ31.scala:405:30, :474:33, :481:27
wire [13:0] _T_75 = _T_26 ? io_b[48:35] : 14'h0; // DivSqrtRecF64_mulAddZ31.scala:496:29, :592:12
wire [2:0] _io_b_51to49 = io_b[51:49]; // DivSqrtRecF64_mulAddZ31.scala:498:53
wire _T_76 = _T_26 & _io_b_51to49 == 3'h0; // DivSqrtRecF64_mulAddZ31.scala:117:30, :498:{41,62}
wire _T_77 = _T_26 & _io_b_51to49 == 3'h1; // DivSqrtRecF64_mulAddZ31.scala:405:30, :499:{41,62}
wire _T_78 = _T_26 & _io_b_51to49 == 3'h2; // DivSqrtRecF64_mulAddZ31.scala:404:30, :500:{41,62}
wire _T_79 = _T_26 & _io_b_51to49 == 3'h3; // DivSqrtRecF64_mulAddZ31.scala:501:{41,62}, :827:59
wire _T_80 = _T_26 & _io_b_51to49 == 3'h4; // DivSqrtRecF64_mulAddZ31.scala:398:35, :502:{41,62}
wire _T_81 = _T_26 & _io_b_51to49 == 3'h5; // DivSqrtRecF64_mulAddZ31.scala:397:35, :503:{41,62}
wire _T_82 = _T_26 & _io_b_51to49 == 3'h6; // DivSqrtRecF64_mulAddZ31.scala:391:16, :504:{41,62}
wire _T_83 = _T_26 & &_io_b_51to49; // DivSqrtRecF64_mulAddZ31.scala:505:{41,62}
wire [8:0] _T_84 = _T_27 ? io_b[50:42] : 9'h0; // DivSqrtRecF64_mulAddZ31.scala:507:12, :525:30
wire _io_b_52 = io_b[52]; // DivSqrtRecF64_mulAddZ31.scala:527:55
wire _T_85 = _T_27 & ~_io_b_52; // DivSqrtRecF64_mulAddZ31.scala:527:{44,47}
wire _T_86 = _T_85 & ~_io_b_51; // DivSqrtRecF64_mulAddZ31.scala:527:{59,62}
wire _T_87 = _T_85 & _io_b_51; // DivSqrtRecF64_mulAddZ31.scala:528:59
wire _T_88 = _T_27 & _io_b_52; // DivSqrtRecF64_mulAddZ31.scala:529:44
wire _T_89 = _T_88 & ~_io_b_51; // DivSqrtRecF64_mulAddZ31.scala:527:62, :529:59
wire _T_90 = _T_88 & _io_b_51; // DivSqrtRecF64_mulAddZ31.scala:530:59
wire _exp_PA_0 = exp_PA[0]; // DivSqrtRecF64_mulAddZ31.scala:255:16, :542:55
wire _T_91 = _T_49 & ~_exp_PA_0; // DivSqrtRecF64_mulAddZ31.scala:542:{44,47}
wire _T_92 = _T_49 & _exp_PA_0; // DivSqrtRecF64_mulAddZ31.scala:544:44
wire [19:0] _T_93 = {(_T_86 ? 10'h2F : 10'h0) | (_T_87 ? 10'h1DF : 10'h0) | (_T_89 ? 10'h14D : 10'h0) | (_T_90
? 10'h27E : 10'h0), {10{_T_27}}} | {_T_49, (_T_91 & ~fractB_51_PA ? 13'h1A : 13'h0) |
(_T_91 & fractB_51_PA ? 13'hBCA : 13'h0) | (_T_92 & ~fractB_51_PA ? 13'h12D3 : 13'h0) |
(_T_92 & fractB_51_PA ? 13'h1B17 : 13'h0), {6{_T_49}}}; // Bitwise.scala:71:12, Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:247:25, :537:{12,35}, :538:{12,35}, :539:{12,35,63}, :540:{12,35}, :542:{59,62}, :543:59, :544:59, :545:59, :547:{12,35}, :548:{12,35}, :549:{12,35,64}, :550:{12,35}, :559:71
wire [19:0] _T_94 = _T_50 ? {1'h0, fractR0_A, 10'h0} + 20'h40000 : 20'h0; // DivSqrtRecF64_mulAddZ31.scala:78:30, :537:12, :563:{12,42,54}
wire [11:0] _T_95 = _T_93[19:8] | (_T_76 ? 12'h1C : 12'h0) | (_T_77 ? 12'h3A2 : 12'h0) | (_T_78 ? 12'h675 :
12'h0) | (_T_79 ? 12'h8C6 : 12'h0) | (_T_80 ? 12'hAB4 : 12'h0) | (_T_81 ? 12'hC56 : 12'h0)
| (_T_82 ? 12'hDBD : 12'h0) | (_T_83 ? 12'hEF4 : 12'h0) | _T_94[19:8]; // DivSqrtRecF64_mulAddZ31.scala:516:{12,33}, :517:{12,33}, :518:{12,33}, :519:{12,33}, :520:{12,33}, :521:{12,33}, :522:{12,33}, :523:{12,33}, :560:71, :561:71
wire _hiSqrR0_A_sqrt_9 = hiSqrR0_A_sqrt[9]; // DivSqrtRecF64_mulAddZ31.scala:564:44
wire [23:0] _T_96 = _T_57 ? {fractR0_A, 15'h0} : 24'h0; // DivSqrtRecF64_mulAddZ31.scala:563:54, :571:{12,45}, :583:12
wire [24:0] _T_97 = (_T_58 ? {fractR0_A, 16'h0} : 25'h0) | {1'h0, _T_96[23:21], {_T_26, _T_95[11:3], _T_95[2] |
_T_51 & ~_hiSqrR0_A_sqrt_9, _T_95[1:0], _T_93[7:0] | {8{_T_26}} | _T_94[7:0]} | (_T_51 &
_hiSqrR0_A_sqrt_9 | _T_56 ? fractB_other_PA[46:26] + 21'h400 : 21'h0) | (_T_53 & sqrtOp_PA
| _T_54 ? partNegSigma0_A : 21'h0) | _T_96[20:0]}; // Bitwise.scala:71:12, DivSqrtRecF64_mulAddZ31.scala:78:30, :244:25, :260:25, :411:30, :560:71, :561:71, :563:{54,70}, :564:{25,28}, :565:{12,26,48}, :566:{20,29}, :569:{12,25}, :570:{12,45,62}
wire [18:0] _T_98 = {1'h0, {9'h0, _T_75[13:5] | (_T_86 ? 9'h1C8 : 9'h0) | (_T_87 ? 9'hC1 : 9'h0) | (_T_89 ?
9'h143 : 9'h0) | (_T_90 ? 9'h89 : 9'h0) | (_T_22 ? 9'h0 : nextMulAdd9A_A)} * {9'h0, (_T_76
? 9'h1C7 : 9'h0) | (_T_77 ? 9'h16C : 9'h0) | (_T_78 ? 9'h12A : 9'h0) | (_T_79 ? 9'hF8 :
9'h0) | (_T_80 ? 9'hD2 : 9'h0) | (_T_81 ? 9'hB4 : 9'h0) | (_T_82 ? 9'h9C : 9'h0) | (_T_83 ?
9'h89 : 9'h0) | _T_84 | (_T_22 ? 9'h0 : nextMulAdd9B_A)}} + {1'h0, _T_97[17:0]}; // DivSqrtRecF64_mulAddZ31.scala:78:30, :507:12, :508:12, :509:12, :510:12, :511:12, :512:12, :513:12, :514:12, :532:12, :533:12, :534:12, :535:12, :553:{23,46}, :554:16, :556:46, :557:16, :573:{20,33,61}
wire [6:0] _T_99 = _T_97[24:18]; // DivSqrtRecF64_mulAddZ31.scala:576:27
wire [6:0] _T_100 = _T_98[18] ? _T_99 + 7'h1 : _T_99; // DivSqrtRecF64_mulAddZ31.scala:575:{16,31}, :576:36
wire [8:0] _T_101 = _T_98[17:9]; // DivSqrtRecF64_mulAddZ31.scala:601:54
wire [14:0] _T_102 = sqrtOp_PA ? {_T_100, _T_98[17:10]} : {_T_100[5:0], _T_101}; // DivSqrtRecF64_mulAddZ31.scala:244:25, :601:{12,36}
wire [16:0] _T_103 = _exp_PA_0 ? {1'h1, _T_102, 1'h0} : {2'h1, _T_102}; // Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:78:30, :603:{26,43}
wire _T_104 = _T_55 | _T_14; // DivSqrtRecF64_mulAddZ31.scala:426:33, :647:16
wire _T_105 = _T_104 | _T_65 | _T_63 | _T_13 | _T_68 | _T_4 | _T_70; // DivSqrtRecF64_mulAddZ31.scala:431:27, :457:27, :648:35
wire [45:0] _T_106 = _T_13 | _T_68 ? io_mulAddResult_3[104:59] : 46'h0; // DivSqrtRecF64_mulAddZ31.scala:431:27, :655:{12,20,48}
wire [45:0] _T_107 = _T_4 & ~sqrtOp_PB ? {sigXN_C[57:25], 13'h0} : 46'h0; // DivSqrtRecF64_mulAddZ31.scala:294:25, :438:29, :457:27, :463:29, :547:12, :655:12, :656:{12,43,51}
wire [45:0] _T_108 = _T_72 ? {u_C_sqrt, 15'h0} : 46'h0; // DivSqrtRecF64_mulAddZ31.scala:583:12, :655:12, :657:{12,44}
wire [51:0] _T_109 = (_T_55 ? {1'h1, _T_102, 36'h0} : 52'h0) | {1'h0, _T_14 ? {ESqrR1_B_sqrt, 19'h0} : 51'h0}; // Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:78:30, :426:33, :496:29, :650:51, :652:67, :664:{12,31,55}, :665:{12,39}
wire [45:0] _T_110 = _T_109[45:0] | _T_1; // DivSqrtRecF64_mulAddZ31.scala:666:55, :702:22
wire [32:0] _T_111 = _T_4 ? sqrSigma1_C : 33'h0; // DivSqrtRecF64_mulAddZ31.scala:457:27, :668:37, :669:12
wire [103:0] _T_112 = _T_68 ? {sigX1_B, 46'h0} : 104'h0; // DivSqrtRecF64_mulAddZ31.scala:655:12, :688:45, :689:{12,45}
wire _fractB_other_PC_0 = fractB_other_PC[0]; // DivSqrtRecF64_mulAddZ31.scala:343:25, :694:29
assign _T_1 = _T_63 ? ~(io_mulAddResult_3[90:45]) : 46'h0; // DivSqrtRecF64_mulAddZ31.scala:655:12, :702:{22,31,49}
wire _io_mulAddResult_3_104 = io_mulAddResult_3[104]; // DivSqrtRecF64_mulAddZ31.scala:705:39
wire [53:0] _io_mulAddResult_3_104to51 = io_mulAddResult_3[104:51]; // DivSqrtRecF64_mulAddZ31.scala:708:31
assign _T_0 = (_T_71 & _io_mulAddResult_3_104 | _T_73 ? ~_io_mulAddResult_3_104to51 : 54'h0) | (_T_71 &
~_io_mulAddResult_3_104 ? {1'h0, ~(io_mulAddResult_3[102:50])} : 54'h0); // Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:78:30, :691:12, :705:20, :707:{12,25,40}, :708:13, :710:11, :711:{12,24}, :712:{29,47}
assign _T = _T_73 ? ~_io_mulAddResult_3_104to51 : 54'h0; // DivSqrtRecF64_mulAddZ31.scala:691:12, :708:13, :716:12
always @(posedge clock) begin // DivSqrtRecF64_mulAddZ31.scala:244:25
automatic logic _T_161 = ~io_sqrtOp & io_a[64] ^ _io_b_64; // DivSqrtRecF64_mulAddZ31.scala:207:24, :221:21
automatic logic _T_162 = _T_26 | _T_27; // DivSqrtRecF64_mulAddZ31.scala:231:36
automatic logic _T_163 = _T_162 | _T_22 & (valid_PA | ~_T_16); // DivSqrtRecF64_mulAddZ31.scala:233:{32,42,55,58}, :322:28
automatic logic _T_164 = _T_22 & ~(io_sqrtOp ? _T_25 : _T_24) & ~valid_PA; // DivSqrtRecF64_mulAddZ31.scala:226:27, :233:55, :235:{18,33,36}
automatic logic _T_165 = _T_163 & ~io_sqrtOp; // DivSqrtRecF64_mulAddZ31.scala:203:55, :250:23
automatic logic _io_a_51 = io_a[51]; // DivSqrtRecF64_mulAddZ31.scala:252:36
automatic logic _T_166 = valid_PA & _T_29 & _T_30; // DivSqrtRecF64_mulAddZ31.scala:233:55, :287:35
automatic logic _T_167 = _T_164 & (_T_36 | ~valid_PB & ~_T_15) | _T_32; // DivSqrtRecF64_mulAddZ31.scala:235:47, :236:{25,29,40,43}, :288:37, :382:28
automatic logic _T_168 = valid_PB & _T_34 & _T_3; // DivSqrtRecF64_mulAddZ31.scala:236:29, :325:35, :458:27
automatic logic _T_169 = _T_164 & ~valid_PB & _T_15 | _T_36; // DivSqrtRecF64_mulAddZ31.scala:236:29, :238:61, :326:37, :382:28
automatic logic _T_170 = cycleNum_E == 3'h2; // DivSqrtRecF64_mulAddZ31.scala:404:30, :474:33, :480:27
automatic logic [17:0] _T_171 = _T_98[17:0]; // DivSqrtRecF64_mulAddZ31.scala:579:27
automatic logic [17:0] _T_172 = ~{_T_100[1:0], _T_98[17:2]}; // DivSqrtRecF64_mulAddZ31.scala:584:13
automatic logic [8:0] _T_173 = _T_49 & _T_100[1] ? _T_172[16:8] : 9'h0; // DivSqrtRecF64_mulAddZ31.scala:507:12, :583:{12,25,40}
automatic logic [18:0] _T_174 = _exp_PA_0 ? {_T_100[0], _T_171} : {_T_100[1:0], _T_98[17:1]}; // DivSqrtRecF64_mulAddZ31.scala:590:28
automatic logic [8:0] _T_175 = _T_26 & _T_100[2] ? _T_172[17:9] : 9'h0; // DivSqrtRecF64_mulAddZ31.scala:507:12, :592:{12,24,39}
automatic logic _T_176 = _T_27 | _T_49 | _T_50 | _T_52; // DivSqrtRecF64_mulAddZ31.scala:620:51
automatic logic [57:0] _io_mulAddResult_3_104to47 = io_mulAddResult_3[104:47]; // DivSqrtRecF64_mulAddZ31.scala:704:38
automatic logic [53:0] _T_177 = ~_T_0; // DivSqrtRecF64_mulAddZ31.scala:710:11, :720:19
if (reset) begin // DivSqrtRecF64_mulAddZ31.scala:78:30
valid_PA <= 1'h0; // DivSqrtRecF64_mulAddZ31.scala:78:30
valid_PB <= 1'h0; // DivSqrtRecF64_mulAddZ31.scala:78:30, :91:30
valid_PC <= 1'h0; // DivSqrtRecF64_mulAddZ31.scala:78:30, :104:30
cycleNum_A <= 3'h0; // DivSqrtRecF64_mulAddZ31.scala:117:30
cycleNum_B <= 4'h0; // DivSqrtRecF64_mulAddZ31.scala:118:30
cycleNum_C <= 3'h0; // DivSqrtRecF64_mulAddZ31.scala:117:30, :119:30
cycleNum_E <= 3'h0; // DivSqrtRecF64_mulAddZ31.scala:117:30, :120:30
end
else begin // DivSqrtRecF64_mulAddZ31.scala:78:30
valid_PA <= _T_163 | _T_32 ? _T_163 : valid_PA; // DivSqrtRecF64_mulAddZ31.scala:233:55, :240:23, :241:18
valid_PB <= _T_167 | _T_36 ? _T_167 : valid_PB; // DivSqrtRecF64_mulAddZ31.scala:236:29, :290:23, :291:18
valid_PC <= _T_169 | _T_48 ? _T_169 : valid_PC; // DivSqrtRecF64_mulAddZ31.scala:328:23, :329:18
cycleNum_A <= _T_162 | |cycleNum_A ? {1'h0, {2{_T_26}}} | (_T_27 ? 3'h6 : 3'h0) | (_T_162 ? 3'h0 :
cycleNum_A - 3'h1) : cycleNum_A; // DivSqrtRecF64_mulAddZ31.scala:78:30, :117:30, :388:{34,49}, :389:20, :390:{16,74}, :391:{16,74}, :392:{16,54}
cycleNum_B <= _T_55 | |cycleNum_B ? (_T_55 ? (sqrtOp_PA ? 4'hA : 4'h6) : cycleNum_B - 4'h1) : cycleNum_B; // DivSqrtRecF64_mulAddZ31.scala:244:25, :415:{18,33}, :416:20, :417:16, :418:20, :419:28
cycleNum_C <= _T_64 | |cycleNum_C ? (_T_64 ? (sqrtOp_PB ? 3'h6 : 3'h5) : cycleNum_C - 3'h1) : cycleNum_C; // DivSqrtRecF64_mulAddZ31.scala:294:25, :391:16, :397:35, :449:{18,33}, :450:20, :451:{16,28,70}
cycleNum_E <= _T_70 | |cycleNum_E ? (_T_70 ? 3'h4 : cycleNum_E - 3'h1) : cycleNum_E; // DivSqrtRecF64_mulAddZ31.scala:398:35, :474:{18,33}, :475:{20,26,55}
end
sqrtOp_PA <= _T_163 ? io_sqrtOp : sqrtOp_PA; // DivSqrtRecF64_mulAddZ31.scala:244:25
sign_PA <= _T_163 ? _T_161 : sign_PA; // DivSqrtRecF64_mulAddZ31.scala:245:25
specialCodeB_PA <= _T_163 ? _io_b_63to61 : specialCodeB_PA; // DivSqrtRecF64_mulAddZ31.scala:246:25
fractB_51_PA <= _T_163 ? _io_b_51 : fractB_51_PA; // DivSqrtRecF64_mulAddZ31.scala:247:25
roundingMode_PA <= _T_163 ? io_roundingMode : roundingMode_PA; // DivSqrtRecF64_mulAddZ31.scala:248:25
specialCodeA_PA <= _T_165 ? _io_a_63to61 : specialCodeA_PA; // DivSqrtRecF64_mulAddZ31.scala:251:25
fractA_51_PA <= _T_165 ? _io_a_51 : fractA_51_PA; // DivSqrtRecF64_mulAddZ31.scala:252:25
exp_PA <= _T_162 ? (io_sqrtOp ? {2'h0, io_b[63:52]} : {2'h0, io_a[63:52]} + {{3{io_b[63]}},
~(io_b[62:52])}) : exp_PA; // Bitwise.scala:71:12, DivSqrtRecF64_mulAddZ31.scala:208:24, :215:24, :255:16, :256:16, :258:{24,44,51,58}, :390:16
fractB_other_PA <= _T_162 ? io_b[50:0] : fractB_other_PA; // DivSqrtRecF64_mulAddZ31.scala:260:{25,36}
fractA_other_PA <= _T_26 ? io_a[50:0] : fractA_other_PA; // DivSqrtRecF64_mulAddZ31.scala:263:{25,36}
sqrtOp_PB <= _T_167 ? (valid_PA ? sqrtOp_PA : io_sqrtOp) : sqrtOp_PB; // DivSqrtRecF64_mulAddZ31.scala:233:55, :244:25, :294:{25,31}
sign_PB <= _T_167 ? (valid_PA ? sign_PA : _T_161) : sign_PB; // DivSqrtRecF64_mulAddZ31.scala:233:55, :245:25, :295:{25,31}
specialCodeA_PB <= _T_167 ? (valid_PA ? specialCodeA_PA : _io_a_63to61) : specialCodeA_PB; // DivSqrtRecF64_mulAddZ31.scala:233:55, :251:25, :296:{25,31}
fractA_51_PB <= _T_167 ? (valid_PA ? fractA_51_PA : _io_a_51) : fractA_51_PB; // DivSqrtRecF64_mulAddZ31.scala:233:55, :252:25, :297:{25,31}
specialCodeB_PB <= _T_167 ? (valid_PA ? specialCodeB_PA : _io_b_63to61) : specialCodeB_PB; // DivSqrtRecF64_mulAddZ31.scala:233:55, :246:25, :298:{25,31}
fractB_51_PB <= _T_167 ? (valid_PA ? fractB_51_PA : _io_b_51) : fractB_51_PB; // DivSqrtRecF64_mulAddZ31.scala:233:55, :247:25, :299:{25,31}
roundingMode_PB <= _T_167 ? (valid_PA ? roundingMode_PA : io_roundingMode) : roundingMode_PB; // DivSqrtRecF64_mulAddZ31.scala:233:55, :248:25, :300:{25,31}
exp_PB <= _T_166 ? exp_PA : exp_PB; // DivSqrtRecF64_mulAddZ31.scala:255:16, :303:25
fractA_0_PB <= _T_166 ? fractA_other_PA[0] : fractA_0_PB; // DivSqrtRecF64_mulAddZ31.scala:263:25, :304:{25,43}
fractB_other_PB <= _T_166 ? fractB_other_PA : fractB_other_PB; // DivSqrtRecF64_mulAddZ31.scala:260:25, :305:25
sqrtOp_PC <= _T_169 ? (valid_PB ? sqrtOp_PB : io_sqrtOp) : sqrtOp_PC; // DivSqrtRecF64_mulAddZ31.scala:236:29, :294:25, :332:{25,31}
sign_PC <= _T_169 ? (valid_PB ? sign_PB : _T_161) : sign_PC; // DivSqrtRecF64_mulAddZ31.scala:236:29, :295:25, :333:{25,31}
specialCodeA_PC <= _T_169 ? (valid_PB ? specialCodeA_PB : _io_a_63to61) : specialCodeA_PC; // DivSqrtRecF64_mulAddZ31.scala:236:29, :296:25, :334:{25,31}
fractA_51_PC <= _T_169 ? (valid_PB ? fractA_51_PB : _io_a_51) : fractA_51_PC; // DivSqrtRecF64_mulAddZ31.scala:236:29, :297:25, :335:{25,31}
specialCodeB_PC <= _T_169 ? (valid_PB ? specialCodeB_PB : _io_b_63to61) : specialCodeB_PC; // DivSqrtRecF64_mulAddZ31.scala:236:29, :298:25, :336:{25,31}
fractB_51_PC <= _T_169 ? (valid_PB ? fractB_51_PB : _io_b_51) : fractB_51_PC; // DivSqrtRecF64_mulAddZ31.scala:236:29, :299:25, :337:{25,31}
roundingMode_PC <= _T_169 ? (valid_PB ? roundingMode_PB : io_roundingMode) : roundingMode_PC; // DivSqrtRecF64_mulAddZ31.scala:236:29, :300:25, :338:{25,31}
exp_PC <= _T_168 ? exp_PB : exp_PC; // DivSqrtRecF64_mulAddZ31.scala:303:25, :341:25
fractA_0_PC <= _T_168 ? fractA_0_PB : fractA_0_PC; // DivSqrtRecF64_mulAddZ31.scala:304:25, :342:25
fractB_other_PC <= _T_168 ? fractB_other_PB : fractB_other_PC; // DivSqrtRecF64_mulAddZ31.scala:305:25, :343:25
fractR0_A <= _T_49 | _T_26 ? _T_173 | _T_175 : fractR0_A; // DivSqrtRecF64_mulAddZ31.scala:563:54, :605:23, :606:{19,39}
hiSqrR0_A_sqrt <= _T_50 ? _T_174[18:9] : hiSqrR0_A_sqrt; // DivSqrtRecF64_mulAddZ31.scala:564:44, :610:24
partNegSigma0_A <= _T_51 | _T_53 ? (_T_51 ? {_T_100[2:0], _T_171} : {5'h0, _T_100, _T_101}) : partNegSigma0_A; // DivSqrtRecF64_mulAddZ31.scala:569:12, :613:23, :615:25, :616:16, :623:68
nextMulAdd9A_A <= _T_176 | _T_53 | _T_54 ? (_T_27 ? _T_172[17:9] : 9'h0) | _T_173 | (_T_51 ?
fractB_other_PA[43:35] : 9'h0) | _T_75[8:0] | (_T_50 | _T_53 ? {1'h1, fractB_51_PA,
fractB_other_PA[50:44]} : 9'h0) | (_T_54 & _T_98[11] ? _T_172[8:0] : 9'h0) : nextMulAdd9A_A; // Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:247:25, :260:25, :507:12, :554:16, :598:{12,20,35}, :620:71, :622:24, :623:16, :625:{16,47}, :626:27, :627:{16,29,47,68}
nextMulAdd9B_A <= _T_176 | _T_54 ? _T_84 | _T_173 | (_T_50 ? _T_174[8:0] : 9'h0) | _T_175 | (_T_51 ?
hiSqrR0_A_sqrt[8:0] : 9'h0) | (_T_54 ? {1'h1, fractR0_A[8:1]} : 9'h0) : nextMulAdd9B_A; // Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:507:12, :557:16, :563:54, :564:44, :630:63, :631:24, :634:{16,43}, :636:{16,44,73}, :637:{16,55}
ER1_B_sqrt <= _T_58 ? _T_103 : ER1_B_sqrt; // DivSqrtRecF64_mulAddZ31.scala:641:20
ESqrR1_B_sqrt <= _T_60 ? io_mulAddResult_3[103:72] : ESqrR1_B_sqrt; // DivSqrtRecF64_mulAddZ31.scala:665:39, :701:43, :724:23
sigX1_B <= _T_13 ? _io_mulAddResult_3_104to47 : sigX1_B; // DivSqrtRecF64_mulAddZ31.scala:431:27, :688:45, :727:17
sqrSigma1_C <= _T_64 ? io_mulAddResult_3[79:47] : sqrSigma1_C; // DivSqrtRecF64_mulAddZ31.scala:668:37, :703:41, :730:21
sigXN_C <= _T_68 | _T_5 & ~sqrtOp_PB | _T_3 & sqrtOp_PB ? _io_mulAddResult_3_104to47 : sigXN_C; // DivSqrtRecF64_mulAddZ31.scala:294:25, :438:29, :456:27, :458:27, :462:29, :470:30, :656:43, :733:37, :734:17
u_C_sqrt <= _T_5 & sqrtOp_PB ? io_mulAddResult_3[103:73] : u_C_sqrt; // DivSqrtRecF64_mulAddZ31.scala:294:25, :456:27, :468:30, :657:44, :737:{18,33}
E_E_div <= _T_70 ? ~_io_mulAddResult_3_104 : E_E_div; // DivSqrtRecF64_mulAddZ31.scala:691:27, :705:20, :740:18
sigT_E <= _T_70 ? _T_177[53:1] : sigT_E; // DivSqrtRecF64_mulAddZ31.scala:741:{18,28}
extraT_E <= _T_70 ? _T_177[0] : extraT_E; // DivSqrtRecF64_mulAddZ31.scala:696:22, :742:{18,28}
isNegRemT_E <= _T_170 ? (sqrtOp_PC ? io_mulAddResult_3[55] : io_mulAddResult_3[53]) : isNegRemT_E; // DivSqrtRecF64_mulAddZ31.scala:332:25, :746:{21,27,47,61}
isZeroRemT_E <= _T_170 ? io_mulAddResult_3[53:0] == 54'h0 & (~sqrtOp_PC | io_mulAddResult_3[55:54] == 2'h0)
: isZeroRemT_E; // DivSqrtRecF64_mulAddZ31.scala:332:25, :383:39, :390:16, :691:12, :747:22, :748:{21,29,42}, :749:{30,41,50}
end // always @(posedge)
wire [13:0] _T_113 = (~sqrtOp_PC & E_E_div ? exp_PC : 14'h0) | (sqrtOp_PC | E_E_div ? 14'h0 : _T_44) | {1'h0,
sqrtOp_PC ? _exp_PC_13to1 + 13'h400 : 13'h0}; // DivSqrtRecF64_mulAddZ31.scala:78:30, :332:25, :341:25, :383:39, :547:12, :592:12, :691:27, :755:{12,25}, :756:{12,76}, :757:{12,47}
wire [12:0] _T_114 = _T_113[12:0]; // DivSqrtRecF64_mulAddZ31.scala:759:28
wire [12:0] _T_115 = ~_T_114; // primitives.scala:50:21
wire _T_116 = _T_115[9]; // primitives.scala:56:25
wire _T_117 = _T_115[8]; // primitives.scala:56:25
wire _T_118 = _T_115[7]; // primitives.scala:56:25
wire _T_119 = _T_115[6]; // primitives.scala:56:25
wire [64:0] _T_120 = $signed(65'sh10000000000000000 >>> _T_115[5:0]); // primitives.scala:57:26, :68:52
wire [52:0] _T_121 = _T_115[12] & _T_115[11] ? (_T_115[10] ? {~(_T_116 | _T_117 | _T_118 | _T_119 ? 50'h0 :
~{_T_120[14], _T_120[15], _T_120[16], _T_120[17], _T_120[18], _T_120[19], _T_120[20],
_T_120[21], _T_120[22], _T_120[23], _T_120[24], _T_120[25], _T_120[26], _T_120[27],
_T_120[28], _T_120[29], _T_120[30], _T_120[31], _T_120[32], _T_120[33], _T_120[34],
_T_120[35], _T_120[36], _T_120[37], _T_120[38], _T_120[39], _T_120[40], _T_120[41],
_T_120[42], _T_120[43], _T_120[44], _T_120[45], _T_120[46], _T_120[47], _T_120[48],
_T_120[49], _T_120[50], _T_120[51], _T_120[52], _T_120[53], _T_120[54], _T_120[55],
_T_120[56], _T_120[57], _T_120[58], _T_120[59], _T_120[60], _T_120[61], _T_120[62],
_T_120[63]}), 3'h7} : {50'h0, _T_116 & _T_117 & _T_118 & _T_119 ? {_T_120[0], _T_120[1],
_T_120[2]} : 3'h0}) : 53'h0; // Bitwise.scala:71:12, :102:{21,46}, :108:{18,44}, Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:117:30, :650:12, primitives.scala:56:25, :59:20, :61:20, :65:{17,21,36}
wire [53:0] _T_122 = {1'h1, ~_T_121} & {_T_121, 1'h1}; // Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:763:{9,39}
wire [52:0] _T_123 = sigT_E & _T_122[53:1]; // DivSqrtRecF64_mulAddZ31.scala:741:18, :765:{36,51}
wire [51:0] _T_124 = ~(sigT_E[51:0]) & _T_121[52:1]; // DivSqrtRecF64_mulAddZ31.scala:741:18, :766:55, :767:{34,42}
wire _T_125 = _T_121[0]; // DivSqrtRecF64_mulAddZ31.scala:769:23
wire _T_126 = (~_T_125 | |_T_123) & ~(|_T_124); // DivSqrtRecF64_mulAddZ31.scala:765:56, :767:60, :769:{10,27,48}
wire [53:0] _T_127 = {1'h0, sigT_E} + {53'h0, _T_45}; // DivSqrtRecF64_mulAddZ31.scala:78:30, :650:12, :741:18, :773:42
wire _T_128 = sqrtOp_PC ? ~isNegRemT_E & ~isZeroRemT_E : isNegRemT_E; // DivSqrtRecF64_mulAddZ31.scala:332:25, :746:21, :747:22, :783:{12,24,38,41}
wire _T_129 = |_T_123 ^ _T_125 & ~_T_128 & ~(|_T_124) & extraT_E; // DivSqrtRecF64_mulAddZ31.scala:696:22, :765:56, :767:60, :792:26, :793:{32,69}
wire _T_130 = ~isZeroRemT_E | ~extraT_E | |_T_124; // DivSqrtRecF64_mulAddZ31.scala:696:22, :747:22, :767:60, :783:41, :795:55
wire _T_131 = extraT_E & ~_T_128; // DivSqrtRecF64_mulAddZ31.scala:696:22, :793:32, :806:29
wire [53:0] _T_132 = (~_T_45 & |roundingMode_PC & extraT_E & ~_T_128 & _T_126 | _T_45 & (_T_131 & ~isZeroRemT_E
| ~_T_126) | ~(|roundingMode_PC) & (|_T_123 | (extraT_E | ~_T_128) & ~_T_125 | _T_131 &
~(|_T_124)) ? (_T_127 | {1'h0, _T_121}) + 54'h1 : _T_127 & {1'h1, ~_T_121}) &
~(~(|roundingMode_PC) & _T_129 & ~_T_130 ? _T_122 : 54'h0); // Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:78:30, :338:25, :370:54, :378:27, :691:12, :696:22, :747:22, :765:56, :767:60, :769:10, :774:{29,47}, :775:{30,62}, :783:41, :793:32, :797:{12,59}, :798:17, :804:{12,58}, :805:28, :806:{45,62}, :807:{23,43}, :808:40, :810:{34,51,72}, :811:49, :814:{11,13}
wire _T_133 = _T_129 | _T_130; // DivSqrtRecF64_mulAddZ31.scala:816:40
wire _T_134 = _T_132[53]; // DivSqrtRecF64_mulAddZ31.scala:818:22
wire _T_135 = _T_134 & ~sqrtOp_PC; // DivSqrtRecF64_mulAddZ31.scala:332:25, :383:39, :819:25
wire [13:0] _T_136 = (_T_134 ? 14'h0 : _T_113) | (_T_135 & E_E_div ? _T_44 : 14'h0) | (_T_135 & ~E_E_div ? _T_42
: 14'h0) | {1'h0, _T_134 & sqrtOp_PC ? _T_43 + 13'h400 : 13'h0}; // DivSqrtRecF64_mulAddZ31.scala:78:30, :332:25, :547:12, :592:12, :691:27, :757:47, :818:12, :819:{12,40}, :820:{12,40,73}, :821:{12,25}, :822:27
wire _T_137 = _T_136[13]; // DivSqrtRecF64_mulAddZ31.scala:827:34
wire _T_138 = _T_137 | _T_136[12:0] < 13'h3CE; // DivSqrtRecF64_mulAddZ31.scala:830:{22,34,42}
wire _T_139 = sqrtOp_PC ? ~_T_40 & |specialCodeB_PC & sign_PC : ~(|specialCodeA_PC) & ~(|specialCodeB_PC)
| _T_37 & _T_39; // DivSqrtRecF64_mulAddZ31.scala:332:25, :333:25, :334:25, :336:25, :346:42, :352:42, :838:12, :839:{13,41}, :840:{25,40,54}
wire _T_140 = _T_41 & ~_T_137 & _T_136[12:10] > 3'h2; // DivSqrtRecF64_mulAddZ31.scala:404:30, :827:{24,59,70}, :847:37
wire _T_141 = _T_41 & (_T_138 | _T_114 < 13'h402 & _T_133); // DivSqrtRecF64_mulAddZ31.scala:832:28, :833:{25,56}, :848:38
wire _T_142 = sqrtOp_PC ? ~(|specialCodeB_PC) : ~(|specialCodeA_PC) | _T_39 | _T_138 & ~_T_45; // DivSqrtRecF64_mulAddZ31.scala:332:25, :334:25, :336:25, :346:42, :352:42, :378:27, :855:12, :857:{37,60}
wire _T_143 = _T_41 & _T_138 & _T_45; // DivSqrtRecF64_mulAddZ31.scala:860:45
wire _T_144 = _T_140 & ~_T_46; // DivSqrtRecF64_mulAddZ31.scala:861:{45,48}
wire _T_145 = sqrtOp_PC ? _T_39 : _T_37 | ~(|specialCodeB_PC) | _T_140 & _T_46; // DivSqrtRecF64_mulAddZ31.scala:332:25, :336:25, :352:42, :863:12, :865:{37,53}
wire _T_146 = ~sqrtOp_PC & _T_38 | _T_40 | _T_139; // DivSqrtRecF64_mulAddZ31.scala:332:25, :383:39, :868:{22,49}
assign io_inReady_div = _T_18; // ../perf/regress/FPU.fir:2974:10
assign io_inReady_sqrt = _T_19; // ../perf/regress/FPU.fir:2974:10
assign io_outValid_div = _T_48 & ~sqrtOp_PC; // ../perf/regress/FPU.fir:2974:10, DivSqrtRecF64_mulAddZ31.scala:332:25, :383:{36,39}
assign io_outValid_sqrt = _T_48 & sqrtOp_PC; // ../perf/regress/FPU.fir:2974:10, DivSqrtRecF64_mulAddZ31.scala:332:25, :384:36
assign io_out = {~_T_146 & (~sqrtOp_PC | ~(|specialCodeB_PC)) & sign_PC, _T_136[11:0] & ~(_T_142 ? 12'hE00
: 12'h0) & ~(_T_143 ? 12'hC31 : 12'h0) & {1'h1, ~_T_144, 10'h3FF} & {2'h3, ~_T_145, 9'h1FF}
| (_T_143 ? 12'h3CE : 12'h0) | (_T_144 ? 12'hBFF : 12'h0) | (_T_145 ? 12'hC00 : 12'h0) |
(_T_146 ? 12'hE00 : 12'h0), (_T_142 | _T_138 | _T_146 ? {_T_146, 51'h0} : _T_132[51:0]) |
{52{_T_144}}}; // ../perf/regress/FPU.fir:2974:10, Bitwise.scala:71:12, Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:212:46, :332:25, :333:25, :336:25, :352:42, :516:12, :665:12, :815:28, :825:27, :871:{9,23,29}, :874:{14,18}, :875:19, :878:{14,18}, :879:19, :882:{14,18}, :883:19, :885:16, :886:{14,18}, :890:16, :891:16, :892:{16,76}, :893:16, :895:{12,59}, :896:16, :898:11
assign io_exceptionFlags = {~sqrtOp_PC & _T_38 & ~fractA_51_PC | _T_40 & ~fractB_51_PC | _T_139, ~sqrtOp_PC &
~(&_specialCodeA_PC_2to1) & |specialCodeA_PC & ~(|specialCodeB_PC), _T_140, _T_141, _T_140
| _T_141 | _T_41 & _T_133}; // ../perf/regress/FPU.fir:2974:10, Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:332:25, :334:25, :335:25, :336:25, :337:25, :346:42, :347:48, :350:38, :352:42, :356:{35,38}, :361:13, :383:39, :843:{22,55}, :845:56, :852:{37,55}
assign io_usingMulAdd = {_T_52 | _T_56 | _T_57 | cycleNum_B == 4'hA | _T_59 | _T_14 | _T_61 | _T_8 | _T_66 | _T_10
| _T_6 | _T_4, _T_53 | _T_54 & ~sqrtOp_PA | _T_59 | _T_60 | _T_61 | _T_62 | _T_7 | _T_67 |
_T_64 & ~sqrtOp_PB | _T_68 | _T_3, _T_54 | _T_57 | _T_60 | _T_14 | _T_62 | _T_63 | _T_66 |
_T_6 | _T_5 | _T_69, _T_105 | _T_61 | _T_67}; // ../perf/regress/FPU.fir:2974:10, Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:244:25, :294:25, :407:32, :408:29, :415:33, :418:20, :423:33, :426:33, :438:29, :439:26, :440:26, :443:39, :444:39, :447:27, :456:27, :457:27, :458:27, :674:73, :678:73, :682:54, :684:41
assign io_latchMulAddA_0 = _T_105; // ../perf/regress/FPU.fir:2974:10
assign io_mulAddA_0 = {1'h0, (_T_58 ? {_T_103, 36'h0} : 53'h0) | (_T_14 | _T_57 ? {1'h1, fractB_51_PA,
fractB_other_PA} : 53'h0) | (_T_65 ? {1'h1, fractA_51_PA, fractA_other_PA} : 53'h0) |
{7'h0, _T_106[45:34] | _T_107[45:34] | _T_108[45:34], _T_1[45:12] | _T_106[33:0] |
_T_107[33:0] | _T_108[33:0]} | (_T_71 ? {1'h1, fractB_51_PC, fractB_other_PC} : 53'h0)} |
_T; // ../perf/regress/FPU.fir:2974:10, Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:78:30, :247:25, :252:25, :260:25, :263:25, :337:25, :343:25, :426:33, :576:36, :650:{12,51}, :651:{12,25}, :652:12, :653:{19,67}, :655:67, :656:67, :657:67, :658:{12,67}, :702:22, :716:12
assign io_latchMulAddB_0 = _T_104 | _T_9 | _T_63 | _T_68 | _T_4 | _T_70; // ../perf/regress/FPU.fir:2974:10, DivSqrtRecF64_mulAddZ31.scala:442:39, :457:27, :662:35
assign io_mulAddB_0 = {1'h0, (_T_9 ? {ER1_B_sqrt, 36'h0} : 53'h0) | {1'h0, _T_109[51:46], _T_110[45:33],
_T_110[32:30] | _T_111[32:30], _T_110[29:0] | (_T_68 ? sqrSigma1_C[30:1] : 30'h0) |
_T_111[29:0]}} | _T_0; // ../perf/regress/FPU.fir:2974:10, DivSqrtRecF64_mulAddZ31.scala:78:30, :442:39, :641:20, :650:{12,51}, :666:{12,36,55}, :667:55, :668:{12,37,55}, :669:55, :710:11
assign io_mulAddC_2 = (_T_64 ? {sigX1_B, 47'h0} : 105'h0) | (_T_72 | _T_69 ? {sigXN_C, 47'h0} : 105'h0) | {1'h0,
_T_112[103:56], _T_112[55:54] | (_T_74 & sqrtOp_PC ? (_exp_PC_0 ? {_fractB_other_PC_0,
1'h0} : {fractB_other_PC[1] ^ _fractB_other_PC_0, _fractB_other_PC_0}) ^ {~extraT_E, 1'h0}
: 2'h0), _T_112[53:0] | (_T_74 & ~sqrtOp_PC & ~E_E_div ? {fractA_0_PC, 53'h0} : 54'h0)}; // ../perf/regress/FPU.fir:2974:10, Cat.scala:30:58, DivSqrtRecF64_mulAddZ31.scala:78:30, :332:25, :342:25, :343:25, :383:39, :390:16, :489:30, :650:12, :656:43, :688:{12,45}, :690:{12,25,45,64}, :691:{12,24,27,49,64}, :692:12, :693:17, :695:{29,33}, :696:{16,22}
endmodule
module Mul54( // ../perf/regress/FPU.fir:4419:10
input clock, reset, io_val_s0, io_latch_a_s0,
input [53:0] io_a_s0,
input io_latch_b_s0,
input [53:0] io_b_s0,
input [104:0] io_c_s2,
output [104:0] io_result_s3);
reg val_s1; // DivSqrtRecF64.scala:96:21
reg val_s2; // DivSqrtRecF64.scala:97:21
reg [53:0] reg_a_s1; // DivSqrtRecF64.scala:98:23
reg [53:0] reg_b_s1; // DivSqrtRecF64.scala:99:23
reg [53:0] reg_a_s2; // DivSqrtRecF64.scala:100:23
reg [53:0] reg_b_s2; // DivSqrtRecF64.scala:101:23
reg [104:0] reg_result_s3; // DivSqrtRecF64.scala:102:28
`ifndef SYNTHESIS // DivSqrtRecF64.scala:96:21
initial begin // DivSqrtRecF64.scala:96:21
automatic logic [31:0] _RANDOM; // DivSqrtRecF64.scala:96:21
automatic logic [31:0] _RANDOM_0; // DivSqrtRecF64.scala:98:23
automatic logic [31:0] _RANDOM_1; // DivSqrtRecF64.scala:99:23
automatic logic [31:0] _RANDOM_2; // DivSqrtRecF64.scala:100:23
automatic logic [31:0] _RANDOM_3; // DivSqrtRecF64.scala:101:23
automatic logic [31:0] _RANDOM_4; // DivSqrtRecF64.scala:102:28
`INIT_RANDOM_PROLOG_ // DivSqrtRecF64.scala:96:21
`ifdef RANDOMIZE_REG_INIT // DivSqrtRecF64.scala:96:21
_RANDOM = `RANDOM; // DivSqrtRecF64.scala:96:21
val_s1 = _RANDOM[0]; // DivSqrtRecF64.scala:96:21
val_s2 = _RANDOM[1]; // DivSqrtRecF64.scala:97:21
_RANDOM_0 = `RANDOM; // DivSqrtRecF64.scala:98:23
reg_a_s1 = {_RANDOM[31:2], _RANDOM_0[23:0]}; // DivSqrtRecF64.scala:98:23
_RANDOM_1 = `RANDOM; // DivSqrtRecF64.scala:99:23
reg_b_s1 = {_RANDOM_0[31:24], `RANDOM, _RANDOM_1[13:0]}; // DivSqrtRecF64.scala:99:23
_RANDOM_2 = `RANDOM; // DivSqrtRecF64.scala:100:23
reg_a_s2 = {_RANDOM_1[31:14], `RANDOM, _RANDOM_2[3:0]}; // DivSqrtRecF64.scala:100:23
_RANDOM_3 = `RANDOM; // DivSqrtRecF64.scala:101:23
reg_b_s2 = {_RANDOM_2[31:4], _RANDOM_3[25:0]}; // DivSqrtRecF64.scala:101:23
_RANDOM_4 = `RANDOM; // DivSqrtRecF64.scala:102:28
reg_result_s3 = {_RANDOM_3[31:26], `RANDOM, `RANDOM, `RANDOM, _RANDOM_4[2:0]}; // DivSqrtRecF64.scala:102:28
`endif
end // initial
`endif
always @(posedge clock) begin // DivSqrtRecF64.scala:104:12
val_s1 <= io_val_s0; // DivSqrtRecF64.scala:104:12
val_s2 <= val_s1; // DivSqrtRecF64.scala:105:12
reg_a_s1 <= io_val_s0 & io_latch_a_s0 ? io_a_s0 : reg_a_s1; // DivSqrtRecF64.scala:109:22
reg_b_s1 <= io_val_s0 & io_latch_b_s0 ? io_b_s0 : reg_b_s1; // DivSqrtRecF64.scala:112:22
reg_a_s2 <= val_s1 ? reg_a_s1 : reg_a_s2; // DivSqrtRecF64.scala:105:12, :109:22, :117:18
reg_b_s2 <= val_s1 ? reg_b_s1 : reg_b_s2; // DivSqrtRecF64.scala:105:12, :112:22, :118:18
reg_result_s3 <= val_s2 ? {51'h0, reg_a_s2} * {51'h0, reg_b_s2} + io_c_s2 : reg_result_s3; // DivSqrtRecF64.scala:117:18, :118:18, :122:{23,36,55}
end // always @(posedge)
assign io_result_s3 = reg_result_s3; // ../perf/regress/FPU.fir:4419:10, DivSqrtRecF64.scala:122:23
endmodule
module RoundRawFNToRecFN_1( // ../perf/regress/FPU.fir:4456:10
input clock,
input reset,
input io_invalidExc,
input io_infiniteExc,
input struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [9:0] sExp; logic [26:0] sig; } io_in,
input [1:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags);
wire _T = io_roundingMode == 2'h0; // RoundRawFNToRecFN.scala:88:54
wire _T_0 = io_in.sign; // RoundRawFNToRecFN.scala:94:27
wire _T_1 = io_roundingMode == 2'h2 & _T_0 | &io_roundingMode & ~_T_0; // RoundRawFNToRecFN.scala:90:54, :91:54, :94:{27,42,63,66}
wire [26:0] _T_2 = io_in.sig; // RoundRawFNToRecFN.scala:98:36
wire _T_3 = _T_2[26]; // RoundRawFNToRecFN.scala:98:36
wire [9:0] _T_4 = io_in.sExp; // RoundRawFNToRecFN.scala:99:32
wire _T_5 = $signed(_T_4) < 10'sh0; // RoundRawFNToRecFN.scala:99:32
wire [8:0] _T_6 = ~(_T_4[8:0]); // RoundRawFNToRecFN.scala:103:31, primitives.scala:50:21
wire _T_7 = _T_6[6]; // primitives.scala:56:25
wire [64:0] _T_8 = $signed(65'sh10000000000000000 >>> _T_6[5:0]); // primitives.scala:57:26, :68:52
wire [24:0] _T_9 = {25{_T_5}} | (_T_6[8] ? (_T_6[7] ? {~(_T_7 ? 22'h0 : ~{_T_8[42], _T_8[43], _T_8[44],
_T_8[45], _T_8[46], _T_8[47], _T_8[48], _T_8[49], _T_8[50], _T_8[51], _T_8[52], _T_8[53],
_T_8[54], _T_8[55], _T_8[56], _T_8[57], _T_8[58], _T_8[59], _T_8[60], _T_8[61], _T_8[62],
_T_8[63]}), 3'h7} : {22'h0, _T_7 ? {_T_8[0], _T_8[1], _T_8[2]} : 3'h0}) : 25'h0) | {24'h0,
_T_3}; // Bitwise.scala:71:12, :102:{21,46}, :108:{18,44}, Cat.scala:30:58, RoundRawFNToRecFN.scala:106:19, primitives.scala:56:25, :59:20, :61:20, :65:{17,21,36}
wire [25:0] _T_10 = _T_2[26:1] & {~_T_5, ~_T_9} & {_T_9, 1'h1}; // RoundRawFNToRecFN.scala:110:24, :111:34, :118:43
wire [26:0] _T_11 = _T_2 & {_T_5, _T_9, 1'h1}; // RoundRawFNToRecFN.scala:109:52, :112:36, :118:43
wire _T_12 = |_T_10 | |_T_11; // RoundRawFNToRecFN.scala:111:50, :112:56, :113:32
wire _T_13 = _T & |_T_10; // RoundRawFNToRecFN.scala:111:50, :116:40
wire [25:0] _T_14 = _T_13 | _T_1 & _T_12 ? {1'h0, _T_2[26:2] | _T_9} + 26'h1 & ~(_T_13 & ~(|_T_11) ? {_T_9,
1'h1} : 26'h0) : {1'h0, _T_2[26:2] & ~_T_9}; // RoundRawFNToRecFN.scala:94:66, :112:56, :116:{12,56}, :117:29, :118:{26,43,55}, :119:{17,21,63}, :120:26, :121:31, :124:{24,26}
wire [10:0] _T_15 = {_T_4[9], _T_4} + {9'h0, _T_14[25:24]}; // RoundRawFNToRecFN.scala:127:{34,48}, :163:18
wire _T_16 = $signed(_T_15) < 11'sh6B; // RoundRawFNToRecFN.scala:138:46
wire _T_17 = io_invalidExc | io_in.isNaN; // RoundRawFNToRecFN.scala:147:34
wire _T_18 = io_infiniteExc | io_in.isInf; // RoundRawFNToRecFN.scala:148:49
wire _T_19 = io_in.isZero; // RoundRawFNToRecFN.scala:149:64
wire _T_20 = ~_T_17 & ~_T_18 & ~_T_19; // RoundRawFNToRecFN.scala:149:{22,36,61,64}
wire _T_21 = _T_20 & $signed(_T_15[10:7]) > 4'sh2; // RoundRawFNToRecFN.scala:136:{39,56}, :150:32
wire _T_22 = _T | _T_1; // RoundRawFNToRecFN.scala:154:57
wire _T_23 = _T_20 & _T_16 & _T_1; // RoundRawFNToRecFN.scala:155:67
wire _T_24 = _T_20 & _T_21 & ~_T_22; // RoundRawFNToRecFN.scala:156:{53,56}
wire _T_25 = _T_18 | _T_21 & _T_22; // RoundRawFNToRecFN.scala:158:{32,45}
assign io_out = {~_T_17 & _T_0, _T_15[8:0] & ~(_T_19 | _T_16 ? 9'h1C0 : 9'h0) & ~(_T_23 ? 9'h194 : 9'h0) &
{1'h1, ~_T_24, 7'h7F} & {2'h3, ~_T_25, 6'h3F} | (_T_23 ? 9'h6B : 9'h0) | (_T_24 ? 9'h17F :
9'h0) | (_T_25 ? 9'h180 : 9'h0) | (_T_17 ? 9'h1C0 : 9'h0), (_T_16 | _T_17 ? {_T_17, 22'h0}
: _T_3 ? _T_14[23:1] : _T_14[22:0]) | {23{_T_24}}}; // ../perf/regress/FPU.fir:4456:10, Bitwise.scala:71:12, Cat.scala:30:58, RoundRawFNToRecFN.scala:91:54, :118:43, :129:36, :131:12, :132:23, :133:23, :160:22, :163:{14,18,32}, :167:{14,18}, :168:19, :171:{14,18}, :174:17, :175:{14,18}, :179:16, :183:16, :187:{16,71}, :188:16, :190:{12,35}, :191:16, :193:11, primitives.scala:65:21
assign io_exceptionFlags = {io_invalidExc, io_infiniteExc, _T_21, _T_20 & _T_12 & $signed(_T_4) < $signed({1'h0, _T_3
? 9'h81 : 9'h82}), _T_21 | _T_20 & _T_12}; // ../perf/regress/FPU.fir:4456:10, Cat.scala:30:58, RoundRawFNToRecFN.scala:94:66, :141:25, :142:21, :151:32, :152:{28,43}
endmodule
module MulAddRecFN_preMul( // ../perf/regress/FPU.fir:4659:10
input clock,
input reset,
input [1:0] io_op,
input [32:0] io_a,
input [32:0] io_b,
input [32:0] io_c,
input [1:0] io_roundingMode,
output [23:0] io_mulAddA,
output [23:0] io_mulAddB,
output [47:0] io_mulAddC,
output struct packed {logic [2:0] highExpA; logic isNaN_isQuietNaNA; logic [2:0] highExpB; logic isNaN_isQuietNaNB; logic signProd; logic isZeroProd; logic opSignC; logic [2:0] highExpC; logic isNaN_isQuietNaNC; logic isCDominant; logic CAlignDist_0; logic [6:0] CAlignDist; logic bit0AlignedNegSigC; logic [25:0] highAlignedNegSigC; logic [10:0] sExpSum; logic [1:0] roundingMode; } io_toPostMul);
wire struct packed {logic [2:0] highExpA; logic isNaN_isQuietNaNA; logic [2:0] highExpB; logic isNaN_isQuietNaNB; logic signProd; logic isZeroProd; logic opSignC; logic [2:0] highExpC; logic isNaN_isQuietNaNC; logic isCDominant; logic CAlignDist_0; logic [6:0] CAlignDist; logic bit0AlignedNegSigC; logic [25:0] highAlignedNegSigC; logic [10:0] sExpSum; logic [1:0] roundingMode; } _io_toPostMul_output; // ../perf/regress/FPU.fir:4659:10
wire [2:0] _io_a_31to29 = io_a[31:29]; // MulAddRecFN.scala:105:24
wire [2:0] _io_b_31to29 = io_b[31:29]; // MulAddRecFN.scala:111:24
wire _T = io_c[32] ^ io_op[0]; // MulAddRecFN.scala:114:{23,45,52}
wire [8:0] _io_c_31to23 = io_c[31:23]; // MulAddRecFN.scala:115:22
wire [2:0] _io_c_31to29 = io_c[31:29]; // MulAddRecFN.scala:117:24
wire [23:0] _T_0 = {|_io_c_31to29, io_c[22:0]}; // Cat.scala:30:58, MulAddRecFN.scala:116:22, :117:49
wire _T_1 = io_a[32] ^ io_b[32] ^ io_op[1]; // MulAddRecFN.scala:102:22, :108:22, :122:{34,41}
wire _T_2 = ~(|_io_a_31to29) | ~(|_io_b_31to29); // MulAddRecFN.scala:105:49, :111:49, :123:30
wire [10:0] _T_3 = {2'h0, io_a[31:23]} + {{3{~(io_b[31])}}, io_b[30:23]} + 11'h1B; // Bitwise.scala:71:12, MulAddRecFN.scala:103:22, :125:{14,28,34,51,70}, :148:22
wire _T_4 = _T_1 ^ _T; // MulAddRecFN.scala:130:30
wire [10:0] _T_5 = _T_3 - {2'h0, _io_c_31to23}; // MulAddRecFN.scala:132:42, :148:22
wire _T_6 = _T_2 | _T_5[10]; // MulAddRecFN.scala:133:{39,56}
wire [9:0] _T_7 = _T_5[9:0]; // MulAddRecFN.scala:135:44
wire [6:0] _T_8 = _T_6 ? 7'h0 : _T_7 < 10'h4A ? _T_5[6:0] : 7'h4A; // MulAddRecFN.scala:141:12, :143:{16,49}, :144:31
wire [64:0] _T_9 = $signed(65'sh10000000000000000 >>> _T_8[5:0]); // primitives.scala:57:26, :68:52
wire [74:0] _T_10 = $signed($signed({_T_4, {24{_T_4}} ^ _T_0, {50{_T_4}}}) >>> _T_8); // Bitwise.scala:71:12, Cat.scala:30:58, MulAddRecFN.scala:151:22, :154:70
assign _io_toPostMul_output.highExpA = _io_a_31to29; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:163:37
assign _io_toPostMul_output.isNaN_isQuietNaNA = io_a[22]; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:164:{37,46}
assign _io_toPostMul_output.highExpB = _io_b_31to29; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:165:37
assign _io_toPostMul_output.isNaN_isQuietNaNB = io_b[22]; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:166:{37,46}
assign _io_toPostMul_output.signProd = _T_1; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:167:37
assign _io_toPostMul_output.isZeroProd = _T_2; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:168:37
assign _io_toPostMul_output.opSignC = _T; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:169:37
assign _io_toPostMul_output.highExpC = _io_c_31to29; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:170:37
assign _io_toPostMul_output.isNaN_isQuietNaNC = io_c[22]; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:171:{37,46}
assign _io_toPostMul_output.isCDominant = |_io_c_31to29 & (_T_6 | _T_7 < 10'h19); // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:117:49, :137:19, :138:31, :139:51, :172:37
assign _io_toPostMul_output.CAlignDist_0 = _T_6 | _T_7 == 10'h0; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:135:{26,62}, :173:37
assign _io_toPostMul_output.CAlignDist = _T_8; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:174:37
assign _io_toPostMul_output.bit0AlignedNegSigC = |(_T_0 & (_T_8[6] ? {_T_9[54], _T_9[55], _T_9[56], _T_9[57], _T_9[58], _T_9[59], _T_9[60],
_T_9[61], _T_9[62], _T_9[63], 14'h3FFF} : {10'h0, _T_9[0], _T_9[1], _T_9[2], _T_9[3],
_T_9[4], _T_9[5], _T_9[6], _T_9[7], _T_9[8], _T_9[9], _T_9[10], _T_9[11], _T_9[12],
_T_9[13]})) ^ _T_4; // ../perf/regress/FPU.fir:4664:8, Bitwise.scala:102:{21,46}, :108:{18,44}, Cat.scala:30:58, MulAddRecFN.scala:135:62, :156:{19,33,37}, :175:37, primitives.scala:56:25, :61:20
assign _io_toPostMul_output.highAlignedNegSigC = _T_10[73:48]; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:176:37, :177:23
assign _io_toPostMul_output.sExpSum = _T_6 ? {2'h0, _io_c_31to23} : _T_3; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:148:22, :178:37
assign _io_toPostMul_output.roundingMode = io_roundingMode; // ../perf/regress/FPU.fir:4664:8, MulAddRecFN.scala:179:37
assign io_mulAddA = {|_io_a_31to29, io_a[22:0]}; // ../perf/regress/FPU.fir:4659:10, Cat.scala:30:58, MulAddRecFN.scala:104:22, :105:49
assign io_mulAddB = {|_io_b_31to29, io_b[22:0]}; // ../perf/regress/FPU.fir:4659:10, Cat.scala:30:58, MulAddRecFN.scala:110:22, :111:49
assign io_mulAddC = _T_10[47:0]; // ../perf/regress/FPU.fir:4659:10, MulAddRecFN.scala:161:33
assign io_toPostMul = _io_toPostMul_output; // ../perf/regress/FPU.fir:4659:10
endmodule
module MulAddRecFN_postMul( // ../perf/regress/FPU.fir:4856:10
input clock,
input reset,
input struct packed {logic [2:0] highExpA; logic isNaN_isQuietNaNA; logic [2:0] highExpB; logic isNaN_isQuietNaNB; logic signProd; logic isZeroProd; logic opSignC; logic [2:0] highExpC; logic isNaN_isQuietNaNC; logic isCDominant; logic CAlignDist_0; logic [6:0] CAlignDist; logic bit0AlignedNegSigC; logic [25:0] highAlignedNegSigC; logic [10:0] sExpSum; logic [1:0] roundingMode; } io_fromPreMul,
input [48:0] io_mulAddResult,
output [32:0] io_out,
output [4:0] io_exceptionFlags);
wire [2:0] _T = io_fromPreMul.highExpA; // MulAddRecFN.scala:207:46
wire [1:0] _T_0 = _T[2:1]; // MulAddRecFN.scala:208:45
wire _T_1 = _T[0]; // MulAddRecFN.scala:209:56
wire _T_2 = &_T_0 & ~_T_1; // MulAddRecFN.scala:208:52, :209:{29,32}
wire _T_3 = &_T_0 & _T_1; // MulAddRecFN.scala:208:52, :210:29
wire [2:0] _T_4 = io_fromPreMul.highExpB; // MulAddRecFN.scala:213:46
wire [1:0] _T_5 = _T_4[2:1]; // MulAddRecFN.scala:214:45
wire _T_6 = _T_4[0]; // MulAddRecFN.scala:215:56
wire _T_7 = &_T_5 & ~_T_6; // MulAddRecFN.scala:214:52, :215:{29,32}
wire _T_8 = &_T_5 & _T_6; // MulAddRecFN.scala:214:52, :216:29
wire [2:0] _T_9 = io_fromPreMul.highExpC; // MulAddRecFN.scala:219:46
wire [1:0] _T_10 = _T_9[2:1]; // MulAddRecFN.scala:220:45
wire _T_11 = _T_9[0]; // MulAddRecFN.scala:221:56
wire _T_12 = &_T_10 & ~_T_11; // MulAddRecFN.scala:220:52, :221:{29,32}
wire _T_13 = &_T_10 & _T_11; // MulAddRecFN.scala:220:52, :222:29
wire [1:0] _T_14 = io_fromPreMul.roundingMode; // MulAddRecFN.scala:226:37
wire _T_15 = _T_14 == 2'h0; // MulAddRecFN.scala:226:37
wire _T_16 = _T_14 == 2'h2; // MulAddRecFN.scala:228:59
wire _T_17 = io_fromPreMul.signProd; // MulAddRecFN.scala:232:44
wire _T_18 = io_fromPreMul.opSignC; // MulAddRecFN.scala:232:44
wire _T_19 = _T_17 ^ _T_18; // MulAddRecFN.scala:232:44
wire [25:0] _T_20 = io_fromPreMul.highAlignedNegSigC; // MulAddRecFN.scala:238:50
wire [25:0] _T_21 = io_mulAddResult[48] ? _T_20 + 26'h1 : _T_20; // MulAddRecFN.scala:237:{16,32}, :238:50
wire [47:0] _io_mulAddResult_47to0 = io_mulAddResult[47:0]; // MulAddRecFN.scala:241:28
wire _T_22 = io_fromPreMul.bit0AlignedNegSigC; // Cat.scala:30:58
wire [48:0] _T_23 = {_T_21[1:0], io_mulAddResult[47:1]} ^ {_T_21[0], _io_mulAddResult_47to0}; // MulAddRecFN.scala:191:32, :248:38
wire [17:0] _T_24 = _T_23[48:31]; // CircuitMath.scala:35:17
wire [1:0] _T_25 = _T_23[48:47]; // CircuitMath.scala:35:17
wire [7:0] _T_26 = _T_23[46:39]; // CircuitMath.scala:35:17
wire [3:0] _T_27 = _T_23[46:43]; // CircuitMath.scala:35:17
wire [3:0] _T_28 = _T_23[38:35]; // CircuitMath.scala:35:17
wire [15:0] _T_29 = _T_23[30:15]; // CircuitMath.scala:35:17
wire [7:0] _T_30 = _T_23[30:23]; // CircuitMath.scala:35:17
wire [3:0] _T_31 = _T_23[30:27]; // CircuitMath.scala:35:17
wire [3:0] _T_32 = _T_23[22:19]; // CircuitMath.scala:35:17
wire [7:0] _T_33 = _T_23[14:7]; // CircuitMath.scala:35:17
wire [3:0] _T_34 = _T_23[14:11]; // CircuitMath.scala:35:17
wire [3:0] _T_35 = _T_23[6:3]; // CircuitMath.scala:35:17
wire [6:0] _T_36 = 7'h49 - {1'h0, |_T_24, |_T_24 ? {|_T_25, |_T_25 ? {3'h0, _T_23[48]} : {|_T_26, |_T_26 ?
{|_T_27, |_T_27 ? (_T_23[46] ? 2'h3 : _T_23[45] ? 2'h2 : {1'h0, _T_23[44]}) : _T_23[42] ?
2'h3 : _T_23[41] ? 2'h2 : {1'h0, _T_23[40]}} : {|_T_28, |_T_28 ? (_T_23[38] ? 2'h3 :
_T_23[37] ? 2'h2 : {1'h0, _T_23[36]}) : _T_23[34] ? 2'h3 : _T_23[33] ? 2'h2 : {1'h0,
_T_23[32]}}}} : {|_T_29, |_T_29 ? {|_T_30, |_T_30 ? {|_T_31, |_T_31 ? (_T_23[30] ? 2'h3 :
_T_23[29] ? 2'h2 : {1'h0, _T_23[28]}) : _T_23[26] ? 2'h3 : _T_23[25] ? 2'h2 : {1'h0,
_T_23[24]}} : {|_T_32, |_T_32 ? (_T_23[22] ? 2'h3 : _T_23[21] ? 2'h2 : {1'h0, _T_23[20]}) :
_T_23[18] ? 2'h3 : _T_23[17] ? 2'h2 : {1'h0, _T_23[16]}}} : {|_T_33, |_T_33 ? {|_T_34,
|_T_34 ? (_T_23[14] ? 2'h3 : _T_23[13] ? 2'h2 : {1'h0, _T_23[12]}) : _T_23[10] ? 2'h3 :
_T_23[9] ? 2'h2 : {1'h0, _T_23[8]}} : {|_T_35, |_T_35 ? (_T_23[6] ? 2'h3 : _T_23[5] ? 2'h2
: {1'h0, _T_23[4]}) : _T_23[2] ? 2'h3 : _T_23[1] ? 2'h2 : {1'h0, _T_23[0]}}}}}; // Cat.scala:30:58, CircuitMath.scala:30:8, :32:{10,12}, :37:22, :38:21, MulAddRecFN.scala:207:46, :208:52, :228:59, primitives.scala:79:25
wire [17:0] _T_37 = {io_mulAddResult[16:0], _T_22}; // MulAddRecFN.scala:255:19
wire [74:0] _T_38 = ~{_T_21, _io_mulAddResult_47to0, _T_22}; // Cat.scala:30:58, MulAddRecFN.scala:257:23
wire [17:0] _T_39 = _T_38[17:0]; // MulAddRecFN.scala:262:24
wire [6:0] _T_40 = io_fromPreMul.CAlignDist; // MulAddRecFN.scala:268:39
wire [6:0] _T_41 = io_fromPreMul.CAlignDist_0 | _T_19 ? _T_40 : {2'h0, _T_40[4:0] - 5'h1}; // MulAddRecFN.scala:226:37, :266:{12,40}, :268:39
wire _T_42 = _T_41[4]; // MulAddRecFN.scala:271:46
wire [41:0] _T_43 = (_T_19 | _T_42 ? 42'h0 : {_T_21, io_mulAddResult[47:33], |{|(io_mulAddResult[32:17]),
|_T_37}}) | (~_T_19 & _T_42 ? {_T_21[9:0], io_mulAddResult[47:17], |_T_37} : 42'h0) |
(_T_19 & ~_T_42 ? {_T_38[74:34], |{|(_T_38[33:18]), |_T_39}} : 42'h0) | (_T_19 & _T_42 ?
{_T_38[58:18], |_T_39} : 42'h0); // Cat.scala:30:58, MulAddRecFN.scala:252:19, :254:15, :255:57, :259:24, :261:15, :262:62, :271:{12,13,28}, :272:23, :273:35, :277:{12,25}, :278:23, :286:{12,23}, :287:28, :288:40, :291:11, :292:{12,23}, :293:28
wire _T_44 = _T_36[5]; // MulAddRecFN.scala:338:28
wire _T_45 = _T_36[4]; // MulAddRecFN.scala:339:33
wire _T_46 = _T_21[2]; // MulAddRecFN.scala:392:36
wire _T_47 = io_fromPreMul.isCDominant; // MulAddRecFN.scala:394:12
wire [6:0] _T_48 = _T_47 ? _T_41 : _T_36; // MulAddRecFN.scala:399:12
wire [42:0] _T_49 = _T_46 ? (_T_47 ? {1'h0, _T_43} : _T_44 ? (_T_45 ? {_T_38[27:1], 16'h0} : {1'h0,
_T_38[42:1]}) : _T_45 ? {10'h0, _T_38[49:18], |_T_39} : {_T_38[11:1], 32'h0}) : {1'h0,
_T_47 ? _T_43 : _T_44 ? (_T_45 ? {io_mulAddResult[25:0], {16{_T_19}}} :
io_mulAddResult[41:0]) : _T_45 ? {8'h0, _T_21[1:0], io_mulAddResult[47:17], _T_19 ?
~(|_T_39) : |_T_37} : {io_mulAddResult[9:0], {32{_T_19}}}}; // Bitwise.scala:71:12, Cat.scala:30:58, CircuitMath.scala:37:22, MulAddRecFN.scala:207:46, :255:57, :262:62, :308:23, :309:20, :310:21, :314:24, :338:12, :339:17, :340:28, :345:17, :347:28, :360:28, :363:29, :379:12, :380:17, :381:{29,64}, :385:17, :387:{29,64}, :407:12, :408:16, :412:16
wire _T_50 = ~_T_47 & ~_T_46 & _T_19; // MulAddRecFN.scala:418:{9,40,61}
wire [3:0] _T_51 = _T_48[3:0]; // MulAddRecFN.scala:419:36
wire [16:0] _T_52 = $signed(17'sh10000 >>> ~_T_51); // MulAddRecFN.scala:420:28, primitives.scala:68:52
wire [15:0] _T_53 = {_T_52[1], _T_52[2], _T_52[3], _T_52[4], _T_52[5], _T_52[6], _T_52[7], _T_52[8], _T_52[9],
_T_52[10], _T_52[11], _T_52[12], _T_52[13], _T_52[14], _T_52[15], 1'h1}; // Bitwise.scala:102:{21,46}, :108:{18,44}, Cat.scala:30:58, MulAddRecFN.scala:231:35
wire [41:0] _T_54 = _T_49[42:1] >> ~_T_51; // MulAddRecFN.scala:420:28, :424:{32,65}
wire [15:0] _T_55 = _T_49[15:0]; // MulAddRecFN.scala:427:39
wire _T_56 = _T_50 ? (~_T_55 & _T_53) == 16'h0 : |(_T_55 & _T_53); // Bitwise.scala:71:12, MulAddRecFN.scala:426:16, :427:{19,62}, :428:43, :430:61, :431:43
wire _T_57 = _T_54[26:25] == 2'h0; // MulAddRecFN.scala:226:37, :436:{29,58}
wire [10:0] _T_58 = io_fromPreMul.sExpSum - {4'h0, _T_48}; // MulAddRecFN.scala:437:40, primitives.scala:59:20
wire [2:0] _T_59 = _T_54[26:24]; // MulAddRecFN.scala:439:25
wire _T_60 = |_T_59 ? _T_17 ^ (_T_47 ? _T_19 & |_T_9 : _T_46) : _T_16; // MulAddRecFN.scala:219:46, :394:12, :395:23, :439:54, :442:12, :444:36
wire [9:0] _T_61 = _T_58[9:0]; // MulAddRecFN.scala:446:27
wire _T_62 = _T_58[10]; // MulAddRecFN.scala:448:34
wire [9:0] _T_63 = ~_T_61; // primitives.scala:50:21
wire _T_64 = _T_63[6]; // primitives.scala:56:25
wire [64:0] _T_65 = $signed(65'sh10000000000000000 >>> _T_63[5:0]); // primitives.scala:57:26, :68:52
wire [26:0] _T_66 = {27{_T_62}} | {(_T_63[9] & _T_63[8] ? (_T_63[7] ? {~(_T_64 ? 21'h0 : ~{_T_65[43],
_T_65[44], _T_65[45], _T_65[46], _T_65[47], _T_65[48], _T_65[49], _T_65[50], _T_65[51],
_T_65[52], _T_65[53], _T_65[54], _T_65[55], _T_65[56], _T_65[57], _T_65[58], _T_65[59],
_T_65[60], _T_65[61], _T_65[62], _T_65[63]}), 4'hF} : {21'h0, _T_64 ? {_T_65[0], _T_65[1],
_T_65[2], _T_65[3]} : 4'h0}) : 25'h0) | {24'h0, _T_54[25]}, 2'h3}; // Bitwise.scala:71:12, :101:47, :102:{21,46}, :108:{18,44}, Cat.scala:30:58, MulAddRecFN.scala:208:52, :448:50, :449:75, :450:26, primitives.scala:56:25, :59:20, :61:20, :65:{17,21,36}
wire [25:0] _T_67 = _T_66[26:1]; // MulAddRecFN.scala:454:35
wire [25:0] _T_68 = {_T_54[24:0], _T_56} & ~_T_67 & _T_66[25:0]; // MulAddRecFN.scala:454:{24,40}, :455:30
wire [25:0] _T_69 = {_T_54[24:0], _T_56} & _T_67; // MulAddRecFN.scala:456:34
wire _T_70 = (~{_T_54[24:0], _T_56} & _T_67) == 26'h0; // MulAddRecFN.scala:457:{27,34,50}, :477:12
wire _T_71 = |_T_68 | |_T_69; // MulAddRecFN.scala:455:46, :456:50, :458:32
wire _T_72 = |_T_68 & _T_70; // MulAddRecFN.scala:455:46, :459:32
wire _T_73 = _T_60 ? _T_16 : &_T_14; // MulAddRecFN.scala:229:59, :460:28
wire _T_74 = ~_T_50 & _T_15 & |_T_68 & |_T_69 | ~_T_50 & _T_73 & _T_71 | _T_50 & _T_72 | _T_50 & _T_15 &
|_T_68 | _T_50 & _T_73; // MulAddRecFN.scala:455:46, :456:50, :462:10, :463:60, :464:49, :465:49, :466:{49,65}, :467:20
wire _T_75 = _T_50 ? _T_15 & ~(|_T_68) & _T_70 : _T_15 & |_T_68 & ~(|_T_69); // MulAddRecFN.scala:455:46, :456:50, :469:12, :470:{42,56}, :471:{56,59}
wire _T_76 = _T_50 ? ~_T_72 : _T_71; // MulAddRecFN.scala:473:{27,39}
wire [25:0] _T_77 = {_T_54[26], _T_54[25:1] | _T_66[26:2]} + 26'h1; // MulAddRecFN.scala:238:50, :475:{18,35}
wire [25:0] _T_78 = (_T_74 | _T_75 ? 26'h0 : _T_54[26:1] & {1'h0, ~(_T_66[26:2])}) | (_T_74 ? _T_77 : 26'h0) |
(_T_75 ? _T_77 & ~_T_67 : 26'h0); // MulAddRecFN.scala:207:46, :454:24, :477:{12,46,48}, :478:{12,79}, :479:{12,51}
wire [9:0] _T_79 = (_T_78[25] ? _T_58[9:0] + 10'h1 : 10'h0) | (_T_78[24] ? _T_58[9:0] : 10'h0) | (_T_78[25:24]
== 2'h0 ? _T_58[9:0] - 10'h1 : 10'h0); // MulAddRecFN.scala:226:37, :385:17, :482:{12,18,41}, :483:{12,18,61}, :484:{12,19,44}, :485:20
wire [8:0] _T_80 = _T_79[8:0]; // MulAddRecFN.scala:488:21
wire _T_81 = |_T_59 & (_T_79[9] | _T_80 < 9'h6B); // MulAddRecFN.scala:439:54, :495:19, :496:{19,34,57}, :557:16
wire _T_82 = _T_16 & _T_60 | &_T_14 & ~_T_60; // MulAddRecFN.scala:229:59, :506:{27,37,58,61}
wire _T_83 = _T_15 | _T_82; // MulAddRecFN.scala:507:58
wire _T_84 = &_T_0 | &_T_5; // MulAddRecFN.scala:208:52, :214:52, :511:33
wire _T_85 = io_fromPreMul.isZeroProd & ~(|_T_9); // MulAddRecFN.scala:219:46, :513:56
wire _T_86 = ~(_T_84 | &_T_10) & ~_T_85; // MulAddRecFN.scala:220:52, :512:33, :514:{22,35,38}
wire _T_87 = _T_2 | _T_7; // MulAddRecFN.scala:518:46
wire _T_88 = _T_2 & _T_4 == 3'h0 | _T == 3'h0 & _T_7 | ~_T_3 & ~_T_8 & _T_87 & _T_12 & _T_19; // MulAddRecFN.scala:207:46, :213:46, :517:{17,41,52}, :518:{14,26,67}
wire _T_89 = _T_86 & _T_79[9:7] == 3'h3; // MulAddRecFN.scala:492:{27,56}, :520:32
wire _T_90 = _T_86 & _T_81 & _T_82; // MulAddRecFN.scala:526:60
wire _T_91 = _T_89 & ~_T_83; // MulAddRecFN.scala:527:{39,42}
wire _T_92 = _T_87 | _T_12 | _T_89 & _T_83; // MulAddRecFN.scala:529:{36,49}
wire _T_93 = _T_3 | _T_8 | _T_13 | _T_88; // MulAddRecFN.scala:530:47
assign io_out = {~_T_93 & (~_T_19 & _T_18 | _T_84 & ~(&_T_10) & _T_17 | ~_T_84 & &_T_10 & _T_18 | ~_T_84 &
_T_85 & _T_19 & _T_16) | _T_86 & _T_60, _T_80 & ~(_T_85 | ~(|_T_59) | _T_81 ? 9'h1C0 :
9'h0) & ~(_T_90 ? 9'h194 : 9'h0) & {1'h1, ~_T_91, 7'h7F} & {2'h3, ~_T_92, 6'h3F} | (_T_90 ?
9'h6B : 9'h0) | (_T_91 ? 9'h17F : 9'h0) | (_T_92 ? 9'h180 : 9'h0) | (_T_93 ? 9'h1C0 :
9'h0), (_T_81 & _T_82 | _T_93 ? {_T_93, 22'h0} : _T_57 ? _T_78[22:0] : _T_78[23:1]) |
{23{_T_91}}}; // ../perf/regress/FPU.fir:4856:10, Bitwise.scala:71:12, Cat.scala:30:58, MulAddRecFN.scala:208:52, :220:52, :231:35, :271:13, :439:54, :490:{12,31,55}, :525:40, :533:51, :534:{24,51}, :535:{10,51,78}, :536:59, :538:{20,31,55,70}, :541:{14,18}, :545:{14,18}, :546:19, :549:{14,18}, :552:17, :553:{14,18}, :557:16, :558:16, :562:16, :565:15, :566:16, :568:{12,30,45}, :569:16, :571:11
assign io_exceptionFlags = {_T_3 & ~io_fromPreMul.isNaN_isQuietNaNA | _T_8 & ~io_fromPreMul.isNaN_isQuietNaNB | _T_13
& ~io_fromPreMul.isNaN_isQuietNaNC | _T_88, 1'h0, _T_89, _T_86 & _T_76 & (_T_62 | _T_61 <=
{2'h0, _T_57 ? 8'h82 : 8'h81}), _T_89 | _T_86 & _T_76}; // ../perf/regress/FPU.fir:4856:10, Cat.scala:30:58, MulAddRecFN.scala:207:46, :211:{28,31}, :217:{28,31}, :223:{28,31}, :226:37, :499:35, :500:29, :501:26, :519:55, :521:32, :522:{28,43}
endmodule
module RoundRawFNToRecFN( // ../perf/regress/FPU.fir:5491:10
input clock,
input reset,
input io_invalidExc,
input io_infiniteExc,
input struct packed {logic sign; logic isNaN; logic isInf; logic isZero; logic [9:0] sExp; logic [26:0] sig; } io_in,
input [1:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags);
wire _T = io_roundingMode == 2'h0; // RoundRawFNToRecFN.scala:88:54
wire _T_0 = io_in.sign; // RoundRawFNToRecFN.scala:94:27
wire _T_1 = io_roundingMode == 2'h2 & _T_0 | &io_roundingMode & ~_T_0; // RoundRawFNToRecFN.scala:90:54, :91:54, :94:{27,42,63,66}
wire [26:0] _T_2 = io_in.sig; // RoundRawFNToRecFN.scala:98:36
wire _T_3 = _T_2[26]; // RoundRawFNToRecFN.scala:98:36
wire [9:0] _T_4 = io_in.sExp; // RoundRawFNToRecFN.scala:99:32
wire _T_5 = $signed(_T_4) < 10'sh0; // RoundRawFNToRecFN.scala:99:32
wire [8:0] _T_6 = ~(_T_4[8:0]); // RoundRawFNToRecFN.scala:103:31, primitives.scala:50:21
wire _T_7 = _T_6[6]; // primitives.scala:56:25
wire [64:0] _T_8 = $signed(65'sh10000000000000000 >>> _T_6[5:0]); // primitives.scala:57:26, :68:52
wire [24:0] _T_9 = {25{_T_5}} | (_T_6[8] ? (_T_6[7] ? {~(_T_7 ? 22'h0 : ~{_T_8[42], _T_8[43], _T_8[44],
_T_8[45], _T_8[46], _T_8[47], _T_8[48], _T_8[49], _T_8[50], _T_8[51], _T_8[52], _T_8[53],
_T_8[54], _T_8[55], _T_8[56], _T_8[57], _T_8[58], _T_8[59], _T_8[60], _T_8[61], _T_8[62],
_T_8[63]}), 3'h7} : {22'h0, _T_7 ? {_T_8[0], _T_8[1], _T_8[2]} : 3'h0}) : 25'h0) | {24'h0,
_T_3}; // Bitwise.scala:71:12, :102:{21,46}, :108:{18,44}, Cat.scala:30:58, RoundRawFNToRecFN.scala:106:19, primitives.scala:56:25, :59:20, :61:20, :65:{17,21,36}
wire [25:0] _T_10 = _T_2[26:1] & {~_T_5, ~_T_9} & {_T_9, 1'h1}; // RoundRawFNToRecFN.scala:110:24, :111:34, :118:43
wire [26:0] _T_11 = _T_2 & {_T_5, _T_9, 1'h1}; // RoundRawFNToRecFN.scala:109:52, :112:36, :118:43
wire _T_12 = |_T_10 | |_T_11; // RoundRawFNToRecFN.scala:111:50, :112:56, :113:32
wire _T_13 = _T & |_T_10; // RoundRawFNToRecFN.scala:111:50, :116:40
wire [25:0] _T_14 = _T_13 | _T_1 & _T_12 ? {1'h0, _T_2[26:2] | _T_9} + 26'h1 & ~(_T_13 & ~(|_T_11) ? {_T_9,
1'h1} : 26'h0) : {1'h0, _T_2[26:2] & ~_T_9}; // RoundRawFNToRecFN.scala:94:66, :112:56, :116:{12,56}, :117:29, :118:{26,43,55}, :119:{17,21,63}, :120:26, :121:31, :124:{24,26}
wire [10:0] _T_15 = {_T_4[9], _T_4} + {9'h0, _T_14[25:24]}; // RoundRawFNToRecFN.scala:127:{34,48}, :163:18
wire _T_16 = $signed(_T_15) < 11'sh6B; // RoundRawFNToRecFN.scala:138:46
wire _T_17 = io_invalidExc | io_in.isNaN; // RoundRawFNToRecFN.scala:147:34
wire _T_18 = io_infiniteExc | io_in.isInf; // RoundRawFNToRecFN.scala:148:49
wire _T_19 = io_in.isZero; // RoundRawFNToRecFN.scala:149:64
wire _T_20 = ~_T_17 & ~_T_18 & ~_T_19; // RoundRawFNToRecFN.scala:149:{22,36,61,64}
wire _T_21 = _T_20 & $signed(_T_15[10:7]) > 4'sh2; // RoundRawFNToRecFN.scala:136:{39,56}, :150:32
wire _T_22 = _T | _T_1; // RoundRawFNToRecFN.scala:154:57
wire _T_23 = _T_20 & _T_16 & _T_1; // RoundRawFNToRecFN.scala:155:67
wire _T_24 = _T_20 & _T_21 & ~_T_22; // RoundRawFNToRecFN.scala:156:{53,56}
wire _T_25 = _T_18 | _T_21 & _T_22; // RoundRawFNToRecFN.scala:158:{32,45}
assign io_out = {~_T_17 & _T_0, _T_15[8:0] & ~(_T_19 | _T_16 ? 9'h1C0 : 9'h0) & ~(_T_23 ? 9'h194 : 9'h0) &
{1'h1, ~_T_24, 7'h7F} & {2'h3, ~_T_25, 6'h3F} | (_T_23 ? 9'h6B : 9'h0) | (_T_24 ? 9'h17F :
9'h0) | (_T_25 ? 9'h180 : 9'h0) | (_T_17 ? 9'h1C0 : 9'h0), (_T_16 | _T_17 ? {_T_17, 22'h0}
: _T_3 ? _T_14[23:1] : _T_14[22:0]) | {23{_T_24}}}; // ../perf/regress/FPU.fir:5491:10, Bitwise.scala:71:12, Cat.scala:30:58, RoundRawFNToRecFN.scala:91:54, :118:43, :129:36, :131:12, :132:23, :133:23, :160:22, :163:{14,18,32}, :167:{14,18}, :168:19, :171:{14,18}, :174:17, :175:{14,18}, :179:16, :183:16, :187:{16,71}, :188:16, :190:{12,35}, :191:16, :193:11, primitives.scala:65:21
assign io_exceptionFlags = {io_invalidExc, io_infiniteExc, _T_21, _T_20 & _T_12 & $signed(_T_4) < $signed({1'h0, _T_3
? 9'h81 : 9'h82}), _T_21 | _T_20 & _T_12}; // ../perf/regress/FPU.fir:5491:10, Cat.scala:30:58, RoundRawFNToRecFN.scala:94:66, :141:25, :142:21, :151:32, :152:{28,43}
endmodule
module MulAddRecFN_preMul_1( // ../perf/regress/FPU.fir:5694:10
input clock,
input reset,
input [1:0] io_op,
input [64:0] io_a,
input [64:0] io_b,
input [64:0] io_c,
input [1:0] io_roundingMode,
output [52:0] io_mulAddA,
output [52:0] io_mulAddB,
output [105:0] io_mulAddC,
output struct packed {logic [2:0] highExpA; logic isNaN_isQuietNaNA; logic [2:0] highExpB; logic isNaN_isQuietNaNB; logic signProd; logic isZeroProd; logic opSignC; logic [2:0] highExpC; logic isNaN_isQuietNaNC; logic isCDominant; logic CAlignDist_0; logic [7:0] CAlignDist; logic bit0AlignedNegSigC; logic [54:0] highAlignedNegSigC; logic [13:0] sExpSum; logic [1:0] roundingMode; } io_toPostMul);
wire struct packed {logic [2:0] highExpA; logic isNaN_isQuietNaNA; logic [2:0] highExpB; logic isNaN_isQuietNaNB; logic signProd; logic isZeroProd; logic opSignC; logic [2:0] highExpC; logic isNaN_isQuietNaNC; logic isCDominant; logic CAlignDist_0; logic [7:0] CAlignDist; logic bit0AlignedNegSigC; logic [54:0] highAlignedNegSigC; logic [13:0] sExpSum; logic [1:0] roundingMode; } _io_toPostMul_output; // ../perf/regress/FPU.fir:5694:10
wire [2:0] _io_a_63to61 = io_a[63:61]; // MulAddRecFN.scala:105:24
wire [2:0] _io_b_63to61 = io_b[63:61]; // MulAddRecFN.scala:111:24
wire _T = io_c[64] ^ io_op[0]; // MulAddRecFN.scala:114:{23,45,52}
wire [11:0] _io_c_63to52 = io_c[63:52]; // MulAddRecFN.scala:115:22
wire [2:0] _io_c_63to61 = io_c[63:61]; // MulAddRecFN.scala:117:24
wire [52:0] _T_0 = {|_io_c_63to61, io_c[51:0]}; // Cat.scala:30:58, MulAddRecFN.scala:116:22, :117:49
wire _T_1 = io_a[64] ^ io_b[64] ^ io_op[1]; // MulAddRecFN.scala:102:22, :108:22, :122:{34,41}
wire _T_2 = ~(|_io_a_63to61) | ~(|_io_b_63to61); // MulAddRecFN.scala:105:49, :111:49, :123:30
wire [13:0] _T_3 = {2'h0, io_a[63:52]} + {{3{~(io_b[63])}}, io_b[62:52]} + 14'h38; // Bitwise.scala:71:12, MulAddRecFN.scala:103:22, :125:{14,28,34,51,70}, :148:22
wire _T_4 = _T_1 ^ _T; // MulAddRecFN.scala:130:30
wire [13:0] _T_5 = _T_3 - {2'h0, _io_c_63to52}; // MulAddRecFN.scala:132:42, :148:22
wire _T_6 = _T_2 | _T_5[13]; // MulAddRecFN.scala:133:{39,56}
wire [12:0] _T_7 = _T_5[12:0]; // MulAddRecFN.scala:135:44
wire [7:0] _T_8 = _T_6 ? 8'h0 : _T_7 < 13'hA1 ? _T_5[7:0] : 8'hA1; // MulAddRecFN.scala:141:12, :143:{16,49}, :144:31
wire _T_9 = _T_8[6]; // primitives.scala:56:25
wire [64:0] _T_10 = $signed(65'sh10000000000000000 >>> _T_8[5:0]); // primitives.scala:57:26, :68:52
wire [161:0] _T_11 = $signed($signed({_T_4, {53{_T_4}} ^ _T_0, {108{_T_4}}}) >>> _T_8); // Bitwise.scala:71:12, Cat.scala:30:58, MulAddRecFN.scala:151:22, :154:70
assign _io_toPostMul_output.highExpA = _io_a_63to61; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:163:37
assign _io_toPostMul_output.isNaN_isQuietNaNA = io_a[51]; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:164:{37,46}
assign _io_toPostMul_output.highExpB = _io_b_63to61; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:165:37
assign _io_toPostMul_output.isNaN_isQuietNaNB = io_b[51]; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:166:{37,46}
assign _io_toPostMul_output.signProd = _T_1; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:167:37
assign _io_toPostMul_output.isZeroProd = _T_2; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:168:37
assign _io_toPostMul_output.opSignC = _T; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:169:37
assign _io_toPostMul_output.highExpC = _io_c_63to61; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:170:37
assign _io_toPostMul_output.isNaN_isQuietNaNC = io_c[51]; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:171:{37,46}
assign _io_toPostMul_output.isCDominant = |_io_c_63to61 & (_T_6 | _T_7 < 13'h36); // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:117:49, :137:19, :138:31, :139:51, :172:37
assign _io_toPostMul_output.CAlignDist_0 = _T_6 | _T_7 == 13'h0; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:135:{26,62}, :173:37
assign _io_toPostMul_output.CAlignDist = _T_8; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:174:37
assign _io_toPostMul_output.bit0AlignedNegSigC = |(_T_0 & (_T_8[7] ? {~(_T_9 ? 33'h0 : ~{_T_10[31], _T_10[32], _T_10[33], _T_10[34],
_T_10[35], _T_10[36], _T_10[37], _T_10[38], _T_10[39], _T_10[40], _T_10[41], _T_10[42],
_T_10[43], _T_10[44], _T_10[45], _T_10[46], _T_10[47], _T_10[48], _T_10[49], _T_10[50],
_T_10[51], _T_10[52], _T_10[53], _T_10[54], _T_10[55], _T_10[56], _T_10[57], _T_10[58],
_T_10[59], _T_10[60], _T_10[61], _T_10[62], _T_10[63]}), 20'hFFFFF} : {33'h0, _T_9 ?
{_T_10[0], _T_10[1], _T_10[2], _T_10[3], _T_10[4], _T_10[5], _T_10[6], _T_10[7], _T_10[8],
_T_10[9], _T_10[10], _T_10[11], _T_10[12], _T_10[13], _T_10[14], _T_10[15], _T_10[16],
_T_10[17], _T_10[18], _T_10[19]} : 20'h0})) ^ _T_4; // ../perf/regress/FPU.fir:5699:8, Bitwise.scala:102:{21,46}, :108:{18,44}, Cat.scala:30:58, MulAddRecFN.scala:156:{19,33,37}, :175:37, primitives.scala:56:25, :59:20, :61:20, :65:{17,21,36}
assign _io_toPostMul_output.highAlignedNegSigC = _T_11[160:106]; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:176:37, :177:23
assign _io_toPostMul_output.sExpSum = _T_6 ? {2'h0, _io_c_63to52} : _T_3; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:148:22, :178:37
assign _io_toPostMul_output.roundingMode = io_roundingMode; // ../perf/regress/FPU.fir:5699:8, MulAddRecFN.scala:179:37
assign io_mulAddA = {|_io_a_63to61, io_a[51:0]}; // ../perf/regress/FPU.fir:5694:10, Cat.scala:30:58, MulAddRecFN.scala:104:22, :105:49
assign io_mulAddB = {|_io_b_63to61, io_b[51:0]}; // ../perf/regress/FPU.fir:5694:10, Cat.scala:30:58, MulAddRecFN.scala:110:22, :111:49
assign io_mulAddC = _T_11[105:0]; // ../perf/regress/FPU.fir:5694:10, MulAddRecFN.scala:161:33
assign io_toPostMul = _io_toPostMul_output; // ../perf/regress/FPU.fir:5694:10
endmodule
module MulAddRecFN_postMul_1( // ../perf/regress/FPU.fir:5920:10
input clock,
input reset,
input struct packed {logic [2:0] highExpA; logic isNaN_isQuietNaNA; logic [2:0] highExpB; logic isNaN_isQuietNaNB; logic signProd; logic isZeroProd; logic opSignC; logic [2:0] highExpC; logic isNaN_isQuietNaNC; logic isCDominant; logic CAlignDist_0; logic [7:0] CAlignDist; logic bit0AlignedNegSigC; logic [54:0] highAlignedNegSigC; logic [13:0] sExpSum; logic [1:0] roundingMode; } io_fromPreMul,
input [106:0] io_mulAddResult,
output [64:0] io_out,
output [4:0] io_exceptionFlags);
wire [2:0] _T = io_fromPreMul.highExpA; // MulAddRecFN.scala:207:46
wire [1:0] _T_0 = _T[2:1]; // MulAddRecFN.scala:208:45
wire _T_1 = _T[0]; // MulAddRecFN.scala:209:56
wire _T_2 = &_T_0 & ~_T_1; // MulAddRecFN.scala:208:52, :209:{29,32}
wire _T_3 = &_T_0 & _T_1; // MulAddRecFN.scala:208:52, :210:29
wire [2:0] _T_4 = io_fromPreMul.highExpB; // MulAddRecFN.scala:213:46
wire [1:0] _T_5 = _T_4[2:1]; // MulAddRecFN.scala:214:45
wire _T_6 = _T_4[0]; // MulAddRecFN.scala:215:56
wire _T_7 = &_T_5 & ~_T_6; // MulAddRecFN.scala:214:52, :215:{29,32}
wire _T_8 = &_T_5 & _T_6; // MulAddRecFN.scala:214:52, :216:29
wire [2:0] _T_9 = io_fromPreMul.highExpC; // MulAddRecFN.scala:219:46
wire [1:0] _T_10 = _T_9[2:1]; // MulAddRecFN.scala:220:45
wire _T_11 = _T_9[0]; // MulAddRecFN.scala:221:56
wire _T_12 = &_T_10 & ~_T_11; // MulAddRecFN.scala:220:52, :221:{29,32}
wire _T_13 = &_T_10 & _T_11; // MulAddRecFN.scala:220:52, :222:29
wire [1:0] _T_14 = io_fromPreMul.roundingMode; // MulAddRecFN.scala:226:37
wire _T_15 = _T_14 == 2'h0; // MulAddRecFN.scala:226:37
wire _T_16 = _T_14 == 2'h2; // MulAddRecFN.scala:228:59
wire _T_17 = io_fromPreMul.signProd; // MulAddRecFN.scala:232:44
wire _T_18 = io_fromPreMul.opSignC; // MulAddRecFN.scala:232:44
wire _T_19 = _T_17 ^ _T_18; // MulAddRecFN.scala:232:44
wire [54:0] _T_20 = io_fromPreMul.highAlignedNegSigC; // MulAddRecFN.scala:238:50
wire [54:0] _T_21 = io_mulAddResult[106] ? _T_20 + 55'h1 : _T_20; // MulAddRecFN.scala:237:{16,32}, :238:50
wire [105:0] _io_mulAddResult_105to0 = io_mulAddResult[105:0]; // MulAddRecFN.scala:241:28
wire _T_22 = io_fromPreMul.bit0AlignedNegSigC; // Cat.scala:30:58
wire [106:0] _T_23 = {_T_21[1:0], io_mulAddResult[105:1]} ^ {_T_21[0], _io_mulAddResult_105to0}; // MulAddRecFN.scala:191:32, :248:38
wire [43:0] _T_24 = _T_23[106:63]; // CircuitMath.scala:35:17
wire [11:0] _T_25 = _T_23[106:95]; // CircuitMath.scala:35:17
wire [3:0] _T_26 = _T_23[106:103]; // CircuitMath.scala:35:17
wire [3:0] _T_27 = _T_23[102:99]; // CircuitMath.scala:35:17
wire [15:0] _T_28 = _T_23[94:79]; // CircuitMath.scala:35:17
wire [7:0] _T_29 = _T_23[94:87]; // CircuitMath.scala:35:17
wire [3:0] _T_30 = _T_23[94:91]; // CircuitMath.scala:35:17
wire [3:0] _T_31 = _T_23[86:83]; // CircuitMath.scala:35:17
wire [7:0] _T_32 = _T_23[78:71]; // CircuitMath.scala:35:17
wire [3:0] _T_33 = _T_23[78:75]; // CircuitMath.scala:35:17
wire [3:0] _T_34 = _T_23[70:67]; // CircuitMath.scala:35:17
wire [31:0] _T_35 = _T_23[62:31]; // CircuitMath.scala:35:17
wire [15:0] _T_36 = _T_23[62:47]; // CircuitMath.scala:35:17
wire [7:0] _T_37 = _T_23[62:55]; // CircuitMath.scala:35:17
wire [3:0] _T_38 = _T_23[62:59]; // CircuitMath.scala:35:17
wire [3:0] _T_39 = _T_23[54:51]; // CircuitMath.scala:35:17
wire [7:0] _T_40 = _T_23[46:39]; // CircuitMath.scala:35:17
wire [3:0] _T_41 = _T_23[46:43]; // CircuitMath.scala:35:17
wire [3:0] _T_42 = _T_23[38:35]; // CircuitMath.scala:35:17
wire [15:0] _T_43 = _T_23[30:15]; // CircuitMath.scala:35:17
wire [7:0] _T_44 = _T_23[30:23]; // CircuitMath.scala:35:17
wire [3:0] _T_45 = _T_23[30:27]; // CircuitMath.scala:35:17
wire [3:0] _T_46 = _T_23[22:19]; // CircuitMath.scala:35:17
wire [7:0] _T_47 = _T_23[14:7]; // CircuitMath.scala:35:17
wire [3:0] _T_48 = _T_23[14:11]; // CircuitMath.scala:35:17
wire [3:0] _T_49 = _T_23[6:3]; // CircuitMath.scala:35:17
wire [7:0] _T_50 = 8'hA0 - {1'h0, |_T_24, |_T_24 ? {|_T_25, |_T_25 ? {1'h0, |_T_26, |_T_26 ? {1'h0, _T_23[106]
? 2'h3 : _T_23[105] ? 2'h2 : {1'h0, _T_23[104]}} : {|_T_27, |_T_27 ? (_T_23[102] ? 2'h3 :
_T_23[101] ? 2'h2 : {1'h0, _T_23[100]}) : _T_23[98] ? 2'h3 : _T_23[97] ? 2'h2 : {1'h0,
_T_23[96]}}} : {|_T_28, |_T_28 ? {|_T_29, |_T_29 ? {|_T_30, |_T_30 ? (_T_23[94] ? 2'h3 :
_T_23[93] ? 2'h2 : {1'h0, _T_23[92]}) : _T_23[90] ? 2'h3 : _T_23[89] ? 2'h2 : {1'h0,
_T_23[88]}} : {|_T_31, |_T_31 ? (_T_23[86] ? 2'h3 : _T_23[85] ? 2'h2 : {1'h0, _T_23[84]}) :
_T_23[82] ? 2'h3 : _T_23[81] ? 2'h2 : {1'h0, _T_23[80]}}} : {|_T_32, |_T_32 ? {|_T_33,
|_T_33 ? (_T_23[78] ? 2'h3 : _T_23[77] ? 2'h2 : {1'h0, _T_23[76]}) : _T_23[74] ? 2'h3 :
_T_23[73] ? 2'h2 : {1'h0, _T_23[72]}} : {|_T_34, |_T_34 ? (_T_23[70] ? 2'h3 : _T_23[69] ?
2'h2 : {1'h0, _T_23[68]}) : _T_23[66] ? 2'h3 : _T_23[65] ? 2'h2 : {1'h0, _T_23[64]}}}}} :
{|_T_35, |_T_35 ? {|_T_36, |_T_36 ? {|_T_37, |_T_37 ? {|_T_38, |_T_38 ? (_T_23[62] ? 2'h3 :
_T_23[61] ? 2'h2 : {1'h0, _T_23[60]}) : _T_23[58] ? 2'h3 : _T_23[57] ? 2'h2 : {1'h0,
_T_23[56]}} : {|_T_39, |_T_39 ? (_T_23[54] ? 2'h3 : _T_23[53] ? 2'h2 : {1'h0, _T_23[52]}) :
_T_23[50] ? 2'h3 : _T_23[49] ? 2'h2 : {1'h0, _T_23[48]}}} : {|_T_40, |_T_40 ? {|_T_41,
|_T_41 ? (_T_23[46] ? 2'h3 : _T_23[45] ? 2'h2 : {1'h0, _T_23[44]}) : _T_23[42] ? 2'h3 :
_T_23[41] ? 2'h2 : {1'h0, _T_23[40]}} : {|_T_42, |_T_42 ? (_T_23[38] ? 2'h3 : _T_23[37] ?
2'h2 : {1'h0, _T_23[36]}) : _T_23[34] ? 2'h3 : _T_23[33] ? 2'h2 : {1'h0, _T_23[32]}}}} :
{|_T_43, |_T_43 ? {|_T_44, |_T_44 ? {|_T_45, |_T_45 ? (_T_23[30] ? 2'h3 : _T_23[29] ? 2'h2
: {1'h0, _T_23[28]}) : _T_23[26] ? 2'h3 : _T_23[25] ? 2'h2 : {1'h0, _T_23[24]}} : {|_T_46,
|_T_46 ? (_T_23[22] ? 2'h3 : _T_23[21] ? 2'h2 : {1'h0, _T_23[20]}) : _T_23[18] ? 2'h3 :
_T_23[17] ? 2'h2 : {1'h0, _T_23[16]}}} : {|_T_47, |_T_47 ? {|_T_48, |_T_48 ? (_T_23[14] ?
2'h3 : _T_23[13] ? 2'h2 : {1'h0, _T_23[12]}) : _T_23[10] ? 2'h3 : _T_23[9] ? 2'h2 : {1'h0,
_T_23[8]}} : {|_T_49, |_T_49 ? (_T_23[6] ? 2'h3 : _T_23[5] ? 2'h2 : {1'h0, _T_23[4]}) :
_T_23[2] ? 2'h3 : _T_23[1] ? 2'h2 : {1'h0, _T_23[0]}}}}}}; // Cat.scala:30:58, CircuitMath.scala:30:8, :32:{10,12}, :37:22, :38:21, MulAddRecFN.scala:207:46, :208:52, :228:59, primitives.scala:79:25
wire [43:0] _T_51 = {io_mulAddResult[42:0], _T_22}; // MulAddRecFN.scala:255:19
wire [161:0] _T_52 = ~{_T_21, _io_mulAddResult_105to0, _T_22}; // Cat.scala:30:58, MulAddRecFN.scala:257:23
wire [43:0] _T_53 = _T_52[43:0]; // MulAddRecFN.scala:262:24
wire [7:0] _T_54 = io_fromPreMul.CAlignDist; // MulAddRecFN.scala:268:39
wire [7:0] _T_55 = io_fromPreMul.CAlignDist_0 | _T_19 ? _T_54 : {2'h0, _T_54[5:0] - 6'h1}; // MulAddRecFN.scala:226:37, :266:{12,40}, :268:39
wire _T_56 = _T_55[5]; // MulAddRecFN.scala:271:46
wire [86:0] _T_57 = (_T_19 | _T_56 ? 87'h0 : {_T_21, io_mulAddResult[105:75], |{|(io_mulAddResult[74:43]),
|_T_51}}) | (~_T_19 & _T_56 ? {_T_21[22:0], io_mulAddResult[105:43], |_T_51} : 87'h0) |
(_T_19 & ~_T_56 ? {_T_52[161:76], |{|(_T_52[75:44]), |_T_53}} : 87'h0) | (_T_19 & _T_56 ?
{_T_52[129:44], |_T_53} : 87'h0); // Cat.scala:30:58, MulAddRecFN.scala:252:19, :254:15, :255:57, :259:24, :261:15, :262:62, :271:{12,13,28}, :272:23, :273:35, :277:{12,25}, :278:23, :286:{12,23}, :287:28, :288:40, :291:11, :292:{12,23}, :293:28
wire _T_58 = _T_50[4]; // MulAddRecFN.scala:316:37
wire [10:0] _T_59 = _T_52[11:1]; // MulAddRecFN.scala:329:39
wire _T_60 = _T_50[6]; // MulAddRecFN.scala:338:28
wire _T_61 = _T_50[5]; // MulAddRecFN.scala:339:33
wire _T_62 = _T_21[2]; // MulAddRecFN.scala:392:36
wire _T_63 = io_fromPreMul.isCDominant; // MulAddRecFN.scala:394:12
wire [7:0] _T_64 = _T_63 ? _T_55 : _T_50; // MulAddRecFN.scala:399:12
wire [87:0] _T_65 = _T_62 ? (_T_63 ? {1'h0, _T_57} : _T_60 ? (_T_61 ? {_T_52[66:1], 22'h0} : {_T_52[98:12],
|_T_59}) : _T_61 ? (_T_58 ? {23'h0, _T_52[107:44], |_T_53} : {_T_52[2:1], 86'h0}) :
{_T_52[34:1], 54'h0}) : {1'h0, _T_63 ? _T_57 : _T_60 ? (_T_61 ? {io_mulAddResult[64:0],
{22{_T_19}}} : {io_mulAddResult[96:11], _T_19 ? ~(|_T_59) : |(io_mulAddResult[10:0])}) :
_T_61 ? (_T_58 ? {21'h0, _T_21[1:0], io_mulAddResult[105:43], _T_19 ? ~(|_T_53) : |_T_51} :
{io_mulAddResult[0], {86{_T_19}}}) : {io_mulAddResult[32:0], {54{_T_19}}}}; // Bitwise.scala:71:12, Cat.scala:30:58, MulAddRecFN.scala:207:46, :255:57, :262:62, :308:23, :309:20, :310:21, :316:21, :318:32, :324:28, :328:26, :329:77, :331:{34,72}, :338:12, :339:17, :340:28, :345:17, :347:28, :360:28, :365:21, :367:{33,68}, :372:33, :379:12, :380:17, :381:{29,64}, :385:17, :387:{29,64}, :407:12, :408:16, :412:16
wire _T_66 = ~_T_63 & ~_T_62 & _T_19; // MulAddRecFN.scala:418:{9,40,61}
wire [4:0] _T_67 = _T_64[4:0]; // MulAddRecFN.scala:419:36
wire [32:0] _T_68 = $signed(33'sh100000000 >>> ~_T_67); // MulAddRecFN.scala:420:28, primitives.scala:68:52
wire [31:0] _T_69 = {_T_68[1], _T_68[2], _T_68[3], _T_68[4], _T_68[5], _T_68[6], _T_68[7], _T_68[8], _T_68[9],
_T_68[10], _T_68[11], _T_68[12], _T_68[13], _T_68[14], _T_68[15], _T_68[16], _T_68[17],
_T_68[18], _T_68[19], _T_68[20], _T_68[21], _T_68[22], _T_68[23], _T_68[24], _T_68[25],
_T_68[26], _T_68[27], _T_68[28], _T_68[29], _T_68[30], _T_68[31], 1'h1}; // Bitwise.scala:102:{21,46}, :108:{18,44}, Cat.scala:30:58, MulAddRecFN.scala:231:35
wire [86:0] _T_70 = _T_65[87:1] >> ~_T_67; // MulAddRecFN.scala:420:28, :424:{32,65}
wire [31:0] _T_71 = _T_65[31:0]; // MulAddRecFN.scala:427:39
wire _T_72 = _T_66 ? (~_T_71 & _T_69) == 32'h0 : |(_T_71 & _T_69); // CircuitMath.scala:37:22, MulAddRecFN.scala:426:16, :427:{19,62}, :428:43, :430:61, :431:43
wire _T_73 = _T_70[55:54] == 2'h0; // MulAddRecFN.scala:226:37, :436:{29,58}
wire [13:0] _T_74 = io_fromPreMul.sExpSum - {6'h0, _T_64}; // MulAddRecFN.scala:437:40
wire [2:0] _T_75 = _T_70[55:53]; // MulAddRecFN.scala:439:25
wire _T_76 = |_T_75 ? _T_17 ^ (_T_63 ? _T_19 & |_T_9 : _T_62) : _T_16; // MulAddRecFN.scala:219:46, :394:12, :395:23, :439:54, :442:12, :444:36
wire [12:0] _T_77 = _T_74[12:0]; // MulAddRecFN.scala:446:27
wire _T_78 = _T_74[13]; // MulAddRecFN.scala:448:34
wire [12:0] _T_79 = ~_T_77; // primitives.scala:50:21
wire _T_80 = _T_79[9]; // primitives.scala:56:25
wire _T_81 = _T_79[8]; // primitives.scala:56:25
wire _T_82 = _T_79[7]; // primitives.scala:56:25
wire _T_83 = _T_79[6]; // primitives.scala:56:25
wire [64:0] _T_84 = $signed(65'sh10000000000000000 >>> _T_79[5:0]); // primitives.scala:57:26, :68:52
wire [55:0] _T_85 = {56{_T_78}} | {(_T_79[12] & _T_79[11] ? (_T_79[10] ? {~(_T_80 | _T_81 | _T_82 | _T_83 ?
50'h0 : ~{_T_84[14], _T_84[15], _T_84[16], _T_84[17], _T_84[18], _T_84[19], _T_84[20],
_T_84[21], _T_84[22], _T_84[23], _T_84[24], _T_84[25], _T_84[26], _T_84[27], _T_84[28],
_T_84[29], _T_84[30], _T_84[31], _T_84[32], _T_84[33], _T_84[34], _T_84[35], _T_84[36],
_T_84[37], _T_84[38], _T_84[39], _T_84[40], _T_84[41], _T_84[42], _T_84[43], _T_84[44],
_T_84[45], _T_84[46], _T_84[47], _T_84[48], _T_84[49], _T_84[50], _T_84[51], _T_84[52],
_T_84[53], _T_84[54], _T_84[55], _T_84[56], _T_84[57], _T_84[58], _T_84[59], _T_84[60],
_T_84[61], _T_84[62], _T_84[63]}), 4'hF} : {50'h0, _T_80 & _T_81 & _T_82 & _T_83 ?
{_T_84[0], _T_84[1], _T_84[2], _T_84[3]} : 4'h0}) : 54'h0) | {53'h0, _T_70[54]}, 2'h3}; // Bitwise.scala:71:12, :101:47, :102:{21,46}, :108:{18,44}, Cat.scala:30:58, MulAddRecFN.scala:208:52, :448:50, :449:75, :450:26, primitives.scala:56:25, :59:20, :61:20, :65:{17,21,36}
wire [54:0] _T_86 = _T_85[55:1]; // MulAddRecFN.scala:454:35
wire [54:0] _T_87 = {_T_70[53:0], _T_72} & ~_T_86 & _T_85[54:0]; // MulAddRecFN.scala:454:{24,40}, :455:30
wire [54:0] _T_88 = {_T_70[53:0], _T_72} & _T_86; // MulAddRecFN.scala:456:34
wire _T_89 = (~{_T_70[53:0], _T_72} & _T_86) == 55'h0; // MulAddRecFN.scala:457:{27,34,50}, :477:12
wire _T_90 = |_T_87 | |_T_88; // MulAddRecFN.scala:455:46, :456:50, :458:32
wire _T_91 = |_T_87 & _T_89; // MulAddRecFN.scala:455:46, :459:32
wire _T_92 = _T_76 ? _T_16 : &_T_14; // MulAddRecFN.scala:229:59, :460:28
wire _T_93 = ~_T_66 & _T_15 & |_T_87 & |_T_88 | ~_T_66 & _T_92 & _T_90 | _T_66 & _T_91 | _T_66 & _T_15 &
|_T_87 | _T_66 & _T_92; // MulAddRecFN.scala:455:46, :456:50, :462:10, :463:60, :464:49, :465:49, :466:{49,65}, :467:20
wire _T_94 = _T_66 ? _T_15 & ~(|_T_87) & _T_89 : _T_15 & |_T_87 & ~(|_T_88); // MulAddRecFN.scala:455:46, :456:50, :469:12, :470:{42,56}, :471:{56,59}
wire _T_95 = _T_66 ? ~_T_91 : _T_90; // MulAddRecFN.scala:473:{27,39}
wire [54:0] _T_96 = {_T_70[55], _T_70[54:1] | _T_85[55:2]} + 55'h1; // MulAddRecFN.scala:238:50, :475:{18,35}
wire [54:0] _T_97 = (_T_93 | _T_94 ? 55'h0 : _T_70[55:1] & {1'h0, ~(_T_85[55:2])}) | (_T_93 ? _T_96 : 55'h0) |
(_T_94 ? _T_96 & ~_T_86 : 55'h0); // MulAddRecFN.scala:207:46, :454:24, :477:{12,46,48}, :478:{12,79}, :479:{12,51}
wire [12:0] _T_98 = (_T_97[54] ? _T_74[12:0] + 13'h1 : 13'h0) | (_T_97[53] ? _T_74[12:0] : 13'h0) |
(_T_97[54:53] == 2'h0 ? _T_74[12:0] - 13'h1 : 13'h0); // MulAddRecFN.scala:226:37, :482:{12,18,41}, :483:{12,18,61}, :484:{12,19,44}, :485:20
wire [11:0] _T_99 = _T_98[11:0]; // MulAddRecFN.scala:488:21
wire _T_100 = |_T_75 & (_T_98[12] | _T_99 < 12'h3CE); // MulAddRecFN.scala:439:54, :495:19, :496:{19,34,57}, :557:16
wire _T_101 = _T_16 & _T_76 | &_T_14 & ~_T_76; // MulAddRecFN.scala:229:59, :506:{27,37,58,61}
wire _T_102 = _T_15 | _T_101; // MulAddRecFN.scala:507:58
wire _T_103 = &_T_0 | &_T_5; // MulAddRecFN.scala:208:52, :214:52, :511:33
wire _T_104 = io_fromPreMul.isZeroProd & ~(|_T_9); // MulAddRecFN.scala:219:46, :513:56
wire _T_105 = ~(_T_103 | &_T_10) & ~_T_104; // MulAddRecFN.scala:220:52, :512:33, :514:{22,35,38}
wire _T_106 = _T_2 | _T_7; // MulAddRecFN.scala:518:46
wire _T_107 = _T_2 & _T_4 == 3'h0 | _T == 3'h0 & _T_7 | ~_T_3 & ~_T_8 & _T_106 & _T_12 & _T_19; // MulAddRecFN.scala:207:46, :213:46, :517:{17,41,52}, :518:{14,26,67}
wire _T_108 = _T_105 & _T_98[12:10] == 3'h3; // MulAddRecFN.scala:492:{27,56}, :520:32
wire _T_109 = _T_105 & _T_100 & _T_101; // MulAddRecFN.scala:526:60
wire _T_110 = _T_108 & ~_T_102; // MulAddRecFN.scala:527:{39,42}
wire _T_111 = _T_106 | _T_12 | _T_108 & _T_102; // MulAddRecFN.scala:529:{36,49}
wire _T_112 = _T_3 | _T_8 | _T_13 | _T_107; // MulAddRecFN.scala:530:47
assign io_out = {~_T_112 & (~_T_19 & _T_18 | _T_103 & ~(&_T_10) & _T_17 | ~_T_103 & &_T_10 & _T_18 |
~_T_103 & _T_104 & _T_19 & _T_16) | _T_105 & _T_76, _T_99 & ~(_T_104 | ~(|_T_75) | _T_100 ?
12'hE00 : 12'h0) & ~(_T_109 ? 12'hC31 : 12'h0) & {1'h1, ~_T_110, 10'h3FF} & {2'h3, ~_T_111,
9'h1FF} | (_T_109 ? 12'h3CE : 12'h0) | (_T_110 ? 12'hBFF : 12'h0) | (_T_111 ? 12'hC00 :
12'h0) | (_T_112 ? 12'hE00 : 12'h0), (_T_100 & _T_101 | _T_112 ? {_T_112, 51'h0} : _T_73 ?
_T_97[51:0] : _T_97[52:1]) | {52{_T_110}}}; // ../perf/regress/FPU.fir:5920:10, Bitwise.scala:71:12, Cat.scala:30:58, MulAddRecFN.scala:208:52, :220:52, :231:35, :271:13, :439:54, :490:{12,31,55}, :525:40, :533:51, :534:{24,51}, :535:{10,51,78}, :536:59, :538:{20,31,55,70}, :541:{14,18}, :545:{14,18}, :546:19, :549:{14,18}, :552:17, :553:{14,18}, :557:16, :558:16, :562:16, :565:15, :566:16, :568:{12,30,45}, :569:16, :571:11
assign io_exceptionFlags = {_T_3 & ~io_fromPreMul.isNaN_isQuietNaNA | _T_8 & ~io_fromPreMul.isNaN_isQuietNaNB | _T_13
& ~io_fromPreMul.isNaN_isQuietNaNC | _T_107, 1'h0, _T_108, _T_105 & _T_95 & (_T_78 | _T_77
<= {2'h0, _T_73 ? 11'h402 : 11'h401}), _T_108 | _T_105 & _T_95}; // ../perf/regress/FPU.fir:5920:10, Cat.scala:30:58, MulAddRecFN.scala:207:46, :211:{28,31}, :217:{28,31}, :223:{28,31}, :226:37, :499:35, :500:29, :501:26, :519:55, :521:32, :522:{28,43}
endmodule
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment