encoder.v

`default_nettype none
`timescale 1ns/1ns
module encoder (
    input clk,
    input reset,
    input a,
    input b,
    output reg [7:0] value
);

reg old_a;
reg old_b;

wire [3:0] inputs = {a, old_a, b, old_b};

always @(posedge clk) begin
    if (reset) begin
        old_a <= 0;
        old_b <= 0;
        value <= 0;
    end else begin
        if (inputs == 4'b1000 || inputs == 4'b0111) begin
            value <= value + 1;
        end else if (inputs === 4'b0010 || inputs == 4'b1101) begin
            value <= value - 1;
        end
        old_a = a;
        old_b = b;
    end
end

endmodule