Parallel Scan Wrapper

scan_wrapper.v

`default_nettype none
/*
`ifdef COCOTB
`define UNIT_DELAY #1
`define FUNCTIONAL
`define USE_POWER_PINS
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`endif
*/

module scan_wrapper_USER_MODULE_ID (
    input wire clk_in,
    input wire io_read_in,
    input wire io_write_in,
    input wire latch_in,
    input wire [8:0] chain_id_in,
    output wire clk_out,
    output wire io_read_out,
    output wire io_write_out,
    output wire latch_out,
    );
    
    assign io_read_out = io_read_in;
    assign latch_out = latch_in;
    assign clk_out = clk_in;
    wire clk = clk_in;

    /*
    `ifdef COCOTB
    initial begin
        $dumpfile ("scan_wrapper.vcd");
        $dumpvars (0, scan_wrapper_USER_MODULE_ID);
        #1;
    end
    `endif
    */

    reg selected;
    reg [7:0] io_read;
    reg [7:0] io_write;

    parameter NUM_IOS = 8;
    parameter REG_SIZE = NUM_IOS + 2; // 1 extra bit for address, 1 extra bit for selected

    wire selected_data = (scan_data_out[8:0] == chain_id_in);
    wire selected_gate = latch_in && scan_data_out[NUM_IOS-1];
    wire selected;                      // this module is currently active
 
    // wires needed
    wire [REG_SIZE-1:0] scan_data_out;  // output of the each scan chain flop
    wire [REG_SIZE-1:0] scan_data_in;   // input of each scan chain flop
    wire [NUM_IOS-1:0] module_data_in;  // the data that enters the user module
    wire [NUM_IOS-1:0] module_data_out; // the data from the user module

    // scan chain - link all the flops, with data coming from io_read_in
    assign scan_data_in = {scan_data_out[REG_SIZE-2:0], io_read_in};
    
    // end of the chain is the last scan flop's out
    assign io_write_out = selected ? scan_data_out[REG_SIZE-1] : io_write_in;

    `ifndef FORMAL
    `ifndef FORMAL_COMPAT

    // latch determines if this module is currently active
    sky130_fd_sc_hd__dlxtp_1 selected_latch (
        .D          (selected_data),
        .GATE       (selected_gate),
        .Q          (selected),
        .VPWR       (1'b1),
        .VGND       (1'b0)
    );

    // scan flops have a mux on their inputs to choose either data from the user module or the previous flop's output
    // https://antmicro-skywater-pdk-docs.readthedocs.io/en/test-submodules-in-rtd/contents/libraries/sky130_fd_sc_ls/cells/sdfxtp/README.html
    sky130_fd_sc_hd__sdfxtp_1 scan_flop [REG_SIZE-1:0] (
        .CLK        (clk), 
        .D          (scan_data_in),
        .SCD        ({2'b00, module_data_out}),
        .SCE        (latch_in),
        .Q          (scan_data_out),
        .VPWR       (1'b1),
        .VGND       (1'b0)
    );

    // latch is used to latch the input data of the user module while the scan chain is used to capture the user module's outputs
    // https://antmicro-skywater-pdk-docs.readthedocs.io/en/test-submodules-in-rtd/contents/libraries/sky130_fd_sc_hd/cells/dlxtp/README.html
    sky130_fd_sc_hd__dlxtp_1 latch [NUM_IOS-1:0] (
        .D          (scan_data_out[NUM_IOS-1:0]),
        .GATE       (latch_in),
        .Q          (module_data_in),
        .VPWR       (1'b1),
        .VGND       (1'b0)
    );
    `endif
    `endif

    // instantiate the wokwi module
    user_module_USER_MODULE_ID user_module(
        .io_in     (module_data_in),
        .io_out    (module_data_out)
    );

endmodule