gistfile1.txt

*** Running vivado
    with args -log top.vds -m64 -mode batch -messageDb vivado.pb -notrace -source top.tcl


****** Vivado v2016.2 (64-bit)
  **** SW Build 1577090 on Thu Jun  2 16:32:35 MDT 2016
  **** IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source top.tcl -notrace
Command: synth_design -top top -part xc7a100tcsg324-3
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 11615 
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Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1005.238 ; gain = 129.137 ; free physical = 483 ; free virtual = 18441
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INFO: [Synth 8-638] synthesizing module 'top' [/home/vadix/project/system/uarc/core/0/nexys4/src/top.sv:1]
INFO: [Synth 8-256] done synthesizing module 'top' (1#1) [/home/vadix/project/system/uarc/core/0/nexys4/src/top.sv:1]
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Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1044.676 ; gain = 168.574 ; free physical = 443 ; free virtual = 18401
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Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1044.676 ; gain = 168.574 ; free physical = 443 ; free virtual = 18401
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INFO: [Device 21-403] Loading part xc7a100tcsg324-3
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/vadix/project/system/uarc/core/0/nexys4/Nexys4_Master.xdc]
Finished Parsing XDC File [/home/vadix/project/system/uarc/core/0/nexys4/Nexys4_Master.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/vadix/project/system/uarc/core/0/nexys4/Nexys4_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1339.629 ; gain = 0.000 ; free physical = 275 ; free virtual = 18234
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Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1339.629 ; gain = 463.527 ; free physical = 275 ; free virtual = 18233
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Start Loading Part and Timing Information
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Loading part: xc7a100tcsg324-3
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1339.629 ; gain = 463.527 ; free physical = 275 ; free virtual = 18233
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Start Applying 'set_property' XDC Constraints
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1339.629 ; gain = 463.527 ; free physical = 275 ; free virtual = 18233
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1339.629 ; gain = 463.527 ; free physical = 267 ; free virtual = 18225
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Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
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Start RTL Component Statistics 
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Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
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Finished RTL Component Statistics 
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Start RTL Hierarchical Component Statistics 
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Hierarchical RTL Component report 
Module top 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
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Finished RTL Hierarchical Component Statistics
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Start Part Resource Summary
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Abnormal program termination (11)
Please check '/home/vadix/project/system/uarc/core/0/nexys4/nexys4.runs/synth_1/hs_err_pid11612.log' for details
Parent process (pid 11612) has died. This helper process will now exit