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I'm a broken fence in the yard of annoyance.

whitequark whitequark

I'm a broken fence in the yard of annoyance.
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This document was originally written several years ago. At the time I was working as an execution core verification engineer at Arm. The following points are coloured heavily by working in and around the execution cores of various processors. Apply a pinch of salt; points contain varying degrees of opinion.

It is still my opinion that RISC-V could be much better designed; though I will also say that if I was building a 32 or 64-bit CPU today I'd likely implement the architecture to benefit from the existing tooling.

Mostly based upon the RISC-V ISA spec v2.0. Some updates have been made for v2.2

Original Foreword: Some Opinion

The RISC-V ISA has pursued minimalism to a fault. There is a large emphasis on minimizing instruction count, normalizing encoding, etc. This pursuit of minimalism has resulted in false orthogonalities (such as reusing the same instruction for branches, calls and returns) and a requirement for superfluous instructions which impacts code density both in terms of size and

#!/usr/bin/env python3
import sys
import textwrap
# Very basic bitstream to SVF converter, tested with the ULX3S WiFi interface
flash_page_size = 256
erase_block_size = 64*1024
smunaut /
Last active May 5, 2020
iCE40 Global Networks

UP5k SG48:

ID Use SB_IO_GB SB_GB Special
x/y/z (pin) x/y x/y type
0 Clk / Reset 19/ 0/1 (20) 13/ 0
1 Clk / CE 6/ 0/1 (44) 13/31
2 Clk / Reset 13/31/0 (37) 19/31 12/31 PLL_B
3 Clk / CE 6/31
marcan / ghettohci.c
Created Apr 24, 2018
GhettOHCI - perhaps the world's smallest and stupidest OHCI stack.
View ghettohci.c
mini - a Free Software replacement for the Nintendo/BroadOn IOS.
ghettohci - debug over FT232 over OHCI
Copyright (C) 2012 Hector Martin "marcan" <>
# This code is licensed to you under the terms of the GNU GPL, version 2;
# see file COPYING or
pdn4kd /
Last active May 23, 2020 — forked from eggrobin/
#kspacademia topicquotes

The conversation that led to the creation of the channel:

<ferram4|afk> So, I continue following references on supersonic wing stuff,
and I find a paper that tries to tweak linear supersonic flow to work for
high AoA, hypersonic flight.
<KinglyRedLion> the FUCK
<ferram4|afk> I love technical papers. ^_^
<KinglyRedLion> Why would you do high AOA hypersonic?
<egg|zzz|egg> KinglyRedLion: to publish
essen /
Last active Mar 26, 2017
HTTP and related specifications
kachayev /
Last active Aug 9, 2020
Channels Are Not Enough or Why Pipelining Is Not That Easy
View gist:9176925
static OSStatus
SSLVerifySignedServerKeyExchange(SSLContext *ctx, bool isRsa, SSLBuffer signedParams,
uint8_t *signature, UInt16 signatureLen)
OSStatus err;
SSLBuffer hashOut, hashCtx, clientRandom, serverRandom;
SSLBuffer signedHashes;
uint8_t *dataToSign;
size_t dataToSignLen;
jvns /
Last active Apr 16, 2020
Tech blogs I subscribe to
gasche /
Created Nov 20, 2013
A type-conv syntax extension to convert constant constructors into consecutive integers.
(*pp camlp4orf *)
(* ty_enum_to_int : Camlp4 (3.10) Syntax extension
type test = | A | B | C | D with to_int
translates to :
type test = | A | B | C | D
let test_to_int = function | A -> 0 | B -> 1 | C -> 2 | D -> 3
let test_of_int = function | 0 -> A | 1 -> B | 2 -> C | 3 -> D
Compilation command :
You can’t perform that action at this time.