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@cfelton
Created October 2, 2013 02:06
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myhdl function conversion example
from myhdl import *
def simple_add(a,b,):
c = a + b
return c
def top(clock,reset,a,b,c):
@always_seq(clock.posedge, reset=reset)
def rtl():
c.next = simple_add(a,b)
return rtl
def convert():
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
a,b,c = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)]
toVerilog(top,clock,reset,a,b,c)
toVHDL(top,clock,reset,a,b,c)
if __name__ == '__main__':
convert()
// File: top.v
// Generated by MyHDL 0.9dev
// Date: Tue Oct 1 21:00:00 2013
`timescale 1ns/10ps
module top (
clock,
reset,
a,
b,
c
);
input clock;
input reset;
input signed [3:0] a;
input signed [3:0] b;
output signed [3:0] c;
reg signed [3:0] c;
function integer MYHDL2_simple_add;
input signed [4-1:0] a;
input signed [4-1:0] b;
integer c;
begin: MYHDL3_RETURN
c = (a + b);
MYHDL2_simple_add = c;
disable MYHDL3_RETURN;
end
endfunction
always @(posedge clock, negedge reset) begin: TOP_RTL
if (reset == 0) begin
c <= 0;
end
else begin
c <= MYHDL2_simple_add(a, b);
end
end
endmodule
-- File: top.vhd
-- Generated by MyHDL 0.9dev
-- Date: Tue Oct 1 21:00:00 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_09.all;
entity top is
port (
clock: in std_logic;
reset: in std_logic;
a: in signed (3 downto 0);
b: in signed (3 downto 0);
c: out signed (3 downto 0)
);
end entity top;
architecture MyHDL of top is
function MYHDL5_simple_add(
a: in signed;
b: in signed
) return integer is
variable c: integer;
begin
c := to_integer(a + b);
return c;
end function MYHDL5_simple_add;
begin
TOP_RTL: process (clock, reset) is
begin
if (reset = '0') then
c <= to_signed(0, 4);
elsif rising_edge(clock) then
c <= MYHDL5_simple_add(a, b);
end if;
end process TOP_RTL;
end architecture MyHDL;
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