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@cfelton
Forked from ravijain056/mem2d_edit.py
Last active August 29, 2015 14:17
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from random import randint
from myhdl import *
def switchchannels(mem2d, q, clk):
@always(clk.posedge)
def switch():
#print('switch')
#print(mem2d)
x = mem2d[0]
mem2d[0] = mem2d[1]
mem2d[1] = x
#print(mem2d)
@always(clk.posedge)
def logic():
#print('logic')
#print(q, mem2d)
mem2d[0][0].next = mem2d[0][1]
mem2d[0][1].next = q
#print(mem2d)
return switch, logic
from random import randrange
def test_switchchannels():
clk = Signal(bool(0))
q = Signal(intbv(0)[4:])
mem2d = [[Signal(intbv(0)[4:]), Signal(intbv(0)[4:])] ,
[Signal(intbv(1)[4:]), Signal(intbv(1)[4:])]]
print('init')
print(q)
print(clk)
print(mem2d)
switch_inst = switchchannels(mem2d, q, clk)
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
for ii in range(10):
q.next = randint(0,15)
print("time {:<8d}: q = {}".format(now(), int(q)))
for ii,row in enumerate(mem2d):
print(" {}: {:4d} {:4d}".format(ii, *map(int, row)))
yield clk.posedge
raise StopSimulation
return switch_inst, clkgen, stimulus
def simulate(timesteps):
traceSignals.timescale = "1ps"
tb = traceSignals(test_switchchannels)
sim = Simulation(tb)
sim.run()
simulate(40)
@cfelton
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cfelton commented Mar 27, 2015

Output

$ python mem2d_edit.py
init
0
False
[[Signal(intbv(0L)), Signal(intbv(0L))], [Signal(intbv(1L)), Signal(intbv(1L))]]
time 0       : q = 0
   0:    0     0
   1:    1     1
time 10      : q = 10
   0:    1     1
   1:    0     0
time 30      : q = 7
   0:    1    10
   1:    0     0
time 50      : q = 0
   0:   10     7
   1:    0     0
time 70      : q = 9
   0:    7     0
   1:    0     0
time 90      : q = 2
   0:    0     9
   1:    0     0
time 110     : q = 13
   0:    9     2
   1:    0     0
time 130     : q = 14
   0:    2    13
   1:    0     0
time 150     : q = 1
   0:   13    14
   1:    0     0
time 170     : q = 14
   0:   14     1
   1:    0     0

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