A Verilog VGA module

/* A Verilog VGA module without state machines or weird bit assignments.
 * Works with 50MHz clock, 800x600@72Hz. */
module vga(clk, in_R, in_G, in_B, out_R, out_G, out_B, Hsync, Vsync, video_on, x, y);

input clk, in_R, in_G, in_B;

output wire out_R, out_G, out_B, Hsync, Vsync, video_on;
output reg[9:0] x, y;

/* counters. increment y at the start of hsync. reset x at the end of front porch. */
always @(posedge clk) begin
	if(x == 858) y <= y + 1;
	if(x == 1022) x <= 10'b0;
	else x <= x + 1;

	if(y == 666) y <= 10'b0;
end

assign video_on = (x < 800 && y < 600);
assign out_R = video_on ? in_R : 1'b0;
assign out_G = video_on ? in_G : 1'b0;
assign out_B = video_on ? in_B : 1'b0;

assign Hsync = ~(x > 858 && x < 970);
assign Vsync = ~(y > 623 && y < 629);

endmodule