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January 6, 2012 22:00
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base_instructionset.h
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| #ifndef BASE_INSTRUCTIONSET_H | |
| #define BASE_INSTRUCTIONSET_H | |
| #include "cpu.h" | |
| #include "instructions.h" | |
| #include "instructionset.h" | |
| #include "references.h" | |
| void initialize_base_instructionset(InstructionSet *instructionSet, CPU *cpu) { | |
| Instruction *op0; | |
| ReferenceInstruction<byte> *op1; | |
| ReferenceInstruction<word> *op2; | |
| // 00 1 4 NOP | |
| op0 = new NOP_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0x00; | |
| op0->length = 1; | |
| op0->cycles0 = 4; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "NOP"; | |
| instructionSet->add(op0); | |
| // 01 3 12 LD BC,d16 | |
| op2 = new LD_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x01; | |
| op2->length = 3; | |
| op2->cycles0 = 12; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "LD BC,d16"; | |
| op2->ref0 = new RegisterReference<word>(cpu->bc); | |
| op2->ref1 = new MemoryReference<word>(cpu, cpu->pc); | |
| instructionSet->add(op2); | |
| // 03 1 8 INC BC | |
| op2 = new INC_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x03; | |
| op2->length = 1; | |
| op2->cycles0 = 8; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "INC BC"; | |
| op2->ref0 = new RegisterReference<word>(cpu->bc); | |
| instructionSet->add(op2); | |
| // 04 1 4 INC B | |
| op1 = new INC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x04; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "INC B"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->b); | |
| instructionSet->add(op1); | |
| // 05 1 4 DEC B | |
| op1 = new DEC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x05; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "DEC B"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->b); | |
| instructionSet->add(op1); | |
| // 06 2 8 LD B,d8 | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x06; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD B,d8"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->b); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // 07 1 4 RLCA | |
| op0 = new RLCA_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0x07; | |
| op0->length = 1; | |
| op0->cycles0 = 4; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "RLCA"; | |
| instructionSet->add(op0); | |
| // 08 3 20 LD [a16],SP | |
| op2 = new LD_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x08; | |
| op2->length = 3; | |
| op2->cycles0 = 20; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "LD [a16],SP"; | |
| op2->ref0 = new Memory_a16_Reference<word>(cpu, cpu->pc); | |
| op2->ref1 = new RegisterReference<word>(cpu->sp); | |
| instructionSet->add(op2); | |
| // 09 1 8 ADD HL,BC | |
| op2 = new ADD_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x09; | |
| op2->length = 1; | |
| op2->cycles0 = 8; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "ADD HL,BC"; | |
| op2->ref0 = new RegisterReference<word>(cpu->hl); | |
| op2->ref1 = new RegisterReference<word>(cpu->bc); | |
| instructionSet->add(op2); | |
| // 0a 1 8 LD A,(BC) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x0a; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,(BC)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->bc); | |
| instructionSet->add(op1); | |
| // 0b 1 8 DEC BC | |
| op2 = new DEC_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x0b; | |
| op2->length = 1; | |
| op2->cycles0 = 8; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "DEC BC"; | |
| op2->ref0 = new RegisterReference<word>(cpu->bc); | |
| instructionSet->add(op2); | |
| // 0c 1 4 INC C | |
| op1 = new INC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x0c; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "INC C"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->c); | |
| instructionSet->add(op1); | |
| // 0d 1 4 DEC C | |
| op1 = new DEC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x0d; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "DEC C"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->c); | |
| instructionSet->add(op1); | |
| // 0e 2 8 LD C,d8 | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x0e; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD C,d8"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->c); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // 0f 1 4 RRCA | |
| op0 = new RRCA_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0x0f; | |
| op0->length = 1; | |
| op0->cycles0 = 4; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "RRCA"; | |
| instructionSet->add(op0); | |
| // 11 3 12 LD DE,d16 | |
| op2 = new LD_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x11; | |
| op2->length = 3; | |
| op2->cycles0 = 12; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "LD DE,d16"; | |
| op2->ref0 = new RegisterReference<word>(cpu->de); | |
| op2->ref1 = new MemoryReference<word>(cpu, cpu->pc); | |
| instructionSet->add(op2); | |
| // 12 1 8 LD (DE),A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x12; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (DE),A"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->de); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 13 1 8 INC DE | |
| op2 = new INC_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x13; | |
| op2->length = 1; | |
| op2->cycles0 = 8; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "INC DE"; | |
| op2->ref0 = new RegisterReference<word>(cpu->de); | |
| instructionSet->add(op2); | |
| // 15 1 4 DEC D | |
| op1 = new DEC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x15; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "DEC D"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->d); | |
| instructionSet->add(op1); | |
| // 16 2 8 LD D,d8 | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x16; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD D,d8"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->d); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // 17 1 4 RLA | |
| op0 = new RLA_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0x17; | |
| op0->length = 1; | |
| op0->cycles0 = 4; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "RLA"; | |
| instructionSet->add(op0); | |
| // 18 2 12 JR r8 | |
| op1 = new JR_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x18; | |
| op1->length = 2; | |
| op1->cycles0 = 12; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "JR r8"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // 19 1 8 ADD HL,DE | |
| op2 = new ADD_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x19; | |
| op2->length = 1; | |
| op2->cycles0 = 8; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "ADD HL,DE"; | |
| op2->ref0 = new RegisterReference<word>(cpu->hl); | |
| op2->ref1 = new RegisterReference<word>(cpu->de); | |
| instructionSet->add(op2); | |
| // 1a 1 8 LD A,(DE) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x1a; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,(DE)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->de); | |
| instructionSet->add(op1); | |
| // 1c 1 4 INC E | |
| op1 = new INC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x1c; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "INC E"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->e); | |
| instructionSet->add(op1); | |
| // 1d 1 4 DEC E | |
| op1 = new DEC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x1d; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "DEC E"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->e); | |
| instructionSet->add(op1); | |
| // 1e 2 8 LD E,d8 | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x1e; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD E,d8"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->e); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // 20 2 12/8 JR NZ,r8 | |
| op1 = new JR_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x20; | |
| op1->length = 2; | |
| op1->cycles0 = 12; | |
| op1->cycles1 = 8; | |
| op1->mnemonic = "JR NZ,r8"; | |
| op1->condition = new NZ_Condition(); | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // 21 3 12 LD HL,d16 | |
| op2 = new LD_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x21; | |
| op2->length = 3; | |
| op2->cycles0 = 12; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "LD HL,d16"; | |
| op2->ref0 = new RegisterReference<word>(cpu->hl); | |
| op2->ref1 = new MemoryReference<word>(cpu, cpu->pc); | |
| instructionSet->add(op2); | |
| // 22 1 8 LD (HL+),A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x22; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (HL+),A"; | |
| op1->ref0 = new Memory_HL_Reference<byte>(cpu, cpu->hl, 1); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 23 1 8 INC HL | |
| op2 = new INC_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x23; | |
| op2->length = 1; | |
| op2->cycles0 = 8; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "INC HL"; | |
| op2->ref0 = new RegisterReference<word>(cpu->hl); | |
| instructionSet->add(op2); | |
| // 24 1 4 INC H | |
| op1 = new INC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x24; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "INC H"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->h); | |
| instructionSet->add(op1); | |
| // 26 2 8 LD H,d8 | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x26; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD H,d8"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->h); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // 28 2 12/8 JR Z,r8 | |
| op1 = new JR_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x28; | |
| op1->length = 2; | |
| op1->cycles0 = 12; | |
| op1->cycles1 = 8; | |
| op1->mnemonic = "JR Z,r8"; | |
| op1->condition = new Z_Condition(); | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // 2a 1 8 LD A,(HL+) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x2a; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,(HL+)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new Memory_HL_Reference<byte>(cpu, cpu->hl, 1); | |
| instructionSet->add(op1); | |
| // 2c 1 4 INC L | |
| op1 = new INC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x2c; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "INC L"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->l); | |
| instructionSet->add(op1); | |
| // 2d 1 4 DEC L | |
| op1 = new DEC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x2d; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "DEC L"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->l); | |
| instructionSet->add(op1); | |
| // 2f 1 4 CPL | |
| op0 = new CPL_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0x2f; | |
| op0->length = 1; | |
| op0->cycles0 = 4; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "CPL"; | |
| instructionSet->add(op0); | |
| // 31 3 12 LD SP,d16 | |
| op2 = new LD_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x31; | |
| op2->length = 3; | |
| op2->cycles0 = 12; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "LD SP,d16"; | |
| op2->ref0 = new RegisterReference<word>(cpu->sp); | |
| op2->ref1 = new MemoryReference<word>(cpu, cpu->pc); | |
| instructionSet->add(op2); | |
| // 32 1 8 LD (HL-),A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x32; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (HL-),A"; | |
| op1->ref0 = new Memory_HL_Reference<byte>(cpu, cpu->hl, -1); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 34 1 12 INC (HL) | |
| op1 = new INC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x34; | |
| op1->length = 1; | |
| op1->cycles0 = 12; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "INC (HL)"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->hl); | |
| instructionSet->add(op1); | |
| // 35 1 12 DEC (HL) | |
| op1 = new DEC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x35; | |
| op1->length = 1; | |
| op1->cycles0 = 12; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "DEC (HL)"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->hl); | |
| instructionSet->add(op1); | |
| // 36 2 12 LD (HL),d8 | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x36; | |
| op1->length = 2; | |
| op1->cycles0 = 12; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (HL),d8"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->hl); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // 37 1 4 SCF | |
| op0 = new SCF_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0x37; | |
| op0->length = 1; | |
| op0->cycles0 = 4; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "SCF"; | |
| instructionSet->add(op0); | |
| // 39 1 8 ADD HL,SP | |
| op2 = new ADD_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0x39; | |
| op2->length = 1; | |
| op2->cycles0 = 8; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "ADD HL,SP"; | |
| op2->ref0 = new RegisterReference<word>(cpu->hl); | |
| op2->ref1 = new RegisterReference<word>(cpu->sp); | |
| instructionSet->add(op2); | |
| // 3a 1 8 LD A,(HL-) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x3a; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,(HL-)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new Memory_HL_Reference<byte>(cpu, cpu->hl, -1); | |
| instructionSet->add(op1); | |
| // 3c 1 4 INC A | |
| op1 = new INC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x3c; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "INC A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 3d 1 4 DEC A | |
| op1 = new DEC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x3d; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "DEC A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 3e 2 8 LD A,d8 | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x3e; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,d8"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // 40 1 4 LD B,B | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x40; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD B,B"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->b); | |
| op1->ref1 = new RegisterReference<byte>(cpu->b); | |
| instructionSet->add(op1); | |
| // 41 1 4 LD B,C | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x41; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD B,C"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->b); | |
| op1->ref1 = new RegisterReference<byte>(cpu->c); | |
| instructionSet->add(op1); | |
| // 43 1 4 LD B,E | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x43; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD B,E"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->b); | |
| op1->ref1 = new RegisterReference<byte>(cpu->e); | |
| instructionSet->add(op1); | |
| // 46 1 8 LD B,(HL) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x46; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD B,(HL)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->b); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->hl); | |
| instructionSet->add(op1); | |
| // 47 1 4 LD B,A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x47; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD B,A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->b); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 4b 1 4 LD C,E | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x4b; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD C,E"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->c); | |
| op1->ref1 = new RegisterReference<byte>(cpu->e); | |
| instructionSet->add(op1); | |
| // 4c 1 4 LD C,H | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x4c; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD C,H"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->c); | |
| op1->ref1 = new RegisterReference<byte>(cpu->h); | |
| instructionSet->add(op1); | |
| // 4e 1 8 LD C,(HL) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x4e; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD C,(HL)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->c); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->hl); | |
| instructionSet->add(op1); | |
| // 4f 1 4 LD C,A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x4f; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD C,A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->c); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 54 1 4 LD D,H | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x54; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD D,H"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->d); | |
| op1->ref1 = new RegisterReference<byte>(cpu->h); | |
| instructionSet->add(op1); | |
| // 56 1 8 LD D,(HL) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x56; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD D,(HL)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->d); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->hl); | |
| instructionSet->add(op1); | |
| // 57 1 4 LD D,A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x57; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD D,A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->d); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 5a 1 4 LD E,D | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x5a; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD E,D"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->e); | |
| op1->ref1 = new RegisterReference<byte>(cpu->d); | |
| instructionSet->add(op1); | |
| // 5d 1 4 LD E,L | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x5d; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD E,L"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->e); | |
| op1->ref1 = new RegisterReference<byte>(cpu->l); | |
| instructionSet->add(op1); | |
| // 5e 1 8 LD E,(HL) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x5e; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD E,(HL)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->e); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->hl); | |
| instructionSet->add(op1); | |
| // 5f 1 4 LD E,A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x5f; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD E,A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->e); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 60 1 4 LD H,B | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x60; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD H,B"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->h); | |
| op1->ref1 = new RegisterReference<byte>(cpu->b); | |
| instructionSet->add(op1); | |
| // 62 1 4 LD H,D | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x62; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD H,D"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->h); | |
| op1->ref1 = new RegisterReference<byte>(cpu->d); | |
| instructionSet->add(op1); | |
| // 67 1 4 LD H,A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x67; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD H,A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->h); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 69 1 4 LD L,C | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x69; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD L,C"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->l); | |
| op1->ref1 = new RegisterReference<byte>(cpu->c); | |
| instructionSet->add(op1); | |
| // 6b 1 4 LD L,E | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x6b; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD L,E"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->l); | |
| op1->ref1 = new RegisterReference<byte>(cpu->e); | |
| instructionSet->add(op1); | |
| // 6f 1 4 LD L,A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x6f; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD L,A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->l); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 70 1 8 LD (HL),B | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x70; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (HL),B"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->hl); | |
| op1->ref1 = new RegisterReference<byte>(cpu->b); | |
| instructionSet->add(op1); | |
| // 71 1 8 LD (HL),C | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x71; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (HL),C"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->hl); | |
| op1->ref1 = new RegisterReference<byte>(cpu->c); | |
| instructionSet->add(op1); | |
| // 72 1 8 LD (HL),D | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x72; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (HL),D"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->hl); | |
| op1->ref1 = new RegisterReference<byte>(cpu->d); | |
| instructionSet->add(op1); | |
| // 73 1 8 LD (HL),E | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x73; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (HL),E"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->hl); | |
| op1->ref1 = new RegisterReference<byte>(cpu->e); | |
| instructionSet->add(op1); | |
| // 74 1 8 LD (HL),H | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x74; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (HL),H"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->hl); | |
| op1->ref1 = new RegisterReference<byte>(cpu->h); | |
| instructionSet->add(op1); | |
| // 77 1 8 LD (HL),A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x77; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (HL),A"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->hl); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 78 1 4 LD A,B | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x78; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,B"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->b); | |
| instructionSet->add(op1); | |
| // 79 1 4 LD A,C | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x79; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,C"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->c); | |
| instructionSet->add(op1); | |
| // 7a 1 4 LD A,D | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x7a; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,D"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->d); | |
| instructionSet->add(op1); | |
| // 7b 1 4 LD A,E | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x7b; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,E"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->e); | |
| instructionSet->add(op1); | |
| // 7c 1 4 LD A,H | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x7c; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,H"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->h); | |
| instructionSet->add(op1); | |
| // 7d 1 4 LD A,L | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x7d; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,L"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->l); | |
| instructionSet->add(op1); | |
| // 7e 1 8 LD A,(HL) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x7e; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,(HL)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->hl); | |
| instructionSet->add(op1); | |
| // 7f 1 4 LD A,A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x7f; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 80 1 4 ADD A,B | |
| op1 = new ADD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x80; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "ADD A,B"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->b); | |
| instructionSet->add(op1); | |
| // 85 1 4 ADD A,L | |
| op1 = new ADD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x85; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "ADD A,L"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->l); | |
| instructionSet->add(op1); | |
| // 87 1 4 ADD A,A | |
| op1 = new ADD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x87; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "ADD A,A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // 89 1 4 ADC A,C | |
| op1 = new ADC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x89; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "ADC A,C"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->c); | |
| instructionSet->add(op1); | |
| // 95 1 4 SUB L | |
| op1 = new SUB_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x95; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "SUB L"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->l); | |
| instructionSet->add(op1); | |
| // 9b 1 4 SBC A,E | |
| op1 = new SBC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0x9b; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "SBC A,E"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new RegisterReference<byte>(cpu->e); | |
| instructionSet->add(op1); | |
| // a1 1 4 AND C | |
| op1 = new AND_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xa1; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "AND C"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->c); | |
| instructionSet->add(op1); | |
| // a7 1 4 AND A | |
| op1 = new AND_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xa7; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "AND A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // a9 1 4 XOR C | |
| op1 = new XOR_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xa9; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "XOR C"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->c); | |
| instructionSet->add(op1); | |
| // af 1 4 XOR A | |
| op1 = new XOR_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xaf; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "XOR A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // b0 1 4 OR B | |
| op1 = new OR_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xb0; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "OR B"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->b); | |
| instructionSet->add(op1); | |
| // b1 1 4 OR C | |
| op1 = new OR_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xb1; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "OR C"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->c); | |
| instructionSet->add(op1); | |
| // b7 1 4 OR A | |
| op1 = new OR_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xb7; | |
| op1->length = 1; | |
| op1->cycles0 = 4; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "OR A"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // be 1 8 CP (HL) | |
| op1 = new CP_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xbe; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "CP (HL)"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->hl); | |
| instructionSet->add(op1); | |
| // c0 1 20/8 RET NZ | |
| op0 = new RET_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xc0; | |
| op0->length = 1; | |
| op0->cycles0 = 20; | |
| op0->cycles1 = 8; | |
| op0->mnemonic = "RET NZ"; | |
| op0->condition = new NZ_Condition(); | |
| instructionSet->add(op0); | |
| // c1 1 12 POP BC | |
| op2 = new POP_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xc1; | |
| op2->length = 1; | |
| op2->cycles0 = 12; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "POP BC"; | |
| op2->ref0 = new RegisterReference<word>(cpu->bc); | |
| instructionSet->add(op2); | |
| // c2 3 16/12 JP NZ,a16 | |
| op2 = new JP_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xc2; | |
| op2->length = 3; | |
| op2->cycles0 = 16; | |
| op2->cycles1 = 12; | |
| op2->mnemonic = "JP NZ,a16"; | |
| op2->condition = new NZ_Condition(); | |
| op2->ref0 = new MemoryReference<word>(cpu, cpu->pc); | |
| instructionSet->add(op2); | |
| // c3 3 16 JP a16 | |
| op2 = new JP_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xc3; | |
| op2->length = 3; | |
| op2->cycles0 = 16; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "JP a16"; | |
| op2->ref0 = new MemoryReference<word>(cpu, cpu->pc); | |
| instructionSet->add(op2); | |
| // c5 1 16 PUSH BC | |
| op2 = new PUSH_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xc5; | |
| op2->length = 1; | |
| op2->cycles0 = 16; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "PUSH BC"; | |
| op2->ref0 = new RegisterReference<word>(cpu->bc); | |
| instructionSet->add(op2); | |
| // c6 2 8 ADD A,d8 | |
| op1 = new ADD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xc6; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "ADD A,d8"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // c8 1 20/8 RET Z | |
| op0 = new RET_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xc8; | |
| op0->length = 1; | |
| op0->cycles0 = 20; | |
| op0->cycles1 = 8; | |
| op0->mnemonic = "RET Z"; | |
| op0->condition = new Z_Condition(); | |
| instructionSet->add(op0); | |
| // c9 1 16 RET | |
| op0 = new RET_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xc9; | |
| op0->length = 1; | |
| op0->cycles0 = 16; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "RET"; | |
| instructionSet->add(op0); | |
| // ca 3 16/12 JP Z,a16 | |
| op2 = new JP_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xca; | |
| op2->length = 3; | |
| op2->cycles0 = 16; | |
| op2->cycles1 = 12; | |
| op2->mnemonic = "JP Z,a16"; | |
| op2->condition = new Z_Condition(); | |
| op2->ref0 = new MemoryReference<word>(cpu, cpu->pc); | |
| instructionSet->add(op2); | |
| // cb 1 0 CB | |
| op0 = new CB_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xcb; | |
| op0->length = 1; | |
| op0->cycles0 = 0; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "CB"; | |
| instructionSet->add(op0); | |
| // cd 3 24 CALL a16 | |
| op2 = new CALL_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xcd; | |
| op2->length = 3; | |
| op2->cycles0 = 24; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "CALL a16"; | |
| op2->ref0 = new MemoryReference<word>(cpu, cpu->pc); | |
| instructionSet->add(op2); | |
| // cf 1 16 RST 16H | |
| op0 = new RST_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xcf; | |
| op0->length = 1; | |
| op0->cycles0 = 16; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "RST 16H"; | |
| op0->arg = 0x16; | |
| instructionSet->add(op0); | |
| // d0 1 20/8 RET NC | |
| op0 = new RET_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xd0; | |
| op0->length = 1; | |
| op0->cycles0 = 20; | |
| op0->cycles1 = 8; | |
| op0->mnemonic = "RET NC"; | |
| op0->condition = new NC_Condition(); | |
| instructionSet->add(op0); | |
| // d1 1 12 POP DE | |
| op2 = new POP_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xd1; | |
| op2->length = 1; | |
| op2->cycles0 = 12; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "POP DE"; | |
| op2->ref0 = new RegisterReference<word>(cpu->de); | |
| instructionSet->add(op2); | |
| // d5 1 16 PUSH DE | |
| op2 = new PUSH_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xd5; | |
| op2->length = 1; | |
| op2->cycles0 = 16; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "PUSH DE"; | |
| op2->ref0 = new RegisterReference<word>(cpu->de); | |
| instructionSet->add(op2); | |
| // d6 2 8 SUB d8 | |
| op1 = new SUB_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xd6; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "SUB d8"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // d8 1 20/8 RET C | |
| op0 = new RET_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xd8; | |
| op0->length = 1; | |
| op0->cycles0 = 20; | |
| op0->cycles1 = 8; | |
| op0->mnemonic = "RET C"; | |
| op0->condition = new C_Condition(); | |
| instructionSet->add(op0); | |
| // d9 1 16 RETI | |
| op0 = new RETI_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xd9; | |
| op0->length = 1; | |
| op0->cycles0 = 16; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "RETI"; | |
| instructionSet->add(op0); | |
| // dc 3 24/12 CALL C,a16 | |
| op2 = new CALL_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xdc; | |
| op2->length = 3; | |
| op2->cycles0 = 24; | |
| op2->cycles1 = 12; | |
| op2->mnemonic = "CALL C,a16"; | |
| op2->condition = new C_Condition(); | |
| op2->ref0 = new MemoryReference<word>(cpu, cpu->pc); | |
| instructionSet->add(op2); | |
| // de 2 8 SBC A,d8 | |
| op1 = new SBC_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xde; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "SBC A,d8"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // df 1 16 RST 18H | |
| op0 = new RST_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xdf; | |
| op0->length = 1; | |
| op0->cycles0 = 16; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "RST 18H"; | |
| op0->arg = 0x18; | |
| instructionSet->add(op0); | |
| // e0 2 12 LD (a8),A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xe0; | |
| op1->length = 2; | |
| op1->cycles0 = 12; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (a8),A"; | |
| op1->ref0 = new Memory_a8_Reference<byte>(cpu, cpu->pc); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // e1 1 12 POP HL | |
| op2 = new POP_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xe1; | |
| op2->length = 1; | |
| op2->cycles0 = 12; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "POP HL"; | |
| op2->ref0 = new RegisterReference<word>(cpu->hl); | |
| instructionSet->add(op2); | |
| // e2 1 8 LD (C),A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xe2; | |
| op1->length = 1; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (C),A"; | |
| op1->ref0 = new Memory_SingleRegister_Reference<byte>(cpu, cpu->c); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // e5 1 16 PUSH HL | |
| op2 = new PUSH_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xe5; | |
| op2->length = 1; | |
| op2->cycles0 = 16; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "PUSH HL"; | |
| op2->ref0 = new RegisterReference<word>(cpu->hl); | |
| instructionSet->add(op2); | |
| // e6 2 8 AND d8 | |
| op1 = new AND_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xe6; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "AND d8"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // e9 1 4 JP HL | |
| op2 = new JP_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xe9; | |
| op2->length = 1; | |
| op2->cycles0 = 4; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "JP HL"; | |
| op2->ref0 = new RegisterReference<word>(cpu->hl); | |
| instructionSet->add(op2); | |
| // ea 3 16 LD (a16),A | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xea; | |
| op1->length = 3; | |
| op1->cycles0 = 16; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD (a16),A"; | |
| op1->ref0 = new Memory_a16_Reference<byte>(cpu, cpu->pc); | |
| op1->ref1 = new RegisterReference<byte>(cpu->a); | |
| instructionSet->add(op1); | |
| // ee 2 8 XOR d8 | |
| op1 = new XOR_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xee; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "XOR d8"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // ef 1 16 RST 28H | |
| op0 = new RST_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xef; | |
| op0->length = 1; | |
| op0->cycles0 = 16; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "RST 28H"; | |
| op0->arg = 0x28; | |
| instructionSet->add(op0); | |
| // f0 2 12 LD A,(a8) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xf0; | |
| op1->length = 2; | |
| op1->cycles0 = 12; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,(a8)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new Memory_a8_Reference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // f1 1 12 POP AF | |
| op2 = new POP_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xf1; | |
| op2->length = 1; | |
| op2->cycles0 = 12; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "POP AF"; | |
| op2->ref0 = new RegisterReference<word>(cpu->af); | |
| instructionSet->add(op2); | |
| // f3 1 4 DI | |
| op0 = new DI_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xf3; | |
| op0->length = 1; | |
| op0->cycles0 = 4; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "DI"; | |
| instructionSet->add(op0); | |
| // f5 1 16 PUSH AF | |
| op2 = new PUSH_Instruction<word>(); | |
| op2->cpu = cpu; | |
| op2->code = 0xf5; | |
| op2->length = 1; | |
| op2->cycles0 = 16; | |
| op2->cycles1 = 0; | |
| op2->mnemonic = "PUSH AF"; | |
| op2->ref0 = new RegisterReference<word>(cpu->af); | |
| instructionSet->add(op2); | |
| // f6 2 8 OR d8 | |
| op1 = new OR_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xf6; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "OR d8"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // fa 3 16 LD A,(a16) | |
| op1 = new LD_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xfa; | |
| op1->length = 3; | |
| op1->cycles0 = 16; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "LD A,(a16)"; | |
| op1->ref0 = new RegisterReference<byte>(cpu->a); | |
| op1->ref1 = new Memory_a16_Reference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // fb 1 4 EI | |
| op0 = new EI_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xfb; | |
| op0->length = 1; | |
| op0->cycles0 = 4; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "EI"; | |
| instructionSet->add(op0); | |
| // fe 2 8 CP d8 | |
| op1 = new CP_Instruction<byte>(); | |
| op1->cpu = cpu; | |
| op1->code = 0xfe; | |
| op1->length = 2; | |
| op1->cycles0 = 8; | |
| op1->cycles1 = 0; | |
| op1->mnemonic = "CP d8"; | |
| op1->ref0 = new MemoryReference<byte>(cpu, cpu->pc); | |
| instructionSet->add(op1); | |
| // ff 1 16 RST 38H | |
| op0 = new RST_Instruction(); | |
| op0->cpu = cpu; | |
| op0->code = 0xff; | |
| op0->length = 1; | |
| op0->cycles0 = 16; | |
| op0->cycles1 = 0; | |
| op0->mnemonic = "RST 38H"; | |
| op0->arg = 0x38; | |
| instructionSet->add(op0); | |
| } | |
| #endif |
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