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October 2, 2014 15:19
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Starting. Buffer size is 4410 frames | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
448221664861 15636 15608 0 1 4410 0 4 1 2 | |
136 15772 15767 22 2 4409 0 4 1 2 | |
65 15837 15833 45 3 4408 0 4 1 2 | |
54 15891 15887 68 4 4407 0 4 1 2 | |
55 15946 15942 90 5 4406 0 4 1 2 | |
53 15999 15995 113 6 4405 0 4 1 2 | |
55 16054 16050 136 7 4404 0 4 1 2 | |
52 16106 16103 158 8 4403 0 4 1 2 | |
51 16157 16154 181 9 4402 0 4 1 2 | |
55 16212 16208 204 10 4401 0 4 1 2 | |
52 16264 16260 226 11 4400 0 4 1 2 | |
127 16391 16386 249 12 4399 0 4 1 2 | |
104 16495 16490 272 13 4398 0 4 1 2 | |
146 16641 16636 294 14 4397 0 4 1 2 | |
71 16712 16708 317 15 4396 0 4 1 2 | |
58 16770 16765 340 16 4395 0 4 1 2 | |
56 16826 16822 362 17 4394 0 4 1 2 | |
54 16880 16876 385 18 4393 0 4 1 2 | |
54 16934 16931 408 19 4392 0 4 1 2 | |
52 16986 16982 430 20 4391 0 4 1 2 | |
55 17041 17036 453 21 4390 0 4 1 2 | |
52 17093 17089 476 22 4389 0 4 1 2 | |
53 17146 17142 498 23 4388 0 4 1 2 | |
56 17202 17198 521 24 4387 0 4 1 2 | |
52 17254 17250 544 25 4386 0 4 1 2 | |
93 17347 17343 566 26 4385 0 4 1 2 | |
61 17408 17404 589 27 4384 0 4 1 2 | |
59 17467 17463 612 28 4383 0 4 1 2 | |
55 17522 17518 634 29 4382 0 4 1 2 | |
128 17650 17645 657 30 4381 0 4 1 2 | |
64 17714 17710 680 31 4380 0 4 1 2 | |
54 17768 17764 702 32 4379 0 4 1 2 | |
57 17825 17821 725 33 4378 0 4 1 2 | |
54 17879 17875 748 34 4377 0 4 1 2 | |
54 17933 17928 770 35 4376 0 4 1 2 | |
53 17986 17982 793 36 4375 0 4 1 2 | |
51 18037 18034 816 37 4374 0 4 1 2 | |
55 18092 18088 839 38 4373 0 4 1 2 | |
52 18144 18140 861 39 4372 0 4 1 2 | |
54 18198 18194 884 40 4371 0 4 1 2 | |
53 18251 18247 907 41 4370 0 4 1 2 | |
90 18341 18336 929 42 4369 0 4 1 2 | |
63 18404 18399 952 43 4368 0 4 1 2 | |
60 18464 18460 975 44 4367 0 4 1 2 | |
52 18516 18512 997 45 4366 0 4 1 2 | |
124 18640 18635 1020 46 4365 0 4 1 2 | |
66 18706 18701 1043 47 4364 0 4 1 2 | |
55 18761 18758 1065 48 4363 0 4 1 2 | |
57 18818 18815 1088 49 4362 0 4 1 2 | |
53 18871 18867 1111 50 4361 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
54 18925 18921 1133 51 4360 0 4 1 2 | |
57 18982 18978 1156 52 4359 0 4 1 2 | |
53 19035 19031 1179 53 4358 0 4 1 2 | |
55 19090 19086 1201 54 4357 0 4 1 2 | |
54 19144 19140 1224 55 4356 0 4 1 2 | |
54 19198 19194 1247 56 4355 0 4 1 2 | |
53 19251 19247 1269 57 4354 0 4 1 2 | |
90 19341 19336 1292 58 4353 0 4 1 2 | |
62 19403 19399 1315 59 4352 0 4 1 2 | |
59 19462 19458 1337 60 4351 0 4 1 2 | |
55 19517 19513 1360 61 4350 0 4 1 2 | |
124 19641 19636 1383 62 4349 0 4 1 2 | |
63 19704 19700 1405 63 4348 0 4 1 2 | |
55 19759 19755 1428 64 4347 0 4 1 2 | |
54 19813 19810 1451 65 4346 0 4 1 2 | |
54 19867 19863 1473 66 4345 0 4 1 2 | |
53 19920 19916 1496 67 4344 0 4 1 2 | |
52 19972 19968 1519 68 4343 0 4 1 2 | |
52 20024 20021 1541 69 4342 0 4 1 2 | |
56 20080 20076 1564 70 4341 0 4 1 2 | |
51 20131 20128 1587 71 4340 0 4 1 2 | |
55 20186 20182 1609 72 4339 0 4 1 2 | |
51 20237 20234 1632 73 4338 0 4 1 2 | |
51 20288 20285 1655 74 4337 0 4 1 2 | |
99 20387 20382 1678 75 4336 0 4 1 2 | |
60 20447 20443 1700 76 4335 0 4 1 2 | |
55 20502 20498 1723 77 4334 0 4 1 2 | |
117 20619 20614 1746 78 4333 0 4 1 2 | |
70 20689 20685 1768 79 4332 0 4 1 2 | |
57 20746 20742 1791 80 4331 0 4 1 2 | |
164 20910 20905 1814 81 4330 0 4 1 2 | |
69 20979 20975 1836 82 4329 0 4 1 2 | |
55 21034 21030 1859 83 4328 0 4 1 2 | |
56 21090 21086 1882 84 4327 0 4 1 2 | |
53 21143 21139 1904 85 4326 0 4 1 2 | |
55 21198 21194 1927 86 4325 0 4 1 2 | |
53 21251 21247 1950 87 4324 0 4 1 2 | |
93 21344 21339 1972 88 4323 0 4 1 2 | |
63 21407 21403 1995 89 4322 0 4 1 2 | |
61 21468 21463 2018 90 4321 0 4 1 2 | |
52 21520 21517 2040 91 4320 0 4 1 2 | |
136 21656 21651 2063 92 4319 0 4 1 2 | |
66 21722 21717 2086 93 4318 0 4 1 2 | |
57 21779 21774 2108 94 4317 0 4 1 2 | |
55 21834 21830 2131 95 4316 0 4 1 2 | |
55 21889 21885 2154 96 4315 0 4 1 2 | |
54 21943 21939 2176 97 4314 0 4 1 2 | |
53 21996 21993 2199 98 4313 0 4 1 2 | |
55 22051 22047 2222 99 4312 0 4 1 2 | |
53 22104 22100 2244 100 4311 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
53 22157 22153 2267 101 4310 0 4 1 2 | |
60 22217 22213 2290 102 4309 0 4 1 2 | |
52 22269 22265 2312 103 4308 0 4 1 2 | |
97 22366 22361 2335 104 4307 0 4 1 2 | |
64 22430 22426 2358 105 4306 0 4 1 2 | |
57 22487 22483 2380 106 4305 0 4 1 2 | |
56 22543 22537 2403 107 4304 0 4 1 2 | |
130 22673 22667 2426 108 4303 0 4 1 2 | |
57 22730 22726 2448 109 4302 0 4 1 2 | |
127 22857 22852 2471 110 4301 0 4 1 2 | |
63 22920 22914 2494 111 4300 0 4 1 2 | |
56 22976 22971 2517 112 4299 0 4 1 2 | |
53 23029 23025 2539 113 4298 0 4 1 2 | |
56 23085 23080 2562 114 4297 0 4 1 2 | |
52 23137 23133 2585 115 4296 0 4 1 2 | |
55 23192 23188 2607 116 4295 0 4 1 2 | |
54 23246 23242 2630 117 4294 0 4 1 2 | |
95 23341 23337 2653 118 4293 0 4 1 2 | |
64 23405 23401 2675 119 4292 0 4 1 2 | |
62 23467 23462 2698 120 4291 0 4 1 2 | |
54 23521 23517 2721 121 4290 0 4 1 2 | |
133 23654 23648 2743 122 4289 0 4 1 2 | |
66 23720 23715 2766 123 4288 0 4 1 2 | |
56 23776 23772 2789 124 4287 0 4 1 2 | |
57 23833 23829 2811 125 4286 0 4 1 2 | |
53 23886 23882 2834 126 4285 0 4 1 2 | |
56 23942 23939 2857 127 4284 0 4 1 2 | |
53 23995 23991 2879 128 4283 0 4 1 2 | |
53 24048 24044 2902 129 4282 0 4 1 2 | |
52 24100 24097 2925 130 4281 0 4 1 2 | |
51 24151 24147 2947 131 4280 0 4 1 2 | |
55 24206 24202 2970 132 4279 0 4 1 2 | |
53 24259 24255 2993 133 4278 0 4 1 2 | |
97 24356 24351 3015 134 4277 0 4 1 2 | |
94 24450 24413 3038 135 4276 0 4 1 2 | |
66 24516 24511 3061 136 4275 0 4 1 2 | |
125 24641 24636 3083 137 4274 0 4 1 2 | |
65 24706 24702 3106 138 4273 0 4 1 2 | |
59 24765 24761 3129 139 4272 0 4 1 2 | |
57 24822 24818 3151 140 4271 0 4 1 2 | |
51 24873 24870 3174 141 4270 0 4 1 2 | |
55 24928 24925 3197 142 4269 0 4 1 2 | |
53 24981 24978 3219 143 4268 0 4 1 2 | |
53 25034 25030 3242 144 4267 0 4 1 2 | |
54 25088 25085 3265 145 4266 0 4 1 2 | |
53 25141 25137 3287 146 4265 0 4 1 2 | |
56 25197 25193 3310 147 4264 0 4 1 2 | |
54 25251 25247 3333 148 4263 0 4 1 2 | |
90 25341 25336 3356 149 4262 0 4 1 2 | |
63 25404 25400 3378 150 4261 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
59 25463 25459 3401 151 4260 0 4 1 2 | |
60 25523 25519 3424 152 4259 0 4 1 2 | |
129 25652 25646 3446 153 4258 0 4 1 2 | |
66 25718 25713 3469 154 4257 0 4 1 2 | |
54 25772 25768 3492 155 4256 0 4 1 2 | |
56 25828 25824 3514 156 4255 0 4 1 2 | |
54 25882 25878 3537 157 4254 0 4 1 2 | |
54 25936 25933 3560 158 4253 0 4 1 2 | |
53 25989 25985 3582 159 4252 0 4 1 2 | |
53 26042 26036 3605 160 4251 0 4 1 2 | |
53 26095 26091 3628 161 4250 0 4 1 2 | |
52 26147 26144 3650 162 4249 0 4 1 2 | |
55 26202 26198 3673 163 4248 0 4 1 2 | |
53 26255 26251 3696 164 4247 0 4 1 2 | |
91 26346 26341 3718 165 4246 0 4 1 2 | |
61 26407 26403 3741 166 4245 0 4 1 2 | |
59 26466 26462 3764 167 4244 0 4 1 2 | |
56 26522 26518 3786 168 4243 0 4 1 2 | |
156 26678 26672 3809 169 4242 0 4 1 2 | |
64 26742 26738 3832 170 4241 0 4 1 2 | |
59 26801 26797 3854 171 4240 0 4 1 2 | |
54 26855 26851 3877 172 4239 0 4 1 2 | |
54 26909 26905 3900 173 4238 0 4 1 2 | |
55 26964 26960 3922 174 4237 0 4 1 2 | |
54 27018 27014 3945 175 4236 0 4 1 2 | |
55 27073 27069 3968 176 4235 0 4 1 2 | |
52 27125 27121 3990 177 4234 0 4 1 2 | |
54 27179 27175 4013 178 4233 0 4 1 2 | |
52 27231 27228 4036 179 4232 0 4 1 2 | |
53 27284 27280 4058 180 4231 0 4 1 2 | |
97 27381 27376 4081 181 4230 0 4 1 2 | |
61 27442 27438 4104 182 4229 0 4 1 2 | |
55 27497 27493 4126 183 4228 0 4 1 2 | |
116 27613 27607 4149 184 4227 0 4 1 2 | |
69 27682 27678 4172 185 4226 0 4 1 2 | |
59 27741 27738 4195 186 4225 0 4 1 2 | |
56 27797 27793 4217 187 4224 0 4 1 2 | |
55 27852 27848 4240 188 4223 0 4 1 2 | |
53 27905 27901 4263 189 4222 0 4 1 2 | |
55 27960 27956 4285 190 4221 0 4 1 2 | |
52 28012 28008 4308 191 4220 0 4 1 2 | |
55 28067 28064 4331 192 4219 0 4 1 2 | |
53 28120 28117 4353 193 4218 0 4 1 2 | |
57 28177 28172 4376 194 4217 0 4 1 2 | |
52 28229 28226 4399 195 4216 0 4 1 2 | |
54 28283 28279 4421 196 4215 0 4 1 2 | |
98 28381 28376 4444 197 4214 0 4 1 2 | |
61 28442 28437 4467 198 4213 0 4 1 2 | |
56 28498 28494 4489 199 4212 0 4 1 2 | |
119 28617 28612 4512 200 4211 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
71 28688 28683 4535 201 4210 0 4 1 2 | |
64 28752 28748 4557 202 4209 0 4 1 2 | |
58 28810 28806 4580 203 4208 0 4 1 2 | |
57 28867 28863 4603 204 4207 0 4 1 2 | |
56 28923 28919 4625 205 4206 0 4 1 2 | |
54 28977 28973 4648 206 4205 0 4 1 2 | |
53 29030 29026 4671 207 4204 0 4 1 2 | |
54 29084 29081 4693 208 4203 0 4 1 2 | |
53 29137 29133 4716 209 4202 0 4 1 2 | |
54 29191 29187 4739 210 4201 0 4 1 2 | |
51 29242 29239 4761 211 4200 0 4 1 2 | |
90 29332 29326 4784 212 4199 0 4 1 2 | |
63 29395 29391 4807 213 4198 0 4 1 2 | |
60 29455 29452 4829 214 4197 0 4 1 2 | |
55 29510 29506 4852 215 4196 0 4 1 2 | |
114 29624 29620 4875 216 4195 0 4 1 2 | |
108 29732 29727 4897 217 4194 0 4 1 2 | |
65 29797 29793 4920 218 4193 0 4 1 2 | |
56 29853 29849 4943 219 4192 0 4 1 2 | |
55 29908 29904 4965 220 4191 0 4 1 2 | |
55 29963 29959 4988 221 4190 0 4 1 2 | |
53 30016 30012 5011 222 4189 0 4 1 2 | |
54 30070 30066 5034 223 4188 0 4 1 2 | |
52 30122 30118 5056 224 4187 0 4 1 2 | |
55 30177 30173 5079 225 4186 0 4 1 2 | |
52 30229 30226 5102 226 4185 0 4 1 2 | |
53 30282 30278 5124 227 4184 0 4 1 2 | |
98 30380 30376 5147 228 4183 0 4 1 2 | |
63 30443 30439 5170 229 4182 0 4 1 2 | |
57 30500 30497 5192 230 4181 0 4 1 2 | |
123 30623 30618 5215 231 4180 0 4 1 2 | |
70 30693 30688 5238 232 4179 0 4 1 2 | |
58 30751 30747 5260 233 4178 0 4 1 2 | |
128 30879 30874 5283 234 4177 0 4 1 2 | |
65 30944 30939 5306 235 4176 0 4 1 2 | |
55 30999 30996 5328 236 4175 0 4 1 2 | |
58 31057 31053 5351 237 4174 0 4 1 2 | |
53 31110 31106 5374 238 4173 0 4 1 2 | |
52 31162 31158 5396 239 4172 0 4 1 2 | |
56 31218 31215 5419 240 4171 0 4 1 2 | |
54 31272 31268 5442 241 4170 0 4 1 2 | |
96 31368 31364 5464 242 4169 0 4 1 2 | |
64 31432 31427 5487 243 4168 0 4 1 2 | |
56 31488 31484 5510 244 4167 0 4 1 2 | |
56 31544 31538 5532 245 4166 0 4 1 2 | |
141 31685 31679 5555 246 4165 0 4 1 2 | |
59 31744 31740 5578 247 4164 0 4 1 2 | |
56 31800 31796 5600 248 4163 0 4 1 2 | |
53 31853 31849 5623 249 4162 0 4 1 2 | |
52 31905 31901 5646 250 4161 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
56 31961 31957 5668 251 4160 0 4 1 2 | |
57 32018 32014 5691 252 4159 0 4 1 2 | |
55 32073 32069 5714 253 4158 0 4 1 2 | |
53 32126 32122 5736 254 4157 0 4 1 2 | |
54 32180 32176 5759 255 4156 0 4 1 2 | |
52 32232 32229 5782 256 4155 0 4 1 2 | |
53 32285 32281 5804 257 4154 0 4 1 2 | |
103 32388 32384 5827 258 4153 0 4 1 2 | |
99 32487 32482 5850 259 4152 0 4 1 2 | |
121 32608 32545 5873 260 4151 0 4 1 2 | |
73 32681 32676 5895 261 4150 0 4 1 2 | |
58 32739 32735 5918 262 4149 0 4 1 2 | |
57 32796 32790 5941 263 4148 0 4 1 2 | |
55 32851 32848 5963 264 4147 0 4 1 2 | |
53 32904 32900 5986 265 4146 0 4 1 2 | |
55 32959 32955 6009 266 4145 0 4 1 2 | |
53 33012 33008 6031 267 4144 0 4 1 2 | |
55 33067 33063 6054 268 4143 0 4 1 2 | |
54 33121 33117 6077 269 4142 0 4 1 2 | |
55 33176 33172 6099 270 4141 0 4 1 2 | |
54 33230 33226 6122 271 4140 0 4 1 2 | |
52 33282 33279 6145 272 4139 0 4 1 2 | |
95 33377 33373 6167 273 4138 0 4 1 2 | |
63 33440 33436 6190 274 4137 0 4 1 2 | |
56 33496 33492 6213 275 4136 0 4 1 2 | |
115 33611 33605 6235 276 4135 0 4 1 2 | |
72 33683 33678 6258 277 4134 0 4 1 2 | |
57 33740 33736 6281 278 4133 0 4 1 2 | |
56 33796 33792 6303 279 4132 0 4 1 2 | |
54 33850 33846 6326 280 4131 0 4 1 2 | |
52 33902 33898 6349 281 4130 0 4 1 2 | |
55 33957 33954 6371 282 4129 0 4 1 2 | |
53 34010 34006 6394 283 4128 0 4 1 2 | |
55 34065 34061 6417 284 4127 0 4 1 2 | |
54 34119 34114 6439 285 4126 0 4 1 2 | |
54 34173 34169 6462 286 4125 0 4 1 2 | |
52 34225 34221 6485 287 4124 0 4 1 2 | |
52 34277 34273 6507 288 4123 0 4 1 2 | |
95 34372 34367 6530 289 4122 0 4 1 2 | |
63 34435 34431 6553 290 4121 0 4 1 2 | |
56 34491 34487 6575 291 4120 0 4 1 2 | |
117 34608 34544 6598 292 4119 0 4 1 2 | |
73 34681 34676 6621 293 4118 0 4 1 2 | |
58 34739 34735 6643 294 4117 0 4 1 2 | |
57 34796 34792 6666 295 4116 0 4 1 2 | |
56 34852 34848 6689 296 4115 0 4 1 2 | |
52 34904 34900 6712 297 4114 0 4 1 2 | |
56 34960 34956 6734 298 4113 0 4 1 2 | |
53 35013 35009 6757 299 4112 0 4 1 2 | |
55 35068 35064 6780 300 4111 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
53 35121 35118 6802 301 4110 0 4 1 2 | |
61 35182 35178 6825 302 4109 0 4 1 2 | |
53 35235 35232 6848 303 4108 0 4 1 2 | |
53 35288 35284 6870 304 4107 0 4 1 2 | |
99 35387 35382 6893 305 4106 0 4 1 2 | |
62 35449 35445 6916 306 4105 0 4 1 2 | |
55 35504 35500 6938 307 4104 0 4 1 2 | |
122 35626 35620 6961 308 4103 0 4 1 2 | |
69 35695 35691 6984 309 4102 0 4 1 2 | |
58 35753 35749 7006 310 4101 0 4 1 2 | |
55 35808 35804 7029 311 4100 0 4 1 2 | |
54 35862 35858 7052 312 4099 0 4 1 2 | |
53 35915 35912 7074 313 4098 0 4 1 2 | |
56 35971 35967 7097 314 4097 0 4 1 2 | |
51 36022 36019 7120 315 4096 0 4 1 2 | |
56 36078 36074 7142 316 4095 0 4 1 2 | |
53 36131 36128 7165 317 4094 0 4 1 2 | |
55 36186 36183 7188 318 4093 0 4 1 2 | |
53 36239 36235 7210 319 4092 0 4 1 2 | |
85 36324 36288 7233 320 4091 0 4 1 2 | |
66 36390 36386 7256 321 4090 0 4 1 2 | |
62 36452 36448 7278 322 4089 0 4 1 2 | |
54 36506 36502 7301 323 4088 0 4 1 2 | |
174 36680 36674 7324 324 4087 0 4 1 2 | |
65 36745 36740 7346 325 4086 0 4 1 2 | |
59 36804 36800 7369 326 4085 0 4 1 2 | |
55 36859 36855 7392 327 4084 0 4 1 2 | |
52 36911 36907 7414 328 4083 0 4 1 2 | |
55 36966 36962 7437 329 4082 0 4 1 2 | |
52 37018 37015 7460 330 4081 0 4 1 2 | |
56 37074 37070 7482 331 4080 0 4 1 2 | |
53 37127 37124 7505 332 4079 0 4 1 2 | |
54 37181 37177 7528 333 4078 0 4 1 2 | |
52 37233 37230 7551 334 4077 0 4 1 2 | |
52 37285 37281 7573 335 4076 0 4 1 2 | |
99 37384 37379 7596 336 4075 0 4 1 2 | |
64 37448 37444 7619 337 4074 0 4 1 2 | |
56 37504 37500 7641 338 4073 0 4 1 2 | |
121 37625 37620 7664 339 4072 0 4 1 2 | |
69 37694 37689 7687 340 4071 0 4 1 2 | |
57 37751 37748 7709 341 4070 0 4 1 2 | |
57 37808 37804 7732 342 4069 0 4 1 2 | |
53 37861 37857 7755 343 4068 0 4 1 2 | |
53 37914 37910 7777 344 4067 0 4 1 2 | |
54 37968 37964 7800 345 4066 0 4 1 2 | |
53 38021 38017 7823 346 4065 0 4 1 2 | |
54 38075 38072 7845 347 4064 0 4 1 2 | |
54 38129 38125 7868 348 4063 0 4 1 2 | |
55 38184 38180 7891 349 4062 0 4 1 2 | |
52 38236 38233 7913 350 4061 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
53 38289 38285 7936 351 4060 0 4 1 2 | |
103 38392 38387 7959 352 4059 0 4 1 2 | |
61 38453 38449 7981 353 4058 0 4 1 2 | |
55 38508 38504 8004 354 4057 0 4 1 2 | |
122 38630 38625 8027 355 4056 0 4 1 2 | |
71 38701 38697 8049 356 4055 0 4 1 2 | |
58 38759 38755 8072 357 4054 0 4 1 2 | |
58 38817 38813 8095 358 4053 0 4 1 2 | |
53 38870 38867 8117 359 4052 0 4 1 2 | |
56 38926 38922 8140 360 4051 0 4 1 2 | |
53 38979 38976 8163 361 4050 0 4 1 2 | |
52 39031 39027 8185 362 4049 0 4 1 2 | |
56 39087 39083 8208 363 4048 0 4 1 2 | |
52 39139 39135 8231 364 4047 0 4 1 2 | |
55 39194 39191 8253 365 4046 0 4 1 2 | |
51 39245 39242 8276 366 4045 0 4 1 2 | |
90 39335 39330 8299 367 4044 0 4 1 2 | |
65 39400 39396 8321 368 4043 0 4 1 2 | |
60 39460 39456 8344 369 4042 0 4 1 2 | |
54 39514 39511 8367 370 4041 0 4 1 2 | |
128 39642 39637 8390 371 4040 0 4 1 2 | |
66 39708 39704 8412 372 4039 0 4 1 2 | |
54 39762 39759 8435 373 4038 0 4 1 2 | |
58 39820 39816 8458 374 4037 0 4 1 2 | |
54 39874 39870 8480 375 4036 0 4 1 2 | |
55 39929 39925 8503 376 4035 0 4 1 2 | |
51 39980 39977 8526 377 4034 0 4 1 2 | |
54 40034 40031 8548 378 4033 0 4 1 2 | |
54 40088 40084 8571 379 4032 0 4 1 2 | |
51 40139 40136 8594 380 4031 0 4 1 2 | |
55 40194 40189 8616 381 4030 0 4 1 2 | |
52 40246 40243 8639 382 4029 0 4 1 2 | |
94 40340 40334 8662 383 4028 0 4 1 2 | |
63 40403 40399 8684 384 4027 0 4 1 2 | |
93 40496 40491 8707 385 4026 0 4 1 2 | |
119 40615 40610 8730 386 4025 0 4 1 2 | |
68 40683 40679 8752 387 4024 0 4 1 2 | |
57 40740 40736 8775 388 4023 0 4 1 2 | |
137 40877 40872 8798 389 4022 0 4 1 2 | |
72 40949 40945 8820 390 4021 0 4 1 2 | |
57 41006 41002 8843 391 4020 0 4 1 2 | |
56 41062 41059 8866 392 4019 0 4 1 2 | |
53 41115 41111 8888 393 4018 0 4 1 2 | |
55 41170 41164 8911 394 4017 0 4 1 2 | |
53 41223 41219 8934 395 4016 0 4 1 2 | |
51 41274 41270 8956 396 4015 0 4 1 2 | |
98 41372 41368 8979 397 4014 0 4 1 2 | |
66 41438 41433 9002 398 4013 0 4 1 2 | |
56 41494 41490 9024 399 4012 0 4 1 2 | |
118 41612 41546 9047 400 4011 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
74 41686 41681 9070 401 4010 0 4 1 2 | |
63 41749 41745 9092 402 4009 0 4 1 2 | |
56 41805 41801 9115 403 4008 0 4 1 2 | |
55 41860 41857 9138 404 4007 0 4 1 2 | |
54 41914 41911 9160 405 4006 0 4 1 2 | |
55 41969 41965 9183 406 4005 0 4 1 2 | |
51 42020 42016 9206 407 4004 0 4 1 2 | |
55 42075 42072 9229 408 4003 0 4 1 2 | |
53 42128 42125 9251 409 4002 0 4 1 2 | |
56 42184 42180 9274 410 4001 0 4 1 2 | |
53 42237 42233 9297 411 4000 0 4 1 2 | |
52 42289 42285 9319 412 3999 0 4 1 2 | |
98 42387 42382 9342 413 3998 0 4 1 2 | |
60 42447 42443 9365 414 3997 0 4 1 2 | |
56 42503 42499 9387 415 3996 0 4 1 2 | |
118 42621 42616 9410 416 3995 0 4 1 2 | |
70 42691 42687 9433 417 3994 0 4 1 2 | |
56 42747 42743 9455 418 3993 0 4 1 2 | |
58 42805 42800 9478 419 3992 0 4 1 2 | |
54 42859 42855 9501 420 3991 0 4 1 2 | |
53 42912 42908 9523 421 3990 0 4 1 2 | |
55 42967 42963 9546 422 3989 0 4 1 2 | |
52 43019 43015 9569 423 3988 0 4 1 2 | |
54 43073 43070 9591 424 3987 0 4 1 2 | |
53 43126 43122 9614 425 3986 0 4 1 2 | |
54 43180 43176 9637 426 3985 0 4 1 2 | |
53 43233 43229 9659 427 3984 0 4 1 2 | |
51 43284 43281 9682 428 3983 0 4 1 2 | |
96 43380 43375 9705 429 3982 0 4 1 2 | |
61 43441 43438 9727 430 3981 0 4 1 2 | |
173 43614 43540 9750 431 3980 0 4 1 2 | |
80 43694 43689 9773 432 3979 0 4 1 2 | |
59 43753 43749 9795 433 3978 0 4 1 2 | |
56 43809 43805 9818 434 3977 0 4 1 2 | |
54 43863 43859 9841 435 3976 0 4 1 2 | |
53 43916 43912 9863 436 3975 0 4 1 2 | |
55 43971 43967 9886 437 3974 0 4 1 2 | |
53 44024 44020 9909 438 3973 0 4 1 2 | |
54 44078 44075 9931 439 3972 0 4 1 2 | |
53 44131 44128 9954 440 3971 0 4 1 2 | |
57 44188 44183 9977 441 3970 0 4 1 2 | |
51 44239 44235 10000 442 3969 0 4 1 2 | |
52 44291 44287 10022 443 3968 0 4 1 2 | |
99 44390 44385 10045 444 3967 0 4 1 2 | |
61 44451 44447 10068 445 3966 0 4 1 2 | |
54 44505 44501 10090 446 3965 0 4 1 2 | |
118 44623 44618 10113 447 3964 0 4 1 2 | |
68 44691 44687 10136 448 3963 0 4 1 2 | |
59 44750 44746 10158 449 3962 0 4 1 2 | |
57 44807 44803 10181 450 3961 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
55 44862 44858 10204 451 3960 0 4 1 2 | |
58 44920 44914 10226 452 3959 0 4 1 2 | |
55 44975 44971 10249 453 3958 0 4 1 2 | |
55 45030 45026 10272 454 3957 0 4 1 2 | |
57 45087 45083 10294 455 3956 0 4 1 2 | |
53 45140 45136 10317 456 3955 0 4 1 2 | |
55 45195 45191 10340 457 3954 0 4 1 2 | |
53 45248 45244 10362 458 3953 0 4 1 2 | |
90 45338 45334 10385 459 3952 0 4 1 2 | |
63 45401 45398 10408 460 3951 0 4 1 2 | |
59 45460 45457 10430 461 3950 0 4 1 2 | |
54 45514 45510 10453 462 3949 0 4 1 2 | |
121 45635 45629 10476 463 3948 0 4 1 2 | |
69 45704 45699 10498 464 3947 0 4 1 2 | |
56 45760 45756 10521 465 3946 0 4 1 2 | |
55 45815 45811 10544 466 3945 0 4 1 2 | |
53 45868 45865 10566 467 3944 0 4 1 2 | |
57 45925 45921 10589 468 3943 0 4 1 2 | |
53 45978 45974 10612 469 3942 0 4 1 2 | |
54 46032 46028 10634 470 3941 0 4 1 2 | |
57 46089 46084 10657 471 3940 0 4 1 2 | |
53 46142 46139 10680 472 3939 0 4 1 2 | |
56 46198 46194 10702 473 3938 0 4 1 2 | |
53 46251 46247 10725 474 3937 0 4 1 2 | |
90 46341 46336 10748 475 3936 0 4 1 2 | |
62 46403 46399 10770 476 3935 0 4 1 2 | |
59 46462 46458 10793 477 3934 0 4 1 2 | |
55 46517 46513 10816 478 3933 0 4 1 2 | |
122 46639 46634 10839 479 3932 0 4 1 2 | |
65 46704 46700 10861 480 3931 0 4 1 2 | |
56 46760 46756 10884 481 3930 0 4 1 2 | |
55 46815 46811 10907 482 3929 0 4 1 2 | |
51 46866 46862 10929 483 3928 0 4 1 2 | |
56 46922 46916 10952 484 3927 0 4 1 2 | |
52 46974 46970 10975 485 3926 0 4 1 2 | |
53 47027 47024 10997 486 3925 0 4 1 2 | |
55 47082 47078 11020 487 3924 0 4 1 2 | |
53 47135 47131 11043 488 3923 0 4 1 2 | |
54 47189 47185 11065 489 3922 0 4 1 2 | |
51 47240 47237 11088 490 3921 0 4 1 2 | |
52 47292 47288 11111 491 3920 0 4 1 2 | |
100 47392 47387 11133 492 3919 0 4 1 2 | |
62 47454 47449 11156 493 3918 0 4 1 2 | |
56 47510 47505 11179 494 3917 0 4 1 2 | |
120 47630 47624 11201 495 3916 0 4 1 2 | |
68 47698 47694 11224 496 3915 0 4 1 2 | |
57 47755 47752 11247 497 3914 0 4 1 2 | |
57 47812 47808 11269 498 3913 0 4 1 2 | |
53 47865 47861 11292 499 3912 0 4 1 2 | |
55 47920 47914 11315 500 3911 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
53 47973 47970 11337 501 3910 0 4 1 2 | |
57 48030 48025 11360 502 3909 0 4 1 2 | |
56 48086 48082 11383 503 3908 0 4 1 2 | |
55 48141 48137 11405 504 3907 0 4 1 2 | |
58 48199 48195 11428 505 3906 0 4 1 2 | |
51 48250 48247 11451 506 3905 0 4 1 2 | |
97 48347 48342 11473 507 3904 0 4 1 2 | |
65 48412 48408 11496 508 3903 0 4 1 2 | |
97 48509 48505 11519 509 3902 0 4 1 2 | |
126 48635 48630 11541 510 3901 0 4 1 2 | |
68 48703 48698 11564 511 3900 0 4 1 2 | |
57 48760 48756 11587 512 3899 0 4 1 2 | |
55 48815 48811 11609 513 3898 0 4 1 2 | |
54 48869 48865 11632 514 3897 0 4 1 2 | |
55 48924 48919 11655 515 3896 0 4 1 2 | |
52 48976 48973 11678 516 3895 0 4 1 2 | |
53 49029 49025 11700 517 3894 0 4 1 2 | |
55 49084 49080 11723 518 3893 0 4 1 2 | |
53 49137 49133 11746 519 3892 0 4 1 2 | |
54 49191 49187 11768 520 3891 0 4 1 2 | |
52 49243 49240 11791 521 3890 0 4 1 2 | |
88 49331 49292 11814 522 3889 0 4 1 2 | |
64 49395 49390 11836 523 3888 0 4 1 2 | |
60 49455 49452 11859 524 3887 0 4 1 2 | |
54 49509 49506 11882 525 3886 0 4 1 2 | |
119 49628 49623 11904 526 3885 0 4 1 2 | |
68 49696 49691 11927 527 3884 0 4 1 2 | |
57 49753 49749 11950 528 3883 0 4 1 2 | |
56 49809 49805 11972 529 3882 0 4 1 2 | |
53 49862 49859 11995 530 3881 0 4 1 2 | |
53 49915 49911 12018 531 3880 0 4 1 2 | |
56 49971 49967 12040 532 3879 0 4 1 2 | |
52 50023 50019 12063 533 3878 0 4 1 2 | |
55 50078 50074 12086 534 3877 0 4 1 2 | |
54 50132 50128 12108 535 3876 0 4 1 2 | |
93 50225 50220 12131 536 3875 0 4 1 2 | |
58 50283 50279 12154 537 3874 0 4 1 2 | |
102 50385 50380 12176 538 3873 0 4 1 2 | |
64 50449 50445 12199 539 3872 0 4 1 2 | |
54 50503 50500 12222 540 3871 0 4 1 2 | |
124 50627 50621 12244 541 3870 0 4 1 2 | |
73 50700 50695 12267 542 3869 0 4 1 2 | |
58 50758 50754 12290 543 3868 0 4 1 2 | |
122 50880 50874 12312 544 3867 0 4 1 2 | |
65 50945 50941 12335 545 3866 0 4 1 2 | |
57 51002 50998 12358 546 3865 0 4 1 2 | |
56 51058 51054 12380 547 3864 0 4 1 2 | |
54 51112 51108 12403 548 3863 0 4 1 2 | |
52 51164 51160 12426 549 3862 0 4 1 2 | |
55 51219 51215 12448 550 3861 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
53 51272 51268 12471 551 3860 0 4 1 2 | |
100 51372 51367 12494 552 3859 0 4 1 2 | |
65 51437 51432 12517 553 3858 0 4 1 2 | |
56 51493 51489 12539 554 3857 0 4 1 2 | |
113 51606 51542 12562 555 3856 0 4 1 2 | |
77 51683 51678 12585 556 3855 0 4 1 2 | |
59 51742 51738 12607 557 3854 0 4 1 2 | |
56 51798 51792 12630 558 3853 0 4 1 2 | |
54 51852 51848 12653 559 3852 0 4 1 2 | |
54 51906 51902 12675 560 3851 0 4 1 2 | |
55 51961 51957 12698 561 3850 0 4 1 2 | |
53 52014 52011 12721 562 3849 0 4 1 2 | |
55 52069 52066 12743 563 3848 0 4 1 2 | |
53 52122 52118 12766 564 3847 0 4 1 2 | |
57 52179 52175 12789 565 3846 0 4 1 2 | |
53 52232 52228 12811 566 3845 0 4 1 2 | |
52 52284 52280 12834 567 3844 0 4 1 2 | |
96 52380 52375 12857 568 3843 0 4 1 2 | |
64 52444 52440 12879 569 3842 0 4 1 2 | |
56 52500 52496 12902 570 3841 0 4 1 2 | |
119 52619 52613 12925 571 3840 0 4 1 2 | |
70 52689 52685 12947 572 3839 0 4 1 2 | |
59 52748 52744 12970 573 3838 0 4 1 2 | |
56 52804 52800 12993 574 3837 0 4 1 2 | |
54 52858 52854 13015 575 3836 0 4 1 2 | |
53 52911 52908 13038 576 3835 0 4 1 2 | |
56 52967 52963 13061 577 3834 0 4 1 2 | |
53 53020 53016 13083 578 3833 0 4 1 2 | |
56 53076 53072 13106 579 3832 0 4 1 2 | |
53 53129 53125 13129 580 3831 0 4 1 2 | |
55 53184 53180 13151 581 3830 0 4 1 2 | |
51 53235 53232 13174 582 3829 0 4 1 2 | |
54 53289 53285 13197 583 3828 0 4 1 2 | |
94 53383 53378 13219 584 3827 0 4 1 2 | |
62 53445 53441 13242 585 3826 0 4 1 2 | |
57 53502 53498 13265 586 3825 0 4 1 2 | |
119 53621 53616 13287 587 3824 0 4 1 2 | |
71 53692 53687 13310 588 3823 0 4 1 2 | |
58 53750 53746 13333 589 3822 0 4 1 2 | |
56 53806 53803 13356 590 3821 0 4 1 2 | |
55 53861 53857 13378 591 3820 0 4 1 2 | |
55 53916 53911 13401 592 3819 0 4 1 2 | |
54 53970 53967 13424 593 3818 0 4 1 2 | |
52 54022 54018 13446 594 3817 0 4 1 2 | |
55 54077 54073 13469 595 3816 0 4 1 2 | |
54 54131 54127 13492 596 3815 0 4 1 2 | |
55 54186 54182 13514 597 3814 0 4 1 2 | |
53 54239 54235 13537 598 3813 0 4 1 2 | |
53 54292 54288 13560 599 3812 0 4 1 2 | |
97 54389 54384 13582 600 3811 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
63 54452 54448 13605 601 3810 0 4 1 2 | |
59 54511 54507 13628 602 3809 0 4 1 2 | |
122 54633 54629 13650 603 3808 0 4 1 2 | |
70 54703 54698 13673 604 3807 0 4 1 2 | |
58 54761 54757 13696 605 3806 0 4 1 2 | |
57 54818 54814 13718 606 3805 0 4 1 2 | |
54 54872 54868 13741 607 3804 0 4 1 2 | |
56 54928 54924 13764 608 3803 0 4 1 2 | |
53 54981 54977 13786 609 3802 0 4 1 2 | |
52 55033 55029 13809 610 3801 0 4 1 2 | |
55 55088 55084 13832 611 3800 0 4 1 2 | |
53 55141 55137 13854 612 3799 0 4 1 2 | |
56 55197 55193 13877 613 3798 0 4 1 2 | |
54 55251 55247 13900 614 3797 0 4 1 2 | |
91 55342 55338 13922 615 3796 0 4 1 2 | |
66 55408 55404 13945 616 3795 0 4 1 2 | |
62 55470 55466 13968 617 3794 0 4 1 2 | |
54 55524 55520 13990 618 3793 0 4 1 2 | |
135 55659 55654 14013 619 3792 0 4 1 2 | |
68 55727 55723 14036 620 3791 0 4 1 2 | |
56 55783 55779 14058 621 3790 0 4 1 2 | |
55 55838 55834 14081 622 3789 0 4 1 2 | |
53 55891 55888 14104 623 3788 0 4 1 2 | |
56 55947 55943 14126 624 3787 0 4 1 2 | |
53 56000 55996 14149 625 3786 0 4 1 2 | |
55 56055 56051 14172 626 3785 0 4 1 2 | |
52 56107 56104 14195 627 3784 0 4 1 2 | |
54 56161 56157 14217 628 3783 0 4 1 2 | |
55 56216 56212 14240 629 3782 0 4 1 2 | |
53 56269 56265 14263 630 3781 0 4 1 2 | |
101 56370 56366 14285 631 3780 0 4 1 2 | |
97 56467 56462 14308 632 3779 0 4 1 2 | |
64 56531 56527 14331 633 3778 0 4 1 2 | |
129 56660 56654 14353 634 3777 0 4 1 2 | |
63 56723 56719 14376 635 3776 0 4 1 2 | |
55 56778 56774 14399 636 3775 0 4 1 2 | |
55 56833 56829 14421 637 3774 0 4 1 2 | |
53 56886 56883 14444 638 3773 0 4 1 2 | |
54 56940 56937 14467 639 3772 0 4 1 2 | |
99 57039 57035 14489 640 3771 0 4 1 2 | |
64 57103 57099 14512 641 3770 0 4 1 2 | |
55 57158 57154 14535 642 3769 0 4 1 2 | |
57 57215 57210 14557 643 3768 0 4 1 2 | |
54 57269 57265 14580 644 3767 0 4 1 2 | |
97 57366 57361 14603 645 3766 0 4 1 2 | |
64 57430 57426 14625 646 3765 0 4 1 2 | |
56 57486 57483 14648 647 3764 0 4 1 2 | |
54 57540 57536 14671 648 3763 0 4 1 2 | |
132 57672 57666 14693 649 3762 0 4 1 2 | |
62 57734 57730 14716 650 3761 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
55 57789 57785 14739 651 3760 0 4 1 2 | |
61 57850 57846 14761 652 3759 0 4 1 2 | |
55 57905 57901 14784 653 3758 0 4 1 2 | |
54 57959 57955 14807 654 3757 0 4 1 2 | |
52 58011 58008 14829 655 3756 0 4 1 2 | |
55 58066 58062 14852 656 3755 0 4 1 2 | |
53 58119 58116 14875 657 3754 0 4 1 2 | |
54 58173 58168 14897 658 3753 0 4 1 2 | |
52 58225 58222 14920 659 3752 0 4 1 2 | |
52 58277 58274 14943 660 3751 0 4 1 2 | |
92 58369 58365 14965 661 3750 0 4 1 2 | |
65 58434 58430 14988 662 3749 0 4 1 2 | |
56 58490 58486 15011 663 3748 0 4 1 2 | |
54 58544 58540 15034 664 3747 0 4 1 2 | |
134 58678 58673 15056 665 3746 0 4 1 2 | |
60 58738 58734 15079 666 3745 0 4 1 2 | |
55 58793 58789 15102 667 3744 0 4 1 2 | |
56 58849 58845 15124 668 3743 0 4 1 2 | |
53 58902 58899 15147 669 3742 0 4 1 2 | |
57 58959 58955 15170 670 3741 0 4 1 2 | |
55 59014 59009 15192 671 3740 0 4 1 2 | |
55 59069 59066 15215 672 3739 0 4 1 2 | |
54 59123 59119 15238 673 3738 0 4 1 2 | |
55 59178 59174 15260 674 3737 0 4 1 2 | |
52 59230 59227 15283 675 3736 0 4 1 2 | |
53 59283 59280 15306 676 3735 0 4 1 2 | |
97 59380 59375 15328 677 3734 0 4 1 2 | |
62 59442 59437 15351 678 3733 0 4 1 2 | |
56 59498 59494 15374 679 3732 0 4 1 2 | |
118 59616 59609 15396 680 3731 0 4 1 2 | |
70 59686 59681 15419 681 3730 0 4 1 2 | |
57 59743 59739 15442 682 3729 0 4 1 2 | |
56 59799 59794 15464 683 3728 0 4 1 2 | |
54 59853 59849 15487 684 3727 0 4 1 2 | |
54 59907 59903 15510 685 3726 0 4 1 2 | |
54 59961 59957 15532 686 3725 0 4 1 2 | |
52 60013 60009 15555 687 3724 0 4 1 2 | |
52 60065 60062 15578 688 3723 0 4 1 2 | |
53 60118 60115 15600 689 3722 0 4 1 2 | |
53 60171 60166 15623 690 3721 0 4 1 2 | |
52 60223 60219 15646 691 3720 0 4 1 2 | |
53 60276 60272 15668 692 3719 0 4 1 2 | |
92 60368 60363 15691 693 3718 0 4 1 2 | |
64 60432 60428 15714 694 3717 0 4 1 2 | |
54 60486 60482 15736 695 3716 0 4 1 2 | |
52 60538 60535 15759 696 3715 0 4 1 2 | |
126 60664 60659 15782 697 3714 0 4 1 2 | |
63 60727 60723 15804 698 3713 0 4 1 2 | |
116 60843 60838 15827 699 3712 0 4 1 2 | |
71 60914 60909 15850 700 3711 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
62 60976 60971 15873 701 3710 0 4 1 2 | |
60 61036 61032 15895 702 3709 0 4 1 2 | |
57 61093 61089 15918 703 3708 0 4 1 2 | |
53 61146 61142 15941 704 3707 0 4 1 2 | |
55 61201 61198 15963 705 3706 0 4 1 2 | |
54 61255 61251 15986 706 3705 0 4 1 2 | |
91 61346 61342 16009 707 3704 0 4 1 2 | |
64 61410 61406 16031 708 3703 0 4 1 2 | |
62 61472 61468 16054 709 3702 0 4 1 2 | |
54 61526 61523 16077 710 3701 0 4 1 2 | |
133 61659 61654 16099 711 3700 0 4 1 2 | |
66 61725 61721 16122 712 3699 0 4 1 2 | |
55 61780 61776 16145 713 3698 0 4 1 2 | |
55 61835 61832 16167 714 3697 0 4 1 2 | |
53 61888 61885 16190 715 3696 0 4 1 2 | |
56 61944 61940 16213 716 3695 0 4 1 2 | |
53 61997 61993 16235 717 3694 0 4 1 2 | |
54 62051 62047 16258 718 3693 0 4 1 2 | |
53 62104 62100 16281 719 3692 0 4 1 2 | |
51 62155 62152 16303 720 3691 0 4 1 2 | |
54 62209 62206 16326 721 3690 0 4 1 2 | |
52 62261 62258 16349 722 3689 0 4 1 2 | |
92 62353 62348 16371 723 3688 0 4 1 2 | |
63 62416 62411 16394 724 3687 0 4 1 2 | |
60 62476 62471 16417 725 3686 0 4 1 2 | |
54 62530 62526 16439 726 3685 0 4 1 2 | |
122 62652 62647 16462 727 3684 0 4 1 2 | |
65 62717 62713 16485 728 3683 0 4 1 2 | |
56 62773 62769 16507 729 3682 0 4 1 2 | |
58 62831 62827 16530 730 3681 0 4 1 2 | |
54 62885 62881 16553 731 3680 0 4 1 2 | |
57 62942 62937 16575 732 3679 0 4 1 2 | |
55 62997 62992 16598 733 3678 0 4 1 2 | |
55 63052 63049 16621 734 3677 0 4 1 2 | |
53 63105 63101 16643 735 3676 0 4 1 2 | |
53 63158 63154 16666 736 3675 0 4 1 2 | |
55 63213 63209 16689 737 3674 0 4 1 2 | |
53 63266 63262 16712 738 3673 0 4 1 2 | |
96 63362 63357 16734 739 3672 0 4 1 2 | |
66 63428 63423 16757 740 3671 0 4 1 2 | |
56 63484 63481 16780 741 3670 0 4 1 2 | |
54 63538 63535 16802 742 3669 0 4 1 2 | |
126 63664 63658 16825 743 3668 0 4 1 2 | |
108 63772 63767 16848 744 3667 0 4 1 2 | |
63 63835 63831 16870 745 3666 0 4 1 2 | |
56 63891 63887 16893 746 3665 0 4 1 2 | |
57 63948 63944 16916 747 3664 0 4 1 2 | |
54 64002 63998 16938 748 3663 0 4 1 2 | |
55 64057 64053 16961 749 3662 0 4 1 2 | |
54 64111 64107 16984 750 3661 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
53 64164 64160 17006 751 3660 0 4 1 2 | |
62 64226 64223 17029 752 3659 0 4 1 2 | |
55 64281 64277 17052 753 3658 0 4 1 2 | |
104 64385 64381 17074 754 3657 0 4 1 2 | |
98 64483 64477 17097 755 3656 0 4 1 2 | |
61 64544 64540 17120 756 3655 0 4 1 2 | |
134 64678 64673 17142 757 3654 0 4 1 2 | |
60 64738 64734 17165 758 3653 0 4 1 2 | |
54 64792 64788 17188 759 3652 0 4 1 2 | |
56 64848 64844 17210 760 3651 0 4 1 2 | |
52 64900 64897 17233 761 3650 0 4 1 2 | |
56 64956 64952 17256 762 3649 0 4 1 2 | |
52 65008 65004 17278 763 3648 0 4 1 2 | |
55 65063 65059 17301 764 3647 0 4 1 2 | |
54 65117 65113 17324 765 3646 0 4 1 2 | |
52 65169 65165 17346 766 3645 0 4 1 2 | |
54 65223 65220 17369 767 3644 0 4 1 2 | |
52 65275 65271 17392 768 3643 0 4 1 2 | |
95 65370 65365 17414 769 3642 0 4 1 2 | |
66 65436 65431 17437 770 3641 0 4 1 2 | |
56 65492 65488 17460 771 3640 0 4 1 2 | |
55 65547 65542 17482 772 3639 0 4 1 2 | |
131 65678 65673 17505 773 3638 0 4 1 2 | |
60 65738 65734 17528 774 3637 0 4 1 2 | |
54 65792 65788 17551 775 3636 0 4 1 2 | |
55 65847 65844 17573 776 3635 0 4 1 2 | |
53 65900 65897 17596 777 3634 0 4 1 2 | |
55 65955 65951 17619 778 3633 0 4 1 2 | |
53 66008 66005 17641 779 3632 0 4 1 2 | |
55 66063 66059 17664 780 3631 0 4 1 2 | |
52 66115 66112 17687 781 3630 0 4 1 2 | |
53 66168 66164 17709 782 3629 0 4 1 2 | |
54 66222 66219 17732 783 3628 0 4 1 2 | |
52 66274 66271 17755 784 3627 0 4 1 2 | |
95 66369 66364 17777 785 3626 0 4 1 2 | |
64 66433 66429 17800 786 3625 0 4 1 2 | |
56 66489 66485 17823 787 3624 0 4 1 2 | |
52 66541 66538 17845 788 3623 0 4 1 2 | |
128 66669 66664 17868 789 3622 0 4 1 2 | |
61 66730 66726 17891 790 3621 0 4 1 2 | |
54 66784 66781 17913 791 3620 0 4 1 2 | |
57 66841 66837 17936 792 3619 0 4 1 2 | |
51 66892 66889 17959 793 3618 0 4 1 2 | |
54 66946 66943 17981 794 3617 0 4 1 2 | |
51 66997 66994 18004 795 3616 0 4 1 2 | |
56 67053 67049 18027 796 3615 0 4 1 2 | |
52 67105 67102 18049 797 3614 0 4 1 2 | |
52 67157 67153 18072 798 3613 0 4 1 2 | |
54 67211 67207 18095 799 3612 0 4 1 2 | |
51 67262 67259 18117 800 3611 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
90 67352 67348 18140 801 3610 0 4 1 2 | |
67 67419 67415 18163 802 3609 0 4 1 2 | |
61 67480 67476 18185 803 3608 0 4 1 2 | |
53 67533 67530 18208 804 3607 0 4 1 2 | |
126 67659 67654 18231 805 3606 0 4 1 2 | |
65 67724 67720 18253 806 3605 0 4 1 2 | |
55 67779 67775 18276 807 3604 0 4 1 2 | |
56 67835 67831 18299 808 3603 0 4 1 2 | |
53 67888 67884 18321 809 3602 0 4 1 2 | |
55 67943 67939 18344 810 3601 0 4 1 2 | |
52 67995 67992 18367 811 3600 0 4 1 2 | |
55 68050 68045 18390 812 3599 0 4 1 2 | |
54 68104 68100 18412 813 3598 0 4 1 2 | |
53 68157 68153 18435 814 3597 0 4 1 2 | |
55 68212 68208 18458 815 3596 0 4 1 2 | |
54 68266 68262 18480 816 3595 0 4 1 2 | |
94 68360 68355 18503 817 3594 0 4 1 2 | |
65 68425 68417 18526 818 3593 0 4 1 2 | |
57 68482 68478 18548 819 3592 0 4 1 2 | |
54 68536 68533 18571 820 3591 0 4 1 2 | |
123 68659 68654 18594 821 3590 0 4 1 2 | |
63 68722 68718 18616 822 3589 0 4 1 2 | |
57 68779 68775 18639 823 3588 0 4 1 2 | |
56 68835 68831 18662 824 3587 0 4 1 2 | |
53 68888 68884 18684 825 3586 0 4 1 2 | |
55 68943 68940 18707 826 3585 0 4 1 2 | |
53 68996 68993 18730 827 3584 0 4 1 2 | |
54 69050 69045 18752 828 3583 0 4 1 2 | |
54 69104 69100 18775 829 3582 0 4 1 2 | |
51 69155 69151 18798 830 3581 0 4 1 2 | |
55 69210 69206 18820 831 3580 0 4 1 2 | |
53 69263 69260 18843 832 3579 0 4 1 2 | |
92 69355 69350 18866 833 3578 0 4 1 2 | |
62 69417 69413 18888 834 3577 0 4 1 2 | |
60 69477 69473 18911 835 3576 0 4 1 2 | |
54 69531 69527 18934 836 3575 0 4 1 2 | |
125 69656 69651 18956 837 3574 0 4 1 2 | |
64 69720 69716 18979 838 3573 0 4 1 2 | |
56 69776 69772 19002 839 3572 0 4 1 2 | |
55 69831 69828 19024 840 3571 0 4 1 2 | |
54 69885 69881 19047 841 3570 0 4 1 2 | |
54 69939 69935 19070 842 3569 0 4 1 2 | |
53 69992 69988 19092 843 3568 0 4 1 2 | |
52 70044 70040 19115 844 3567 0 4 1 2 | |
54 70098 70094 19138 845 3566 0 4 1 2 | |
52 70150 70147 19160 846 3565 0 4 1 2 | |
55 70205 70202 19183 847 3564 0 4 1 2 | |
127 70332 70292 19206 848 3563 0 4 1 2 | |
70 70402 70398 19229 849 3562 0 4 1 2 | |
62 70464 70460 19251 850 3561 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
55 70519 70516 19274 851 3560 0 4 1 2 | |
135 70654 70649 19297 852 3559 0 4 1 2 | |
68 70722 70717 19319 853 3558 0 4 1 2 | |
116 70838 70832 19342 854 3557 0 4 1 2 | |
68 70906 70902 19365 855 3556 0 4 1 2 | |
60 70966 70962 19387 856 3555 0 4 1 2 | |
55 71021 71017 19410 857 3554 0 4 1 2 | |
56 71077 71073 19433 858 3553 0 4 1 2 | |
53 71130 71126 19455 859 3552 0 4 1 2 | |
55 71185 71181 19478 860 3551 0 4 1 2 | |
54 71239 71235 19501 861 3550 0 4 1 2 | |
52 71291 71288 19523 862 3549 0 4 1 2 | |
101 71392 71387 19546 863 3548 0 4 1 2 | |
62 71454 71450 19569 864 3547 0 4 1 2 | |
55 71509 71505 19591 865 3546 0 4 1 2 | |
121 71630 71624 19614 866 3545 0 4 1 2 | |
68 71698 71694 19637 867 3544 0 4 1 2 | |
57 71755 71751 19659 868 3543 0 4 1 2 | |
56 71811 71808 19682 869 3542 0 4 1 2 | |
55 71866 71862 19705 870 3541 0 4 1 2 | |
53 71919 71915 19727 871 3540 0 4 1 2 | |
56 71975 71972 19750 872 3539 0 4 1 2 | |
52 72027 72024 19773 873 3538 0 4 1 2 | |
55 72082 72079 19795 874 3537 0 4 1 2 | |
52 72134 72131 19818 875 3536 0 4 1 2 | |
55 72189 72185 19841 876 3535 0 4 1 2 | |
52 72241 72238 19863 877 3534 0 4 1 2 | |
53 72294 72290 19886 878 3533 0 4 1 2 | |
104 72398 72393 19909 879 3532 0 4 1 2 | |
94 72492 72488 19931 880 3531 0 4 1 2 | |
125 72617 72609 19954 881 3530 0 4 1 2 | |
73 72690 72686 19977 882 3529 0 4 1 2 | |
58 72748 72744 20000 883 3528 0 4 1 2 | |
56 72804 72800 20022 884 3527 0 4 1 2 | |
54 72858 72854 20045 885 3526 0 4 1 2 | |
52 72910 72906 20068 886 3525 0 4 1 2 | |
55 72965 72962 20090 887 3524 0 4 1 2 | |
53 73018 73014 20113 888 3523 0 4 1 2 | |
56 73074 73070 20136 889 3522 0 4 1 2 | |
52 73126 73122 20158 890 3521 0 4 1 2 | |
55 73181 73177 20181 891 3520 0 4 1 2 | |
53 73234 73230 20204 892 3519 0 4 1 2 | |
51 73285 73282 20226 893 3518 0 4 1 2 | |
96 73381 73376 20249 894 3517 0 4 1 2 | |
61 73442 73438 20272 895 3516 0 4 1 2 | |
58 73500 73496 20294 896 3515 0 4 1 2 | |
114 73614 73554 20317 897 3514 0 4 1 2 | |
73 73687 73682 20340 898 3513 0 4 1 2 | |
58 73745 73741 20362 899 3512 0 4 1 2 | |
57 73802 73798 20385 900 3511 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
54 73856 73852 20408 901 3510 0 4 1 2 | |
56 73912 73909 20430 902 3509 0 4 1 2 | |
57 73969 73965 20453 903 3508 0 4 1 2 | |
53 74022 74018 20476 904 3507 0 4 1 2 | |
55 74077 74074 20498 905 3506 0 4 1 2 | |
53 74130 74126 20521 906 3505 0 4 1 2 | |
55 74185 74181 20544 907 3504 0 4 1 2 | |
53 74238 74234 20566 908 3503 0 4 1 2 | |
52 74290 74286 20589 909 3502 0 4 1 2 | |
96 74386 74382 20612 910 3501 0 4 1 2 | |
62 74448 74444 20634 911 3500 0 4 1 2 | |
55 74503 74499 20657 912 3499 0 4 1 2 | |
117 74620 74613 20680 913 3498 0 4 1 2 | |
71 74691 74687 20702 914 3497 0 4 1 2 | |
59 74750 74746 20725 915 3496 0 4 1 2 | |
56 74806 74803 20748 916 3495 0 4 1 2 | |
55 74861 74857 20770 917 3494 0 4 1 2 | |
53 74914 74910 20793 918 3493 0 4 1 2 | |
56 74970 74965 20816 919 3492 0 4 1 2 | |
52 75022 75019 20839 920 3491 0 4 1 2 | |
55 75077 75073 20861 921 3490 0 4 1 2 | |
52 75129 75125 20884 922 3489 0 4 1 2 | |
55 75184 75179 20907 923 3488 0 4 1 2 | |
54 75238 75234 20929 924 3487 0 4 1 2 | |
54 75292 75288 20952 925 3486 0 4 1 2 | |
97 75389 75384 20975 926 3485 0 4 1 2 | |
61 75450 75446 20997 927 3484 0 4 1 2 | |
56 75506 75502 21020 928 3483 0 4 1 2 | |
120 75626 75621 21043 929 3482 0 4 1 2 | |
69 75695 75691 21065 930 3481 0 4 1 2 | |
57 75752 75748 21088 931 3480 0 4 1 2 | |
57 75809 75805 21111 932 3479 0 4 1 2 | |
53 75862 75858 21133 933 3478 0 4 1 2 | |
53 75915 75912 21156 934 3477 0 4 1 2 | |
56 75971 75968 21179 935 3476 0 4 1 2 | |
52 76023 76019 21201 936 3475 0 4 1 2 | |
55 76078 76074 21224 937 3474 0 4 1 2 | |
53 76131 76128 21247 938 3473 0 4 1 2 | |
55 76186 76183 21269 939 3472 0 4 1 2 | |
53 76239 76235 21292 940 3471 0 4 1 2 | |
52 76291 76287 21315 941 3470 0 4 1 2 | |
97 76388 76383 21337 942 3469 0 4 1 2 | |
62 76450 76446 21360 943 3468 0 4 1 2 | |
55 76505 76502 21383 944 3467 0 4 1 2 | |
120 76625 76619 21405 945 3466 0 4 1 2 | |
71 76696 76692 21428 946 3465 0 4 1 2 | |
57 76753 76749 21451 947 3464 0 4 1 2 | |
57 76810 76806 21473 948 3463 0 4 1 2 | |
54 76864 76860 21496 949 3462 0 4 1 2 | |
53 76917 76913 21519 950 3461 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
55 76972 76969 21541 951 3460 0 4 1 2 | |
105 77077 77072 21564 952 3459 0 4 1 2 | |
59 77136 77132 21587 953 3458 0 4 1 2 | |
58 77194 77190 21609 954 3457 0 4 1 2 | |
55 77249 77245 21632 955 3456 0 4 1 2 | |
92 77341 77335 21655 956 3455 0 4 1 2 | |
66 77407 77403 21678 957 3454 0 4 1 2 | |
61 77468 77464 21700 958 3453 0 4 1 2 | |
54 77522 77518 21723 959 3452 0 4 1 2 | |
130 77652 77646 21746 960 3451 0 4 1 2 | |
65 77717 77713 21768 961 3450 0 4 1 2 | |
57 77774 77770 21791 962 3449 0 4 1 2 | |
57 77831 77827 21814 963 3448 0 4 1 2 | |
53 77884 77881 21836 964 3447 0 4 1 2 | |
56 77940 77936 21859 965 3446 0 4 1 2 | |
53 77993 77990 21882 966 3445 0 4 1 2 | |
52 78045 78041 21904 967 3444 0 4 1 2 | |
55 78100 78096 21927 968 3443 0 4 1 2 | |
53 78153 78149 21950 969 3442 0 4 1 2 | |
53 78206 78202 21972 970 3441 0 4 1 2 | |
53 78259 78256 21995 971 3440 0 4 1 2 | |
90 78349 78344 22018 972 3439 0 4 1 2 | |
65 78414 78410 22040 973 3438 0 4 1 2 | |
61 78475 78470 22063 974 3437 0 4 1 2 | |
53 78528 78524 22086 975 3436 0 4 1 2 | |
127 78655 78650 22108 976 3435 0 4 1 2 | |
66 78721 78717 22131 977 3434 0 4 1 2 | |
56 78777 78773 22154 978 3433 0 4 1 2 | |
56 78833 78830 22176 979 3432 0 4 1 2 | |
54 78887 78883 22199 980 3431 0 4 1 2 | |
54 78941 78938 22222 981 3430 0 4 1 2 | |
54 78995 78992 22244 982 3429 0 4 1 2 | |
56 79051 79045 22267 983 3428 0 4 1 2 | |
54 79105 79101 22290 984 3427 0 4 1 2 | |
52 79157 79154 22312 985 3426 0 4 1 2 | |
55 79212 79208 22335 986 3425 0 4 1 2 | |
51 79263 79260 22358 987 3424 0 4 1 2 | |
91 79354 79349 22380 988 3423 0 4 1 2 | |
61 79415 79411 22403 989 3422 0 4 1 2 | |
59 79474 79470 22426 990 3421 0 4 1 2 | |
54 79528 79524 22448 991 3420 0 4 1 2 | |
127 79655 79650 22471 992 3419 0 4 1 2 | |
65 79720 79716 22494 993 3418 0 4 1 2 | |
55 79775 79771 22517 994 3417 0 4 1 2 | |
57 79832 79828 22539 995 3416 0 4 1 2 | |
54 79886 79882 22562 996 3415 0 4 1 2 | |
54 79940 79937 22585 997 3414 0 4 1 2 | |
53 79993 79990 22607 998 3413 0 4 1 2 | |
56 80049 80044 22630 999 3412 0 4 1 2 | |
53 80102 80098 22653 1000 3411 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
53 80155 80151 22675 1001 3410 0 4 1 2 | |
60 80215 80211 22698 1002 3409 0 4 1 2 | |
55 80270 80266 22721 1003 3408 0 4 1 2 | |
99 80369 80365 22743 1004 3407 0 4 1 2 | |
93 80462 80457 22766 1005 3406 0 4 1 2 | |
65 80527 80522 22789 1006 3405 0 4 1 2 | |
129 80656 80651 22811 1007 3404 0 4 1 2 | |
67 80723 80718 22834 1008 3403 0 4 1 2 | |
119 80842 80773 22857 1009 3402 0 4 1 2 | |
73 80915 80911 22879 1010 3401 0 4 1 2 | |
62 80977 80973 22902 1011 3400 0 4 1 2 | |
54 81031 81027 22925 1012 3399 0 4 1 2 | |
57 81088 81084 22947 1013 3398 0 4 1 2 | |
53 81141 81138 22970 1014 3397 0 4 1 2 | |
56 81197 81194 22993 1015 3396 0 4 1 2 | |
54 81251 81247 23015 1016 3395 0 4 1 2 | |
93 81344 81338 23038 1017 3394 0 4 1 2 | |
64 81408 81404 23061 1018 3393 0 4 1 2 | |
62 81470 81466 23083 1019 3392 0 4 1 2 | |
55 81525 81521 23106 1020 3391 0 4 1 2 | |
128 81653 81648 23129 1021 3390 0 4 1 2 | |
65 81718 81714 23151 1022 3389 0 4 1 2 | |
56 81774 81770 23174 1023 3388 0 4 1 2 | |
56 81830 81826 23197 1024 3387 0 4 1 2 | |
53 81883 81879 23219 1025 3386 0 4 1 2 | |
54 81937 81933 23242 1026 3385 0 4 1 2 | |
53 81990 81987 23265 1027 3384 0 4 1 2 | |
52 82042 82039 23287 1028 3383 0 4 1 2 | |
55 82097 82094 23310 1029 3382 0 4 1 2 | |
53 82150 82147 23333 1030 3381 0 4 1 2 | |
56 82206 82202 23356 1031 3380 0 4 1 2 | |
53 82259 82255 23378 1032 3379 0 4 1 2 | |
89 82348 82344 23401 1033 3378 0 4 1 2 | |
64 82412 82408 23424 1034 3377 0 4 1 2 | |
59 82471 82467 23446 1035 3376 0 4 1 2 | |
56 82527 82523 23469 1036 3375 0 4 1 2 | |
129 82656 82651 23492 1037 3374 0 4 1 2 | |
66 82722 82717 23514 1038 3373 0 4 1 2 | |
55 82777 82773 23537 1039 3372 0 4 1 2 | |
56 82833 82829 23560 1040 3371 0 4 1 2 | |
54 82887 82883 23582 1041 3370 0 4 1 2 | |
54 82941 82938 23605 1042 3369 0 4 1 2 | |
55 82996 82992 23628 1043 3368 0 4 1 2 | |
55 83051 83045 23650 1044 3367 0 4 1 2 | |
53 83104 83101 23673 1045 3366 0 4 1 2 | |
53 83157 83154 23696 1046 3365 0 4 1 2 | |
55 83212 83208 23718 1047 3364 0 4 1 2 | |
52 83264 83261 23741 1048 3363 0 4 1 2 | |
90 83354 83350 23764 1049 3362 0 4 1 2 | |
61 83415 83411 23786 1050 3361 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
61 83476 83472 23809 1051 3360 0 4 1 2 | |
60 83536 83532 23832 1052 3359 0 4 1 2 | |
129 83665 83659 23854 1053 3358 0 4 1 2 | |
112 83777 83772 23877 1054 3357 0 4 1 2 | |
64 83841 83838 23900 1055 3356 0 4 1 2 | |
56 83897 83893 23922 1056 3355 0 4 1 2 | |
57 83954 83950 23945 1057 3354 0 4 1 2 | |
52 84006 84003 23968 1058 3353 0 4 1 2 | |
54 84060 84057 23990 1059 3352 0 4 1 2 | |
54 84114 84110 24013 1060 3351 0 4 1 2 | |
52 84166 84162 24036 1061 3350 0 4 1 2 | |
55 84221 84217 24058 1062 3349 0 4 1 2 | |
52 84273 84269 24081 1063 3348 0 4 1 2 | |
106 84379 84374 24104 1064 3347 0 4 1 2 | |
67 84446 84441 24126 1065 3346 0 4 1 2 | |
56 84502 84498 24149 1066 3345 0 4 1 2 | |
123 84625 84618 24172 1067 3344 0 4 1 2 | |
70 84695 84690 24195 1068 3343 0 4 1 2 | |
57 84752 84748 24217 1069 3342 0 4 1 2 | |
58 84810 84806 24240 1070 3341 0 4 1 2 | |
53 84863 84860 24263 1071 3340 0 4 1 2 | |
53 84916 84912 24285 1072 3339 0 4 1 2 | |
55 84971 84968 24308 1073 3338 0 4 1 2 | |
54 85025 85021 24331 1074 3337 0 4 1 2 | |
56 85081 85077 24353 1075 3336 0 4 1 2 | |
54 85135 85131 24376 1076 3335 0 4 1 2 | |
53 85188 85184 24399 1077 3334 0 4 1 2 | |
53 85241 85237 24421 1078 3333 0 4 1 2 | |
53 85294 85290 24444 1079 3332 0 4 1 2 | |
97 85391 85386 24467 1080 3331 0 4 1 2 | |
61 85452 85448 24489 1081 3330 0 4 1 2 | |
55 85507 85503 24512 1082 3329 0 4 1 2 | |
117 85624 85619 24535 1083 3328 0 4 1 2 | |
70 85694 85690 24557 1084 3327 0 4 1 2 | |
58 85752 85748 24580 1085 3326 0 4 1 2 | |
57 85809 85805 24603 1086 3325 0 4 1 2 | |
54 85863 85859 24625 1087 3324 0 4 1 2 | |
53 85916 85913 24648 1088 3323 0 4 1 2 | |
54 85970 85966 24671 1089 3322 0 4 1 2 | |
53 86023 86019 24693 1090 3321 0 4 1 2 | |
56 86079 86075 24716 1091 3320 0 4 1 2 | |
52 86131 86127 24739 1092 3319 0 4 1 2 | |
55 86186 86183 24761 1093 3318 0 4 1 2 | |
53 86239 86235 24784 1094 3317 0 4 1 2 | |
53 86292 86289 24807 1095 3316 0 4 1 2 | |
98 86390 86385 24829 1096 3315 0 4 1 2 | |
63 86453 86449 24852 1097 3314 0 4 1 2 | |
55 86508 86504 24875 1098 3313 0 4 1 2 | |
117 86625 86620 24897 1099 3312 0 4 1 2 | |
70 86695 86690 24920 1100 3311 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
58 86753 86749 24943 1101 3310 0 4 1 2 | |
61 86814 86810 24965 1102 3309 0 4 1 2 | |
55 86869 86866 24988 1103 3308 0 4 1 2 | |
53 86922 86918 25011 1104 3307 0 4 1 2 | |
55 86977 86973 25034 1105 3306 0 4 1 2 | |
51 87028 87024 25056 1106 3305 0 4 1 2 | |
55 87083 87079 25079 1107 3304 0 4 1 2 | |
51 87134 87131 25102 1108 3303 0 4 1 2 | |
56 87190 87186 25124 1109 3302 0 4 1 2 | |
54 87244 87240 25147 1110 3301 0 4 1 2 | |
50 87294 87290 25170 1111 3300 0 4 1 2 | |
98 87392 87387 25192 1112 3299 0 4 1 2 | |
62 87454 87450 25215 1113 3298 0 4 1 2 | |
56 87510 87506 25238 1114 3297 0 4 1 2 | |
120 87630 87625 25260 1115 3296 0 4 1 2 | |
72 87702 87697 25283 1116 3295 0 4 1 2 | |
57 87759 87756 25306 1117 3294 0 4 1 2 | |
57 87816 87812 25328 1118 3293 0 4 1 2 | |
53 87869 87865 25351 1119 3292 0 4 1 2 | |
53 87922 87918 25374 1120 3291 0 4 1 2 | |
56 87978 87974 25396 1121 3290 0 4 1 2 | |
52 88030 88026 25419 1122 3289 0 4 1 2 | |
56 88086 88082 25442 1123 3288 0 4 1 2 | |
52 88138 88134 25464 1124 3287 0 4 1 2 | |
55 88193 88188 25487 1125 3286 0 4 1 2 | |
53 88246 88242 25510 1126 3285 0 4 1 2 | |
90 88336 88295 25532 1127 3284 0 4 1 2 | |
69 88405 88400 25555 1128 3283 0 4 1 2 | |
92 88497 88492 25578 1129 3282 0 4 1 2 | |
121 88618 88611 25600 1130 3281 0 4 1 2 | |
71 88689 88685 25623 1131 3280 0 4 1 2 | |
57 88746 88742 25646 1132 3279 0 4 1 2 | |
58 88804 88800 25668 1133 3278 0 4 1 2 | |
52 88856 88853 25691 1134 3277 0 4 1 2 | |
53 88909 88905 25714 1135 3276 0 4 1 2 | |
55 88964 88961 25736 1136 3275 0 4 1 2 | |
54 89018 89015 25759 1137 3274 0 4 1 2 | |
56 89074 89071 25782 1138 3273 0 4 1 2 | |
53 89127 89123 25804 1139 3272 0 4 1 2 | |
53 89180 89177 25827 1140 3271 0 4 1 2 | |
52 89232 89228 25850 1141 3270 0 4 1 2 | |
52 89284 89281 25873 1142 3269 0 4 1 2 | |
94 89378 89373 25895 1143 3268 0 4 1 2 | |
62 89440 89436 25918 1144 3267 0 4 1 2 | |
57 89497 89493 25941 1145 3266 0 4 1 2 | |
115 89612 89551 25963 1146 3265 0 4 1 2 | |
73 89685 89680 25986 1147 3264 0 4 1 2 | |
58 89743 89739 26009 1148 3263 0 4 1 2 | |
55 89798 89795 26031 1149 3262 0 4 1 2 | |
55 89853 89850 26054 1150 3261 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
54 89907 89903 26077 1151 3260 0 4 1 2 | |
58 89965 89961 26099 1152 3259 0 4 1 2 | |
56 90021 90017 26122 1153 3258 0 4 1 2 | |
55 90076 90072 26145 1154 3257 0 4 1 2 | |
92 90168 90163 26167 1155 3256 0 4 1 2 | |
64 90232 90228 26190 1156 3255 0 4 1 2 | |
55 90287 90283 26213 1157 3254 0 4 1 2 | |
99 90386 90382 26235 1158 3253 0 4 1 2 | |
65 90451 90446 26258 1159 3252 0 4 1 2 | |
55 90506 90502 26281 1160 3251 0 4 1 2 | |
121 90627 90621 26303 1161 3250 0 4 1 2 | |
70 90697 90692 26326 1162 3249 0 4 1 2 | |
58 90755 90751 26349 1163 3248 0 4 1 2 | |
120 90875 90871 26371 1164 3247 0 4 1 2 | |
65 90940 90936 26394 1165 3246 0 4 1 2 | |
57 90997 90993 26417 1166 3245 0 4 1 2 | |
55 91052 91047 26439 1167 3244 0 4 1 2 | |
54 91106 91103 26462 1168 3243 0 4 1 2 | |
53 91159 91156 26485 1169 3242 0 4 1 2 | |
56 91215 91210 26507 1170 3241 0 4 1 2 | |
52 91267 91264 26530 1171 3240 0 4 1 2 | |
95 91362 91358 26553 1172 3239 0 4 1 2 | |
66 91428 91421 26575 1173 3238 0 4 1 2 | |
57 91485 91481 26598 1174 3237 0 4 1 2 | |
53 91538 91534 26621 1175 3236 0 4 1 2 | |
132 91670 91665 26643 1176 3235 0 4 1 2 | |
62 91732 91728 26666 1177 3234 0 4 1 2 | |
55 91787 91784 26689 1178 3233 0 4 1 2 | |
55 91842 91838 26712 1179 3232 0 4 1 2 | |
55 91897 91893 26734 1180 3231 0 4 1 2 | |
54 91951 91947 26757 1181 3230 0 4 1 2 | |
53 92004 92000 26780 1182 3229 0 4 1 2 | |
55 92059 92055 26802 1183 3228 0 4 1 2 | |
54 92113 92109 26825 1184 3227 0 4 1 2 | |
51 92164 92161 26848 1185 3226 0 4 1 2 | |
56 92220 92216 26870 1186 3225 0 4 1 2 | |
52 92272 92268 26893 1187 3224 0 4 1 2 | |
94 92366 92361 26916 1188 3223 0 4 1 2 | |
65 92431 92427 26938 1189 3222 0 4 1 2 | |
57 92488 92484 26961 1190 3221 0 4 1 2 | |
53 92541 92537 26984 1191 3220 0 4 1 2 | |
127 92668 92663 27006 1192 3219 0 4 1 2 | |
64 92732 92728 27029 1193 3218 0 4 1 2 | |
56 92788 92784 27052 1194 3217 0 4 1 2 | |
57 92845 92840 27074 1195 3216 0 4 1 2 | |
52 92897 92893 27097 1196 3215 0 4 1 2 | |
57 92954 92950 27120 1197 3214 0 4 1 2 | |
51 93005 93002 27142 1198 3213 0 4 1 2 | |
56 93061 93057 27165 1199 3212 0 4 1 2 | |
53 93114 93111 27188 1200 3211 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
54 93168 93164 27210 1201 3210 0 4 1 2 | |
60 93228 93223 27233 1202 3209 0 4 1 2 | |
54 93282 93278 27256 1203 3208 0 4 1 2 | |
95 93377 93372 27278 1204 3207 0 4 1 2 | |
63 93440 93436 27301 1205 3206 0 4 1 2 | |
57 93497 93493 27324 1206 3205 0 4 1 2 | |
55 93552 93546 27346 1207 3204 0 4 1 2 | |
128 93680 93673 27369 1208 3203 0 4 1 2 | |
61 93741 93737 27392 1209 3202 0 4 1 2 | |
55 93796 93792 27414 1210 3201 0 4 1 2 | |
57 93853 93849 27437 1211 3200 0 4 1 2 | |
53 93906 93902 27460 1212 3199 0 4 1 2 | |
55 93961 93958 27482 1213 3198 0 4 1 2 | |
53 94014 94010 27505 1214 3197 0 4 1 2 | |
53 94067 94063 27528 1215 3196 0 4 1 2 | |
53 94120 94116 27551 1216 3195 0 4 1 2 | |
52 94172 94169 27573 1217 3194 0 4 1 2 | |
56 94228 94224 27596 1218 3193 0 4 1 2 | |
51 94279 94275 27619 1219 3192 0 4 1 2 | |
94 94373 94368 27641 1220 3191 0 4 1 2 | |
63 94436 94432 27664 1221 3190 0 4 1 2 | |
56 94492 94488 27687 1222 3189 0 4 1 2 | |
53 94545 94542 27709 1223 3188 0 4 1 2 | |
132 94677 94670 27732 1224 3187 0 4 1 2 | |
60 94737 94734 27755 1225 3186 0 4 1 2 | |
55 94792 94787 27777 1226 3185 0 4 1 2 | |
56 94848 94844 27800 1227 3184 0 4 1 2 | |
54 94902 94898 27823 1228 3183 0 4 1 2 | |
57 94959 94955 27845 1229 3182 0 4 1 2 | |
52 95011 95007 27868 1230 3181 0 4 1 2 | |
56 95067 95063 27891 1231 3180 0 4 1 2 | |
54 95121 95117 27913 1232 3179 0 4 1 2 | |
52 95173 95169 27936 1233 3178 0 4 1 2 | |
56 95229 95225 27959 1234 3177 0 4 1 2 | |
52 95281 95277 27981 1235 3176 0 4 1 2 | |
93 95374 95369 28004 1236 3175 0 4 1 2 | |
65 95439 95435 28027 1237 3174 0 4 1 2 | |
56 95495 95491 28049 1238 3173 0 4 1 2 | |
56 95551 95545 28072 1239 3172 0 4 1 2 | |
128 95679 95672 28095 1240 3171 0 4 1 2 | |
59 95738 95734 28117 1241 3170 0 4 1 2 | |
55 95793 95789 28140 1242 3169 0 4 1 2 | |
56 95849 95846 28163 1243 3168 0 4 1 2 | |
54 95903 95899 28185 1244 3167 0 4 1 2 | |
56 95959 95955 28208 1245 3166 0 4 1 2 | |
53 96012 96008 28231 1246 3165 0 4 1 2 | |
54 96066 96062 28253 1247 3164 0 4 1 2 | |
53 96119 96115 28276 1248 3163 0 4 1 2 | |
53 96172 96168 28299 1249 3162 0 4 1 2 | |
56 96228 96224 28321 1250 3161 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
53 96281 96277 28344 1251 3160 0 4 1 2 | |
103 96384 96379 28367 1252 3159 0 4 1 2 | |
94 96478 96474 28390 1253 3158 0 4 1 2 | |
63 96541 96537 28412 1254 3157 0 4 1 2 | |
130 96671 96666 28435 1255 3156 0 4 1 2 | |
63 96734 96730 28458 1256 3155 0 4 1 2 | |
105 96839 96834 28480 1257 3154 0 4 1 2 | |
57 96896 96892 28503 1258 3153 0 4 1 2 | |
58 96954 96950 28526 1259 3152 0 4 1 2 | |
53 97007 97004 28548 1260 3151 0 4 1 2 | |
54 97061 97057 28571 1261 3150 0 4 1 2 | |
53 97114 97110 28594 1262 3149 0 4 1 2 | |
52 97166 97162 28616 1263 3148 0 4 1 2 | |
54 97220 97216 28639 1264 3147 0 4 1 2 | |
53 97273 97269 28662 1265 3146 0 4 1 2 | |
97 97370 97366 28684 1266 3145 0 4 1 2 | |
66 97436 97431 28707 1267 3144 0 4 1 2 | |
56 97492 97488 28730 1268 3143 0 4 1 2 | |
53 97545 97542 28752 1269 3142 0 4 1 2 | |
133 97678 97671 28775 1270 3141 0 4 1 2 | |
62 97740 97736 28798 1271 3140 0 4 1 2 | |
56 97796 97792 28820 1272 3139 0 4 1 2 | |
56 97852 97848 28843 1273 3138 0 4 1 2 | |
54 97906 97902 28866 1274 3137 0 4 1 2 | |
54 97960 97956 28888 1275 3136 0 4 1 2 | |
53 98013 98009 28911 1276 3135 0 4 1 2 | |
55 98068 98064 28934 1277 3134 0 4 1 2 | |
53 98121 98118 28956 1278 3133 0 4 1 2 | |
56 98177 98171 28979 1279 3132 0 4 1 2 | |
54 98231 98227 29002 1280 3131 0 4 1 2 | |
53 98284 98280 29024 1281 3130 0 4 1 2 | |
93 98377 98372 29047 1282 3129 0 4 1 2 | |
62 98439 98435 29070 1283 3128 0 4 1 2 | |
57 98496 98492 29092 1284 3127 0 4 1 2 | |
52 98548 98545 29115 1285 3126 0 4 1 2 | |
133 98681 98674 29138 1286 3125 0 4 1 2 | |
59 98740 98736 29160 1287 3124 0 4 1 2 | |
55 98795 98792 29183 1288 3123 0 4 1 2 | |
56 98851 98847 29206 1289 3122 0 4 1 2 | |
53 98904 98901 29229 1290 3121 0 4 1 2 | |
56 98960 98956 29251 1291 3120 0 4 1 2 | |
53 99013 99010 29274 1292 3119 0 4 1 2 | |
56 99069 99065 29297 1293 3118 0 4 1 2 | |
52 99121 99118 29319 1294 3117 0 4 1 2 | |
56 99177 99171 29342 1295 3116 0 4 1 2 | |
53 99230 99226 29365 1296 3115 0 4 1 2 | |
53 99283 99280 29387 1297 3114 0 4 1 2 | |
93 99376 99371 29410 1298 3113 0 4 1 2 | |
64 99440 99436 29433 1299 3112 0 4 1 2 | |
57 99497 99493 29455 1300 3111 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
56 99553 99547 29478 1301 3110 0 4 1 2 | |
135 99688 99683 29501 1302 3109 0 4 1 2 | |
60 99748 99744 29523 1303 3108 0 4 1 2 | |
57 99805 99799 29546 1304 3107 0 4 1 2 | |
55 99860 99857 29569 1305 3106 0 4 1 2 | |
53 99913 99910 29591 1306 3105 0 4 1 2 | |
56 99969 99965 29614 1307 3104 0 4 1 2 | |
54 100023 100019 29637 1308 3103 0 4 1 2 | |
56 100079 100075 29659 1309 3102 0 4 1 2 | |
53 100132 100128 29682 1310 3101 0 4 1 2 | |
55 100187 100183 29705 1311 3100 0 4 1 2 | |
54 100241 100237 29727 1312 3099 0 4 1 2 | |
52 100293 100290 29750 1313 3098 0 4 1 2 | |
99 100392 100387 29773 1314 3097 0 4 1 2 | |
63 100455 100451 29795 1315 3096 0 4 1 2 | |
56 100511 100507 29818 1316 3095 0 4 1 2 | |
121 100632 100627 29841 1317 3094 0 4 1 2 | |
70 100702 100698 29863 1318 3093 0 4 1 2 | |
58 100760 100755 29886 1319 3092 0 4 1 2 | |
126 100886 100881 29909 1320 3091 0 4 1 2 | |
65 100951 100947 29931 1321 3090 0 4 1 2 | |
56 101007 101003 29954 1322 3089 0 4 1 2 | |
56 101063 101059 29977 1323 3088 0 4 1 2 | |
54 101117 101113 30000 1324 3087 0 4 1 2 | |
54 101171 101166 30022 1325 3086 0 4 1 2 | |
56 101227 101222 30045 1326 3085 0 4 1 2 | |
52 101279 101275 30068 1327 3084 0 4 1 2 | |
98 101377 101372 30090 1328 3083 0 4 1 2 | |
64 101441 101437 30113 1329 3082 0 4 1 2 | |
57 101498 101494 30136 1330 3081 0 4 1 2 | |
54 101552 101546 30158 1331 3080 0 4 1 2 | |
137 101689 101683 30181 1332 3079 0 4 1 2 | |
59 101748 101743 30204 1333 3078 0 4 1 2 | |
56 101804 101798 30226 1334 3077 0 4 1 2 | |
55 101859 101855 30249 1335 3076 0 4 1 2 | |
53 101912 101908 30272 1336 3075 0 4 1 2 | |
55 101967 101963 30294 1337 3074 0 4 1 2 | |
53 102020 102016 30317 1338 3073 0 4 1 2 | |
54 102074 102070 30340 1339 3072 0 4 1 2 | |
52 102126 102123 30362 1340 3071 0 4 1 2 | |
56 102182 102178 30385 1341 3070 0 4 1 2 | |
52 102234 102230 30408 1342 3069 0 4 1 2 | |
52 102286 102283 30430 1343 3068 0 4 1 2 | |
95 102381 102376 30453 1344 3067 0 4 1 2 | |
63 102444 102440 30476 1345 3066 0 4 1 2 | |
56 102500 102496 30498 1346 3065 0 4 1 2 | |
114 102614 102552 30521 1347 3064 0 4 1 2 | |
75 102689 102685 30544 1348 3063 0 4 1 2 | |
59 102748 102744 30566 1349 3062 0 4 1 2 | |
56 102804 102798 30589 1350 3061 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
55 102859 102855 30612 1351 3060 0 4 1 2 | |
56 102915 102911 30634 1352 3059 0 4 1 2 | |
57 102972 102968 30657 1353 3058 0 4 1 2 | |
54 103026 103022 30680 1354 3057 0 4 1 2 | |
56 103082 103079 30702 1355 3056 0 4 1 2 | |
106 103188 103183 30725 1356 3055 0 4 1 2 | |
61 103249 103245 30748 1357 3054 0 4 1 2 | |
94 103343 103299 30770 1358 3053 0 4 1 2 | |
66 103409 103405 30793 1359 3052 0 4 1 2 | |
62 103471 103467 30816 1360 3051 0 4 1 2 | |
57 103528 103524 30839 1361 3050 0 4 1 2 | |
132 103660 103655 30861 1362 3049 0 4 1 2 | |
66 103726 103721 30884 1363 3048 0 4 1 2 | |
57 103783 103778 30907 1364 3047 0 4 1 2 | |
56 103839 103836 30929 1365 3046 0 4 1 2 | |
55 103894 103889 30952 1366 3045 0 4 1 2 | |
55 103949 103945 30975 1367 3044 0 4 1 2 | |
54 104003 103999 30997 1368 3043 0 4 1 2 | |
54 104057 104054 31020 1369 3042 0 4 1 2 | |
53 104110 104106 31043 1370 3041 0 4 1 2 | |
52 104162 104159 31065 1371 3040 0 4 1 2 | |
54 104216 104212 31088 1372 3039 0 4 1 2 | |
53 104269 104266 31111 1373 3038 0 4 1 2 | |
96 104365 104361 31133 1374 3037 0 4 1 2 | |
94 104459 104424 31156 1375 3036 0 4 1 2 | |
66 104525 104521 31179 1376 3035 0 4 1 2 | |
131 104656 104651 31201 1377 3034 0 4 1 2 | |
65 104721 104718 31224 1378 3033 0 4 1 2 | |
56 104777 104773 31247 1379 3032 0 4 1 2 | |
55 104832 104828 31269 1380 3031 0 4 1 2 | |
53 104885 104881 31292 1381 3030 0 4 1 2 | |
54 104939 104936 31315 1382 3029 0 4 1 2 | |
54 104993 104989 31337 1383 3028 0 4 1 2 | |
53 105046 105042 31360 1384 3027 0 4 1 2 | |
53 105099 105096 31383 1385 3026 0 4 1 2 | |
53 105152 105149 31405 1386 3025 0 4 1 2 | |
57 105209 105205 31428 1387 3024 0 4 1 2 | |
52 105261 105258 31451 1388 3023 0 4 1 2 | |
94 105355 105351 31473 1389 3022 0 4 1 2 | |
64 105419 105415 31496 1390 3021 0 4 1 2 | |
95 105514 105509 31519 1391 3020 0 4 1 2 | |
126 105640 105635 31541 1392 3019 0 4 1 2 | |
70 105710 105705 31564 1393 3018 0 4 1 2 | |
58 105768 105764 31587 1394 3017 0 4 1 2 | |
58 105826 105822 31609 1395 3016 0 4 1 2 | |
55 105881 105877 31632 1396 3015 0 4 1 2 | |
55 105936 105931 31655 1397 3014 0 4 1 2 | |
54 105990 105986 31678 1398 3013 0 4 1 2 | |
53 106043 106038 31700 1399 3012 0 4 1 2 | |
55 106098 106094 31723 1400 3011 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
53 106151 106147 31746 1401 3010 0 4 1 2 | |
60 106211 106207 31768 1402 3009 0 4 1 2 | |
54 106265 106261 31791 1403 3008 0 4 1 2 | |
89 106354 106349 31814 1404 3007 0 4 1 2 | |
64 106418 106413 31836 1405 3006 0 4 1 2 | |
61 106479 106475 31859 1406 3005 0 4 1 2 | |
55 106534 106530 31882 1407 3004 0 4 1 2 | |
125 106659 106654 31904 1408 3003 0 4 1 2 | |
66 106725 106720 31927 1409 3002 0 4 1 2 | |
56 106781 106777 31950 1410 3001 0 4 1 2 | |
56 106837 106833 31972 1411 3000 0 4 1 2 | |
54 106891 106887 31995 1412 2999 0 4 1 2 | |
56 106947 106944 32018 1413 2998 0 4 1 2 | |
55 107002 106998 32040 1414 2997 0 4 1 2 | |
55 107057 107053 32063 1415 2996 0 4 1 2 | |
54 107111 107107 32086 1416 2995 0 4 1 2 | |
52 107163 107160 32108 1417 2994 0 4 1 2 | |
55 107218 107214 32131 1418 2993 0 4 1 2 | |
52 107270 107266 32154 1419 2992 0 4 1 2 | |
94 107364 107360 32176 1420 2991 0 4 1 2 | |
61 107425 107421 32199 1421 2990 0 4 1 2 | |
61 107486 107482 32222 1422 2989 0 4 1 2 | |
54 107540 107536 32244 1423 2988 0 4 1 2 | |
124 107664 107659 32267 1424 2987 0 4 1 2 | |
63 107727 107722 32290 1425 2986 0 4 1 2 | |
55 107782 107778 32312 1426 2985 0 4 1 2 | |
56 107838 107834 32335 1427 2984 0 4 1 2 | |
54 107892 107888 32358 1428 2983 0 4 1 2 | |
56 107948 107944 32380 1429 2982 0 4 1 2 | |
54 108002 107998 32403 1430 2981 0 4 1 2 | |
55 108057 108053 32426 1431 2980 0 4 1 2 | |
53 108110 108106 32448 1432 2979 0 4 1 2 | |
52 108162 108158 32471 1433 2978 0 4 1 2 | |
56 108218 108213 32494 1434 2977 0 4 1 2 | |
53 108271 108267 32517 1435 2976 0 4 1 2 | |
94 108365 108360 32539 1436 2975 0 4 1 2 | |
65 108430 108422 32562 1437 2974 0 4 1 2 | |
56 108486 108482 32585 1438 2973 0 4 1 2 | |
53 108539 108535 32607 1439 2972 0 4 1 2 | |
122 108661 108656 32630 1440 2971 0 4 1 2 | |
65 108726 108722 32653 1441 2970 0 4 1 2 | |
57 108783 108779 32675 1442 2969 0 4 1 2 | |
57 108840 108836 32698 1443 2968 0 4 1 2 | |
53 108893 108889 32721 1444 2967 0 4 1 2 | |
55 108948 108944 32743 1445 2966 0 4 1 2 | |
54 109002 108997 32766 1446 2965 0 4 1 2 | |
52 109054 109049 32789 1447 2964 0 4 1 2 | |
55 109109 109105 32811 1448 2963 0 4 1 2 | |
53 109162 109159 32834 1449 2962 0 4 1 2 | |
56 109218 109214 32857 1450 2961 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
54 109272 109268 32879 1451 2960 0 4 1 2 | |
98 109370 109365 32902 1452 2959 0 4 1 2 | |
104 109474 109470 32925 1453 2958 0 4 1 2 | |
61 109535 109530 32947 1454 2957 0 4 1 2 | |
133 109668 109663 32970 1455 2956 0 4 1 2 | |
66 109734 109731 32993 1456 2955 0 4 1 2 | |
56 109790 109786 33015 1457 2954 0 4 1 2 | |
55 109845 109841 33038 1458 2953 0 4 1 2 | |
52 109897 109894 33061 1459 2952 0 4 1 2 | |
56 109953 109950 33083 1460 2951 0 4 1 2 | |
55 110008 110004 33106 1461 2950 0 4 1 2 | |
54 110062 110058 33129 1462 2949 0 4 1 2 | |
53 110115 110112 33151 1463 2948 0 4 1 2 | |
54 110169 110165 33174 1464 2947 0 4 1 2 | |
54 110223 110219 33197 1465 2946 0 4 1 2 | |
53 110276 110272 33219 1466 2945 0 4 1 2 | |
94 110370 110365 33242 1467 2944 0 4 1 2 | |
64 110434 110429 33265 1468 2943 0 4 1 2 | |
57 110491 110486 33287 1469 2942 0 4 1 2 | |
53 110544 110540 33310 1470 2941 0 4 1 2 | |
128 110672 110666 33333 1471 2940 0 4 1 2 | |
63 110735 110731 33356 1472 2939 0 4 1 2 | |
114 110849 110844 33378 1473 2938 0 4 1 2 | |
69 110918 110913 33401 1474 2937 0 4 1 2 | |
61 110979 110975 33424 1475 2936 0 4 1 2 | |
56 111035 111031 33446 1476 2935 0 4 1 2 | |
56 111091 111088 33469 1477 2934 0 4 1 2 | |
54 111145 111141 33492 1478 2933 0 4 1 2 | |
55 111200 111196 33514 1479 2932 0 4 1 2 | |
54 111254 111250 33537 1480 2931 0 4 1 2 | |
93 111347 111340 33560 1481 2930 0 4 1 2 | |
63 111410 111406 33582 1482 2929 0 4 1 2 | |
60 111470 111466 33605 1483 2928 0 4 1 2 | |
54 111524 111520 33628 1484 2927 0 4 1 2 | |
130 111654 111649 33650 1485 2926 0 4 1 2 | |
67 111721 111717 33673 1486 2925 0 4 1 2 | |
56 111777 111773 33696 1487 2924 0 4 1 2 | |
58 111835 111831 33718 1488 2923 0 4 1 2 | |
55 111890 111886 33741 1489 2922 0 4 1 2 | |
55 111945 111941 33764 1490 2921 0 4 1 2 | |
53 111998 111994 33786 1491 2920 0 4 1 2 | |
55 112053 112047 33809 1492 2919 0 4 1 2 | |
55 112108 112104 33832 1493 2918 0 4 1 2 | |
53 112161 112157 33854 1494 2917 0 4 1 2 | |
55 112216 112212 33877 1495 2916 0 4 1 2 | |
53 112269 112265 33900 1496 2915 0 4 1 2 | |
100 112369 112364 33922 1497 2914 0 4 1 2 | |
102 112471 112432 33945 1498 2913 0 4 1 2 | |
68 112539 112534 33968 1499 2912 0 4 1 2 | |
128 112667 112661 33990 1500 2911 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
65 112732 112727 34013 1501 2910 0 4 1 2 | |
62 112794 112790 34036 1502 2909 0 4 1 2 | |
57 112851 112847 34058 1503 2908 0 4 1 2 | |
54 112905 112901 34081 1504 2907 0 4 1 2 | |
55 112960 112956 34104 1505 2906 0 4 1 2 | |
53 113013 113009 34126 1506 2905 0 4 1 2 | |
55 113068 113064 34149 1507 2904 0 4 1 2 | |
54 113122 113118 34172 1508 2903 0 4 1 2 | |
53 113175 113172 34195 1509 2902 0 4 1 2 | |
56 113231 113227 34217 1510 2901 0 4 1 2 | |
52 113283 113280 34240 1511 2900 0 4 1 2 | |
97 113380 113375 34263 1512 2899 0 4 1 2 | |
65 113445 113441 34285 1513 2898 0 4 1 2 | |
56 113501 113497 34308 1514 2897 0 4 1 2 | |
118 113619 113554 34331 1515 2896 0 4 1 2 | |
76 113695 113691 34353 1516 2895 0 4 1 2 | |
60 113755 113751 34376 1517 2894 0 4 1 2 | |
59 113814 113810 34399 1518 2893 0 4 1 2 | |
55 113869 113865 34421 1519 2892 0 4 1 2 | |
53 113922 113919 34444 1520 2891 0 4 1 2 | |
57 113979 113975 34467 1521 2890 0 4 1 2 | |
53 114032 114028 34489 1522 2889 0 4 1 2 | |
55 114087 114083 34512 1523 2888 0 4 1 2 | |
52 114139 114135 34535 1524 2887 0 4 1 2 | |
56 114195 114191 34557 1525 2886 0 4 1 2 | |
53 114248 114244 34580 1526 2885 0 4 1 2 | |
53 114301 114297 34603 1527 2884 0 4 1 2 | |
98 114399 114395 34625 1528 2883 0 4 1 2 | |
62 114461 114457 34648 1529 2882 0 4 1 2 | |
55 114516 114512 34671 1530 2881 0 4 1 2 | |
119 114635 114629 34693 1531 2880 0 4 1 2 | |
70 114705 114701 34716 1532 2879 0 4 1 2 | |
57 114762 114758 34739 1533 2878 0 4 1 2 | |
58 114820 114815 34761 1534 2877 0 4 1 2 | |
53 114873 114869 34784 1535 2876 0 4 1 2 | |
53 114926 114922 34807 1536 2875 0 4 1 2 | |
55 114981 114977 34829 1537 2874 0 4 1 2 | |
53 115034 115031 34852 1538 2873 0 4 1 2 | |
56 115090 115086 34875 1539 2872 0 4 1 2 | |
53 115143 115140 34897 1540 2871 0 4 1 2 | |
55 115198 115194 34920 1541 2870 0 4 1 2 | |
55 115253 115249 34943 1542 2869 0 4 1 2 | |
87 115340 115303 34965 1543 2868 0 4 1 2 | |
65 115405 115401 34988 1544 2867 0 4 1 2 | |
62 115467 115463 35011 1545 2866 0 4 1 2 | |
55 115522 115518 35034 1546 2865 0 4 1 2 | |
118 115640 115635 35056 1547 2864 0 4 1 2 | |
68 115708 115703 35079 1548 2863 0 4 1 2 | |
58 115766 115762 35102 1549 2862 0 4 1 2 | |
55 115821 115818 35124 1550 2861 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
101 115922 115918 35147 1551 2860 0 4 1 2 | |
69 115991 115986 35170 1552 2859 0 4 1 2 | |
56 116047 116043 35192 1553 2858 0 4 1 2 | |
56 116103 116100 35215 1554 2857 0 4 1 2 | |
54 116157 116153 35238 1555 2856 0 4 1 2 | |
57 116214 116210 35260 1556 2855 0 4 1 2 | |
55 116269 116265 35283 1557 2854 0 4 1 2 | |
95 116364 116359 35306 1558 2853 0 4 1 2 | |
62 116426 116422 35328 1559 2852 0 4 1 2 | |
59 116485 116481 35351 1560 2851 0 4 1 2 | |
55 116540 116536 35374 1561 2850 0 4 1 2 | |
130 116670 116665 35396 1562 2849 0 4 1 2 | |
64 116734 116730 35419 1563 2848 0 4 1 2 | |
54 116788 116785 35442 1564 2847 0 4 1 2 | |
56 116844 116841 35464 1565 2846 0 4 1 2 | |
56 116900 116896 35487 1566 2845 0 4 1 2 | |
56 116956 116952 35510 1567 2844 0 4 1 2 | |
53 117009 117005 35532 1568 2843 0 4 1 2 | |
56 117065 117061 35555 1569 2842 0 4 1 2 | |
54 117119 117116 35578 1570 2841 0 4 1 2 | |
53 117172 117168 35600 1571 2840 0 4 1 2 | |
55 117227 117223 35623 1572 2839 0 4 1 2 | |
52 117279 117275 35646 1573 2838 0 4 1 2 | |
94 117373 117368 35668 1574 2837 0 4 1 2 | |
64 117437 117432 35691 1575 2836 0 4 1 2 | |
57 117494 117490 35714 1576 2835 0 4 1 2 | |
55 117549 117545 35736 1577 2834 0 4 1 2 | |
127 117676 117671 35759 1578 2833 0 4 1 2 | |
64 117740 117735 35782 1579 2832 0 4 1 2 | |
54 117794 117790 35804 1580 2831 0 4 1 2 | |
58 117852 117848 35827 1581 2830 0 4 1 2 | |
52 117904 117901 35850 1582 2829 0 4 1 2 | |
56 117960 117956 35873 1583 2828 0 4 1 2 | |
53 118013 118010 35895 1584 2827 0 4 1 2 | |
55 118068 118064 35918 1585 2826 0 4 1 2 | |
53 118121 118118 35941 1586 2825 0 4 1 2 | |
53 118174 118170 35963 1587 2824 0 4 1 2 | |
54 118228 118224 35986 1588 2823 0 4 1 2 | |
53 118281 118278 36009 1589 2822 0 4 1 2 | |
96 118377 118372 36031 1590 2821 0 4 1 2 | |
65 118442 118438 36054 1591 2820 0 4 1 2 | |
57 118499 118495 36077 1592 2819 0 4 1 2 | |
55 118554 118549 36099 1593 2818 0 4 1 2 | |
131 118685 118680 36122 1594 2817 0 4 1 2 | |
60 118745 118741 36145 1595 2816 0 4 1 2 | |
55 118800 118796 36167 1596 2815 0 4 1 2 | |
55 118855 118851 36190 1597 2814 0 4 1 2 | |
53 118908 118905 36213 1598 2813 0 4 1 2 | |
55 118963 118959 36235 1599 2812 0 4 1 2 | |
53 119016 119012 36258 1600 2811 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
55 119071 119066 36281 1601 2810 0 4 1 2 | |
55 119126 119122 36303 1602 2809 0 4 1 2 | |
56 119182 119177 36326 1603 2808 0 4 1 2 | |
55 119237 119233 36349 1604 2807 0 4 1 2 | |
52 119289 119285 36371 1605 2806 0 4 1 2 | |
95 119384 119379 36394 1606 2805 0 4 1 2 | |
63 119447 119443 36417 1607 2804 0 4 1 2 | |
56 119503 119500 36439 1608 2803 0 4 1 2 | |
116 119619 119556 36462 1609 2802 0 4 1 2 | |
74 119693 119689 36485 1610 2801 0 4 1 2 | |
57 119750 119747 36507 1611 2800 0 4 1 2 | |
56 119806 119800 36530 1612 2799 0 4 1 2 | |
55 119861 119857 36553 1613 2798 0 4 1 2 | |
53 119914 119911 36575 1614 2797 0 4 1 2 | |
56 119970 119966 36598 1615 2796 0 4 1 2 | |
54 120024 120020 36621 1616 2795 0 4 1 2 | |
56 120080 120076 36643 1617 2794 0 4 1 2 | |
52 120132 120128 36666 1618 2793 0 4 1 2 | |
54 120186 120183 36689 1619 2792 0 4 1 2 | |
54 120240 120236 36712 1620 2791 0 4 1 2 | |
52 120292 120288 36734 1621 2790 0 4 1 2 | |
101 120393 120388 36757 1622 2789 0 4 1 2 | |
97 120490 120485 36780 1623 2788 0 4 1 2 | |
61 120551 120547 36802 1624 2787 0 4 1 2 | |
132 120683 120676 36825 1625 2786 0 4 1 2 | |
59 120742 120738 36848 1626 2785 0 4 1 2 | |
118 120860 120855 36870 1627 2784 0 4 1 2 | |
64 120924 120920 36893 1628 2783 0 4 1 2 | |
58 120982 120978 36916 1629 2782 0 4 1 2 | |
54 121036 121032 36938 1630 2781 0 4 1 2 | |
56 121092 121088 36961 1631 2780 0 4 1 2 | |
54 121146 121142 36984 1632 2779 0 4 1 2 | |
55 121201 121197 37006 1633 2778 0 4 1 2 | |
54 121255 121251 37029 1634 2777 0 4 1 2 | |
91 121346 121339 37052 1635 2776 0 4 1 2 | |
64 121410 121406 37074 1636 2775 0 4 1 2 | |
62 121472 121468 37097 1637 2774 0 4 1 2 | |
55 121527 121523 37120 1638 2773 0 4 1 2 | |
126 121653 121648 37142 1639 2772 0 4 1 2 | |
68 121721 121716 37165 1640 2771 0 4 1 2 | |
56 121777 121774 37188 1641 2770 0 4 1 2 | |
57 121834 121831 37210 1642 2769 0 4 1 2 | |
56 121890 121886 37233 1643 2768 0 4 1 2 | |
54 121944 121940 37256 1644 2767 0 4 1 2 | |
53 121997 121994 37278 1645 2766 0 4 1 2 | |
53 122050 122046 37301 1646 2765 0 4 1 2 | |
99 122149 122145 37324 1647 2764 0 4 1 2 | |
63 122212 122208 37346 1648 2763 0 4 1 2 | |
55 122267 122264 37369 1649 2762 0 4 1 2 | |
94 122361 122357 37392 1650 2761 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
63 122424 122420 37414 1651 2760 0 4 1 2 | |
66 122490 122486 37437 1652 2759 0 4 1 2 | |
56 122546 122542 37460 1653 2758 0 4 1 2 | |
137 122683 122676 37482 1654 2757 0 4 1 2 | |
63 122746 122742 37505 1655 2756 0 4 1 2 | |
55 122801 122797 37528 1656 2755 0 4 1 2 | |
57 122858 122854 37551 1657 2754 0 4 1 2 | |
53 122911 122907 37573 1658 2753 0 4 1 2 | |
56 122967 122964 37596 1659 2752 0 4 1 2 | |
54 123021 123017 37619 1660 2751 0 4 1 2 | |
54 123075 123072 37641 1661 2750 0 4 1 2 | |
54 123129 123125 37664 1662 2749 0 4 1 2 | |
54 123183 123177 37687 1663 2748 0 4 1 2 | |
54 123237 123233 37709 1664 2747 0 4 1 2 | |
53 123290 123286 37732 1665 2746 0 4 1 2 | |
98 123388 123383 37755 1666 2745 0 4 1 2 | |
63 123451 123447 37777 1667 2744 0 4 1 2 | |
59 123510 123506 37800 1668 2743 0 4 1 2 | |
123 123633 123627 37823 1669 2742 0 4 1 2 | |
71 123704 123700 37845 1670 2741 0 4 1 2 | |
57 123761 123757 37868 1671 2740 0 4 1 2 | |
59 123820 123816 37891 1672 2739 0 4 1 2 | |
56 123876 123872 37913 1673 2738 0 4 1 2 | |
54 123930 123925 37936 1674 2737 0 4 1 2 | |
54 123984 123981 37959 1675 2736 0 4 1 2 | |
53 124037 124033 37981 1676 2735 0 4 1 2 | |
56 124093 124089 38004 1677 2734 0 4 1 2 | |
52 124145 124142 38027 1678 2733 0 4 1 2 | |
55 124200 124195 38049 1679 2732 0 4 1 2 | |
52 124252 124249 38072 1680 2731 0 4 1 2 | |
84 124336 124301 38095 1681 2730 0 4 1 2 | |
67 124403 124398 38117 1682 2729 0 4 1 2 | |
62 124465 124460 38140 1683 2728 0 4 1 2 | |
55 124520 124516 38163 1684 2727 0 4 1 2 | |
123 124643 124638 38185 1685 2726 0 4 1 2 | |
71 124714 124709 38208 1686 2725 0 4 1 2 | |
56 124770 124767 38231 1687 2724 0 4 1 2 | |
57 124827 124823 38253 1688 2723 0 4 1 2 | |
54 124881 124877 38276 1689 2722 0 4 1 2 | |
56 124937 124933 38299 1690 2721 0 4 1 2 | |
54 124991 124987 38321 1691 2720 0 4 1 2 | |
52 125043 125039 38344 1692 2719 0 4 1 2 | |
56 125099 125095 38367 1693 2718 0 4 1 2 | |
53 125152 125148 38390 1694 2717 0 4 1 2 | |
57 125209 125205 38412 1695 2716 0 4 1 2 | |
54 125263 125259 38435 1696 2715 0 4 1 2 | |
89 125352 125348 38458 1697 2714 0 4 1 2 | |
64 125416 125412 38480 1698 2713 0 4 1 2 | |
59 125475 125471 38503 1699 2712 0 4 1 2 | |
54 125529 125525 38526 1700 2711 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
123 125652 125647 38548 1701 2710 0 4 1 2 | |
70 125722 125717 38571 1702 2709 0 4 1 2 | |
56 125778 125774 38594 1703 2708 0 4 1 2 | |
58 125836 125832 38616 1704 2707 0 4 1 2 | |
55 125891 125887 38639 1705 2706 0 4 1 2 | |
56 125947 125943 38662 1706 2705 0 4 1 2 | |
52 125999 125995 38684 1707 2704 0 4 1 2 | |
53 126052 126049 38707 1708 2703 0 4 1 2 | |
55 126107 126103 38730 1709 2702 0 4 1 2 | |
53 126160 126156 38752 1710 2701 0 4 1 2 | |
55 126215 126211 38775 1711 2700 0 4 1 2 | |
53 126268 126264 38798 1712 2699 0 4 1 2 | |
89 126357 126353 38820 1713 2698 0 4 1 2 | |
63 126420 126416 38843 1714 2697 0 4 1 2 | |
59 126479 126475 38866 1715 2696 0 4 1 2 | |
56 126535 126531 38888 1716 2695 0 4 1 2 | |
128 126663 126658 38911 1717 2694 0 4 1 2 | |
67 126730 126725 38934 1718 2693 0 4 1 2 | |
57 126787 126783 38956 1719 2692 0 4 1 2 | |
57 126844 126841 38979 1720 2691 0 4 1 2 | |
53 126897 126893 39002 1721 2690 0 4 1 2 | |
55 126952 126949 39024 1722 2689 0 4 1 2 | |
54 127006 127002 39047 1723 2688 0 4 1 2 | |
55 127061 127057 39070 1724 2687 0 4 1 2 | |
52 127113 127109 39092 1725 2686 0 4 1 2 | |
53 127166 127162 39115 1726 2685 0 4 1 2 | |
54 127220 127217 39138 1727 2684 0 4 1 2 | |
54 127274 127270 39160 1728 2683 0 4 1 2 | |
93 127367 127363 39183 1729 2682 0 4 1 2 | |
65 127432 127424 39206 1730 2681 0 4 1 2 | |
57 127489 127485 39229 1731 2680 0 4 1 2 | |
54 127543 127539 39251 1732 2679 0 4 1 2 | |
128 127671 127666 39274 1733 2678 0 4 1 2 | |
64 127735 127732 39297 1734 2677 0 4 1 2 | |
56 127791 127787 39319 1735 2676 0 4 1 2 | |
56 127847 127843 39342 1736 2675 0 4 1 2 | |
54 127901 127897 39365 1737 2674 0 4 1 2 | |
55 127956 127952 39387 1738 2673 0 4 1 2 | |
53 128009 128005 39410 1739 2672 0 4 1 2 | |
55 128064 128060 39433 1740 2671 0 4 1 2 | |
53 128117 128114 39455 1741 2670 0 4 1 2 | |
53 128170 128166 39478 1742 2669 0 4 1 2 | |
55 128225 128222 39501 1743 2668 0 4 1 2 | |
478197 606422 606414 39523 1744 2667 0 4 1 2 | |
61 606483 606480 39546 1745 2666 0 4 1 2 | |
41 606524 606522 39569 1746 2665 0 4 1 2 | |
36 606560 606557 39591 1747 2664 0 4 1 2 | |
34 606594 606592 39614 1748 2663 0 4 1 2 | |
97 606691 606687 39637 1749 2662 0 4 1 2 | |
43 606734 606731 39659 1750 2661 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
38 606772 606770 39682 1751 2660 0 4 1 2 | |
40 606812 606809 39705 1752 2659 0 4 1 2 | |
34 606846 606844 39727 1753 2658 0 4 1 2 | |
36 606882 606879 39750 1754 2657 0 4 1 2 | |
35 606917 606914 39773 1755 2656 0 4 1 2 | |
33 606950 606947 39795 1756 2655 0 4 1 2 | |
33 606983 606981 39818 1757 2654 0 4 1 2 | |
34 607017 607015 39841 1758 2653 0 4 1 2 | |
34 607051 607048 39863 1759 2652 0 4 1 2 | |
32 607083 607081 39886 1760 2651 0 4 1 2 | |
33 607116 607114 39909 1761 2650 0 4 1 2 | |
35 607151 607149 39931 1762 2649 0 4 1 2 | |
34 607185 607183 39954 1763 2648 0 4 1 2 | |
33 607218 607216 39977 1764 2647 0 4 1 2 | |
35 607253 607251 40000 1765 2646 0 4 1 2 | |
34 607287 607285 40022 1766 2645 0 4 1 2 | |
34 607321 607319 40045 1767 2644 0 4 1 2 | |
33 607354 607352 40068 1768 2643 0 4 1 2 | |
61 607415 607412 40090 1769 2642 0 4 1 2 | |
38 607453 607451 40113 1770 2641 0 4 1 2 | |
34 607487 607485 40136 1771 2640 0 4 1 2 | |
37 607524 607522 40158 1772 2639 0 4 1 2 | |
35 607559 607556 40181 1773 2638 0 4 1 2 | |
33 607592 607589 40204 1774 2637 0 4 1 2 | |
74 607666 607661 40226 1775 2636 0 4 1 2 | |
43 607709 607707 40249 1776 2635 0 4 1 2 | |
38 607747 607743 40272 1777 2634 0 4 1 2 | |
34 607781 607779 40294 1778 2633 0 4 1 2 | |
34 607815 607812 40317 1779 2632 0 4 1 2 | |
33 607848 607846 40340 1780 2631 0 4 1 2 | |
36 607884 607881 40362 1781 2630 0 4 1 2 | |
33 607917 607915 40385 1782 2629 0 4 1 2 | |
34 607951 607948 40408 1783 2628 0 4 1 2 | |
33 607984 607981 40430 1784 2627 0 4 1 2 | |
34 608018 608016 40453 1785 2626 0 4 1 2 | |
35 608053 608050 40476 1786 2625 0 4 1 2 | |
33 608086 608084 40498 1787 2624 0 4 1 2 | |
34 608120 608116 40521 1788 2623 0 4 1 2 | |
34 608154 608151 40544 1789 2622 0 4 1 2 | |
33 608187 608184 40566 1790 2621 0 4 1 2 | |
34 608221 608219 40589 1791 2620 0 4 1 2 | |
34 608255 608253 40612 1792 2619 0 4 1 2 | |
34 608289 608287 40634 1793 2618 0 4 1 2 | |
34 608323 608321 40657 1794 2617 0 4 1 2 | |
34 608357 608354 40680 1795 2616 0 4 1 2 | |
65 608422 608418 40702 1796 2615 0 4 1 2 | |
38 608460 608457 40725 1797 2614 0 4 1 2 | |
55 608515 608492 40748 1798 2613 0 4 1 2 | |
41 608556 608554 40770 1799 2612 0 4 1 2 | |
35 608591 608589 40793 1800 2611 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
76 608667 608664 40816 1801 2610 0 4 1 2 | |
44 608711 608708 40839 1802 2609 0 4 1 2 | |
38 608749 608746 40861 1803 2608 0 4 1 2 | |
34 608783 608781 40884 1804 2607 0 4 1 2 | |
34 608817 608815 40907 1805 2606 0 4 1 2 | |
33 608850 608848 40929 1806 2605 0 4 1 2 | |
36 608886 608884 40952 1807 2604 0 4 1 2 | |
33 608919 608917 40975 1808 2603 0 4 1 2 | |
34 608953 608950 40997 1809 2602 0 4 1 2 | |
32 608985 608983 41020 1810 2601 0 4 1 2 | |
35 609020 609017 41043 1811 2600 0 4 1 2 | |
34 609054 609051 41065 1812 2599 0 4 1 2 | |
32 609086 609084 41088 1813 2598 0 4 1 2 | |
34 609120 609117 41111 1814 2597 0 4 1 2 | |
35 609155 609152 41133 1815 2596 0 4 1 2 | |
33 609188 609186 41156 1816 2595 0 4 1 2 | |
33 609221 609219 41179 1817 2594 0 4 1 2 | |
34 609255 609252 41201 1818 2593 0 4 1 2 | |
33 609288 609286 41224 1819 2592 0 4 1 2 | |
34 609322 609319 41247 1820 2591 0 4 1 2 | |
33 609355 609352 41269 1821 2590 0 4 1 2 | |
59 609414 609411 41292 1822 2589 0 4 1 2 | |
38 609452 609449 41315 1823 2588 0 4 1 2 | |
35 609487 609484 41337 1824 2587 0 4 1 2 | |
37 609524 609521 41360 1825 2586 0 4 1 2 | |
34 609558 609555 41383 1826 2585 0 4 1 2 | |
33 609591 609589 41405 1827 2584 0 4 1 2 | |
73 609664 609660 41428 1828 2583 0 4 1 2 | |
42 609706 609704 41451 1829 2582 0 4 1 2 | |
36 609742 609740 41473 1830 2581 0 4 1 2 | |
36 609778 609776 41496 1831 2580 0 4 1 2 | |
35 609813 609810 41519 1832 2579 0 4 1 2 | |
33 609846 609844 41541 1833 2578 0 4 1 2 | |
35 609881 609879 41564 1834 2577 0 4 1 2 | |
34 609915 609913 41587 1835 2576 0 4 1 2 | |
33 609948 609946 41609 1836 2575 0 4 1 2 | |
33 609981 609979 41632 1837 2574 0 4 1 2 | |
35 610016 610014 41655 1838 2573 0 4 1 2 | |
34 610050 610048 41678 1839 2572 0 4 1 2 | |
34 610084 610082 41700 1840 2571 0 4 1 2 | |
64 610148 610145 41723 1841 2570 0 4 1 2 | |
38 610186 610183 41746 1842 2569 0 4 1 2 | |
35 610221 610218 41768 1843 2568 0 4 1 2 | |
34 610255 610253 41791 1844 2567 0 4 1 2 | |
34 610289 610286 41814 1845 2566 0 4 1 2 | |
34 610323 610321 41836 1846 2565 0 4 1 2 | |
35 610358 610355 41859 1847 2564 0 4 1 2 | |
61 610419 610416 41882 1848 2563 0 4 1 2 | |
38 610457 610454 41904 1849 2562 0 4 1 2 | |
36 610493 610490 41927 1850 2561 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
36 610529 610527 41950 1851 2560 0 4 1 2 | |
38 610567 610565 41972 1852 2559 0 4 1 2 | |
34 610601 610599 41995 1853 2558 0 4 1 2 | |
79 610680 610676 42018 1854 2557 0 4 1 2 | |
41 610721 610718 42040 1855 2556 0 4 1 2 | |
37 610758 610755 42063 1856 2555 0 4 1 2 | |
105 610863 610860 42086 1857 2554 0 4 1 2 | |
42 610905 610903 42108 1858 2553 0 4 1 2 | |
35 610940 610937 42131 1859 2552 0 4 1 2 | |
34 610974 610972 42154 1860 2551 0 4 1 2 | |
34 611008 611006 42176 1861 2550 0 4 1 2 | |
34 611042 611040 42199 1862 2549 0 4 1 2 | |
34 611076 611073 42222 1863 2548 0 4 1 2 | |
33 611109 611107 42244 1864 2547 0 4 1 2 | |
35 611144 611141 42267 1865 2546 0 4 1 2 | |
33 611177 611175 42290 1866 2545 0 4 1 2 | |
34 611211 611209 42312 1867 2544 0 4 1 2 | |
34 611245 611242 42335 1868 2543 0 4 1 2 | |
34 611279 611277 42358 1869 2542 0 4 1 2 | |
34 611313 611310 42380 1870 2541 0 4 1 2 | |
34 611347 611344 42403 1871 2540 0 4 1 2 | |
60 611407 611405 42426 1872 2539 0 4 1 2 | |
40 611447 611444 42448 1873 2538 0 4 1 2 | |
35 611482 611479 42471 1874 2537 0 4 1 2 | |
36 611518 611516 42494 1875 2536 0 4 1 2 | |
35 611553 611550 42517 1876 2535 0 4 1 2 | |
34 611587 611584 42539 1877 2534 0 4 1 2 | |
34 611621 611617 42562 1878 2533 0 4 1 2 | |
84 611705 611702 42585 1879 2532 0 4 1 2 | |
37 611742 611740 42607 1880 2531 0 4 1 2 | |
37 611779 611776 42630 1881 2530 0 4 1 2 | |
33 611812 611810 42653 1882 2529 0 4 1 2 | |
34 611846 611843 42675 1883 2528 0 4 1 2 | |
35 611881 611878 42698 1884 2527 0 4 1 2 | |
33 611914 611912 42721 1885 2526 0 4 1 2 | |
34 611948 611945 42743 1886 2525 0 4 1 2 | |
33 611981 611979 42766 1887 2524 0 4 1 2 | |
35 612016 612014 42789 1888 2523 0 4 1 2 | |
35 612051 612048 42811 1889 2522 0 4 1 2 | |
34 612085 612083 42834 1890 2521 0 4 1 2 | |
33 612118 612116 42857 1891 2520 0 4 1 2 | |
35 612153 612150 42879 1892 2519 0 4 1 2 | |
33 612186 612184 42902 1893 2518 0 4 1 2 | |
33 612219 612217 42925 1894 2517 0 4 1 2 | |
35 612254 612252 42947 1895 2516 0 4 1 2 | |
33 612287 612285 42970 1896 2515 0 4 1 2 | |
34 612321 612319 42993 1897 2514 0 4 1 2 | |
34 612355 612353 43015 1898 2513 0 4 1 2 | |
60 612415 612412 43038 1899 2512 0 4 1 2 | |
38 612453 612451 43061 1900 2511 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 612487 612485 43083 1901 2510 0 4 1 2 | |
40 612527 612524 43106 1902 2509 0 4 1 2 | |
34 612561 612559 43129 1903 2508 0 4 1 2 | |
33 612594 612592 43151 1904 2507 0 4 1 2 | |
75 612669 612666 43174 1905 2506 0 4 1 2 | |
42 612711 612709 43197 1906 2505 0 4 1 2 | |
38 612749 612746 43219 1907 2504 0 4 1 2 | |
34 612783 612781 43242 1908 2503 0 4 1 2 | |
33 612816 612814 43265 1909 2502 0 4 1 2 | |
33 612849 612847 43287 1910 2501 0 4 1 2 | |
35 612884 612882 43310 1911 2500 0 4 1 2 | |
34 612918 612916 43333 1912 2499 0 4 1 2 | |
34 612952 612950 43356 1913 2498 0 4 1 2 | |
34 612986 612983 43378 1914 2497 0 4 1 2 | |
35 613021 613018 43401 1915 2496 0 4 1 2 | |
33 613054 613051 43424 1916 2495 0 4 1 2 | |
34 613088 613085 43446 1917 2494 0 4 1 2 | |
34 613122 613118 43469 1918 2493 0 4 1 2 | |
33 613155 613153 43492 1919 2492 0 4 1 2 | |
33 613188 613186 43514 1920 2491 0 4 1 2 | |
34 613222 613219 43537 1921 2490 0 4 1 2 | |
33 613255 613253 43560 1922 2489 0 4 1 2 | |
33 613288 613286 43582 1923 2488 0 4 1 2 | |
34 613322 613320 43605 1924 2487 0 4 1 2 | |
33 613355 613353 43628 1925 2486 0 4 1 2 | |
59 613414 613411 43650 1926 2485 0 4 1 2 | |
37 613451 613449 43673 1927 2484 0 4 1 2 | |
34 613485 613483 43696 1928 2483 0 4 1 2 | |
37 613522 613519 43718 1929 2482 0 4 1 2 | |
33 613555 613553 43741 1930 2481 0 4 1 2 | |
33 613588 613586 43764 1931 2480 0 4 1 2 | |
36 613624 613621 43786 1932 2479 0 4 1 2 | |
82 613706 613704 43809 1933 2478 0 4 1 2 | |
36 613742 613739 43832 1934 2477 0 4 1 2 | |
36 613778 613776 43854 1935 2476 0 4 1 2 | |
33 613811 613809 43877 1936 2475 0 4 1 2 | |
33 613844 613842 43900 1937 2474 0 4 1 2 | |
68 613912 613909 43922 1938 2473 0 4 1 2 | |
37 613949 613946 43945 1939 2472 0 4 1 2 | |
35 613984 613981 43968 1940 2471 0 4 1 2 | |
36 614020 614017 43990 1941 2470 0 4 1 2 | |
33 614053 614051 44013 1942 2469 0 4 1 2 | |
34 614087 614085 44036 1943 2468 0 4 1 2 | |
34 614121 614118 44058 1944 2467 0 4 1 2 | |
35 614156 614154 44081 1945 2466 0 4 1 2 | |
34 614190 614187 44104 1946 2465 0 4 1 2 | |
32 614222 614220 44126 1947 2464 0 4 1 2 | |
35 614257 614255 44149 1948 2463 0 4 1 2 | |
34 614291 614289 44172 1949 2462 0 4 1 2 | |
32 614323 614321 44195 1950 2461 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 614356 614354 44217 1951 2460 0 4 1 2 | |
65 614421 614418 44240 1952 2459 0 4 1 2 | |
38 614459 614456 44263 1953 2458 0 4 1 2 | |
35 614494 614491 44285 1954 2457 0 4 1 2 | |
37 614531 614528 44308 1955 2456 0 4 1 2 | |
33 614564 614561 44331 1956 2455 0 4 1 2 | |
34 614598 614595 44353 1957 2454 0 4 1 2 | |
78 614676 614673 44376 1958 2453 0 4 1 2 | |
43 614719 614716 44399 1959 2452 0 4 1 2 | |
37 614756 614753 44421 1960 2451 0 4 1 2 | |
33 614789 614787 44444 1961 2450 0 4 1 2 | |
33 614822 614820 44467 1962 2449 0 4 1 2 | |
33 614855 614853 44489 1963 2448 0 4 1 2 | |
35 614890 614888 44512 1964 2447 0 4 1 2 | |
35 614925 614922 44535 1965 2446 0 4 1 2 | |
33 614958 614956 44557 1966 2445 0 4 1 2 | |
33 614991 614989 44580 1967 2444 0 4 1 2 | |
35 615026 615023 44603 1968 2443 0 4 1 2 | |
33 615059 615056 44625 1969 2442 0 4 1 2 | |
33 615092 615089 44648 1970 2441 0 4 1 2 | |
34 615126 615124 44671 1971 2440 0 4 1 2 | |
33 615159 615157 44693 1972 2439 0 4 1 2 | |
33 615192 615190 44716 1973 2438 0 4 1 2 | |
34 615226 615224 44739 1974 2437 0 4 1 2 | |
35 615261 615258 44761 1975 2436 0 4 1 2 | |
33 615294 615292 44784 1976 2435 0 4 1 2 | |
33 615327 615325 44807 1977 2434 0 4 1 2 | |
33 615360 615358 44829 1978 2433 0 4 1 2 | |
59 615419 615416 44852 1979 2432 0 4 1 2 | |
37 615456 615453 44875 1980 2431 0 4 1 2 | |
34 615490 615488 44897 1981 2430 0 4 1 2 | |
36 615526 615523 44920 1982 2429 0 4 1 2 | |
34 615560 615558 44943 1983 2428 0 4 1 2 | |
33 615593 615591 44965 1984 2427 0 4 1 2 | |
75 615668 615663 44988 1985 2426 0 4 1 2 | |
43 615711 615708 45011 1986 2425 0 4 1 2 | |
36 615747 615743 45034 1987 2424 0 4 1 2 | |
35 615782 615780 45056 1988 2423 0 4 1 2 | |
34 615816 615813 45079 1989 2422 0 4 1 2 | |
33 615849 615847 45102 1990 2421 0 4 1 2 | |
35 615884 615881 45124 1991 2420 0 4 1 2 | |
33 615917 615915 45147 1992 2419 0 4 1 2 | |
33 615950 615948 45170 1993 2418 0 4 1 2 | |
34 615984 615982 45192 1994 2417 0 4 1 2 | |
34 616018 616016 45215 1995 2416 0 4 1 2 | |
33 616051 616049 45238 1996 2415 0 4 1 2 | |
34 616085 616082 45260 1997 2414 0 4 1 2 | |
33 616118 616116 45283 1998 2413 0 4 1 2 | |
34 616152 616150 45306 1999 2412 0 4 1 2 | |
34 616186 616183 45328 2000 2411 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 616219 616216 45351 2001 2410 0 4 1 2 | |
37 616256 616253 45374 2002 2409 0 4 1 2 | |
33 616289 616287 45396 2003 2408 0 4 1 2 | |
34 616323 616321 45419 2004 2407 0 4 1 2 | |
34 616357 616355 45442 2005 2406 0 4 1 2 | |
64 616421 616419 45464 2006 2405 0 4 1 2 | |
38 616459 616456 45487 2007 2404 0 4 1 2 | |
34 616493 616491 45510 2008 2403 0 4 1 2 | |
59 616552 616549 45532 2009 2402 0 4 1 2 | |
36 616588 616586 45555 2010 2401 0 4 1 2 | |
36 616624 616622 45578 2011 2400 0 4 1 2 | |
76 616700 616697 45600 2012 2399 0 4 1 2 | |
36 616736 616733 45623 2013 2398 0 4 1 2 | |
35 616771 616769 45646 2014 2397 0 4 1 2 | |
35 616806 616804 45668 2015 2396 0 4 1 2 | |
34 616840 616838 45691 2016 2395 0 4 1 2 | |
35 616875 616872 45714 2017 2394 0 4 1 2 | |
34 616909 616906 45736 2018 2393 0 4 1 2 | |
33 616942 616939 45759 2019 2392 0 4 1 2 | |
33 616975 616973 45782 2020 2391 0 4 1 2 | |
35 617010 617008 45804 2021 2390 0 4 1 2 | |
34 617044 617042 45827 2022 2389 0 4 1 2 | |
34 617078 617076 45850 2023 2388 0 4 1 2 | |
32 617110 617108 45873 2024 2387 0 4 1 2 | |
35 617145 617143 45895 2025 2386 0 4 1 2 | |
34 617179 617177 45918 2026 2385 0 4 1 2 | |
33 617212 617210 45941 2027 2384 0 4 1 2 | |
34 617246 617243 45963 2028 2383 0 4 1 2 | |
35 617281 617278 45986 2029 2382 0 4 1 2 | |
33 617314 617311 46009 2030 2381 0 4 1 2 | |
33 617347 617345 46031 2031 2380 0 4 1 2 | |
59 617406 617404 46054 2032 2379 0 4 1 2 | |
40 617446 617443 46077 2033 2378 0 4 1 2 | |
80 617526 617523 46099 2034 2377 0 4 1 2 | |
42 617568 617565 46122 2035 2376 0 4 1 2 | |
36 617604 617601 46145 2036 2375 0 4 1 2 | |
82 617686 617682 46167 2037 2374 0 4 1 2 | |
41 617727 617724 46190 2038 2373 0 4 1 2 | |
37 617764 617761 46213 2039 2372 0 4 1 2 | |
33 617797 617795 46235 2040 2371 0 4 1 2 | |
34 617831 617829 46258 2041 2370 0 4 1 2 | |
34 617865 617862 46281 2042 2369 0 4 1 2 | |
35 617900 617898 46303 2043 2368 0 4 1 2 | |
34 617934 617931 46326 2044 2367 0 4 1 2 | |
33 617967 617965 46349 2045 2366 0 4 1 2 | |
36 618003 618000 46371 2046 2365 0 4 1 2 | |
33 618036 618034 46394 2047 2364 0 4 1 2 | |
34 618070 618067 46417 2048 2363 0 4 1 2 | |
32 618102 618100 46439 2049 2362 0 4 1 2 | |
36 618138 618135 46462 2050 2361 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 618171 618169 46485 2051 2360 0 4 1 2 | |
37 618208 618206 46507 2052 2359 0 4 1 2 | |
34 618242 618239 46530 2053 2358 0 4 1 2 | |
33 618275 618273 46553 2054 2357 0 4 1 2 | |
33 618308 618306 46575 2055 2356 0 4 1 2 | |
33 618341 618339 46598 2056 2355 0 4 1 2 | |
57 618398 618394 46621 2057 2354 0 4 1 2 | |
40 618438 618435 46643 2058 2353 0 4 1 2 | |
34 618472 618470 46666 2059 2352 0 4 1 2 | |
36 618508 618506 46689 2060 2351 0 4 1 2 | |
34 618542 618540 46712 2061 2350 0 4 1 2 | |
34 618576 618574 46734 2062 2349 0 4 1 2 | |
33 618609 618606 46757 2063 2348 0 4 1 2 | |
78 618687 618684 46780 2064 2347 0 4 1 2 | |
40 618727 618724 46802 2065 2346 0 4 1 2 | |
37 618764 618761 46825 2066 2345 0 4 1 2 | |
34 618798 618796 46848 2067 2344 0 4 1 2 | |
34 618832 618829 46870 2068 2343 0 4 1 2 | |
33 618865 618863 46893 2069 2342 0 4 1 2 | |
35 618900 618898 46916 2070 2341 0 4 1 2 | |
34 618934 618932 46938 2071 2340 0 4 1 2 | |
34 618968 618965 46961 2072 2339 0 4 1 2 | |
35 619003 619000 46984 2073 2338 0 4 1 2 | |
34 619037 619034 47006 2074 2337 0 4 1 2 | |
33 619070 619068 47029 2075 2336 0 4 1 2 | |
34 619104 619101 47052 2076 2335 0 4 1 2 | |
34 619138 619136 47074 2077 2334 0 4 1 2 | |
33 619171 619169 47097 2078 2333 0 4 1 2 | |
33 619204 619202 47120 2079 2332 0 4 1 2 | |
34 619238 619235 47142 2080 2331 0 4 1 2 | |
34 619272 619270 47165 2081 2330 0 4 1 2 | |
33 619305 619303 47188 2082 2329 0 4 1 2 | |
33 619338 619336 47210 2083 2328 0 4 1 2 | |
52 619390 619368 47233 2084 2327 0 4 1 2 | |
41 619431 619428 47256 2085 2326 0 4 1 2 | |
36 619467 619464 47278 2086 2325 0 4 1 2 | |
37 619504 619502 47301 2087 2324 0 4 1 2 | |
34 619538 619536 47324 2088 2323 0 4 1 2 | |
33 619571 619569 47346 2089 2322 0 4 1 2 | |
34 619605 619603 47369 2090 2321 0 4 1 2 | |
76 619681 619678 47392 2091 2320 0 4 1 2 | |
39 619720 619717 47414 2092 2319 0 4 1 2 | |
37 619757 619755 47437 2093 2318 0 4 1 2 | |
35 619792 619789 47460 2094 2317 0 4 1 2 | |
34 619826 619824 47482 2095 2316 0 4 1 2 | |
33 619859 619857 47505 2096 2315 0 4 1 2 | |
35 619894 619891 47528 2097 2314 0 4 1 2 | |
34 619928 619925 47551 2098 2313 0 4 1 2 | |
32 619960 619958 47573 2099 2312 0 4 1 2 | |
34 619994 619991 47596 2100 2311 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 620028 620026 47619 2101 2310 0 4 1 2 | |
36 620064 620062 47641 2102 2309 0 4 1 2 | |
33 620097 620095 47664 2103 2308 0 4 1 2 | |
36 620133 620131 47687 2104 2307 0 4 1 2 | |
35 620168 620165 47709 2105 2306 0 4 1 2 | |
32 620200 620198 47732 2106 2305 0 4 1 2 | |
33 620233 620231 47755 2107 2304 0 4 1 2 | |
35 620268 620266 47777 2108 2303 0 4 1 2 | |
33 620301 620299 47800 2109 2302 0 4 1 2 | |
34 620335 620332 47823 2110 2301 0 4 1 2 | |
33 620368 620365 47845 2111 2300 0 4 1 2 | |
60 620428 620425 47868 2112 2299 0 4 1 2 | |
37 620465 620462 47891 2113 2298 0 4 1 2 | |
37 620502 620499 47913 2114 2297 0 4 1 2 | |
34 620536 620534 47936 2115 2296 0 4 1 2 | |
33 620569 620567 47959 2116 2295 0 4 1 2 | |
33 620602 620600 47981 2117 2294 0 4 1 2 | |
73 620675 620672 48004 2118 2293 0 4 1 2 | |
41 620716 620713 48027 2119 2292 0 4 1 2 | |
37 620753 620750 48049 2120 2291 0 4 1 2 | |
76 620829 620826 48072 2121 2290 0 4 1 2 | |
41 620870 620867 48095 2122 2289 0 4 1 2 | |
37 620907 620905 48117 2123 2288 0 4 1 2 | |
34 620941 620939 48140 2124 2287 0 4 1 2 | |
34 620975 620972 48163 2125 2286 0 4 1 2 | |
35 621010 621008 48185 2126 2285 0 4 1 2 | |
34 621044 621042 48208 2127 2284 0 4 1 2 | |
33 621077 621075 48231 2128 2283 0 4 1 2 | |
34 621111 621108 48253 2129 2282 0 4 1 2 | |
35 621146 621143 48276 2130 2281 0 4 1 2 | |
62 621208 621205 48299 2131 2280 0 4 1 2 | |
39 621247 621243 48321 2132 2279 0 4 1 2 | |
35 621282 621280 48344 2133 2278 0 4 1 2 | |
34 621316 621313 48367 2134 2277 0 4 1 2 | |
34 621350 621347 48390 2135 2276 0 4 1 2 | |
61 621411 621408 48412 2136 2275 0 4 1 2 | |
38 621449 621447 48435 2137 2274 0 4 1 2 | |
35 621484 621481 48458 2138 2273 0 4 1 2 | |
37 621521 621518 48480 2139 2272 0 4 1 2 | |
34 621555 621553 48503 2140 2271 0 4 1 2 | |
33 621588 621586 48526 2141 2270 0 4 1 2 | |
35 621623 621619 48548 2142 2269 0 4 1 2 | |
87 621710 621707 48571 2143 2268 0 4 1 2 | |
38 621748 621744 48594 2144 2267 0 4 1 2 | |
35 621783 621780 48616 2145 2266 0 4 1 2 | |
33 621816 621814 48639 2146 2265 0 4 1 2 | |
33 621849 621847 48662 2147 2264 0 4 1 2 | |
35 621884 621881 48684 2148 2263 0 4 1 2 | |
34 621918 621915 48707 2149 2262 0 4 1 2 | |
33 621951 621949 48730 2150 2261 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 621984 621982 48752 2151 2260 0 4 1 2 | |
38 622022 622019 48775 2152 2259 0 4 1 2 | |
34 622056 622053 48798 2153 2258 0 4 1 2 | |
33 622089 622087 48820 2154 2257 0 4 1 2 | |
35 622124 622120 48843 2155 2256 0 4 1 2 | |
34 622158 622155 48866 2156 2255 0 4 1 2 | |
34 622192 622189 48888 2157 2254 0 4 1 2 | |
33 622225 622223 48911 2158 2253 0 4 1 2 | |
34 622259 622257 48934 2159 2252 0 4 1 2 | |
33 622292 622290 48956 2160 2251 0 4 1 2 | |
34 622326 622324 48979 2161 2250 0 4 1 2 | |
33 622359 622356 49002 2162 2249 0 4 1 2 | |
59 622418 622415 49024 2163 2248 0 4 1 2 | |
37 622455 622453 49047 2164 2247 0 4 1 2 | |
34 622489 622487 49070 2165 2246 0 4 1 2 | |
36 622525 622523 49092 2166 2245 0 4 1 2 | |
34 622559 622557 49115 2167 2244 0 4 1 2 | |
34 622593 622591 49138 2168 2243 0 4 1 2 | |
70 622663 622627 49160 2169 2242 0 4 1 2 | |
44 622707 622705 49183 2170 2241 0 4 1 2 | |
36 622743 622740 49206 2171 2240 0 4 1 2 | |
35 622778 622776 49229 2172 2239 0 4 1 2 | |
34 622812 622810 49251 2173 2238 0 4 1 2 | |
33 622845 622843 49274 2174 2237 0 4 1 2 | |
35 622880 622878 49297 2175 2236 0 4 1 2 | |
34 622914 622912 49319 2176 2235 0 4 1 2 | |
33 622947 622945 49342 2177 2234 0 4 1 2 | |
32 622979 622977 49365 2178 2233 0 4 1 2 | |
36 623015 623012 49387 2179 2232 0 4 1 2 | |
33 623048 623046 49410 2180 2231 0 4 1 2 | |
33 623081 623079 49433 2181 2230 0 4 1 2 | |
33 623114 623112 49455 2182 2229 0 4 1 2 | |
35 623149 623147 49478 2183 2228 0 4 1 2 | |
33 623182 623179 49501 2184 2227 0 4 1 2 | |
34 623216 623213 49523 2185 2226 0 4 1 2 | |
34 623250 623247 49546 2186 2225 0 4 1 2 | |
34 623284 623282 49569 2187 2224 0 4 1 2 | |
34 623318 623315 49591 2188 2223 0 4 1 2 | |
33 623351 623348 49614 2189 2222 0 4 1 2 | |
55 623406 623403 49637 2190 2221 0 4 1 2 | |
39 623445 623442 49659 2191 2220 0 4 1 2 | |
35 623480 623477 49682 2192 2219 0 4 1 2 | |
37 623517 623514 49705 2193 2218 0 4 1 2 | |
34 623551 623549 49727 2194 2217 0 4 1 2 | |
34 623585 623582 49750 2195 2216 0 4 1 2 | |
33 623618 623615 49773 2196 2215 0 4 1 2 | |
79 623697 623694 49795 2197 2214 0 4 1 2 | |
39 623736 623733 49818 2198 2213 0 4 1 2 | |
36 623772 623770 49841 2199 2212 0 4 1 2 | |
35 623807 623805 49863 2200 2211 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 623841 623838 49886 2201 2210 0 4 1 2 | |
37 623878 623876 49909 2202 2209 0 4 1 2 | |
35 623913 623910 49931 2203 2208 0 4 1 2 | |
34 623947 623944 49954 2204 2207 0 4 1 2 | |
33 623980 623978 49977 2205 2206 0 4 1 2 | |
36 624016 624013 50000 2206 2205 0 4 1 2 | |
34 624050 624048 50022 2207 2204 0 4 1 2 | |
34 624084 624081 50045 2208 2203 0 4 1 2 | |
32 624116 624114 50068 2209 2202 0 4 1 2 | |
35 624151 624149 50090 2210 2201 0 4 1 2 | |
34 624185 624183 50113 2211 2200 0 4 1 2 | |
34 624219 624217 50136 2212 2199 0 4 1 2 | |
33 624252 624250 50158 2213 2198 0 4 1 2 | |
34 624286 624283 50181 2214 2197 0 4 1 2 | |
34 624320 624317 50204 2215 2196 0 4 1 2 | |
33 624353 624351 50226 2216 2195 0 4 1 2 | |
63 624416 624413 50249 2217 2194 0 4 1 2 | |
38 624454 624451 50272 2218 2193 0 4 1 2 | |
34 624488 624486 50294 2219 2192 0 4 1 2 | |
58 624546 624543 50317 2220 2191 0 4 1 2 | |
37 624583 624580 50340 2221 2190 0 4 1 2 | |
34 624617 624615 50362 2222 2189 0 4 1 2 | |
78 624695 624692 50385 2223 2188 0 4 1 2 | |
38 624733 624731 50408 2224 2187 0 4 1 2 | |
38 624771 624768 50430 2225 2186 0 4 1 2 | |
35 624806 624803 50453 2226 2185 0 4 1 2 | |
34 624840 624837 50476 2227 2184 0 4 1 2 | |
59 624899 624896 50498 2228 2183 0 4 1 2 | |
38 624937 624935 50521 2229 2182 0 4 1 2 | |
34 624971 624969 50544 2230 2181 0 4 1 2 | |
36 625007 625004 50566 2231 2180 0 4 1 2 | |
33 625040 625038 50589 2232 2179 0 4 1 2 | |
34 625074 625071 50612 2233 2178 0 4 1 2 | |
33 625107 625105 50634 2234 2177 0 4 1 2 | |
35 625142 625140 50657 2235 2176 0 4 1 2 | |
34 625176 625173 50680 2236 2175 0 4 1 2 | |
33 625209 625207 50702 2237 2174 0 4 1 2 | |
34 625243 625240 50725 2238 2173 0 4 1 2 | |
35 625278 625276 50748 2239 2172 0 4 1 2 | |
33 625311 625308 50770 2240 2171 0 4 1 2 | |
33 625344 625341 50793 2241 2170 0 4 1 2 | |
57 625401 625398 50816 2242 2169 0 4 1 2 | |
39 625440 625438 50839 2243 2168 0 4 1 2 | |
36 625476 625473 50861 2244 2167 0 4 1 2 | |
36 625512 625510 50884 2245 2166 0 4 1 2 | |
34 625546 625544 50907 2246 2165 0 4 1 2 | |
34 625580 625578 50929 2247 2164 0 4 1 2 | |
33 625613 625611 50952 2248 2163 0 4 1 2 | |
81 625694 625690 50975 2249 2162 0 4 1 2 | |
39 625733 625731 50997 2250 2161 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
37 625770 625768 51020 2251 2160 0 4 1 2 | |
38 625808 625805 51043 2252 2159 0 4 1 2 | |
34 625842 625839 51065 2253 2158 0 4 1 2 | |
35 625877 625874 51088 2254 2157 0 4 1 2 | |
34 625911 625908 51111 2255 2156 0 4 1 2 | |
33 625944 625942 51133 2256 2155 0 4 1 2 | |
33 625977 625974 51156 2257 2154 0 4 1 2 | |
34 626011 626009 51179 2258 2153 0 4 1 2 | |
33 626044 626042 51201 2259 2152 0 4 1 2 | |
33 626077 626075 51224 2260 2151 0 4 1 2 | |
33 626110 626108 51247 2261 2150 0 4 1 2 | |
35 626145 626142 51269 2262 2149 0 4 1 2 | |
34 626179 626176 51292 2263 2148 0 4 1 2 | |
32 626211 626209 51315 2264 2147 0 4 1 2 | |
34 626245 626242 51337 2265 2146 0 4 1 2 | |
34 626279 626277 51360 2266 2145 0 4 1 2 | |
33 626312 626310 51383 2267 2144 0 4 1 2 | |
33 626345 626343 51405 2268 2143 0 4 1 2 | |
57 626402 626400 51428 2269 2142 0 4 1 2 | |
40 626442 626440 51451 2270 2141 0 4 1 2 | |
35 626477 626475 51473 2271 2140 0 4 1 2 | |
37 626514 626512 51496 2272 2139 0 4 1 2 | |
34 626548 626546 51519 2273 2138 0 4 1 2 | |
33 626581 626579 51541 2274 2137 0 4 1 2 | |
34 626615 626612 51564 2275 2136 0 4 1 2 | |
77 626692 626689 51587 2276 2135 0 4 1 2 | |
39 626731 626729 51609 2277 2134 0 4 1 2 | |
37 626768 626766 51632 2278 2133 0 4 1 2 | |
34 626802 626799 51655 2279 2132 0 4 1 2 | |
35 626837 626834 51678 2280 2131 0 4 1 2 | |
34 626871 626868 51700 2281 2130 0 4 1 2 | |
34 626905 626903 51723 2282 2129 0 4 1 2 | |
33 626938 626936 51746 2283 2128 0 4 1 2 | |
33 626971 626969 51768 2284 2127 0 4 1 2 | |
35 627006 627003 51791 2285 2126 0 4 1 2 | |
34 627040 627037 51814 2286 2125 0 4 1 2 | |
33 627073 627070 51836 2287 2124 0 4 1 2 | |
33 627106 627104 51859 2288 2123 0 4 1 2 | |
35 627141 627138 51882 2289 2122 0 4 1 2 | |
33 627174 627172 51904 2290 2121 0 4 1 2 | |
34 627208 627206 51927 2291 2120 0 4 1 2 | |
33 627241 627239 51950 2292 2119 0 4 1 2 | |
35 627276 627274 51972 2293 2118 0 4 1 2 | |
34 627310 627307 51995 2294 2117 0 4 1 2 | |
33 627343 627341 52018 2295 2116 0 4 1 2 | |
56 627399 627396 52040 2296 2115 0 4 1 2 | |
38 627437 627435 52063 2297 2114 0 4 1 2 | |
36 627473 627470 52086 2298 2113 0 4 1 2 | |
36 627509 627506 52108 2299 2112 0 4 1 2 | |
35 627544 627541 52131 2300 2111 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 627577 627574 52154 2301 2110 0 4 1 2 | |
35 627612 627610 52176 2302 2109 0 4 1 2 | |
96 627708 627704 52199 2303 2108 0 4 1 2 | |
43 627751 627746 52222 2304 2107 0 4 1 2 | |
35 627786 627784 52244 2305 2106 0 4 1 2 | |
34 627820 627818 52267 2306 2105 0 4 1 2 | |
33 627853 627851 52290 2307 2104 0 4 1 2 | |
34 627887 627885 52312 2308 2103 0 4 1 2 | |
34 627921 627918 52335 2309 2102 0 4 1 2 | |
32 627953 627951 52358 2310 2101 0 4 1 2 | |
34 627987 627985 52380 2311 2100 0 4 1 2 | |
34 628021 628019 52403 2312 2099 0 4 1 2 | |
33 628054 628052 52426 2313 2098 0 4 1 2 | |
33 628087 628085 52448 2314 2097 0 4 1 2 | |
34 628121 628118 52471 2315 2096 0 4 1 2 | |
34 628155 628153 52494 2316 2095 0 4 1 2 | |
34 628189 628187 52517 2317 2094 0 4 1 2 | |
33 628222 628220 52539 2318 2093 0 4 1 2 | |
35 628257 628254 52562 2319 2092 0 4 1 2 | |
33 628290 628288 52585 2320 2091 0 4 1 2 | |
34 628324 628322 52607 2321 2090 0 4 1 2 | |
33 628357 628354 52630 2322 2089 0 4 1 2 | |
59 628416 628413 52653 2323 2088 0 4 1 2 | |
37 628453 628451 52675 2324 2087 0 4 1 2 | |
62 628515 628512 52698 2325 2086 0 4 1 2 | |
39 628554 628551 52721 2326 2085 0 4 1 2 | |
34 628588 628586 52743 2327 2084 0 4 1 2 | |
35 628623 628619 52766 2328 2083 0 4 1 2 | |
86 628709 628706 52789 2329 2082 0 4 1 2 | |
39 628748 628744 52811 2330 2081 0 4 1 2 | |
35 628783 628781 52834 2331 2080 0 4 1 2 | |
34 628817 628815 52857 2332 2079 0 4 1 2 | |
34 628851 628849 52879 2333 2078 0 4 1 2 | |
36 628887 628884 52902 2334 2077 0 4 1 2 | |
32 628919 628917 52925 2335 2076 0 4 1 2 | |
35 628954 628952 52947 2336 2075 0 4 1 2 | |
32 628986 628984 52970 2337 2074 0 4 1 2 | |
35 629021 629018 52993 2338 2073 0 4 1 2 | |
33 629054 629052 53015 2339 2072 0 4 1 2 | |
33 629087 629085 53038 2340 2071 0 4 1 2 | |
34 629121 629118 53061 2341 2070 0 4 1 2 | |
35 629156 629154 53083 2342 2069 0 4 1 2 | |
34 629190 629188 53106 2343 2068 0 4 1 2 | |
33 629223 629221 53129 2344 2067 0 4 1 2 | |
34 629257 629255 53151 2345 2066 0 4 1 2 | |
33 629290 629288 53174 2346 2065 0 4 1 2 | |
33 629323 629321 53197 2347 2064 0 4 1 2 | |
33 629356 629354 53219 2348 2063 0 4 1 2 | |
60 629416 629413 53242 2349 2062 0 4 1 2 | |
37 629453 629451 53265 2350 2061 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 629487 629484 53287 2351 2060 0 4 1 2 | |
38 629525 629523 53310 2352 2059 0 4 1 2 | |
34 629559 629557 53333 2353 2058 0 4 1 2 | |
34 629593 629591 53356 2354 2057 0 4 1 2 | |
70 629663 629625 53378 2355 2056 0 4 1 2 | |
44 629707 629704 53401 2356 2055 0 4 1 2 | |
36 629743 629740 53424 2357 2054 0 4 1 2 | |
36 629779 629776 53446 2358 2053 0 4 1 2 | |
34 629813 629811 53469 2359 2052 0 4 1 2 | |
33 629846 629844 53492 2360 2051 0 4 1 2 | |
35 629881 629878 53514 2361 2050 0 4 1 2 | |
34 629915 629912 53537 2362 2049 0 4 1 2 | |
33 629948 629946 53560 2363 2048 0 4 1 2 | |
34 629982 629979 53582 2364 2047 0 4 1 2 | |
35 630017 630015 53605 2365 2046 0 4 1 2 | |
33 630050 630048 53628 2366 2045 0 4 1 2 | |
34 630084 630081 53650 2367 2044 0 4 1 2 | |
33 630117 630115 53673 2368 2043 0 4 1 2 | |
35 630152 630149 53696 2369 2042 0 4 1 2 | |
33 630185 630183 53718 2370 2041 0 4 1 2 | |
34 630219 630217 53741 2371 2040 0 4 1 2 | |
35 630254 630251 53764 2372 2039 0 4 1 2 | |
34 630288 630286 53786 2373 2038 0 4 1 2 | |
33 630321 630319 53809 2374 2037 0 4 1 2 | |
33 630354 630352 53832 2375 2036 0 4 1 2 | |
59 630413 630410 53854 2376 2035 0 4 1 2 | |
37 630450 630448 53877 2377 2034 0 4 1 2 | |
35 630485 630483 53900 2378 2033 0 4 1 2 | |
37 630522 630519 53922 2379 2032 0 4 1 2 | |
33 630555 630553 53945 2380 2031 0 4 1 2 | |
34 630589 630587 53968 2381 2030 0 4 1 2 | |
35 630624 630620 53990 2382 2029 0 4 1 2 | |
79 630703 630699 54013 2383 2028 0 4 1 2 | |
38 630741 630738 54036 2384 2027 0 4 1 2 | |
74 630815 630812 54058 2385 2026 0 4 1 2 | |
43 630858 630855 54081 2386 2025 0 4 1 2 | |
39 630897 630894 54104 2387 2024 0 4 1 2 | |
34 630931 630929 54126 2388 2023 0 4 1 2 | |
34 630965 630962 54149 2389 2022 0 4 1 2 | |
36 631001 630998 54172 2390 2021 0 4 1 2 | |
33 631034 631032 54195 2391 2020 0 4 1 2 | |
34 631068 631066 54217 2392 2019 0 4 1 2 | |
33 631101 631099 54240 2393 2018 0 4 1 2 | |
34 631135 631133 54263 2394 2017 0 4 1 2 | |
34 631169 631167 54285 2395 2016 0 4 1 2 | |
33 631202 631200 54308 2396 2015 0 4 1 2 | |
33 631235 631233 54331 2397 2014 0 4 1 2 | |
35 631270 631267 54353 2398 2013 0 4 1 2 | |
34 631304 631301 54376 2399 2012 0 4 1 2 | |
33 631337 631335 54399 2400 2011 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 631370 631367 54421 2401 2010 0 4 1 2 | |
65 631435 631432 54444 2402 2009 0 4 1 2 | |
36 631471 631468 54467 2403 2008 0 4 1 2 | |
37 631508 631506 54489 2404 2007 0 4 1 2 | |
34 631542 631540 54512 2405 2006 0 4 1 2 | |
34 631576 631574 54535 2406 2005 0 4 1 2 | |
32 631608 631606 54557 2407 2004 0 4 1 2 | |
82 631690 631687 54580 2408 2003 0 4 1 2 | |
41 631731 631728 54603 2409 2002 0 4 1 2 | |
37 631768 631765 54625 2410 2001 0 4 1 2 | |
34 631802 631800 54648 2411 2000 0 4 1 2 | |
34 631836 631834 54671 2412 1999 0 4 1 2 | |
33 631869 631867 54693 2413 1998 0 4 1 2 | |
35 631904 631902 54716 2414 1997 0 4 1 2 | |
33 631937 631935 54739 2415 1996 0 4 1 2 | |
33 631970 631968 54761 2416 1995 0 4 1 2 | |
35 632005 632002 54784 2417 1994 0 4 1 2 | |
33 632038 632036 54807 2418 1993 0 4 1 2 | |
34 632072 632069 54829 2419 1992 0 4 1 2 | |
32 632104 632102 54852 2420 1991 0 4 1 2 | |
36 632140 632138 54875 2421 1990 0 4 1 2 | |
63 632203 632200 54897 2422 1989 0 4 1 2 | |
37 632240 632237 54920 2423 1988 0 4 1 2 | |
38 632278 632275 54943 2424 1987 0 4 1 2 | |
34 632312 632309 54965 2425 1986 0 4 1 2 | |
33 632345 632343 54988 2426 1985 0 4 1 2 | |
64 632409 632406 55011 2427 1984 0 4 1 2 | |
40 632449 632446 55034 2428 1983 0 4 1 2 | |
36 632485 632483 55056 2429 1982 0 4 1 2 | |
57 632542 632539 55079 2430 1981 0 4 1 2 | |
38 632580 632577 55102 2431 1980 0 4 1 2 | |
35 632615 632612 55124 2432 1979 0 4 1 2 | |
80 632695 632692 55147 2433 1978 0 4 1 2 | |
40 632735 632732 55170 2434 1977 0 4 1 2 | |
36 632771 632769 55192 2435 1976 0 4 1 2 | |
34 632805 632803 55215 2436 1975 0 4 1 2 | |
34 632839 632837 55238 2437 1974 0 4 1 2 | |
34 632873 632870 55260 2438 1973 0 4 1 2 | |
33 632906 632904 55283 2439 1972 0 4 1 2 | |
34 632940 632938 55306 2440 1971 0 4 1 2 | |
33 632973 632971 55328 2441 1970 0 4 1 2 | |
35 633008 633005 55351 2442 1969 0 4 1 2 | |
33 633041 633039 55374 2443 1968 0 4 1 2 | |
33 633074 633072 55396 2444 1967 0 4 1 2 | |
33 633107 633105 55419 2445 1966 0 4 1 2 | |
36 633143 633140 55442 2446 1965 0 4 1 2 | |
33 633176 633173 55464 2447 1964 0 4 1 2 | |
34 633210 633207 55487 2448 1963 0 4 1 2 | |
33 633243 633241 55510 2449 1962 0 4 1 2 | |
35 633278 633276 55532 2450 1961 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 633312 633310 55555 2451 1960 0 4 1 2 | |
37 633349 633346 55578 2452 1959 0 4 1 2 | |
57 633406 633403 55600 2453 1958 0 4 1 2 | |
39 633445 633443 55623 2454 1957 0 4 1 2 | |
34 633479 633477 55646 2455 1956 0 4 1 2 | |
37 633516 633514 55668 2456 1955 0 4 1 2 | |
34 633550 633548 55691 2457 1954 0 4 1 2 | |
34 633584 633582 55714 2458 1953 0 4 1 2 | |
34 633618 633616 55736 2459 1952 0 4 1 2 | |
76 633694 633691 55759 2460 1951 0 4 1 2 | |
39 633733 633730 55782 2461 1950 0 4 1 2 | |
36 633769 633767 55804 2462 1949 0 4 1 2 | |
34 633803 633801 55827 2463 1948 0 4 1 2 | |
35 633838 633835 55850 2464 1947 0 4 1 2 | |
33 633871 633868 55873 2465 1946 0 4 1 2 | |
35 633906 633904 55895 2466 1945 0 4 1 2 | |
34 633940 633937 55918 2467 1944 0 4 1 2 | |
33 633973 633970 55941 2468 1943 0 4 1 2 | |
33 634006 634004 55963 2469 1942 0 4 1 2 | |
33 634039 634037 55986 2470 1941 0 4 1 2 | |
33 634072 634070 56009 2471 1940 0 4 1 2 | |
33 634105 634103 56031 2472 1939 0 4 1 2 | |
35 634140 634137 56054 2473 1938 0 4 1 2 | |
33 634173 634171 56077 2474 1937 0 4 1 2 | |
33 634206 634204 56099 2475 1936 0 4 1 2 | |
34 634240 634237 56122 2476 1935 0 4 1 2 | |
34 634274 634272 56145 2477 1934 0 4 1 2 | |
34 634308 634305 56167 2478 1933 0 4 1 2 | |
33 634341 634338 56190 2479 1932 0 4 1 2 | |
54 634395 634373 56213 2480 1931 0 4 1 2 | |
40 634435 634432 56235 2481 1930 0 4 1 2 | |
37 634472 634469 56258 2482 1929 0 4 1 2 | |
37 634509 634506 56281 2483 1928 0 4 1 2 | |
34 634543 634541 56303 2484 1927 0 4 1 2 | |
34 634577 634575 56326 2485 1926 0 4 1 2 | |
33 634610 634608 56349 2486 1925 0 4 1 2 | |
79 634689 634686 56371 2487 1924 0 4 1 2 | |
40 634729 634726 56394 2488 1923 0 4 1 2 | |
36 634765 634763 56417 2489 1922 0 4 1 2 | |
34 634799 634797 56439 2490 1921 0 4 1 2 | |
34 634833 634830 56462 2491 1920 0 4 1 2 | |
33 634866 634864 56485 2492 1919 0 4 1 2 | |
34 634900 634898 56507 2493 1918 0 4 1 2 | |
34 634934 634931 56530 2494 1917 0 4 1 2 | |
32 634966 634964 56553 2495 1916 0 4 1 2 | |
35 635001 634997 56575 2496 1915 0 4 1 2 | |
33 635034 635032 56598 2497 1914 0 4 1 2 | |
33 635067 635065 56621 2498 1913 0 4 1 2 | |
33 635100 635098 56643 2499 1912 0 4 1 2 | |
36 635136 635133 56666 2500 1911 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 635169 635167 56689 2501 1910 0 4 1 2 | |
35 635204 635202 56712 2502 1909 0 4 1 2 | |
35 635239 635236 56734 2503 1908 0 4 1 2 | |
34 635273 635271 56757 2504 1907 0 4 1 2 | |
34 635307 635305 56780 2505 1906 0 4 1 2 | |
33 635340 635338 56802 2506 1905 0 4 1 2 | |
53 635393 635371 56825 2507 1904 0 4 1 2 | |
42 635435 635433 56848 2508 1903 0 4 1 2 | |
37 635472 635469 56870 2509 1902 0 4 1 2 | |
36 635508 635506 56893 2510 1901 0 4 1 2 | |
35 635543 635540 56916 2511 1900 0 4 1 2 | |
34 635577 635575 56938 2512 1899 0 4 1 2 | |
33 635610 635608 56961 2513 1898 0 4 1 2 | |
77 635687 635684 56984 2514 1897 0 4 1 2 | |
40 635727 635724 57006 2515 1896 0 4 1 2 | |
36 635763 635761 57029 2516 1895 0 4 1 2 | |
34 635797 635795 57052 2517 1894 0 4 1 2 | |
33 635830 635828 57074 2518 1893 0 4 1 2 | |
59 635889 635886 57097 2519 1892 0 4 1 2 | |
36 635925 635923 57120 2520 1891 0 4 1 2 | |
35 635960 635958 57142 2521 1890 0 4 1 2 | |
34 635994 635992 57165 2522 1889 0 4 1 2 | |
35 636029 636027 57188 2523 1888 0 4 1 2 | |
33 636062 636060 57210 2524 1887 0 4 1 2 | |
34 636096 636093 57233 2525 1886 0 4 1 2 | |
34 636130 636128 57256 2526 1885 0 4 1 2 | |
33 636163 636161 57278 2527 1884 0 4 1 2 | |
34 636197 636194 57301 2528 1883 0 4 1 2 | |
33 636230 636228 57324 2529 1882 0 4 1 2 | |
34 636264 636262 57346 2530 1881 0 4 1 2 | |
33 636297 636295 57369 2531 1880 0 4 1 2 | |
33 636330 636328 57392 2532 1879 0 4 1 2 | |
34 636364 636361 57414 2533 1878 0 4 1 2 | |
61 636425 636422 57437 2534 1877 0 4 1 2 | |
37 636462 636460 57460 2535 1876 0 4 1 2 | |
35 636497 636494 57482 2536 1875 0 4 1 2 | |
36 636533 636531 57505 2537 1874 0 4 1 2 | |
33 636566 636564 57528 2538 1873 0 4 1 2 | |
33 636599 636597 57551 2539 1872 0 4 1 2 | |
78 636677 636674 57573 2540 1871 0 4 1 2 | |
43 636720 636717 57596 2541 1870 0 4 1 2 | |
38 636758 636755 57619 2542 1869 0 4 1 2 | |
35 636793 636791 57641 2543 1868 0 4 1 2 | |
34 636827 636825 57664 2544 1867 0 4 1 2 | |
33 636860 636857 57687 2545 1866 0 4 1 2 | |
35 636895 636893 57709 2546 1865 0 4 1 2 | |
33 636928 636925 57732 2547 1864 0 4 1 2 | |
33 636961 636959 57755 2548 1863 0 4 1 2 | |
33 636994 636992 57777 2549 1862 0 4 1 2 | |
35 637029 637026 57800 2550 1861 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
32 637061 637059 57823 2551 1860 0 4 1 2 | |
36 637097 637094 57845 2552 1859 0 4 1 2 | |
36 637133 637130 57868 2553 1858 0 4 1 2 | |
34 637167 637164 57891 2554 1857 0 4 1 2 | |
33 637200 637197 57913 2555 1856 0 4 1 2 | |
33 637233 637230 57936 2556 1855 0 4 1 2 | |
34 637267 637265 57959 2557 1854 0 4 1 2 | |
34 637301 637299 57981 2558 1853 0 4 1 2 | |
33 637334 637332 58004 2559 1852 0 4 1 2 | |
34 637368 637366 58027 2560 1851 0 4 1 2 | |
61 637429 637426 58049 2561 1850 0 4 1 2 | |
37 637466 637464 58072 2562 1849 0 4 1 2 | |
37 637503 637500 58095 2563 1848 0 4 1 2 | |
35 637538 637535 58117 2564 1847 0 4 1 2 | |
33 637571 637569 58140 2565 1846 0 4 1 2 | |
33 637604 637602 58163 2566 1845 0 4 1 2 | |
73 637677 637674 58185 2567 1844 0 4 1 2 | |
40 637717 637715 58208 2568 1843 0 4 1 2 | |
37 637754 637752 58231 2569 1842 0 4 1 2 | |
35 637789 637787 58253 2570 1841 0 4 1 2 | |
34 637823 637821 58276 2571 1840 0 4 1 2 | |
33 637856 637854 58299 2572 1839 0 4 1 2 | |
36 637892 637889 58321 2573 1838 0 4 1 2 | |
33 637925 637923 58344 2574 1837 0 4 1 2 | |
34 637959 637957 58367 2575 1836 0 4 1 2 | |
33 637992 637990 58390 2576 1835 0 4 1 2 | |
35 638027 638024 58412 2577 1834 0 4 1 2 | |
33 638060 638058 58435 2578 1833 0 4 1 2 | |
34 638094 638091 58458 2579 1832 0 4 1 2 | |
34 638128 638126 58480 2580 1831 0 4 1 2 | |
34 638162 638159 58503 2581 1830 0 4 1 2 | |
34 638196 638194 58526 2582 1829 0 4 1 2 | |
33 638229 638226 58548 2583 1828 0 4 1 2 | |
35 638264 638261 58571 2584 1827 0 4 1 2 | |
33 638297 638294 58594 2585 1826 0 4 1 2 | |
33 638330 638328 58616 2586 1825 0 4 1 2 | |
32 638362 638360 58639 2587 1824 0 4 1 2 | |
58 638420 638417 58662 2588 1823 0 4 1 2 | |
38 638458 638455 58684 2589 1822 0 4 1 2 | |
35 638493 638490 58707 2590 1821 0 4 1 2 | |
36 638529 638527 58730 2591 1820 0 4 1 2 | |
34 638563 638560 58752 2592 1819 0 4 1 2 | |
33 638596 638594 58775 2593 1818 0 4 1 2 | |
73 638669 638664 58798 2594 1817 0 4 1 2 | |
43 638712 638709 58820 2595 1816 0 4 1 2 | |
37 638749 638745 58843 2596 1815 0 4 1 2 | |
35 638784 638781 58866 2597 1814 0 4 1 2 | |
33 638817 638815 58888 2598 1813 0 4 1 2 | |
34 638851 638848 58911 2599 1812 0 4 1 2 | |
33 638884 638882 58934 2600 1811 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 638918 638915 58956 2601 1810 0 4 1 2 | |
35 638953 638950 58979 2602 1809 0 4 1 2 | |
35 638988 638985 59002 2603 1808 0 4 1 2 | |
34 639022 639020 59024 2604 1807 0 4 1 2 | |
34 639056 639053 59047 2605 1806 0 4 1 2 | |
33 639089 639087 59070 2606 1805 0 4 1 2 | |
35 639124 639120 59092 2607 1804 0 4 1 2 | |
33 639157 639155 59115 2608 1803 0 4 1 2 | |
34 639191 639189 59138 2609 1802 0 4 1 2 | |
33 639224 639221 59160 2610 1801 0 4 1 2 | |
35 639259 639256 59183 2611 1800 0 4 1 2 | |
34 639293 639290 59206 2612 1799 0 4 1 2 | |
33 639326 639324 59229 2613 1798 0 4 1 2 | |
34 639360 639357 59251 2614 1797 0 4 1 2 | |
81 639441 639437 59274 2615 1796 0 4 1 2 | |
39 639480 639477 59297 2616 1795 0 4 1 2 | |
39 639519 639516 59319 2617 1794 0 4 1 2 | |
35 639554 639551 59342 2618 1793 0 4 1 2 | |
34 639588 639586 59365 2619 1792 0 4 1 2 | |
34 639622 639620 59387 2620 1791 0 4 1 2 | |
84 639706 639702 59410 2621 1790 0 4 1 2 | |
36 639742 639740 59433 2622 1789 0 4 1 2 | |
37 639779 639777 59455 2623 1788 0 4 1 2 | |
34 639813 639811 59478 2624 1787 0 4 1 2 | |
33 639846 639844 59501 2625 1786 0 4 1 2 | |
35 639881 639878 59523 2626 1785 0 4 1 2 | |
33 639914 639912 59546 2627 1784 0 4 1 2 | |
33 639947 639945 59569 2628 1783 0 4 1 2 | |
34 639981 639978 59591 2629 1782 0 4 1 2 | |
35 640016 640014 59614 2630 1781 0 4 1 2 | |
34 640050 640047 59637 2631 1780 0 4 1 2 | |
33 640083 640080 59659 2632 1779 0 4 1 2 | |
33 640116 640113 59682 2633 1778 0 4 1 2 | |
35 640151 640148 59705 2634 1777 0 4 1 2 | |
34 640185 640182 59727 2635 1776 0 4 1 2 | |
32 640217 640215 59750 2636 1775 0 4 1 2 | |
34 640251 640249 59773 2637 1774 0 4 1 2 | |
34 640285 640282 59795 2638 1773 0 4 1 2 | |
33 640318 640315 59818 2639 1772 0 4 1 2 | |
33 640351 640349 59841 2640 1771 0 4 1 2 | |
59 640410 640408 59863 2641 1770 0 4 1 2 | |
40 640450 640447 59886 2642 1769 0 4 1 2 | |
36 640486 640483 59909 2643 1768 0 4 1 2 | |
56 640542 640540 59931 2644 1767 0 4 1 2 | |
38 640580 640577 59954 2645 1766 0 4 1 2 | |
35 640615 640612 59977 2646 1765 0 4 1 2 | |
76 640691 640688 60000 2647 1764 0 4 1 2 | |
39 640730 640728 60022 2648 1763 0 4 1 2 | |
38 640768 640766 60045 2649 1762 0 4 1 2 | |
77 640845 640841 60068 2650 1761 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 640884 640881 60090 2651 1760 0 4 1 2 | |
38 640922 640920 60113 2652 1759 0 4 1 2 | |
34 640956 640954 60136 2653 1758 0 4 1 2 | |
34 640990 640987 60158 2654 1757 0 4 1 2 | |
34 641024 641022 60181 2655 1756 0 4 1 2 | |
34 641058 641056 60204 2656 1755 0 4 1 2 | |
33 641091 641089 60226 2657 1754 0 4 1 2 | |
34 641125 641122 60249 2658 1753 0 4 1 2 | |
33 641158 641155 60272 2659 1752 0 4 1 2 | |
33 641191 641188 60294 2660 1751 0 4 1 2 | |
32 641223 641220 60317 2661 1750 0 4 1 2 | |
33 641256 641254 60340 2662 1749 0 4 1 2 | |
34 641290 641288 60362 2663 1748 0 4 1 2 | |
33 641323 641321 60385 2664 1747 0 4 1 2 | |
34 641357 641355 60408 2665 1746 0 4 1 2 | |
60 641417 641414 60430 2666 1745 0 4 1 2 | |
37 641454 641452 60453 2667 1744 0 4 1 2 | |
36 641490 641487 60476 2668 1743 0 4 1 2 | |
36 641526 641524 60498 2669 1742 0 4 1 2 | |
34 641560 641558 60521 2670 1741 0 4 1 2 | |
34 641594 641592 60544 2671 1740 0 4 1 2 | |
71 641665 641627 60566 2672 1739 0 4 1 2 | |
46 641711 641708 60589 2673 1738 0 4 1 2 | |
35 641746 641744 60612 2674 1737 0 4 1 2 | |
37 641783 641780 60634 2675 1736 0 4 1 2 | |
33 641816 641814 60657 2676 1735 0 4 1 2 | |
34 641850 641847 60680 2677 1734 0 4 1 2 | |
35 641885 641883 60702 2678 1733 0 4 1 2 | |
33 641918 641916 60725 2679 1732 0 4 1 2 | |
33 641951 641949 60748 2680 1731 0 4 1 2 | |
33 641984 641982 60770 2681 1730 0 4 1 2 | |
35 642019 642017 60793 2682 1729 0 4 1 2 | |
34 642053 642051 60816 2683 1728 0 4 1 2 | |
34 642087 642084 60839 2684 1727 0 4 1 2 | |
34 642121 642118 60861 2685 1726 0 4 1 2 | |
35 642156 642153 60884 2686 1725 0 4 1 2 | |
33 642189 642186 60907 2687 1724 0 4 1 2 | |
33 642222 642220 60929 2688 1723 0 4 1 2 | |
35 642257 642254 60952 2689 1722 0 4 1 2 | |
33 642290 642288 60975 2690 1721 0 4 1 2 | |
33 642323 642321 60997 2691 1720 0 4 1 2 | |
33 642356 642353 61020 2692 1719 0 4 1 2 | |
59 642415 642412 61043 2693 1718 0 4 1 2 | |
38 642453 642451 61065 2694 1717 0 4 1 2 | |
36 642489 642486 61088 2695 1716 0 4 1 2 | |
35 642524 642522 61111 2696 1715 0 4 1 2 | |
35 642559 642557 61133 2697 1714 0 4 1 2 | |
34 642593 642591 61156 2698 1713 0 4 1 2 | |
34 642627 642625 61179 2699 1712 0 4 1 2 | |
82 642709 642705 61201 2700 1711 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
37 642746 642743 61224 2701 1710 0 4 1 2 | |
38 642784 642782 61247 2702 1709 0 4 1 2 | |
35 642819 642817 61269 2703 1708 0 4 1 2 | |
34 642853 642851 61292 2704 1707 0 4 1 2 | |
35 642888 642886 61315 2705 1706 0 4 1 2 | |
34 642922 642920 61337 2706 1705 0 4 1 2 | |
33 642955 642953 61360 2707 1704 0 4 1 2 | |
33 642988 642986 61383 2708 1703 0 4 1 2 | |
35 643023 643020 61405 2709 1702 0 4 1 2 | |
33 643056 643054 61428 2710 1701 0 4 1 2 | |
34 643090 643087 61451 2711 1700 0 4 1 2 | |
61 643151 643149 61473 2712 1699 0 4 1 2 | |
39 643190 643187 61496 2713 1698 0 4 1 2 | |
34 643224 643222 61519 2714 1697 0 4 1 2 | |
36 643260 643257 61541 2715 1696 0 4 1 2 | |
33 643293 643291 61564 2716 1695 0 4 1 2 | |
34 643327 643324 61587 2717 1694 0 4 1 2 | |
33 643360 643357 61609 2718 1693 0 4 1 2 | |
62 643422 643419 61632 2719 1692 0 4 1 2 | |
37 643459 643457 61655 2720 1691 0 4 1 2 | |
34 643493 643491 61678 2721 1690 0 4 1 2 | |
36 643529 643527 61700 2722 1689 0 4 1 2 | |
34 643563 643561 61723 2723 1688 0 4 1 2 | |
34 643597 643595 61746 2724 1687 0 4 1 2 | |
77 643674 643669 61768 2725 1686 0 4 1 2 | |
42 643716 643714 61791 2726 1685 0 4 1 2 | |
38 643754 643752 61814 2727 1684 0 4 1 2 | |
35 643789 643787 61836 2728 1683 0 4 1 2 | |
34 643823 643821 61859 2729 1682 0 4 1 2 | |
34 643857 643854 61882 2730 1681 0 4 1 2 | |
35 643892 643889 61904 2731 1680 0 4 1 2 | |
33 643925 643923 61927 2732 1679 0 4 1 2 | |
34 643959 643957 61950 2733 1678 0 4 1 2 | |
33 643992 643989 61972 2734 1677 0 4 1 2 | |
35 644027 644024 61995 2735 1676 0 4 1 2 | |
34 644061 644059 62018 2736 1675 0 4 1 2 | |
33 644094 644092 62040 2737 1674 0 4 1 2 | |
35 644129 644126 62063 2738 1673 0 4 1 2 | |
33 644162 644160 62086 2739 1672 0 4 1 2 | |
33 644195 644193 62108 2740 1671 0 4 1 2 | |
35 644230 644227 62131 2741 1670 0 4 1 2 | |
34 644264 644262 62154 2742 1669 0 4 1 2 | |
34 644298 644296 62176 2743 1668 0 4 1 2 | |
33 644331 644329 62199 2744 1667 0 4 1 2 | |
33 644364 644362 62222 2745 1666 0 4 1 2 | |
58 644422 644419 62244 2746 1665 0 4 1 2 | |
37 644459 644457 62267 2747 1664 0 4 1 2 | |
34 644493 644491 62290 2748 1663 0 4 1 2 | |
37 644530 644527 62312 2749 1662 0 4 1 2 | |
33 644563 644560 62335 2750 1661 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 644596 644594 62358 2751 1660 0 4 1 2 | |
77 644673 644669 62380 2752 1659 0 4 1 2 | |
43 644716 644713 62403 2753 1658 0 4 1 2 | |
37 644753 644751 62426 2754 1657 0 4 1 2 | |
36 644789 644787 62448 2755 1656 0 4 1 2 | |
33 644822 644820 62471 2756 1655 0 4 1 2 | |
34 644856 644854 62494 2757 1654 0 4 1 2 | |
36 644892 644890 62517 2758 1653 0 4 1 2 | |
34 644926 644923 62539 2759 1652 0 4 1 2 | |
33 644959 644957 62562 2760 1651 0 4 1 2 | |
32 644991 644989 62585 2761 1650 0 4 1 2 | |
36 645027 645024 62607 2762 1649 0 4 1 2 | |
34 645061 645058 62630 2763 1648 0 4 1 2 | |
33 645094 645092 62653 2764 1647 0 4 1 2 | |
35 645129 645127 62675 2765 1646 0 4 1 2 | |
34 645163 645160 62698 2766 1645 0 4 1 2 | |
34 645197 645194 62721 2767 1644 0 4 1 2 | |
33 645230 645227 62743 2768 1643 0 4 1 2 | |
35 645265 645263 62766 2769 1642 0 4 1 2 | |
34 645299 645296 62789 2770 1641 0 4 1 2 | |
32 645331 645329 62811 2771 1640 0 4 1 2 | |
34 645365 645362 62834 2772 1639 0 4 1 2 | |
58 645423 645420 62857 2773 1638 0 4 1 2 | |
37 645460 645458 62879 2774 1637 0 4 1 2 | |
35 645495 645492 62902 2775 1636 0 4 1 2 | |
37 645532 645529 62925 2776 1635 0 4 1 2 | |
33 645565 645562 62947 2777 1634 0 4 1 2 | |
33 645598 645596 62970 2778 1633 0 4 1 2 | |
73 645671 645667 62993 2779 1632 0 4 1 2 | |
41 645712 645709 63015 2780 1631 0 4 1 2 | |
36 645748 645745 63038 2781 1630 0 4 1 2 | |
36 645784 645781 63061 2782 1629 0 4 1 2 | |
33 645817 645815 63083 2783 1628 0 4 1 2 | |
34 645851 645848 63106 2784 1627 0 4 1 2 | |
34 645885 645883 63129 2785 1626 0 4 1 2 | |
34 645919 645916 63151 2786 1625 0 4 1 2 | |
33 645952 645950 63174 2787 1624 0 4 1 2 | |
34 645986 645984 63197 2788 1623 0 4 1 2 | |
36 646022 646019 63219 2789 1622 0 4 1 2 | |
33 646055 646053 63242 2790 1621 0 4 1 2 | |
34 646089 646087 63265 2791 1620 0 4 1 2 | |
34 646123 646120 63287 2792 1619 0 4 1 2 | |
35 646158 646156 63310 2793 1618 0 4 1 2 | |
34 646192 646189 63333 2794 1617 0 4 1 2 | |
32 646224 646222 63356 2795 1616 0 4 1 2 | |
35 646259 646256 63378 2796 1615 0 4 1 2 | |
34 646293 646290 63401 2797 1614 0 4 1 2 | |
33 646326 646323 63424 2798 1613 0 4 1 2 | |
32 646358 646356 63446 2799 1612 0 4 1 2 | |
58 646416 646413 63469 2800 1611 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
37 646453 646450 63492 2801 1610 0 4 1 2 | |
37 646490 646487 63514 2802 1609 0 4 1 2 | |
36 646526 646524 63537 2803 1608 0 4 1 2 | |
33 646559 646557 63560 2804 1607 0 4 1 2 | |
34 646593 646590 63582 2805 1606 0 4 1 2 | |
35 646628 646625 63605 2806 1605 0 4 1 2 | |
79 646707 646704 63628 2807 1604 0 4 1 2 | |
37 646744 646741 63650 2808 1603 0 4 1 2 | |
59 646803 646800 63673 2809 1602 0 4 1 2 | |
38 646841 646839 63696 2810 1601 0 4 1 2 | |
37 646878 646875 63718 2811 1600 0 4 1 2 | |
34 646912 646909 63741 2812 1599 0 4 1 2 | |
34 646946 646943 63764 2813 1598 0 4 1 2 | |
33 646979 646976 63786 2814 1597 0 4 1 2 | |
34 647013 647011 63809 2815 1596 0 4 1 2 | |
34 647047 647044 63832 2816 1595 0 4 1 2 | |
32 647079 647077 63854 2817 1594 0 4 1 2 | |
33 647112 647110 63877 2818 1593 0 4 1 2 | |
36 647148 647145 63900 2819 1592 0 4 1 2 | |
33 647181 647178 63922 2820 1591 0 4 1 2 | |
34 647215 647213 63945 2821 1590 0 4 1 2 | |
33 647248 647245 63968 2822 1589 0 4 1 2 | |
35 647283 647280 63990 2823 1588 0 4 1 2 | |
33 647316 647314 64013 2824 1587 0 4 1 2 | |
33 647349 647347 64036 2825 1586 0 4 1 2 | |
58 647407 647404 64058 2826 1585 0 4 1 2 | |
39 647446 647443 64081 2827 1584 0 4 1 2 | |
35 647481 647479 64104 2828 1583 0 4 1 2 | |
37 647518 647515 64126 2829 1582 0 4 1 2 | |
33 647551 647549 64149 2830 1581 0 4 1 2 | |
34 647585 647583 64172 2831 1580 0 4 1 2 | |
34 647619 647616 64195 2832 1579 0 4 1 2 | |
80 647699 647696 64217 2833 1578 0 4 1 2 | |
39 647738 647736 64240 2834 1577 0 4 1 2 | |
38 647776 647773 64263 2835 1576 0 4 1 2 | |
33 647809 647807 64285 2836 1575 0 4 1 2 | |
34 647843 647841 64308 2837 1574 0 4 1 2 | |
36 647879 647876 64331 2838 1573 0 4 1 2 | |
33 647912 647910 64353 2839 1572 0 4 1 2 | |
33 647945 647943 64376 2840 1571 0 4 1 2 | |
33 647978 647976 64399 2841 1570 0 4 1 2 | |
35 648013 648010 64421 2842 1569 0 4 1 2 | |
33 648046 648044 64444 2843 1568 0 4 1 2 | |
33 648079 648077 64467 2844 1567 0 4 1 2 | |
34 648113 648110 64489 2845 1566 0 4 1 2 | |
35 648148 648145 64512 2846 1565 0 4 1 2 | |
33 648181 648179 64535 2847 1564 0 4 1 2 | |
33 648214 648212 64557 2848 1563 0 4 1 2 | |
33 648247 648244 64580 2849 1562 0 4 1 2 | |
35 648282 648280 64603 2850 1561 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 648316 648313 64625 2851 1560 0 4 1 2 | |
36 648352 648350 64648 2852 1559 0 4 1 2 | |
61 648413 648410 64671 2853 1558 0 4 1 2 | |
39 648452 648450 64693 2854 1557 0 4 1 2 | |
35 648487 648485 64716 2855 1556 0 4 1 2 | |
58 648545 648542 64739 2856 1555 0 4 1 2 | |
38 648583 648580 64761 2857 1554 0 4 1 2 | |
35 648618 648615 64784 2858 1553 0 4 1 2 | |
76 648694 648691 64807 2859 1552 0 4 1 2 | |
39 648733 648730 64829 2860 1551 0 4 1 2 | |
36 648769 648767 64852 2861 1550 0 4 1 2 | |
35 648804 648802 64875 2862 1549 0 4 1 2 | |
33 648837 648835 64897 2863 1548 0 4 1 2 | |
34 648871 648868 64920 2864 1547 0 4 1 2 | |
34 648905 648903 64943 2865 1546 0 4 1 2 | |
34 648939 648936 64965 2866 1545 0 4 1 2 | |
33 648972 648970 64988 2867 1544 0 4 1 2 | |
34 649006 649003 65011 2868 1543 0 4 1 2 | |
34 649040 649038 65034 2869 1542 0 4 1 2 | |
34 649074 649071 65056 2870 1541 0 4 1 2 | |
33 649107 649105 65079 2871 1540 0 4 1 2 | |
34 649141 649139 65102 2872 1539 0 4 1 2 | |
34 649175 649172 65124 2873 1538 0 4 1 2 | |
33 649208 649206 65147 2874 1537 0 4 1 2 | |
33 649241 649238 65170 2875 1536 0 4 1 2 | |
35 649276 649273 65192 2876 1535 0 4 1 2 | |
33 649309 649306 65215 2877 1534 0 4 1 2 | |
32 649341 649339 65238 2878 1533 0 4 1 2 | |
53 649394 649373 65260 2879 1532 0 4 1 2 | |
42 649436 649433 65283 2880 1531 0 4 1 2 | |
35 649471 649469 65306 2881 1530 0 4 1 2 | |
37 649508 649506 65328 2882 1529 0 4 1 2 | |
34 649542 649540 65351 2883 1528 0 4 1 2 | |
33 649575 649573 65374 2884 1527 0 4 1 2 | |
33 649608 649606 65396 2885 1526 0 4 1 2 | |
76 649684 649681 65419 2886 1525 0 4 1 2 | |
41 649725 649722 65442 2887 1524 0 4 1 2 | |
38 649763 649760 65464 2888 1523 0 4 1 2 | |
34 649797 649795 65487 2889 1522 0 4 1 2 | |
34 649831 649829 65510 2890 1521 0 4 1 2 | |
33 649864 649861 65532 2891 1520 0 4 1 2 | |
35 649899 649897 65555 2892 1519 0 4 1 2 | |
33 649932 649930 65578 2893 1518 0 4 1 2 | |
34 649966 649963 65600 2894 1517 0 4 1 2 | |
32 649998 649996 65623 2895 1516 0 4 1 2 | |
35 650033 650031 65646 2896 1515 0 4 1 2 | |
33 650066 650064 65668 2897 1514 0 4 1 2 | |
33 650099 650097 65691 2898 1513 0 4 1 2 | |
35 650134 650131 65714 2899 1512 0 4 1 2 | |
34 650168 650166 65736 2900 1511 0 4 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 650201 650199 65759 2901 1510 0 4 1 2 | |
36 650237 650234 65782 2902 1509 0 4 1 2 | |
35 650272 650270 65804 2903 1508 0 4 1 2 | |
35 650307 650304 65827 2904 1507 0 4 1 2 | |
33 650340 650338 65850 2905 1506 0 4 1 2 | |
83 650423 650419 65873 2906 1505 0 4 1 2 | |
40 650463 650461 65895 2907 1504 0 4 1 2 | |
36 650499 650496 65918 2908 1503 0 4 1 2 | |
38 650537 650534 65941 2909 1502 0 4 1 2 | |
34 650571 650568 65963 2910 1501 0 4 1 2 | |
33 650604 650602 65986 2911 1500 0 4 1 2 | |
76 650680 650676 66009 2912 1499 0 4 1 2 | |
41 650721 650718 66031 2913 1498 0 4 1 2 | |
38 650759 650756 66054 2914 1497 0 4 1 2 | |
76 650835 650832 66077 2915 1496 0 4 1 2 | |
41 650876 650872 66099 2916 1495 0 4 1 2 | |
36 650912 650909 66122 2917 1494 0 4 1 2 | |
34 650946 650944 66145 2918 1493 0 4 1 2 | |
34 650980 650977 66167 2919 1492 0 4 1 2 | |
35 651015 651012 66190 2920 1491 0 4 1 2 | |
35 651050 651047 66213 2921 1490 0 4 1 2 | |
33 651083 651081 66235 2922 1489 0 4 1 2 | |
34 651117 651114 66258 2923 1488 0 4 1 2 | |
35 651152 651149 66281 2924 1487 0 4 1 2 | |
33 651185 651183 66303 2925 1486 0 4 1 2 | |
33 651218 651216 66326 2926 1485 0 4 1 2 | |
35 651253 651251 66349 2927 1484 0 4 1 2 | |
34 651287 651285 66371 2928 1483 0 4 1 2 | |
34 651321 651319 66394 2929 1482 0 4 1 2 | |
33 651354 651352 66417 2930 1481 0 4 1 2 | |
59 651413 651410 66439 2931 1480 0 4 1 2 | |
38 651451 651448 66462 2932 1479 0 4 1 2 | |
35 651486 651483 66485 2933 1478 0 4 1 2 | |
37 651523 651520 66507 2934 1477 0 4 1 2 | |
33 651556 651554 66530 2935 1476 0 4 1 2 | |
34 651590 651587 66553 2936 1475 0 4 1 2 | |
32 651622 651620 66575 2937 1474 0 4 1 2 | |
84 651706 651703 66598 2938 1473 0 4 1 2 | |
38 651744 651741 66621 2939 1472 0 4 1 2 | |
37 651781 651778 66643 2940 1471 0 4 1 2 | |
34 651815 651813 66666 2941 1470 0 4 1 2 | |
33 651848 651846 66689 2942 1469 0 0 1 2 | |
35 651883 651880 66712 2943 1468 0 0 1 2 | |
33 651916 651914 66734 2944 1467 0 0 1 2 | |
34 651950 651948 66757 2945 1466 0 0 1 2 | |
33 651983 651981 66780 2946 1465 0 0 1 2 | |
35 652018 652016 66802 2947 1464 0 0 1 2 | |
34 652052 652050 66825 2948 1463 0 0 1 2 | |
33 652085 652083 66848 2949 1462 0 0 1 2 | |
32 652117 652115 66870 2950 1461 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
35 652152 652149 66893 2951 1460 0 0 1 2 | |
36 652188 652186 66916 2952 1459 0 0 1 2 | |
33 652221 652219 66938 2953 1458 0 0 1 2 | |
34 652255 652253 66961 2954 1457 0 0 1 2 | |
33 652288 652286 66984 2955 1456 0 0 1 2 | |
34 652322 652319 67006 2956 1455 0 0 1 2 | |
32 652354 652352 67029 2957 1454 0 0 1 2 | |
56 652410 652407 67052 2958 1453 0 0 1 2 | |
39 652449 652446 67074 2959 1452 0 0 1 2 | |
35 652484 652481 67097 2960 1451 0 0 1 2 | |
37 652521 652519 67120 2961 1450 0 0 1 2 | |
34 652555 652553 67142 2962 1449 0 0 1 2 | |
34 652589 652586 67165 2963 1448 0 0 1 2 | |
32 652621 652619 67188 2964 1447 0 0 1 2 | |
78 652699 652696 67210 2965 1446 0 0 1 2 | |
38 652737 652735 67233 2966 1445 0 0 1 2 | |
37 652774 652771 67256 2967 1444 0 0 1 2 | |
35 652809 652806 67278 2968 1443 0 0 1 2 | |
34 652843 652840 67301 2969 1442 0 0 1 2 | |
35 652878 652874 67324 2970 1441 0 0 1 2 | |
33 652911 652909 67346 2971 1440 0 0 1 2 | |
33 652944 652942 67369 2972 1439 0 0 1 2 | |
33 652977 652974 67392 2973 1438 0 0 1 2 | |
34 653011 653009 67414 2974 1437 0 0 1 2 | |
34 653045 653043 67437 2975 1436 0 0 1 2 | |
33 653078 653076 67460 2976 1435 0 0 1 2 | |
33 653111 653109 67482 2977 1434 0 0 1 2 | |
35 653146 653144 67505 2978 1433 0 0 1 2 | |
33 653179 653177 67528 2979 1432 0 0 1 2 | |
32 653211 653209 67551 2980 1431 0 0 1 2 | |
34 653245 653242 67573 2981 1430 0 0 1 2 | |
33 653278 653276 67596 2982 1429 0 0 1 2 | |
33 653311 653309 67619 2983 1428 0 0 1 2 | |
33 653344 653342 67641 2984 1427 0 0 1 2 | |
53 653397 653374 67664 2985 1426 0 0 1 2 | |
41 653438 653435 67687 2986 1425 0 0 1 2 | |
35 653473 653470 67709 2987 1424 0 0 1 2 | |
35 653508 653505 67732 2988 1423 0 0 1 2 | |
34 653542 653540 67755 2989 1422 0 0 1 2 | |
33 653575 653573 67777 2990 1421 0 0 1 2 | |
32 653607 653605 67800 2991 1420 0 0 1 2 | |
75 653682 653679 67823 2992 1419 0 0 1 2 | |
40 653722 653719 67845 2993 1418 0 0 1 2 | |
37 653759 653756 67868 2994 1417 0 0 1 2 | |
35 653794 653791 67891 2995 1416 0 0 1 2 | |
33 653827 653825 67913 2996 1415 0 0 1 2 | |
33 653860 653858 67936 2997 1414 0 0 1 2 | |
35 653895 653893 67959 2998 1413 0 0 1 2 | |
34 653929 653926 67981 2999 1412 0 0 1 2 | |
33 653962 653960 68004 3000 1411 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
32 653994 653992 68027 3001 1410 0 0 1 2 | |
38 654032 654029 68049 3002 1409 0 0 1 2 | |
62 654094 654091 68072 3003 1408 0 0 1 2 | |
39 654133 654130 68095 3004 1407 0 0 1 2 | |
33 654166 654164 68117 3005 1406 0 0 1 2 | |
33 654199 654197 68140 3006 1405 0 0 1 2 | |
33 654232 654230 68163 3007 1404 0 0 1 2 | |
34 654266 654264 68185 3008 1403 0 0 1 2 | |
34 654300 654297 68208 3009 1402 0 0 1 2 | |
32 654332 654330 68231 3010 1401 0 0 1 2 | |
33 654365 654362 68253 3011 1400 0 0 1 2 | |
60 654425 654422 68276 3012 1399 0 0 1 2 | |
38 654463 654461 68299 3013 1398 0 0 1 2 | |
34 654497 654495 68321 3014 1397 0 0 1 2 | |
37 654534 654531 68344 3015 1396 0 0 1 2 | |
33 654567 654565 68367 3016 1395 0 0 1 2 | |
33 654600 654598 68390 3017 1394 0 0 1 2 | |
75 654675 654672 68412 3018 1393 0 0 1 2 | |
42 654717 654714 68435 3019 1392 0 0 1 2 | |
37 654754 654752 68458 3020 1391 0 0 1 2 | |
36 654790 654788 68480 3021 1390 0 0 1 2 | |
34 654824 654822 68503 3022 1389 0 0 1 2 | |
34 654858 654855 68526 3023 1388 0 0 1 2 | |
34 654892 654889 68548 3024 1387 0 0 1 2 | |
33 654925 654922 68571 3025 1386 0 0 1 2 | |
33 654958 654955 68594 3026 1385 0 0 1 2 | |
33 654991 654989 68616 3027 1384 0 0 1 2 | |
34 655025 655023 68639 3028 1383 0 0 1 2 | |
34 655059 655057 68662 3029 1382 0 0 1 2 | |
33 655092 655090 68684 3030 1381 0 0 1 2 | |
33 655125 655122 68707 3031 1380 0 0 1 2 | |
35 655160 655157 68730 3032 1379 0 0 1 2 | |
33 655193 655190 68752 3033 1378 0 0 1 2 | |
32 655225 655223 68775 3034 1377 0 0 1 2 | |
35 655260 655258 68798 3035 1376 0 0 1 2 | |
34 655294 655292 68820 3036 1375 0 0 1 2 | |
34 655328 655325 68843 3037 1374 0 0 1 2 | |
33 655361 655359 68866 3038 1373 0 0 1 2 | |
60 655421 655417 68888 3039 1372 0 0 1 2 | |
37 655458 655456 68911 3040 1371 0 0 1 2 | |
35 655493 655490 68934 3041 1370 0 0 1 2 | |
36 655529 655527 68956 3042 1369 0 0 1 2 | |
33 655562 655560 68979 3043 1368 0 0 1 2 | |
33 655595 655593 69002 3044 1367 0 0 1 2 | |
34 655629 655627 69024 3045 1366 0 0 1 2 | |
81 655710 655707 69047 3046 1365 0 0 1 2 | |
37 655747 655744 69070 3047 1364 0 0 1 2 | |
35 655782 655780 69092 3048 1363 0 0 1 2 | |
34 655816 655814 69115 3049 1362 0 0 1 2 | |
34 655850 655847 69138 3050 1361 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 655884 655882 69160 3051 1360 0 0 1 2 | |
37 655921 655918 69183 3052 1359 0 0 1 2 | |
33 655954 655951 69206 3053 1358 0 0 1 2 | |
33 655987 655985 69229 3054 1357 0 0 1 2 | |
35 656022 656020 69251 3055 1356 0 0 1 2 | |
33 656055 656053 69274 3056 1355 0 0 1 2 | |
33 656088 656086 69297 3057 1354 0 0 1 2 | |
32 656120 656118 69319 3058 1353 0 0 1 2 | |
35 656155 656152 69342 3059 1352 0 0 1 2 | |
33 656188 656185 69365 3060 1351 0 0 1 2 | |
33 656221 656219 69387 3061 1350 0 0 1 2 | |
34 656255 656253 69410 3062 1349 0 0 1 2 | |
34 656289 656287 69433 3063 1348 0 0 1 2 | |
33 656322 656320 69455 3064 1347 0 0 1 2 | |
32 656354 656352 69478 3065 1346 0 0 1 2 | |
59 656413 656410 69501 3066 1345 0 0 1 2 | |
39 656452 656449 69523 3067 1344 0 0 1 2 | |
34 656486 656484 69546 3068 1343 0 0 1 2 | |
62 656548 656546 69569 3069 1342 0 0 1 2 | |
38 656586 656584 69591 3070 1341 0 0 1 2 | |
34 656620 656618 69614 3071 1340 0 0 1 2 | |
79 656699 656696 69637 3072 1339 0 0 1 2 | |
39 656738 656735 69659 3073 1338 0 0 1 2 | |
37 656775 656772 69682 3074 1337 0 0 1 2 | |
34 656809 656807 69705 3075 1336 0 0 1 2 | |
33 656842 656840 69727 3076 1335 0 0 1 2 | |
34 656876 656873 69750 3077 1334 0 0 1 2 | |
34 656910 656907 69773 3078 1333 0 0 1 2 | |
33 656943 656941 69795 3079 1332 0 0 1 2 | |
32 656975 656973 69818 3080 1331 0 0 1 2 | |
34 657009 657006 69841 3081 1330 0 0 1 2 | |
34 657043 657041 69863 3082 1329 0 0 1 2 | |
33 657076 657073 69886 3083 1328 0 0 1 2 | |
33 657109 657107 69909 3084 1327 0 0 1 2 | |
34 657143 657141 69931 3085 1326 0 0 1 2 | |
33 657176 657174 69954 3086 1325 0 0 1 2 | |
33 657209 657207 69977 3087 1324 0 0 1 2 | |
32 657241 657239 70000 3088 1323 0 0 1 2 | |
35 657276 657273 70022 3089 1322 0 0 1 2 | |
33 657309 657307 70045 3090 1321 0 0 1 2 | |
33 657342 657340 70068 3091 1320 0 0 1 2 | |
33 657375 657372 70090 3092 1319 0 0 1 2 | |
60 657435 657432 70113 3093 1318 0 0 1 2 | |
36 657471 657468 70136 3094 1317 0 0 1 2 | |
35 657506 657504 70158 3095 1316 0 0 1 2 | |
34 657540 657538 70181 3096 1315 0 0 1 2 | |
33 657573 657571 70204 3097 1314 0 0 1 2 | |
34 657607 657604 70226 3098 1313 0 0 1 2 | |
74 657681 657678 70249 3099 1312 0 0 1 2 | |
41 657722 657720 70272 3100 1311 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
61 657783 657780 70294 3101 1310 0 0 1 2 | |
40 657823 657820 70317 3102 1309 0 0 1 2 | |
34 657857 657855 70340 3103 1308 0 0 1 2 | |
36 657893 657891 70362 3104 1307 0 0 1 2 | |
34 657927 657924 70385 3105 1306 0 0 1 2 | |
33 657960 657958 70408 3106 1305 0 0 1 2 | |
33 657993 657991 70430 3107 1304 0 0 1 2 | |
35 658028 658026 70453 3108 1303 0 0 1 2 | |
33 658061 658059 70476 3109 1302 0 0 1 2 | |
33 658094 658092 70498 3110 1301 0 0 1 2 | |
35 658129 658127 70521 3111 1300 0 0 1 2 | |
33 658162 658160 70544 3112 1299 0 0 1 2 | |
33 658195 658192 70566 3113 1298 0 0 1 2 | |
32 658227 658225 70589 3114 1297 0 0 1 2 | |
35 658262 658260 70612 3115 1296 0 0 1 2 | |
34 658296 658294 70634 3116 1295 0 0 1 2 | |
32 658328 658326 70657 3117 1294 0 0 1 2 | |
33 658361 658359 70680 3118 1293 0 0 1 2 | |
62 658423 658420 70702 3119 1292 0 0 1 2 | |
37 658460 658458 70725 3120 1291 0 0 1 2 | |
34 658494 658492 70748 3121 1290 0 0 1 2 | |
36 658530 658528 70770 3122 1289 0 0 1 2 | |
34 658564 658562 70793 3123 1288 0 0 1 2 | |
34 658598 658595 70816 3124 1287 0 0 1 2 | |
72 658670 658630 70839 3125 1286 0 0 1 2 | |
45 658715 658711 70861 3126 1285 0 0 1 2 | |
37 658752 658748 70884 3127 1284 0 0 1 2 | |
35 658787 658784 70907 3128 1283 0 0 1 2 | |
33 658820 658817 70929 3129 1282 0 0 1 2 | |
33 658853 658850 70952 3130 1281 0 0 1 2 | |
34 658887 658884 70975 3131 1280 0 0 1 2 | |
33 658920 658918 70997 3132 1279 0 0 1 2 | |
34 658954 658951 71020 3133 1278 0 0 1 2 | |
33 658987 658984 71043 3134 1277 0 0 1 2 | |
34 659021 659018 71065 3135 1276 0 0 1 2 | |
33 659054 659051 71088 3136 1275 0 0 1 2 | |
33 659087 659084 71111 3137 1274 0 0 1 2 | |
33 659120 659118 71133 3138 1273 0 0 1 2 | |
34 659154 659152 71156 3139 1272 0 0 1 2 | |
33 659187 659185 71179 3140 1271 0 0 1 2 | |
33 659220 659218 71201 3141 1270 0 0 1 2 | |
34 659254 659252 71224 3142 1269 0 0 1 2 | |
34 659288 659285 71247 3143 1268 0 0 1 2 | |
33 659321 659319 71269 3144 1267 0 0 1 2 | |
33 659354 659351 71292 3145 1266 0 0 1 2 | |
55 659409 659406 71315 3146 1265 0 0 1 2 | |
38 659447 659445 71337 3147 1264 0 0 1 2 | |
35 659482 659480 71360 3148 1263 0 0 1 2 | |
37 659519 659516 71383 3149 1262 0 0 1 2 | |
33 659552 659550 71405 3150 1261 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 659586 659584 71428 3151 1260 0 0 1 2 | |
35 659621 659619 71451 3152 1259 0 0 1 2 | |
78 659699 659696 71473 3153 1258 0 0 1 2 | |
39 659738 659736 71496 3154 1257 0 0 1 2 | |
36 659774 659771 71519 3155 1256 0 0 1 2 | |
32 659806 659804 71541 3156 1255 0 0 1 2 | |
34 659840 659837 71564 3157 1254 0 0 1 2 | |
33 659873 659870 71587 3158 1253 0 0 1 2 | |
35 659908 659906 71609 3159 1252 0 0 1 2 | |
33 659941 659939 71632 3160 1251 0 0 1 2 | |
33 659974 659971 71655 3161 1250 0 0 1 2 | |
34 660008 660005 71678 3162 1249 0 0 1 2 | |
33 660041 660039 71700 3163 1248 0 0 1 2 | |
33 660074 660071 71723 3164 1247 0 0 1 2 | |
32 660106 660104 71746 3165 1246 0 0 1 2 | |
35 660141 660138 71768 3166 1245 0 0 1 2 | |
33 660174 660172 71791 3167 1244 0 0 1 2 | |
33 660207 660205 71814 3168 1243 0 0 1 2 | |
34 660241 660239 71836 3169 1242 0 0 1 2 | |
34 660275 660273 71859 3170 1241 0 0 1 2 | |
33 660308 660306 71882 3171 1240 0 0 1 2 | |
34 660342 660339 71904 3172 1239 0 0 1 2 | |
32 660374 660372 71927 3173 1238 0 0 1 2 | |
60 660434 660432 71950 3174 1237 0 0 1 2 | |
35 660469 660467 71972 3175 1236 0 0 1 2 | |
37 660506 660504 71995 3176 1235 0 0 1 2 | |
35 660541 660538 72018 3177 1234 0 0 1 2 | |
34 660575 660572 72040 3178 1233 0 0 1 2 | |
32 660607 660605 72063 3179 1232 0 0 1 2 | |
75 660682 660679 72086 3180 1231 0 0 1 2 | |
41 660723 660721 72108 3181 1230 0 0 1 2 | |
37 660760 660758 72131 3182 1229 0 0 1 2 | |
75 660835 660833 72154 3183 1228 0 0 1 2 | |
39 660874 660872 72176 3184 1227 0 0 1 2 | |
37 660911 660909 72199 3185 1226 0 0 1 2 | |
33 660944 660942 72222 3186 1225 0 0 1 2 | |
33 660977 660975 72244 3187 1224 0 0 1 2 | |
35 661012 661010 72267 3188 1223 0 0 1 2 | |
33 661045 661043 72290 3189 1222 0 0 1 2 | |
33 661078 661076 72312 3190 1221 0 0 1 2 | |
32 661110 661108 72335 3191 1220 0 0 1 2 | |
35 661145 661142 72358 3192 1219 0 0 1 2 | |
33 661178 661176 72380 3193 1218 0 0 1 2 | |
33 661211 661208 72403 3194 1217 0 0 1 2 | |
32 661243 661241 72426 3195 1216 0 0 1 2 | |
35 661278 661275 72448 3196 1215 0 0 1 2 | |
33 661311 661308 72471 3197 1214 0 0 1 2 | |
60 661371 661368 72494 3198 1213 0 0 1 2 | |
68 661439 661436 72517 3199 1212 0 0 1 2 | |
36 661475 661472 72539 3200 1211 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
36 661511 661508 72562 3201 1210 0 0 1 2 | |
37 661548 661546 72585 3202 1209 0 0 1 2 | |
33 661581 661579 72607 3203 1208 0 0 1 2 | |
33 661614 661612 72630 3204 1207 0 0 1 2 | |
83 661697 661693 72653 3205 1206 0 0 1 2 | |
38 661735 661733 72675 3206 1205 0 0 1 2 | |
37 661772 661770 72698 3207 1204 0 0 1 2 | |
34 661806 661803 72721 3208 1203 0 0 1 2 | |
33 661839 661837 72743 3209 1202 0 0 1 2 | |
33 661872 661869 72766 3210 1201 0 0 1 2 | |
34 661906 661904 72789 3211 1200 0 0 1 2 | |
33 661939 661937 72811 3212 1199 0 0 1 2 | |
34 661973 661970 72834 3213 1198 0 0 1 2 | |
35 662008 662005 72857 3214 1197 0 0 1 2 | |
33 662041 662039 72879 3215 1196 0 0 1 2 | |
33 662074 662072 72902 3216 1195 0 0 1 2 | |
33 662107 662104 72925 3217 1194 0 0 1 2 | |
35 662142 662140 72947 3218 1193 0 0 1 2 | |
34 662176 662173 72970 3219 1192 0 0 1 2 | |
32 662208 662206 72993 3220 1191 0 0 1 2 | |
33 662241 662239 73015 3221 1190 0 0 1 2 | |
34 662275 662273 73038 3222 1189 0 0 1 2 | |
34 662309 662307 73061 3223 1188 0 0 1 2 | |
32 662341 662339 73083 3224 1187 0 0 1 2 | |
33 662374 662371 73106 3225 1186 0 0 1 2 | |
61 662435 662432 73129 3226 1185 0 0 1 2 | |
36 662471 662469 73151 3227 1184 0 0 1 2 | |
37 662508 662505 73174 3228 1183 0 0 1 2 | |
34 662542 662539 73197 3229 1182 0 0 1 2 | |
33 662575 662573 73219 3230 1181 0 0 1 2 | |
33 662608 662605 73242 3231 1180 0 0 1 2 | |
72 662680 662677 73265 3232 1179 0 0 1 2 | |
41 662721 662718 73287 3233 1178 0 0 1 2 | |
35 662756 662754 73310 3234 1177 0 0 1 2 | |
35 662791 662789 73333 3235 1176 0 0 1 2 | |
34 662825 662823 73356 3236 1175 0 0 1 2 | |
34 662859 662856 73378 3237 1174 0 0 1 2 | |
34 662893 662891 73401 3238 1173 0 0 1 2 | |
33 662926 662924 73424 3239 1172 0 0 1 2 | |
33 662959 662957 73446 3240 1171 0 0 1 2 | |
32 662991 662989 73469 3241 1170 0 0 1 2 | |
35 663026 663023 73492 3242 1169 0 0 1 2 | |
32 663058 663056 73514 3243 1168 0 0 1 2 | |
33 663091 663089 73537 3244 1167 0 0 1 2 | |
33 663124 663122 73560 3245 1166 0 0 1 2 | |
34 663158 663156 73582 3246 1165 0 0 1 2 | |
33 663191 663189 73605 3247 1164 0 0 1 2 | |
33 663224 663222 73628 3248 1163 0 0 1 2 | |
34 663258 663255 73650 3249 1162 0 0 1 2 | |
33 663291 663289 73673 3250 1161 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 663324 663321 73696 3251 1160 0 0 1 2 | |
35 663359 663357 73718 3252 1159 0 0 1 2 | |
58 663417 663415 73741 3253 1158 0 0 1 2 | |
38 663455 663452 73764 3254 1157 0 0 1 2 | |
34 663489 663487 73786 3255 1156 0 0 1 2 | |
36 663525 663523 73809 3256 1155 0 0 1 2 | |
34 663559 663557 73832 3257 1154 0 0 1 2 | |
33 663592 663589 73854 3258 1153 0 0 1 2 | |
32 663624 663622 73877 3259 1152 0 0 1 2 | |
83 663707 663704 73900 3260 1151 0 0 1 2 | |
37 663744 663742 73922 3261 1150 0 0 1 2 | |
37 663781 663778 73945 3262 1149 0 0 1 2 | |
34 663815 663813 73968 3263 1148 0 0 1 2 | |
33 663848 663846 73990 3264 1147 0 0 1 2 | |
35 663883 663881 74013 3265 1146 0 0 1 2 | |
33 663916 663914 74036 3266 1145 0 0 1 2 | |
33 663949 663947 74058 3267 1144 0 0 1 2 | |
33 663982 663980 74081 3268 1143 0 0 1 2 | |
34 664016 664014 74104 3269 1142 0 0 1 2 | |
34 664050 664047 74126 3270 1141 0 0 1 2 | |
32 664082 664080 74149 3271 1140 0 0 1 2 | |
34 664116 664113 74172 3272 1139 0 0 1 2 | |
34 664150 664148 74195 3273 1138 0 0 1 2 | |
33 664183 664180 74217 3274 1137 0 0 1 2 | |
33 664216 664213 74240 3275 1136 0 0 1 2 | |
32 664248 664245 74263 3276 1135 0 0 1 2 | |
34 664282 664280 74285 3277 1134 0 0 1 2 | |
34 664316 664313 74308 3278 1133 0 0 1 2 | |
33 664349 664347 74331 3279 1132 0 0 1 2 | |
59 664408 664405 74353 3280 1131 0 0 1 2 | |
39 664447 664444 74376 3281 1130 0 0 1 2 | |
35 664482 664480 74399 3282 1129 0 0 1 2 | |
56 664538 664535 74421 3283 1128 0 0 1 2 | |
38 664576 664574 74444 3284 1127 0 0 1 2 | |
35 664611 664608 74467 3285 1126 0 0 1 2 | |
76 664687 664684 74489 3286 1125 0 0 1 2 | |
40 664727 664724 74512 3287 1124 0 0 1 2 | |
35 664762 664760 74535 3288 1123 0 0 1 2 | |
34 664796 664793 74557 3289 1122 0 0 1 2 | |
33 664829 664827 74580 3290 1121 0 0 1 2 | |
33 664862 664860 74603 3291 1120 0 0 1 2 | |
35 664897 664895 74625 3292 1119 0 0 1 2 | |
34 664931 664928 74648 3293 1118 0 0 1 2 | |
33 664964 664961 74671 3294 1117 0 0 1 2 | |
522 665486 665480 74693 3295 1116 0 0 1 2 | |
54 665540 665537 74716 3296 1115 0 0 1 2 | |
36 665576 665574 74739 3297 1114 0 0 1 2 | |
35 665611 665608 74761 3298 1113 0 0 1 2 | |
103 665714 665710 74784 3299 1112 0 0 1 2 | |
42 665756 665753 74807 3300 1111 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
37 665793 665790 74829 3301 1110 0 0 1 2 | |
37 665830 665827 74852 3302 1109 0 0 1 2 | |
34 665864 665862 74875 3303 1108 0 0 1 2 | |
36 665900 665898 74897 3304 1107 0 0 1 2 | |
34 665934 665932 74920 3305 1106 0 0 1 2 | |
32 665966 665964 74943 3306 1105 0 0 1 2 | |
33 665999 665997 74965 3307 1104 0 0 1 2 | |
34 666033 666031 74988 3308 1103 0 0 1 2 | |
33 666066 666064 75011 3309 1102 0 0 1 2 | |
32 666098 666096 75034 3310 1101 0 0 1 2 | |
35 666133 666131 75056 3311 1100 0 0 1 2 | |
33 666166 666164 75079 3312 1099 0 0 1 2 | |
33 666199 666197 75102 3313 1098 0 0 1 2 | |
33 666232 666229 75124 3314 1097 0 0 1 2 | |
34 666266 666264 75147 3315 1096 0 0 1 2 | |
33 666299 666297 75170 3316 1095 0 0 1 2 | |
33 666332 666330 75192 3317 1094 0 0 1 2 | |
33 666365 666362 75215 3318 1093 0 0 1 2 | |
61 666426 666423 75238 3319 1092 0 0 1 2 | |
37 666463 666461 75260 3320 1091 0 0 1 2 | |
36 666499 666496 75283 3321 1090 0 0 1 2 | |
36 666535 666532 75306 3322 1089 0 0 1 2 | |
34 666569 666566 75328 3323 1088 0 0 1 2 | |
33 666602 666599 75351 3324 1087 0 0 1 2 | |
74 666676 666672 75374 3325 1086 0 0 1 2 | |
42 666718 666716 75396 3326 1085 0 0 1 2 | |
38 666756 666753 75419 3327 1084 0 0 1 2 | |
34 666790 666788 75442 3328 1083 0 0 1 2 | |
34 666824 666821 75464 3329 1082 0 0 1 2 | |
33 666857 666855 75487 3330 1081 0 0 1 2 | |
35 666892 666890 75510 3331 1080 0 0 1 2 | |
33 666925 666923 75532 3332 1079 0 0 1 2 | |
34 666959 666957 75555 3333 1078 0 0 1 2 | |
33 666992 666989 75578 3334 1077 0 0 1 2 | |
34 667026 667024 75600 3335 1076 0 0 1 2 | |
34 667060 667057 75623 3336 1075 0 0 1 2 | |
33 667093 667090 75646 3337 1074 0 0 1 2 | |
32 667125 667123 75668 3338 1073 0 0 1 2 | |
34 667159 667157 75691 3339 1072 0 0 1 2 | |
33 667192 667189 75714 3340 1071 0 0 1 2 | |
32 667224 667222 75736 3341 1070 0 0 1 2 | |
34 667258 667256 75759 3342 1069 0 0 1 2 | |
33 667291 667289 75782 3343 1068 0 0 1 2 | |
34 667325 667323 75804 3344 1067 0 0 1 2 | |
33 667358 667356 75827 3345 1066 0 0 1 2 | |
58 667416 667414 75850 3346 1065 0 0 1 2 | |
39 667455 667452 75873 3347 1064 0 0 1 2 | |
35 667490 667487 75895 3348 1063 0 0 1 2 | |
37 667527 667524 75918 3349 1062 0 0 1 2 | |
33 667560 667558 75941 3350 1061 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 667594 667591 75963 3351 1060 0 0 1 2 | |
74 667668 667629 75986 3352 1059 0 0 1 2 | |
46 667714 667711 76009 3353 1058 0 0 1 2 | |
37 667751 667748 76031 3354 1057 0 0 1 2 | |
35 667786 667784 76054 3355 1056 0 0 1 2 | |
34 667820 667818 76077 3356 1055 0 0 1 2 | |
33 667853 667850 76099 3357 1054 0 0 1 2 | |
34 667887 667884 76122 3358 1053 0 0 1 2 | |
34 667921 667918 76145 3359 1052 0 0 1 2 | |
32 667953 667951 76167 3360 1051 0 0 1 2 | |
32 667985 667983 76190 3361 1050 0 0 1 2 | |
35 668020 668017 76213 3362 1049 0 0 1 2 | |
33 668053 668050 76235 3363 1048 0 0 1 2 | |
33 668086 668084 76258 3364 1047 0 0 1 2 | |
33 668119 668116 76281 3365 1046 0 0 1 2 | |
34 668153 668151 76303 3366 1045 0 0 1 2 | |
33 668186 668184 76326 3367 1044 0 0 1 2 | |
33 668219 668217 76349 3368 1043 0 0 1 2 | |
32 668251 668249 76371 3369 1042 0 0 1 2 | |
35 668286 668284 76394 3370 1041 0 0 1 2 | |
33 668319 668317 76417 3371 1040 0 0 1 2 | |
34 668353 668350 76439 3372 1039 0 0 1 2 | |
55 668408 668406 76462 3373 1038 0 0 1 2 | |
39 668447 668445 76485 3374 1037 0 0 1 2 | |
35 668482 668480 76507 3375 1036 0 0 1 2 | |
36 668518 668516 76530 3376 1035 0 0 1 2 | |
34 668552 668550 76553 3377 1034 0 0 1 2 | |
34 668586 668584 76575 3378 1033 0 0 1 2 | |
33 668619 668617 76598 3379 1032 0 0 1 2 | |
78 668697 668694 76621 3380 1031 0 0 1 2 | |
40 668737 668734 76643 3381 1030 0 0 1 2 | |
37 668774 668771 76666 3382 1029 0 0 1 2 | |
35 668809 668806 76689 3383 1028 0 0 1 2 | |
34 668843 668840 76712 3384 1027 0 0 1 2 | |
33 668876 668873 76734 3385 1026 0 0 1 2 | |
34 668910 668907 76757 3386 1025 0 0 1 2 | |
34 668944 668941 76780 3387 1024 0 0 1 2 | |
32 668976 668974 76802 3388 1023 0 0 1 2 | |
35 669011 669008 76825 3389 1022 0 0 1 2 | |
34 669045 669042 76848 3390 1021 0 0 1 2 | |
59 669104 669101 76870 3391 1020 0 0 1 2 | |
39 669143 669141 76893 3392 1019 0 0 1 2 | |
34 669177 669175 76916 3393 1018 0 0 1 2 | |
34 669211 669208 76938 3394 1017 0 0 1 2 | |
33 669244 669241 76961 3395 1016 0 0 1 2 | |
34 669278 669276 76984 3396 1015 0 0 1 2 | |
33 669311 669309 77006 3397 1014 0 0 1 2 | |
34 669345 669343 77029 3398 1013 0 0 1 2 | |
56 669401 669375 77052 3399 1012 0 0 1 2 | |
41 669442 669440 77074 3400 1011 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
36 669478 669475 77097 3401 1010 0 0 1 2 | |
39 669517 669515 77120 3402 1009 0 0 1 2 | |
35 669552 669550 77142 3403 1008 0 0 1 2 | |
34 669586 669583 77165 3404 1007 0 0 1 2 | |
32 669618 669616 77188 3405 1006 0 0 1 2 | |
78 669696 669693 77210 3406 1005 0 0 1 2 | |
39 669735 669732 77233 3407 1004 0 0 1 2 | |
37 669772 669769 77256 3408 1003 0 0 1 2 | |
34 669806 669804 77278 3409 1002 0 0 1 2 | |
33 669839 669837 77301 3410 1001 0 0 1 2 | |
34 669873 669870 77324 3411 1000 0 0 1 2 | |
34 669907 669905 77346 3412 999 0 0 1 2 | |
34 669941 669939 77369 3413 998 0 0 1 2 | |
33 669974 669972 77392 3414 997 0 0 1 2 | |
35 670009 670007 77414 3415 996 0 0 1 2 | |
33 670042 670040 77437 3416 995 0 0 1 2 | |
33 670075 670073 77460 3417 994 0 0 1 2 | |
33 670108 670106 77482 3418 993 0 0 1 2 | |
35 670143 670140 77505 3419 992 0 0 1 2 | |
33 670176 670174 77528 3420 991 0 0 1 2 | |
34 670210 670208 77551 3421 990 0 0 1 2 | |
33 670243 670240 77573 3422 989 0 0 1 2 | |
34 670277 670274 77596 3423 988 0 0 1 2 | |
32 670309 670307 77619 3424 987 0 0 1 2 | |
34 670343 670340 77641 3425 986 0 0 1 2 | |
33 670376 670373 77664 3426 985 0 0 1 2 | |
60 670436 670433 77687 3427 984 0 0 1 2 | |
36 670472 670469 77709 3428 983 0 0 1 2 | |
36 670508 670505 77732 3429 982 0 0 1 2 | |
34 670542 670539 77755 3430 981 0 0 1 2 | |
33 670575 670573 77777 3431 980 0 0 1 2 | |
33 670608 670606 77800 3432 979 0 0 1 2 | |
76 670684 670681 77823 3433 978 0 0 1 2 | |
40 670724 670721 77845 3434 977 0 0 1 2 | |
37 670761 670758 77868 3435 976 0 0 1 2 | |
145 670906 670903 77891 3436 975 0 0 1 2 | |
42 670948 670945 77913 3437 974 0 0 1 2 | |
36 670984 670981 77936 3438 973 0 0 1 2 | |
34 671018 671015 77959 3439 972 0 0 1 2 | |
34 671052 671050 77981 3440 971 0 0 1 2 | |
34 671086 671084 78004 3441 970 0 0 1 2 | |
33 671119 671117 78027 3442 969 0 0 1 2 | |
34 671153 671150 78049 3443 968 0 0 1 2 | |
33 671186 671183 78072 3444 967 0 0 1 2 | |
33 671219 671217 78095 3445 966 0 0 1 2 | |
33 671252 671250 78117 3446 965 0 0 1 2 | |
34 671286 671284 78140 3447 964 0 0 1 2 | |
33 671319 671317 78163 3448 963 0 0 1 2 | |
32 671351 671349 78185 3449 962 0 0 1 2 | |
62 671413 671410 78208 3450 961 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 671453 671451 78231 3451 960 0 0 1 2 | |
38 671491 671488 78253 3452 959 0 0 1 2 | |
37 671528 671526 78276 3453 958 0 0 1 2 | |
35 671563 671561 78299 3454 957 0 0 1 2 | |
34 671597 671595 78321 3455 956 0 0 1 2 | |
34 671631 671629 78344 3456 955 0 0 1 2 | |
87 671718 671715 78367 3457 954 0 0 1 2 | |
37 671755 671751 78390 3458 953 0 0 1 2 | |
35 671790 671788 78412 3459 952 0 0 1 2 | |
35 671825 671822 78435 3460 951 0 0 1 2 | |
33 671858 671855 78458 3461 950 0 0 1 2 | |
35 671893 671891 78480 3462 949 0 0 1 2 | |
33 671926 671923 78503 3463 948 0 0 1 2 | |
33 671959 671956 78526 3464 947 0 0 1 2 | |
33 671992 671989 78548 3465 946 0 0 1 2 | |
34 672026 672024 78571 3466 945 0 0 1 2 | |
33 672059 672057 78594 3467 944 0 0 1 2 | |
33 672092 672090 78616 3468 943 0 0 1 2 | |
33 672125 672123 78639 3469 942 0 0 1 2 | |
35 672160 672158 78662 3470 941 0 0 1 2 | |
33 672193 672191 78684 3471 940 0 0 1 2 | |
33 672226 672224 78707 3472 939 0 0 1 2 | |
35 672261 672259 78730 3473 938 0 0 1 2 | |
34 672295 672292 78752 3474 937 0 0 1 2 | |
34 672329 672326 78775 3475 936 0 0 1 2 | |
32 672361 672359 78798 3476 935 0 0 1 2 | |
63 672424 672422 78820 3477 934 0 0 1 2 | |
39 672463 672460 78843 3478 933 0 0 1 2 | |
35 672498 672495 78866 3479 932 0 0 1 2 | |
59 672557 672554 78888 3480 931 0 0 1 2 | |
35 672592 672590 78911 3481 930 0 0 1 2 | |
35 672627 672624 78934 3482 929 0 0 1 2 | |
80 672707 672704 78956 3483 928 0 0 1 2 | |
37 672744 672742 78979 3484 927 0 0 1 2 | |
37 672781 672779 79002 3485 926 0 0 1 2 | |
34 672815 672812 79024 3486 925 0 0 1 2 | |
33 672848 672845 79047 3487 924 0 0 1 2 | |
34 672882 672880 79070 3488 923 0 0 1 2 | |
33 672915 672913 79092 3489 922 0 0 1 2 | |
65 672980 672976 79115 3490 921 0 0 1 2 | |
40 673020 673018 79138 3491 920 0 0 1 2 | |
36 673056 673053 79160 3492 919 0 0 1 2 | |
33 673089 673086 79183 3493 918 0 0 1 2 | |
33 673122 673120 79206 3494 917 0 0 1 2 | |
35 673157 673155 79229 3495 916 0 0 1 2 | |
33 673190 673188 79251 3496 915 0 0 1 2 | |
33 673223 673221 79274 3497 914 0 0 1 2 | |
32 673255 673252 79297 3498 913 0 0 1 2 | |
34 673289 673286 79319 3499 912 0 0 1 2 | |
33 673322 673320 79342 3500 911 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 673355 673353 79365 3501 910 0 0 1 2 | |
63 673418 673415 79387 3502 909 0 0 1 2 | |
38 673456 673454 79410 3503 908 0 0 1 2 | |
35 673491 673488 79433 3504 907 0 0 1 2 | |
36 673527 673525 79455 3505 906 0 0 1 2 | |
34 673561 673559 79478 3506 905 0 0 1 2 | |
33 673594 673591 79501 3507 904 0 0 1 2 | |
32 673626 673624 79523 3508 903 0 0 1 2 | |
85 673711 673708 79546 3509 902 0 0 1 2 | |
39 673750 673747 79569 3510 901 0 0 1 2 | |
36 673786 673783 79591 3511 900 0 0 1 2 | |
34 673820 673818 79614 3512 899 0 0 1 2 | |
34 673854 673851 79637 3513 898 0 0 1 2 | |
34 673888 673885 79659 3514 897 0 0 1 2 | |
33 673921 673919 79682 3515 896 0 0 1 2 | |
33 673954 673951 79705 3516 895 0 0 1 2 | |
32 673986 673984 79727 3517 894 0 0 1 2 | |
35 674021 674019 79750 3518 893 0 0 1 2 | |
33 674054 674052 79773 3519 892 0 0 1 2 | |
33 674087 674085 79795 3520 891 0 0 1 2 | |
33 674120 674118 79818 3521 890 0 0 1 2 | |
35 674155 674152 79841 3522 889 0 0 1 2 | |
33 674188 674186 79863 3523 888 0 0 1 2 | |
33 674221 674219 79886 3524 887 0 0 1 2 | |
34 674255 674252 79909 3525 886 0 0 1 2 | |
34 674289 674287 79931 3526 885 0 0 1 2 | |
33 674322 674319 79954 3527 884 0 0 1 2 | |
33 674355 674352 79977 3528 883 0 0 1 2 | |
55 674410 674408 80000 3529 882 0 0 1 2 | |
39 674449 674447 80022 3530 881 0 0 1 2 | |
35 674484 674481 80045 3531 880 0 0 1 2 | |
36 674520 674518 80068 3532 879 0 0 1 2 | |
34 674554 674552 80090 3533 878 0 0 1 2 | |
33 674587 674584 80113 3534 877 0 0 1 2 | |
32 674619 674617 80136 3535 876 0 0 1 2 | |
78 674697 674694 80158 3536 875 0 0 1 2 | |
40 674737 674734 80181 3537 874 0 0 1 2 | |
37 674774 674772 80204 3538 873 0 0 1 2 | |
34 674808 674806 80226 3539 872 0 0 1 2 | |
33 674841 674838 80249 3540 871 0 0 1 2 | |
33 674874 674871 80272 3541 870 0 0 1 2 | |
34 674908 674906 80294 3542 869 0 0 1 2 | |
33 674941 674938 80317 3543 868 0 0 1 2 | |
33 674974 674971 80340 3544 867 0 0 1 2 | |
34 675008 675006 80362 3545 866 0 0 1 2 | |
33 675041 675039 80385 3546 865 0 0 1 2 | |
34 675075 675072 80408 3547 864 0 0 1 2 | |
32 675107 675105 80430 3548 863 0 0 1 2 | |
35 675142 675139 80453 3549 862 0 0 1 2 | |
32 675174 675172 80476 3550 861 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
35 675209 675206 80498 3551 860 0 0 1 2 | |
35 675244 675242 80521 3552 859 0 0 1 2 | |
35 675279 675277 80544 3553 858 0 0 1 2 | |
34 675313 675310 80566 3554 857 0 0 1 2 | |
33 675346 675343 80589 3555 856 0 0 1 2 | |
55 675401 675377 80612 3556 855 0 0 1 2 | |
39 675440 675438 80634 3557 854 0 0 1 2 | |
34 675474 675472 80657 3558 853 0 0 1 2 | |
36 675510 675508 80680 3559 852 0 0 1 2 | |
35 675545 675542 80702 3560 851 0 0 1 2 | |
34 675579 675576 80725 3561 850 0 0 1 2 | |
33 675612 675609 80748 3562 849 0 0 1 2 | |
74 675686 675683 80770 3563 848 0 0 1 2 | |
40 675726 675723 80793 3564 847 0 0 1 2 | |
36 675762 675760 80816 3565 846 0 0 1 2 | |
34 675796 675794 80839 3566 845 0 0 1 2 | |
34 675830 675827 80861 3567 844 0 0 1 2 | |
33 675863 675861 80884 3568 843 0 0 1 2 | |
36 675899 675896 80907 3569 842 0 0 1 2 | |
33 675932 675930 80929 3570 841 0 0 1 2 | |
33 675965 675963 80952 3571 840 0 0 1 2 | |
34 675999 675996 80975 3572 839 0 0 1 2 | |
35 676034 676031 80997 3573 838 0 0 1 2 | |
33 676067 676065 81020 3574 837 0 0 1 2 | |
34 676101 676098 81043 3575 836 0 0 1 2 | |
35 676136 676133 81065 3576 835 0 0 1 2 | |
33 676169 676166 81088 3577 834 0 0 1 2 | |
32 676201 676199 81111 3578 833 0 0 1 2 | |
33 676234 676232 81133 3579 832 0 0 1 2 | |
35 676269 676267 81156 3580 831 0 0 1 2 | |
33 676302 676300 81179 3581 830 0 0 1 2 | |
33 676335 676333 81201 3582 829 0 0 1 2 | |
33 676368 676365 81224 3583 828 0 0 1 2 | |
57 676425 676422 81247 3584 827 0 0 1 2 | |
37 676462 676459 81269 3585 826 0 0 1 2 | |
34 676496 676494 81292 3586 825 0 0 1 2 | |
36 676532 676530 81315 3587 824 0 0 1 2 | |
34 676566 676563 81337 3588 823 0 0 1 2 | |
56 676622 676619 81360 3589 822 0 0 1 2 | |
89 676711 676707 81383 3590 821 0 0 1 2 | |
39 676750 676747 81405 3591 820 0 0 1 2 | |
38 676788 676785 81428 3592 819 0 0 1 2 | |
33 676821 676819 81451 3593 818 0 0 1 2 | |
32 676853 676851 81473 3594 817 0 0 1 2 | |
35 676888 676885 81496 3595 816 0 0 1 2 | |
34 676922 676919 81519 3596 815 0 0 1 2 | |
33 676955 676953 81541 3597 814 0 0 1 2 | |
33 676988 676986 81564 3598 813 0 0 1 2 | |
35 677023 677020 81587 3599 812 0 0 1 2 | |
33 677056 677054 81609 3600 811 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
32 677088 677086 81632 3601 810 0 0 1 2 | |
36 677124 677121 81655 3602 809 0 0 1 2 | |
35 677159 677157 81678 3603 808 0 0 1 2 | |
33 677192 677190 81700 3604 807 0 0 1 2 | |
33 677225 677223 81723 3605 806 0 0 1 2 | |
34 677259 677256 81746 3606 805 0 0 1 2 | |
33 677292 677290 81768 3607 804 0 0 1 2 | |
32 677324 677322 81791 3608 803 0 0 1 2 | |
33 677357 677355 81814 3609 802 0 0 1 2 | |
57 677414 677411 81836 3610 801 0 0 1 2 | |
39 677453 677450 81859 3611 800 0 0 1 2 | |
34 677487 677485 81882 3612 799 0 0 1 2 | |
37 677524 677521 81904 3613 798 0 0 1 2 | |
33 677557 677555 81927 3614 797 0 0 1 2 | |
33 677590 677588 81950 3615 796 0 0 1 2 | |
33 677623 677620 81972 3616 795 0 0 1 2 | |
79 677702 677699 81995 3617 794 0 0 1 2 | |
38 677740 677738 82018 3618 793 0 0 1 2 | |
37 677777 677774 82040 3619 792 0 0 1 2 | |
33 677810 677808 82063 3620 791 0 0 1 2 | |
33 677843 677841 82086 3621 790 0 0 1 2 | |
32 677875 677873 82108 3622 789 0 0 1 2 | |
35 677910 677907 82131 3623 788 0 0 1 2 | |
33 677943 677941 82154 3624 787 0 0 1 2 | |
33 677976 677974 82176 3625 786 0 0 1 2 | |
34 678010 678008 82199 3626 785 0 0 1 2 | |
33 678043 678041 82222 3627 784 0 0 1 2 | |
33 678076 678074 82244 3628 783 0 0 1 2 | |
32 678108 678106 82267 3629 782 0 0 1 2 | |
35 678143 678141 82290 3630 781 0 0 1 2 | |
33 678176 678174 82312 3631 780 0 0 1 2 | |
33 678209 678207 82335 3632 779 0 0 1 2 | |
33 678242 678240 82358 3633 778 0 0 1 2 | |
34 678276 678274 82380 3634 777 0 0 1 2 | |
33 678309 678307 82403 3635 776 0 0 1 2 | |
34 678343 678340 82426 3636 775 0 0 1 2 | |
32 678375 678373 82448 3637 774 0 0 1 2 | |
62 678437 678433 82471 3638 773 0 0 1 2 | |
36 678473 678470 82494 3639 772 0 0 1 2 | |
36 678509 678507 82517 3640 771 0 0 1 2 | |
34 678543 678540 82539 3641 770 0 0 1 2 | |
34 678577 678574 82562 3642 769 0 0 1 2 | |
32 678609 678607 82585 3643 768 0 0 1 2 | |
73 678682 678679 82607 3644 767 0 0 1 2 | |
41 678723 678721 82630 3645 766 0 0 1 2 | |
36 678759 678757 82653 3646 765 0 0 1 2 | |
34 678793 678790 82675 3647 764 0 0 1 2 | |
33 678826 678823 82698 3648 763 0 0 1 2 | |
32 678858 678856 82721 3649 762 0 0 1 2 | |
33 678891 678889 82743 3650 761 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 678924 678921 82766 3651 760 0 0 1 2 | |
35 678959 678956 82789 3652 759 0 0 1 2 | |
32 678991 678989 82811 3653 758 0 0 1 2 | |
35 679026 679024 82834 3654 757 0 0 1 2 | |
33 679059 679057 82857 3655 756 0 0 1 2 | |
33 679092 679090 82879 3656 755 0 0 1 2 | |
32 679124 679122 82902 3657 754 0 0 1 2 | |
34 679158 679156 82925 3658 753 0 0 1 2 | |
33 679191 679189 82947 3659 752 0 0 1 2 | |
33 679224 679222 82970 3660 751 0 0 1 2 | |
34 679258 679256 82993 3661 750 0 0 1 2 | |
33 679291 679289 83015 3662 749 0 0 1 2 | |
33 679324 679322 83038 3663 748 0 0 1 2 | |
32 679356 679354 83061 3664 747 0 0 1 2 | |
54 679410 679408 83083 3665 746 0 0 1 2 | |
38 679448 679446 83106 3666 745 0 0 1 2 | |
35 679483 679481 83129 3667 744 0 0 1 2 | |
35 679518 679516 83151 3668 743 0 0 1 2 | |
34 679552 679550 83174 3669 742 0 0 1 2 | |
34 679586 679583 83197 3670 741 0 0 1 2 | |
32 679618 679616 83219 3671 740 0 0 1 2 | |
77 679695 679691 83242 3672 739 0 0 1 2 | |
38 679733 679730 83265 3673 738 0 0 1 2 | |
36 679769 679766 83287 3674 737 0 0 1 2 | |
34 679803 679800 83310 3675 736 0 0 1 2 | |
32 679835 679833 83333 3676 735 0 0 1 2 | |
34 679869 679866 83356 3677 734 0 0 1 2 | |
34 679903 679901 83378 3678 733 0 0 1 2 | |
34 679937 679934 83401 3679 732 0 0 1 2 | |
33 679970 679967 83424 3680 731 0 0 1 2 | |
32 680002 680000 83446 3681 730 0 0 1 2 | |
35 680037 680035 83469 3682 729 0 0 1 2 | |
33 680070 680068 83492 3683 728 0 0 1 2 | |
33 680103 680101 83514 3684 727 0 0 1 2 | |
35 680138 680135 83537 3685 726 0 0 1 2 | |
33 680171 680169 83560 3686 725 0 0 1 2 | |
33 680204 680202 83582 3687 724 0 0 1 2 | |
33 680237 680234 83605 3688 723 0 0 1 2 | |
57 680294 680291 83628 3689 722 0 0 1 2 | |
36 680330 680327 83650 3690 721 0 0 1 2 | |
34 680364 680361 83673 3691 720 0 0 1 2 | |
64 680428 680425 83696 3692 719 0 0 1 2 | |
37 680465 680462 83718 3693 718 0 0 1 2 | |
34 680499 680497 83741 3694 717 0 0 1 2 | |
59 680558 680555 83764 3695 716 0 0 1 2 | |
36 680594 680592 83786 3696 715 0 0 1 2 | |
34 680628 680625 83809 3697 714 0 0 1 2 | |
82 680710 680706 83832 3698 713 0 0 1 2 | |
37 680747 680745 83854 3699 712 0 0 1 2 | |
95 680842 680839 83877 3700 711 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
45 680887 680884 83900 3701 710 0 0 1 2 | |
39 680926 680924 83922 3702 709 0 0 1 2 | |
34 680960 680957 83945 3703 708 0 0 1 2 | |
33 680993 680991 83968 3704 707 0 0 1 2 | |
36 681029 681026 83990 3705 706 0 0 1 2 | |
32 681061 681059 84013 3706 705 0 0 1 2 | |
33 681094 681092 84036 3707 704 0 0 1 2 | |
32 681126 681124 84058 3708 703 0 0 1 2 | |
35 681161 681158 84081 3709 702 0 0 1 2 | |
33 681194 681192 84104 3710 701 0 0 1 2 | |
32 681226 681224 84126 3711 700 0 0 1 2 | |
35 681261 681258 84149 3712 699 0 0 1 2 | |
32 681293 681291 84172 3713 698 0 0 1 2 | |
33 681326 681324 84195 3714 697 0 0 1 2 | |
33 681359 681357 84217 3715 696 0 0 1 2 | |
60 681419 681416 84240 3716 695 0 0 1 2 | |
38 681457 681455 84263 3717 694 0 0 1 2 | |
34 681491 681489 84285 3718 693 0 0 1 2 | |
37 681528 681525 84308 3719 692 0 0 1 2 | |
33 681561 681559 84331 3720 691 0 0 1 2 | |
32 681593 681591 84353 3721 690 0 0 1 2 | |
33 681626 681623 84376 3722 689 0 0 1 2 | |
85 681711 681707 84399 3723 688 0 0 1 2 | |
39 681750 681747 84421 3724 687 0 0 1 2 | |
35 681785 681783 84444 3725 686 0 0 1 2 | |
35 681820 681817 84467 3726 685 0 0 1 2 | |
32 681852 681850 84489 3727 684 0 0 1 2 | |
34 681886 681884 84512 3728 683 0 0 1 2 | |
34 681920 681918 84535 3729 682 0 0 1 2 | |
33 681953 681951 84557 3730 681 0 0 1 2 | |
33 681986 681984 84580 3731 680 0 0 1 2 | |
35 682021 682019 84603 3732 679 0 0 1 2 | |
33 682054 682052 84625 3733 678 0 0 1 2 | |
33 682087 682084 84648 3734 677 0 0 1 2 | |
32 682119 682116 84671 3735 676 0 0 1 2 | |
34 682153 682150 84693 3736 675 0 0 1 2 | |
33 682186 682183 84716 3737 674 0 0 1 2 | |
32 682218 682216 84739 3738 673 0 0 1 2 | |
32 682250 682248 84761 3739 672 0 0 1 2 | |
34 682284 682282 84784 3740 671 0 0 1 2 | |
33 682317 682315 84807 3741 670 0 0 1 2 | |
33 682350 682348 84829 3742 669 0 0 1 2 | |
55 682405 682402 84852 3743 668 0 0 1 2 | |
40 682445 682443 84875 3744 667 0 0 1 2 | |
36 682481 682478 84897 3745 666 0 0 1 2 | |
35 682516 682514 84920 3746 665 0 0 1 2 | |
33 682549 682547 84943 3747 664 0 0 1 2 | |
34 682583 682580 84965 3748 663 0 0 1 2 | |
32 682615 682613 84988 3749 662 0 0 1 2 | |
77 682692 682688 85011 3750 661 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 682731 682729 85034 3751 660 0 0 1 2 | |
39 682770 682768 85056 3752 659 0 0 1 2 | |
35 682805 682803 85079 3753 658 0 0 1 2 | |
34 682839 682836 85102 3754 657 0 0 1 2 | |
32 682871 682869 85124 3755 656 0 0 1 2 | |
34 682905 682903 85147 3756 655 0 0 1 2 | |
34 682939 682936 85170 3757 654 0 0 1 2 | |
33 682972 682970 85192 3758 653 0 0 1 2 | |
34 683006 683003 85215 3759 652 0 0 1 2 | |
34 683040 683037 85238 3760 651 0 0 1 2 | |
33 683073 683071 85260 3761 650 0 0 1 2 | |
33 683106 683103 85283 3762 649 0 0 1 2 | |
34 683140 683137 85306 3763 648 0 0 1 2 | |
33 683173 683171 85328 3764 647 0 0 1 2 | |
33 683206 683204 85351 3765 646 0 0 1 2 | |
33 683239 683237 85374 3766 645 0 0 1 2 | |
35 683274 683272 85396 3767 644 0 0 1 2 | |
33 683307 683305 85419 3768 643 0 0 1 2 | |
33 683340 683338 85442 3769 642 0 0 1 2 | |
33 683373 683370 85464 3770 641 0 0 1 2 | |
59 683432 683429 85487 3771 640 0 0 1 2 | |
38 683470 683467 85510 3772 639 0 0 1 2 | |
37 683507 683502 85532 3773 638 0 0 1 2 | |
34 683541 683538 85555 3774 637 0 0 1 2 | |
33 683574 683571 85578 3775 636 0 0 1 2 | |
33 683607 683604 85600 3776 635 0 0 1 2 | |
72 683679 683675 85623 3777 634 0 0 1 2 | |
41 683720 683717 85646 3778 633 0 0 1 2 | |
38 683758 683755 85668 3779 632 0 0 1 2 | |
35 683793 683790 85691 3780 631 0 0 1 2 | |
34 683827 683824 85714 3781 630 0 0 1 2 | |
33 683860 683858 85736 3782 629 0 0 1 2 | |
35 683895 683892 85759 3783 628 0 0 1 2 | |
33 683928 683926 85782 3784 627 0 0 1 2 | |
33 683961 683958 85804 3785 626 0 0 1 2 | |
31 683992 683990 85827 3786 625 0 0 1 2 | |
35 684027 684025 85850 3787 624 0 0 1 2 | |
64 684091 684089 85873 3788 623 0 0 1 2 | |
37 684128 684126 85895 3789 622 0 0 1 2 | |
37 684165 684163 85918 3790 621 0 0 1 2 | |
34 684199 684196 85941 3791 620 0 0 1 2 | |
33 684232 684229 85963 3792 619 0 0 1 2 | |
34 684266 684264 85986 3793 618 0 0 1 2 | |
34 684300 684297 86009 3794 617 0 0 1 2 | |
33 684333 684330 86031 3795 616 0 0 1 2 | |
32 684365 684363 86054 3796 615 0 0 1 2 | |
62 684427 684424 86077 3797 614 0 0 1 2 | |
39 684466 684463 86099 3798 613 0 0 1 2 | |
34 684500 684498 86122 3799 612 0 0 1 2 | |
37 684537 684534 86145 3800 611 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 684570 684568 86167 3801 610 0 0 1 2 | |
36 684606 684604 86190 3802 609 0 0 1 2 | |
76 684682 684679 86213 3803 608 0 0 1 2 | |
42 684724 684722 86235 3804 607 0 0 1 2 | |
38 684762 684760 86258 3805 606 0 0 1 2 | |
34 684796 684794 86281 3806 605 0 0 1 2 | |
33 684829 684827 86303 3807 604 0 0 1 2 | |
33 684862 684860 86326 3808 603 0 0 1 2 | |
36 684898 684895 86349 3809 602 0 0 1 2 | |
33 684931 684929 86371 3810 601 0 0 1 2 | |
33 684964 684962 86394 3811 600 0 0 1 2 | |
33 684997 684994 86417 3812 599 0 0 1 2 | |
34 685031 685028 86439 3813 598 0 0 1 2 | |
33 685064 685062 86462 3814 597 0 0 1 2 | |
34 685098 685095 86485 3815 596 0 0 1 2 | |
33 685131 685128 86507 3816 595 0 0 1 2 | |
34 685165 685162 86530 3817 594 0 0 1 2 | |
32 685197 685195 86553 3818 593 0 0 1 2 | |
33 685230 685228 86575 3819 592 0 0 1 2 | |
34 685264 685261 86598 3820 591 0 0 1 2 | |
33 685297 685295 86621 3821 590 0 0 1 2 | |
33 685330 685328 86643 3822 589 0 0 1 2 | |
32 685362 685360 86666 3823 588 0 0 1 2 | |
74 685436 685433 86689 3824 587 0 0 1 2 | |
39 685475 685473 86712 3825 586 0 0 1 2 | |
38 685513 685510 86734 3826 585 0 0 1 2 | |
35 685548 685545 86757 3827 584 0 0 1 2 | |
33 685581 685579 86780 3828 583 0 0 1 2 | |
33 685614 685612 86802 3829 582 0 0 1 2 | |
80 685694 685690 86825 3830 581 0 0 1 2 | |
39 685733 685730 86848 3831 580 0 0 1 2 | |
36 685769 685767 86870 3832 579 0 0 1 2 | |
35 685804 685801 86893 3833 578 0 0 1 2 | |
33 685837 685835 86916 3834 577 0 0 1 2 | |
33 685870 685868 86938 3835 576 0 0 1 2 | |
34 685904 685902 86961 3836 575 0 0 1 2 | |
33 685937 685935 86984 3837 574 0 0 1 2 | |
32 685969 685967 87006 3838 573 0 0 1 2 | |
33 686002 686000 87029 3839 572 0 0 1 2 | |
35 686037 686034 87052 3840 571 0 0 1 2 | |
33 686070 686067 87074 3841 570 0 0 1 2 | |
33 686103 686100 87097 3842 569 0 0 1 2 | |
33 686136 686134 87120 3843 568 0 0 1 2 | |
33 686169 686167 87142 3844 567 0 0 1 2 | |
33 686202 686199 87165 3845 566 0 0 1 2 | |
32 686234 686232 87188 3846 565 0 0 1 2 | |
34 686268 686266 87210 3847 564 0 0 1 2 | |
34 686302 686300 87233 3848 563 0 0 1 2 | |
32 686334 686332 87256 3849 562 0 0 1 2 | |
33 686367 686365 87278 3850 561 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
59 686426 686423 87301 3851 560 0 0 1 2 | |
41 686467 686464 87324 3852 559 0 0 1 2 | |
35 686502 686499 87346 3853 558 0 0 1 2 | |
36 686538 686535 87369 3854 557 0 0 1 2 | |
33 686571 686569 87392 3855 556 0 0 1 2 | |
33 686604 686602 87414 3856 555 0 0 1 2 | |
74 686678 686674 87437 3857 554 0 0 1 2 | |
42 686720 686717 87460 3858 553 0 0 1 2 | |
37 686757 686753 87482 3859 552 0 0 1 2 | |
35 686792 686790 87505 3860 551 0 0 1 2 | |
34 686826 686824 87528 3861 550 0 0 1 2 | |
34 686860 686858 87551 3862 549 0 0 1 2 | |
35 686895 686893 87573 3863 548 0 0 1 2 | |
34 686929 686926 87596 3864 547 0 0 1 2 | |
33 686962 686960 87619 3865 546 0 0 1 2 | |
33 686995 686992 87641 3866 545 0 0 1 2 | |
34 687029 687026 87664 3867 544 0 0 1 2 | |
33 687062 687060 87687 3868 543 0 0 1 2 | |
33 687095 687093 87709 3869 542 0 0 1 2 | |
33 687128 687126 87732 3870 541 0 0 1 2 | |
35 687163 687160 87755 3871 540 0 0 1 2 | |
33 687196 687194 87777 3872 539 0 0 1 2 | |
33 687229 687227 87800 3873 538 0 0 1 2 | |
33 687262 687260 87823 3874 537 0 0 1 2 | |
33 687295 687293 87845 3875 536 0 0 1 2 | |
33 687328 687326 87868 3876 535 0 0 1 2 | |
33 687361 687359 87891 3877 534 0 0 1 2 | |
57 687418 687415 87913 3878 533 0 0 1 2 | |
39 687457 687454 87936 3879 532 0 0 1 2 | |
35 687492 687489 87959 3880 531 0 0 1 2 | |
36 687528 687526 87981 3881 530 0 0 1 2 | |
34 687562 687560 88004 3882 529 0 0 1 2 | |
34 687596 687594 88027 3883 528 0 0 1 2 | |
35 687631 687627 88049 3884 527 0 0 1 2 | |
77 687708 687705 88072 3885 526 0 0 1 2 | |
36 687744 687742 88095 3886 525 0 0 1 2 | |
61 687805 687802 88117 3887 524 0 0 1 2 | |
38 687843 687841 88140 3888 523 0 0 1 2 | |
35 687878 687876 88163 3889 522 0 0 1 2 | |
35 687913 687911 88185 3890 521 0 0 1 2 | |
34 687947 687944 88208 3891 520 0 0 1 2 | |
33 687980 687978 88231 3892 519 0 0 1 2 | |
34 688014 688012 88253 3893 518 0 0 1 2 | |
34 688048 688045 88276 3894 517 0 0 1 2 | |
34 688082 688080 88299 3895 516 0 0 1 2 | |
34 688116 688113 88321 3896 515 0 0 1 2 | |
35 688151 688149 88344 3897 514 0 0 1 2 | |
33 688184 688182 88367 3898 513 0 0 1 2 | |
33 688217 688215 88390 3899 512 0 0 1 2 | |
34 688251 688248 88412 3900 511 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
34 688285 688282 88435 3901 510 0 0 1 2 | |
36 688321 688319 88458 3902 509 0 0 1 2 | |
34 688355 688352 88480 3903 508 0 0 1 2 | |
62 688417 688414 88503 3904 507 0 0 1 2 | |
40 688457 688454 88526 3905 506 0 0 1 2 | |
34 688491 688488 88548 3906 505 0 0 1 2 | |
57 688548 688545 88571 3907 504 0 0 1 2 | |
37 688585 688582 88594 3908 503 0 0 1 2 | |
35 688620 688618 88616 3909 502 0 0 1 2 | |
81 688701 688697 88639 3910 501 0 0 1 2 | |
38 688739 688737 88662 3911 500 0 0 1 2 | |
37 688776 688774 88684 3912 499 0 0 1 2 | |
34 688810 688808 88707 3913 498 0 0 1 2 | |
34 688844 688841 88730 3914 497 0 0 1 2 | |
33 688877 688874 88752 3915 496 0 0 1 2 | |
34 688911 688909 88775 3916 495 0 0 1 2 | |
33 688944 688942 88798 3917 494 0 0 1 2 | |
33 688977 688975 88820 3918 493 0 0 1 2 | |
34 689011 689008 88843 3919 492 0 0 1 2 | |
33 689044 689041 88866 3920 491 0 0 1 2 | |
33 689077 689075 88888 3921 490 0 0 1 2 | |
32 689109 689107 88911 3922 489 0 0 1 2 | |
35 689144 689141 88934 3923 488 0 0 1 2 | |
33 689177 689174 88956 3924 487 0 0 1 2 | |
33 689210 689207 88979 3925 486 0 0 1 2 | |
33 689243 689241 89002 3926 485 0 0 1 2 | |
35 689278 689275 89024 3927 484 0 0 1 2 | |
32 689310 689308 89047 3928 483 0 0 1 2 | |
33 689343 689341 89070 3929 482 0 0 1 2 | |
32 689375 689373 89092 3930 481 0 0 1 2 | |
60 689435 689432 89115 3931 480 0 0 1 2 | |
38 689473 689470 89138 3932 479 0 0 1 2 | |
35 689508 689504 89160 3933 478 0 0 1 2 | |
35 689543 689540 89183 3934 477 0 0 1 2 | |
33 689576 689574 89206 3935 476 0 0 1 2 | |
33 689609 689607 89229 3936 475 0 0 1 2 | |
72 689681 689678 89251 3937 474 0 0 1 2 | |
41 689722 689720 89274 3938 473 0 0 1 2 | |
37 689759 689756 89297 3939 472 0 0 1 2 | |
35 689794 689791 89319 3940 471 0 0 1 2 | |
33 689827 689824 89342 3941 470 0 0 1 2 | |
33 689860 689857 89365 3942 469 0 0 1 2 | |
34 689894 689892 89387 3943 468 0 0 1 2 | |
34 689928 689925 89410 3944 467 0 0 1 2 | |
33 689961 689958 89433 3945 466 0 0 1 2 | |
32 689993 689991 89455 3946 465 0 0 1 2 | |
36 690029 690027 89478 3947 464 0 0 1 2 | |
33 690062 690060 89501 3948 463 0 0 1 2 | |
34 690096 690094 89523 3949 462 0 0 1 2 | |
33 690129 690126 89546 3950 461 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 690162 690160 89569 3951 460 0 0 1 2 | |
36 690198 690195 89591 3952 459 0 0 1 2 | |
34 690232 690229 89614 3953 458 0 0 1 2 | |
35 690267 690264 89637 3954 457 0 0 1 2 | |
33 690300 690297 89659 3955 456 0 0 1 2 | |
33 690333 690330 89682 3956 455 0 0 1 2 | |
32 690365 690363 89705 3957 454 0 0 1 2 | |
59 690424 690422 89727 3958 453 0 0 1 2 | |
38 690462 690459 89750 3959 452 0 0 1 2 | |
34 690496 690494 89773 3960 451 0 0 1 2 | |
35 690531 690529 89795 3961 450 0 0 1 2 | |
34 690565 690563 89818 3962 449 0 0 1 2 | |
32 690597 690595 89841 3963 448 0 0 1 2 | |
36 690633 690629 89863 3964 447 0 0 1 2 | |
76 690709 690706 89886 3965 446 0 0 1 2 | |
36 690745 690743 89909 3966 445 0 0 1 2 | |
72 690817 690814 89931 3967 444 0 0 1 2 | |
42 690859 690857 89954 3968 443 0 0 1 2 | |
37 690896 690894 89977 3969 442 0 0 1 2 | |
35 690931 690928 90000 3970 441 0 0 1 2 | |
34 690965 690962 90022 3971 440 0 0 1 2 | |
33 690998 690996 90045 3972 439 0 0 1 2 | |
34 691032 691030 90068 3973 438 0 0 1 2 | |
33 691065 691063 90090 3974 437 0 0 1 2 | |
33 691098 691096 90113 3975 436 0 0 1 2 | |
34 691132 691129 90136 3976 435 0 0 1 2 | |
34 691166 691163 90158 3977 434 0 0 1 2 | |
32 691198 691195 90181 3978 433 0 0 1 2 | |
33 691231 691228 90204 3979 432 0 0 1 2 | |
33 691264 691262 90226 3980 431 0 0 1 2 | |
34 691298 691296 90249 3981 430 0 0 1 2 | |
33 691331 691329 90272 3982 429 0 0 1 2 | |
32 691363 691361 90294 3983 428 0 0 1 2 | |
58 691421 691418 90317 3984 427 0 0 1 2 | |
38 691459 691457 90340 3985 426 0 0 1 2 | |
65 691524 691522 90362 3986 425 0 0 1 2 | |
39 691563 691561 90385 3987 424 0 0 1 2 | |
35 691598 691595 90408 3988 423 0 0 1 2 | |
34 691632 691628 90430 3989 422 0 0 1 2 | |
86 691718 691715 90453 3990 421 0 0 1 2 | |
39 691757 691753 90476 3991 420 0 0 1 2 | |
35 691792 691789 90498 3992 419 0 0 1 2 | |
33 691825 691823 90521 3993 418 0 0 1 2 | |
33 691858 691855 90544 3994 417 0 0 1 2 | |
33 691891 691889 90566 3995 416 0 0 1 2 | |
34 691925 691923 90589 3996 415 0 0 1 2 | |
33 691958 691956 90612 3997 414 0 0 1 2 | |
33 691991 691989 90634 3998 413 0 0 1 2 | |
35 692026 692024 90657 3999 412 0 0 1 2 | |
34 692060 692057 90680 4000 411 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
32 692092 692090 90702 4001 410 0 0 1 2 | |
36 692128 692126 90725 4002 409 0 0 1 2 | |
35 692163 692161 90748 4003 408 0 0 1 2 | |
33 692196 692193 90770 4004 407 0 0 1 2 | |
32 692228 692226 90793 4005 406 0 0 1 2 | |
34 692262 692260 90816 4006 405 0 0 1 2 | |
33 692295 692293 90839 4007 404 0 0 1 2 | |
33 692328 692326 90861 4008 403 0 0 1 2 | |
33 692361 692359 90884 4009 402 0 0 1 2 | |
58 692419 692416 90907 4010 401 0 0 1 2 | |
38 692457 692454 90929 4011 400 0 0 1 2 | |
35 692492 692490 90952 4012 399 0 0 1 2 | |
37 692529 692526 90975 4013 398 0 0 1 2 | |
33 692562 692559 90997 4014 397 0 0 1 2 | |
32 692594 692592 91020 4015 396 0 0 1 2 | |
32 692626 692624 91043 4016 395 0 0 1 2 | |
78 692704 692700 91065 4017 394 0 0 1 2 | |
38 692742 692739 91088 4018 393 0 0 1 2 | |
36 692778 692776 91111 4019 392 0 0 1 2 | |
35 692813 692810 91133 4020 391 0 0 1 2 | |
33 692846 692844 91156 4021 390 0 0 1 2 | |
34 692880 692877 91179 4022 389 0 0 1 2 | |
35 692915 692912 91201 4023 388 0 0 1 2 | |
32 692947 692945 91224 4024 387 0 0 1 2 | |
33 692980 692978 91247 4025 386 0 0 1 2 | |
34 693014 693011 91269 4026 385 0 0 1 2 | |
32 693046 693044 91292 4027 384 0 0 1 2 | |
33 693079 693077 91315 4028 383 0 0 1 2 | |
33 693112 693110 91337 4029 382 0 0 1 2 | |
34 693146 693144 91360 4030 381 0 0 1 2 | |
33 693179 693177 91383 4031 380 0 0 1 2 | |
33 693212 693209 91405 4032 379 0 0 1 2 | |
32 693244 693242 91428 4033 378 0 0 1 2 | |
34 693278 693276 91451 4034 377 0 0 1 2 | |
34 693312 693309 91473 4035 376 0 0 1 2 | |
32 693344 693342 91496 4036 375 0 0 1 2 | |
33 693377 693375 91519 4037 374 0 0 1 2 | |
59 693436 693434 91541 4038 373 0 0 1 2 | |
37 693473 693471 91564 4039 372 0 0 1 2 | |
36 693509 693504 91587 4040 371 0 0 1 2 | |
34 693543 693540 91609 4041 370 0 0 1 2 | |
33 693576 693573 91632 4042 369 0 0 1 2 | |
32 693608 693606 91655 4043 368 0 0 1 2 | |
73 693681 693677 91678 4044 367 0 0 1 2 | |
41 693722 693719 91700 4045 366 0 0 1 2 | |
38 693760 693757 91723 4046 365 0 0 1 2 | |
35 693795 693792 91746 4047 364 0 0 1 2 | |
33 693828 693826 91768 4048 363 0 0 1 2 | |
34 693862 693859 91791 4049 362 0 0 1 2 | |
34 693896 693893 91814 4050 361 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 693929 693926 91836 4051 360 0 0 1 2 | |
35 693964 693962 91859 4052 359 0 0 1 2 | |
33 693997 693994 91882 4053 358 0 0 1 2 | |
34 694031 694029 91904 4054 357 0 0 1 2 | |
33 694064 694062 91927 4055 356 0 0 1 2 | |
32 694096 694094 91950 4056 355 0 0 1 2 | |
33 694129 694127 91972 4057 354 0 0 1 2 | |
35 694164 694161 91995 4058 353 0 0 1 2 | |
34 694198 694195 92018 4059 352 0 0 1 2 | |
32 694230 694228 92040 4060 351 0 0 1 2 | |
34 694264 694262 92063 4061 350 0 0 1 2 | |
34 694298 694296 92086 4062 349 0 0 1 2 | |
32 694330 694328 92108 4063 348 0 0 1 2 | |
34 694364 694362 92131 4064 347 0 0 1 2 | |
57 694421 694418 92154 4065 346 0 0 1 2 | |
38 694459 694457 92176 4066 345 0 0 1 2 | |
35 694494 694492 92199 4067 344 0 0 1 2 | |
36 694530 694528 92222 4068 343 0 0 1 2 | |
34 694564 694562 92244 4069 342 0 0 1 2 | |
33 694597 694595 92267 4070 341 0 0 1 2 | |
33 694630 694627 92290 4071 340 0 0 1 2 | |
78 694708 694705 92312 4072 339 0 0 1 2 | |
39 694747 694744 92335 4073 338 0 0 1 2 | |
36 694783 694781 92358 4074 337 0 0 1 2 | |
33 694816 694814 92380 4075 336 0 0 1 2 | |
33 694849 694847 92403 4076 335 0 0 1 2 | |
35 694884 694881 92426 4077 334 0 0 1 2 | |
34 694918 694915 92448 4078 333 0 0 1 2 | |
32 694950 694948 92471 4079 332 0 0 1 2 | |
33 694983 694981 92494 4080 331 0 0 1 2 | |
34 695017 695015 92517 4081 330 0 0 1 2 | |
33 695050 695048 92539 4082 329 0 0 1 2 | |
34 695084 695082 92562 4083 328 0 0 1 2 | |
32 695116 695114 92585 4084 327 0 0 1 2 | |
35 695151 695149 92607 4085 326 0 0 1 2 | |
58 695209 695206 92630 4086 325 0 0 1 2 | |
37 695246 695244 92653 4087 324 0 0 1 2 | |
39 695285 695282 92675 4088 323 0 0 1 2 | |
34 695319 695316 92698 4089 322 0 0 1 2 | |
33 695352 695349 92721 4090 321 0 0 1 2 | |
59 695411 695407 92743 4091 320 0 0 1 2 | |
39 695450 695447 92766 4092 319 0 0 1 2 | |
35 695485 695483 92789 4093 318 0 0 1 2 | |
37 695522 695520 92811 4094 317 0 0 1 2 | |
34 695556 695554 92834 4095 316 0 0 1 2 | |
33 695589 695587 92857 4096 315 0 0 1 2 | |
33 695622 695620 92879 4097 314 0 0 1 2 | |
79 695701 695698 92902 4098 313 0 0 1 2 | |
41 695742 695739 92925 4099 312 0 0 1 2 | |
37 695779 695777 92947 4100 311 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
35 695814 695811 92970 4101 310 0 0 1 2 | |
35 695849 695847 92993 4102 309 0 0 1 2 | |
35 695884 695882 93015 4103 308 0 0 1 2 | |
35 695919 695916 93038 4104 307 0 0 1 2 | |
33 695952 695950 93061 4105 306 0 0 1 2 | |
33 695985 695983 93083 4106 305 0 0 1 2 | |
35 696020 696017 93106 4107 304 0 0 1 2 | |
33 696053 696051 93129 4108 303 0 0 1 2 | |
33 696086 696084 93151 4109 302 0 0 1 2 | |
33 696119 696117 93174 4110 301 0 0 1 2 | |
35 696154 696151 93197 4111 300 0 0 1 2 | |
33 696187 696185 93219 4112 299 0 0 1 2 | |
33 696220 696218 93242 4113 298 0 0 1 2 | |
34 696254 696251 93265 4114 297 0 0 1 2 | |
34 696288 696286 93287 4115 296 0 0 1 2 | |
34 696322 696320 93310 4116 295 0 0 1 2 | |
33 696355 696352 93333 4117 294 0 0 1 2 | |
59 696414 696412 93356 4118 293 0 0 1 2 | |
41 696455 696452 93378 4119 292 0 0 1 2 | |
34 696489 696487 93401 4120 291 0 0 1 2 | |
59 696548 696545 93424 4121 290 0 0 1 2 | |
37 696585 696582 93446 4122 289 0 0 1 2 | |
35 696620 696617 93469 4123 288 0 0 1 2 | |
77 696697 696694 93492 4124 287 0 0 1 2 | |
39 696736 696734 93514 4125 286 0 0 1 2 | |
38 696774 696772 93537 4126 285 0 0 1 2 | |
35 696809 696807 93560 4127 284 0 0 1 2 | |
34 696843 696841 93582 4128 283 0 0 1 2 | |
33 696876 696874 93605 4129 282 0 0 1 2 | |
35 696911 696909 93628 4130 281 0 0 1 2 | |
34 696945 696942 93650 4131 280 0 0 1 2 | |
33 696978 696975 93673 4132 279 0 0 1 2 | |
35 697013 697010 93696 4133 278 0 0 1 2 | |
33 697046 697044 93718 4134 277 0 0 1 2 | |
34 697080 697077 93741 4135 276 0 0 1 2 | |
33 697113 697111 93764 4136 275 0 0 1 2 | |
35 697148 697145 93786 4137 274 0 0 1 2 | |
33 697181 697179 93809 4138 273 0 0 1 2 | |
34 697215 697212 93832 4139 272 0 0 1 2 | |
33 697248 697245 93854 4140 271 0 0 1 2 | |
33 697281 697279 93877 4141 270 0 0 1 2 | |
33 697314 697311 93900 4142 269 0 0 1 2 | |
33 697347 697345 93922 4143 268 0 0 1 2 | |
33 697380 697377 93945 4144 267 0 0 1 2 | |
59 697439 697436 93968 4145 266 0 0 1 2 | |
36 697475 697472 93990 4146 265 0 0 1 2 | |
35 697510 697508 94013 4147 264 0 0 1 2 | |
35 697545 697542 94036 4148 263 0 0 1 2 | |
34 697579 697576 94058 4149 262 0 0 1 2 | |
34 697613 697610 94081 4150 261 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
75 697688 697685 94104 4151 260 0 0 1 2 | |
44 697732 697729 94126 4152 259 0 0 1 2 | |
38 697770 697768 94149 4153 258 0 0 1 2 | |
35 697805 697802 94172 4154 257 0 0 1 2 | |
33 697838 697836 94195 4155 256 0 0 1 2 | |
32 697870 697868 94217 4156 255 0 0 1 2 | |
36 697906 697903 94240 4157 254 0 0 1 2 | |
33 697939 697937 94263 4158 253 0 0 1 2 | |
34 697973 697970 94285 4159 252 0 0 1 2 | |
34 698007 698003 94308 4160 251 0 0 1 2 | |
33 698040 698037 94331 4161 250 0 0 1 2 | |
33 698073 698071 94353 4162 249 0 0 1 2 | |
33 698106 698104 94376 4163 248 0 0 1 2 | |
35 698141 698138 94399 4164 247 0 0 1 2 | |
34 698175 698172 94421 4165 246 0 0 1 2 | |
33 698208 698205 94444 4166 245 0 0 1 2 | |
32 698240 698238 94467 4167 244 0 0 1 2 | |
35 698275 698273 94489 4168 243 0 0 1 2 | |
34 698309 698307 94512 4169 242 0 0 1 2 | |
34 698343 698340 94535 4170 241 0 0 1 2 | |
33 698376 698374 94557 4171 240 0 0 1 2 | |
59 698435 698432 94580 4172 239 0 0 1 2 | |
36 698471 698468 94603 4173 238 0 0 1 2 | |
35 698506 698503 94625 4174 237 0 0 1 2 | |
36 698542 698540 94648 4175 236 0 0 1 2 | |
34 698576 698573 94671 4176 235 0 0 1 2 | |
33 698609 698606 94693 4177 234 0 0 1 2 | |
74 698683 698680 94716 4178 233 0 0 1 2 | |
43 698726 698723 94739 4179 232 0 0 1 2 | |
38 698764 698761 94761 4180 231 0 0 1 2 | |
34 698798 698796 94784 4181 230 0 0 1 2 | |
34 698832 698829 94807 4182 229 0 0 1 2 | |
33 698865 698863 94829 4183 228 0 0 1 2 | |
35 698900 698898 94852 4184 227 0 0 1 2 | |
56 698956 698953 94875 4185 226 0 0 1 2 | |
38 698994 698992 94897 4186 225 0 0 1 2 | |
38 699032 699029 94920 4187 224 0 0 1 2 | |
34 699066 699064 94943 4188 223 0 0 1 2 | |
34 699100 699097 94965 4189 222 0 0 1 2 | |
34 699134 699130 94988 4190 221 0 0 1 2 | |
33 699167 699165 95011 4191 220 0 0 1 2 | |
33 699200 699197 95034 4192 219 0 0 1 2 | |
33 699233 699230 95056 4193 218 0 0 1 2 | |
34 699267 699264 95079 4194 217 0 0 1 2 | |
34 699301 699298 95102 4195 216 0 0 1 2 | |
33 699334 699332 95124 4196 215 0 0 1 2 | |
34 699368 699365 95147 4197 214 0 0 1 2 | |
59 699427 699424 95170 4198 213 0 0 1 2 | |
37 699464 699462 95192 4199 212 0 0 1 2 | |
34 699498 699496 95215 4200 211 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
36 699534 699532 95238 4201 210 0 0 1 2 | |
37 699571 699568 95260 4202 209 0 0 1 2 | |
33 699604 699602 95283 4203 208 0 0 1 2 | |
75 699679 699674 95306 4204 207 0 0 1 2 | |
42 699721 699718 95328 4205 206 0 0 1 2 | |
36 699757 699754 95351 4206 205 0 0 1 2 | |
35 699792 699789 95374 4207 204 0 0 1 2 | |
33 699825 699823 95396 4208 203 0 0 1 2 | |
33 699858 699855 95419 4209 202 0 0 1 2 | |
33 699891 699889 95442 4210 201 0 0 1 2 | |
33 699924 699921 95464 4211 200 0 0 1 2 | |
33 699957 699954 95487 4212 199 0 0 1 2 | |
32 699989 699987 95510 4213 198 0 0 1 2 | |
35 700024 700021 95532 4214 197 0 0 1 2 | |
33 700057 700055 95555 4215 196 0 0 1 2 | |
33 700090 700088 95578 4216 195 0 0 1 2 | |
33 700123 700121 95600 4217 194 0 0 1 2 | |
34 700157 700155 95623 4218 193 0 0 1 2 | |
34 700191 700189 95646 4219 192 0 0 1 2 | |
33 700224 700222 95668 4220 191 0 0 1 2 | |
34 700258 700255 95691 4221 190 0 0 1 2 | |
34 700292 700289 95714 4222 189 0 0 1 2 | |
32 700324 700322 95736 4223 188 0 0 1 2 | |
34 700358 700355 95759 4224 187 0 0 1 2 | |
55 700413 700410 95782 4225 186 0 0 1 2 | |
39 700452 700449 95804 4226 185 0 0 1 2 | |
35 700487 700485 95827 4227 184 0 0 1 2 | |
37 700524 700522 95850 4228 183 0 0 1 2 | |
34 700558 700556 95873 4229 182 0 0 1 2 | |
34 700592 700590 95895 4230 181 0 0 1 2 | |
33 700625 700622 95918 4231 180 0 0 1 2 | |
75 700700 700696 95941 4232 179 0 0 1 2 | |
38 700738 700735 95963 4233 178 0 0 1 2 | |
80 700818 700772 95986 4234 177 0 0 1 2 | |
45 700863 700860 96009 4235 176 0 0 1 2 | |
40 700903 700900 96031 4236 175 0 0 1 2 | |
34 700937 700935 96054 4237 174 0 0 1 2 | |
34 700971 700969 96077 4238 173 0 0 1 2 | |
32 701003 701001 96099 4239 172 0 0 1 2 | |
35 701038 701036 96122 4240 171 0 0 1 2 | |
34 701072 701070 96145 4241 170 0 0 1 2 | |
34 701106 701103 96167 4242 169 0 0 1 2 | |
34 701140 701137 96190 4243 168 0 0 1 2 | |
33 701173 701170 96213 4244 167 0 0 1 2 | |
32 701205 701203 96235 4245 166 0 0 1 2 | |
33 701238 701236 96258 4246 165 0 0 1 2 | |
35 701273 701271 96281 4247 164 0 0 1 2 | |
34 701307 701305 96303 4248 163 0 0 1 2 | |
33 701340 701338 96326 4249 162 0 0 1 2 | |
34 701374 701372 96349 4250 161 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
61 701435 701432 96371 4251 160 0 0 1 2 | |
40 701475 701472 96394 4252 159 0 0 1 2 | |
37 701512 701509 96417 4253 158 0 0 1 2 | |
35 701547 701544 96439 4254 157 0 0 1 2 | |
33 701580 701578 96462 4255 156 0 0 1 2 | |
33 701613 701611 96485 4256 155 0 0 1 2 | |
78 701691 701688 96507 4257 154 0 0 1 2 | |
41 701732 701730 96530 4258 153 0 0 1 2 | |
37 701769 701767 96553 4259 152 0 0 1 2 | |
35 701804 701802 96575 4260 151 0 0 1 2 | |
34 701838 701835 96598 4261 150 0 0 1 2 | |
33 701871 701869 96621 4262 149 0 0 1 2 | |
36 701907 701904 96643 4263 148 0 0 1 2 | |
33 701940 701938 96666 4264 147 0 0 1 2 | |
34 701974 701971 96689 4265 146 0 0 1 2 | |
34 702008 702004 96712 4266 145 0 0 1 2 | |
34 702042 702039 96734 4267 144 0 0 1 2 | |
33 702075 702072 96757 4268 143 0 0 1 2 | |
33 702108 702105 96780 4269 142 0 0 1 2 | |
34 702142 702139 96802 4270 141 0 0 1 2 | |
33 702175 702173 96825 4271 140 0 0 1 2 | |
33 702208 702205 96848 4272 139 0 0 1 2 | |
33 702241 702238 96870 4273 138 0 0 1 2 | |
34 702275 702273 96893 4274 137 0 0 1 2 | |
34 702309 702307 96916 4275 136 0 0 1 2 | |
33 702342 702339 96938 4276 135 0 0 1 2 | |
33 702375 702373 96961 4277 134 0 0 1 2 | |
60 702435 702433 96984 4278 133 0 0 1 2 | |
36 702471 702469 97006 4279 132 0 0 1 2 | |
37 702508 702504 97029 4280 131 0 0 1 2 | |
35 702543 702540 97052 4281 130 0 0 1 2 | |
34 702577 702574 97074 4282 129 0 0 1 2 | |
33 702610 702607 97097 4283 128 0 0 1 2 | |
105 702715 702711 97120 4284 127 0 0 1 2 | |
41 702756 702753 97142 4285 126 0 0 1 2 | |
38 702794 702791 97165 4286 125 0 0 1 2 | |
34 702828 702825 97188 4287 124 0 0 1 2 | |
34 702862 702859 97210 4288 123 0 0 1 2 | |
34 702896 702894 97233 4289 122 0 0 1 2 | |
33 702929 702927 97256 4290 121 0 0 1 2 | |
34 702963 702960 97278 4291 120 0 0 1 2 | |
33 702996 702994 97301 4292 119 0 0 1 2 | |
34 703030 703028 97324 4293 118 0 0 1 2 | |
35 703065 703062 97346 4294 117 0 0 1 2 | |
33 703098 703095 97369 4295 116 0 0 1 2 | |
33 703131 703129 97392 4296 115 0 0 1 2 | |
35 703166 703163 97414 4297 114 0 0 1 2 | |
33 703199 703197 97437 4298 113 0 0 1 2 | |
34 703233 703231 97460 4299 112 0 0 1 2 | |
34 703267 703265 97482 4300 111 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
33 703300 703298 97505 4301 110 0 0 1 2 | |
36 703336 703333 97528 4302 109 0 0 1 2 | |
33 703369 703367 97551 4303 108 0 0 1 2 | |
61 703430 703427 97573 4304 107 0 0 1 2 | |
37 703467 703465 97596 4305 106 0 0 1 2 | |
36 703503 703500 97619 4306 105 0 0 1 2 | |
36 703539 703537 97641 4307 104 0 0 1 2 | |
33 703572 703570 97664 4308 103 0 0 1 2 | |
33 703605 703603 97687 4309 102 0 0 1 2 | |
72 703677 703672 97709 4310 101 0 0 1 2 | |
44 703721 703719 97732 4311 100 0 0 1 2 | |
38 703759 703755 97755 4312 99 0 0 1 2 | |
34 703793 703791 97777 4313 98 0 0 1 2 | |
34 703827 703825 97800 4314 97 0 0 1 2 | |
33 703860 703858 97823 4315 96 0 0 1 2 | |
35 703895 703893 97845 4316 95 0 0 1 2 | |
34 703929 703926 97868 4317 94 0 0 1 2 | |
34 703963 703960 97891 4318 93 0 0 1 2 | |
33 703996 703993 97913 4319 92 0 0 1 2 | |
34 704030 704027 97936 4320 91 0 0 1 2 | |
34 704064 704061 97959 4321 90 0 0 1 2 | |
33 704097 704095 97981 4322 89 0 0 1 2 | |
33 704130 704128 98004 4323 88 0 0 1 2 | |
35 704165 704162 98027 4324 87 0 0 1 2 | |
33 704198 704195 98049 4325 86 0 0 1 2 | |
33 704231 704228 98072 4326 85 0 0 1 2 | |
34 704265 704262 98095 4327 84 0 0 1 2 | |
34 704299 704296 98117 4328 83 0 0 1 2 | |
33 704332 704329 98140 4329 82 0 0 1 2 | |
34 704366 704363 98163 4330 81 0 0 1 2 | |
61 704427 704424 98185 4331 80 0 0 1 2 | |
38 704465 704462 98208 4332 79 0 0 1 2 | |
35 704500 704497 98231 4333 78 0 0 1 2 | |
57 704557 704554 98253 4334 77 0 0 1 2 | |
37 704594 704591 98276 4335 76 0 0 1 2 | |
34 704628 704626 98299 4336 75 0 0 1 2 | |
76 704704 704701 98321 4337 74 0 0 1 2 | |
38 704742 704740 98344 4338 73 0 0 1 2 | |
38 704780 704777 98367 4339 72 0 0 1 2 | |
34 704814 704811 98390 4340 71 0 0 1 2 | |
33 704847 704845 98412 4341 70 0 0 1 2 | |
33 704880 704878 98435 4342 69 0 0 1 2 | |
35 704915 704913 98458 4343 68 0 0 1 2 | |
33 704948 704946 98480 4344 67 0 0 1 2 | |
33 704981 704978 98503 4345 66 0 0 1 2 | |
35 705016 705013 98526 4346 65 0 0 1 2 | |
33 705049 705047 98548 4347 64 0 0 1 2 | |
33 705082 705080 98571 4348 63 0 0 1 2 | |
33 705115 705112 98594 4349 62 0 0 1 2 | |
35 705150 705147 98616 4350 61 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
32 705182 705180 98639 4351 60 0 0 1 2 | |
37 705219 705216 98662 4352 59 0 0 1 2 | |
33 705252 705250 98684 4353 58 0 0 1 2 | |
36 705288 705285 98707 4354 57 0 0 1 2 | |
33 705321 705318 98730 4355 56 0 0 1 2 | |
33 705354 705352 98752 4356 55 0 0 1 2 | |
56 705410 705407 98775 4357 54 0 0 1 2 | |
38 705448 705445 98798 4358 53 0 0 1 2 | |
36 705484 705481 98820 4359 52 0 0 1 2 | |
36 705520 705518 98843 4360 51 0 0 1 2 | |
34 705554 705552 98866 4361 50 0 0 1 2 | |
33 705587 705585 98888 4362 49 0 0 1 2 | |
34 705621 705618 98911 4363 48 0 0 1 2 | |
76 705697 705694 98934 4364 47 0 0 1 2 | |
40 705737 705735 98956 4365 46 0 0 1 2 | |
38 705775 705772 98979 4366 45 0 0 1 2 | |
34 705809 705807 99002 4367 44 0 0 1 2 | |
34 705843 705840 99024 4368 43 0 0 1 2 | |
32 705875 705873 99047 4369 42 0 0 1 2 | |
35 705910 705907 99070 4370 41 0 0 1 2 | |
34 705944 705942 99092 4371 40 0 0 1 2 | |
34 705978 705975 99115 4372 39 0 0 1 2 | |
34 706012 706010 99138 4373 38 0 0 1 2 | |
33 706045 706043 99160 4374 37 0 0 1 2 | |
33 706078 706076 99183 4375 36 0 0 1 2 | |
33 706111 706109 99206 4376 35 0 0 1 2 | |
35 706146 706144 99229 4377 34 0 0 1 2 | |
34 706180 706177 99251 4378 33 0 0 1 2 | |
32 706212 706210 99274 4379 32 0 0 1 2 | |
33 706245 706243 99297 4380 31 0 0 1 2 | |
35 706280 706278 99319 4381 30 0 0 1 2 | |
33 706313 706310 99342 4382 29 0 0 1 2 | |
33 706346 706344 99365 4383 28 0 0 1 2 | |
34 706380 706378 99387 4384 27 0 0 1 2 | |
83 706463 706459 99410 4385 26 0 0 1 2 | |
37 706500 706497 99433 4386 25 0 0 1 2 | |
38 706538 706535 99455 4387 24 0 0 1 2 | |
34 706572 706570 99478 4388 23 0 0 1 2 | |
34 706606 706603 99501 4389 22 0 0 1 2 | |
76 706682 706678 99523 4390 21 0 0 1 2 | |
43 706725 706722 99546 4391 20 0 0 1 2 | |
37 706762 706759 99569 4392 19 0 0 1 2 | |
35 706797 706795 99591 4393 18 0 0 1 2 | |
33 706830 706828 99614 4394 17 0 0 1 2 | |
34 706864 706861 99637 4395 16 0 0 1 2 | |
35 706899 706896 99659 4396 15 0 0 1 2 | |
33 706932 706929 99682 4397 14 0 0 1 2 | |
33 706965 706963 99705 4398 13 0 0 1 2 | |
33 706998 706995 99727 4399 12 0 0 1 2 | |
34 707032 707030 99750 4400 11 0 0 1 2 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
35 707067 707064 99773 4401 10 0 0 1 2 | |
35 707102 707099 99795 4402 9 0 0 1 2 | |
35 707137 707135 99818 4403 8 0 0 1 2 | |
34 707171 707169 99841 4404 7 0 0 1 2 | |
34 707205 707202 99863 4405 6 0 0 1 2 | |
33 707238 707236 99886 4406 5 0 0 1 2 | |
35 707273 707271 99909 4407 4 0 0 1 2 | |
34 707307 707304 99931 4408 3 0 0 1 2 | |
32 707339 707337 99954 4409 2 0 0 1 2 | |
34 707373 707370 99977 4410 1 0 0 1 2 | |
73 707446 0 0 4410 0 4410 0 0 3 | |
263 707709 707696 0 4411 45 4410 0 1 3 | |
47 707756 707696 0 4412 44 4411 0 1 3 | |
43 707799 707696 0 4413 43 4412 0 1 3 | |
39 707838 707696 0 4414 42 4413 0 1 3 | |
40 707878 707696 0 4415 41 4414 0 1 3 | |
41 707919 707696 0 4416 40 4415 0 1 3 | |
40 707959 707696 0 4417 39 4416 0 1 3 | |
39 707998 707696 0 4418 38 4417 0 1 3 | |
40 708038 707696 0 4419 37 4418 0 1 3 | |
40 708078 707696 0 4420 36 4419 0 1 3 | |
39 708117 707696 0 4421 35 4420 0 1 3 | |
41 708158 707696 0 4422 34 4421 0 1 3 | |
39 708197 707696 0 4423 33 4422 0 1 3 | |
39 708236 707696 0 4424 32 4423 0 1 3 | |
40 708276 707696 0 4425 31 4424 0 1 3 | |
40 708316 707696 0 4426 30 4425 0 1 3 | |
38 708354 707696 0 4427 29 4426 0 1 3 | |
64 708418 707696 0 4428 28 4427 0 1 3 | |
46 708464 707696 0 4429 27 4428 0 1 3 | |
41 708505 707696 0 4430 26 4429 0 1 3 | |
43 708548 707696 997 4431 25 4386 0 1 3 | |
40 708588 707696 997 4432 24 4387 0 1 3 | |
39 708627 707696 997 4433 23 4388 0 1 3 | |
89 708716 708701 997 4434 66 4389 0 1 3 | |
45 708761 708701 997 4435 65 4390 0 1 3 | |
42 708803 708701 997 4436 64 4391 0 1 3 | |
41 708844 708701 997 4437 63 4392 0 1 3 | |
39 708883 708701 997 4438 62 4393 0 1 3 | |
41 708924 708701 997 4439 61 4394 0 1 3 | |
40 708964 708701 997 4440 60 4395 0 1 3 | |
39 709003 708701 997 4441 59 4396 0 1 3 | |
40 709043 708701 997 4442 58 4397 0 1 3 | |
40 709083 708701 997 4443 57 4398 0 1 3 | |
39 709122 708701 997 4444 56 4399 0 1 3 | |
41 709163 708701 997 4445 55 4400 0 1 3 | |
39 709202 708701 997 4446 54 4401 0 1 3 | |
39 709241 708701 997 4447 53 4402 0 1 3 | |
41 709282 708701 997 4448 52 4403 0 1 3 | |
40 709322 708701 997 4449 51 4404 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 709361 708701 997 4450 50 4405 0 1 3 | |
69 709430 708701 997 4451 49 4406 0 1 3 | |
44 709474 708701 997 4452 48 4407 0 1 3 | |
43 709517 708701 1995 4453 47 4364 0 1 3 | |
39 709556 708701 1995 4454 46 4365 0 1 3 | |
40 709596 708701 1995 4455 45 4366 0 1 3 | |
40 709636 708701 1995 4456 44 4367 0 1 3 | |
92 709728 709681 1995 4457 87 4368 0 1 3 | |
43 709771 709681 1995 4458 86 4369 0 1 3 | |
41 709812 709681 1995 4459 85 4370 0 1 3 | |
39 709851 709681 1995 4460 84 4371 0 1 3 | |
40 709891 709681 1995 4461 83 4372 0 1 3 | |
40 709931 709681 1995 4462 82 4373 0 1 3 | |
41 709972 709681 1995 4463 81 4374 0 1 3 | |
42 710014 709681 1995 4464 80 4375 0 1 3 | |
40 710054 709681 1995 4465 79 4376 0 1 3 | |
39 710093 709681 1995 4466 78 4377 0 1 3 | |
39 710132 709681 1995 4467 77 4378 0 1 3 | |
40 710172 709681 1995 4468 76 4379 0 1 3 | |
40 710212 709681 1995 4469 75 4380 0 1 3 | |
39 710251 709681 1995 4470 74 4381 0 1 3 | |
41 710292 709681 1995 4471 73 4382 0 1 3 | |
38 710330 709681 1995 4472 72 4383 0 1 3 | |
40 710370 709681 1995 4473 71 4384 0 1 3 | |
64 710434 709681 1995 4474 70 4385 0 1 3 | |
45 710479 709681 1995 4475 69 4386 0 1 3 | |
43 710522 709681 2993 4476 68 4343 0 1 3 | |
40 710562 709681 2993 4477 67 4344 0 1 3 | |
39 710601 709681 2993 4478 66 4345 0 1 3 | |
80 710681 709681 2993 4479 65 4346 0 1 3 | |
54 710735 710687 2993 4480 108 4347 0 1 3 | |
81 710816 710687 2993 4481 107 4348 0 1 3 | |
51 710867 710687 2993 4482 106 4349 0 1 3 | |
45 710912 710687 2993 4483 105 4350 0 1 3 | |
40 710952 710687 2993 4484 104 4351 0 1 3 | |
75 711027 710687 2993 4485 103 4352 0 1 3 | |
44 711071 710687 2993 4486 102 4353 0 1 3 | |
41 711112 710687 2993 4487 101 4354 0 1 3 | |
43 711155 710687 2993 4488 100 4355 0 1 3 | |
40 711195 710687 2993 4489 99 4356 0 1 3 | |
39 711234 710687 2993 4490 98 4357 0 1 3 | |
41 711275 710687 2993 4491 97 4358 0 1 3 | |
39 711314 710687 2993 4492 96 4359 0 1 3 | |
39 711353 710687 2993 4493 95 4360 0 1 3 | |
68 711421 710687 2993 4494 94 4361 0 1 3 | |
46 711467 710687 2993 4495 93 4362 0 1 3 | |
43 711510 710687 2993 4496 92 4363 0 1 3 | |
41 711551 710687 3990 4497 91 4320 0 1 3 | |
40 711591 710687 3990 4498 90 4321 0 1 3 | |
39 711630 710687 3990 4499 89 4322 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
94 711724 711709 3990 4500 132 4323 0 1 3 | |
49 711773 711709 3990 4501 131 4324 0 1 3 | |
41 711814 711709 3990 4502 130 4325 0 1 3 | |
40 711854 711709 3990 4503 129 4326 0 1 3 | |
40 711894 711709 3990 4504 128 4327 0 1 3 | |
40 711934 711709 3990 4505 127 4328 0 1 3 | |
39 711973 711709 3990 4506 126 4329 0 1 3 | |
41 712014 711709 3990 4507 125 4330 0 1 3 | |
39 712053 711709 3990 4508 124 4331 0 1 3 | |
39 712092 711709 3990 4509 123 4332 0 1 3 | |
40 712132 711709 3990 4510 122 4333 0 1 3 | |
41 712173 711709 3990 4511 121 4334 0 1 3 | |
40 712213 711709 3990 4512 120 4335 0 1 3 | |
39 712252 711709 3990 4513 119 4336 0 1 3 | |
41 712293 711709 3990 4514 118 4337 0 1 3 | |
39 712332 711709 3990 4515 117 4338 0 1 3 | |
40 712372 711709 3990 4516 116 4339 0 1 3 | |
70 712442 711709 3990 4517 115 4340 0 1 3 | |
44 712486 711709 3990 4518 114 4341 0 1 3 | |
64 712550 711709 4988 4519 113 4298 0 1 3 | |
43 712593 711709 4988 4520 112 4299 0 1 3 | |
43 712636 711709 4988 4521 111 4300 0 1 3 | |
93 712729 712680 4988 4522 154 4301 0 1 3 | |
45 712774 712680 4988 4523 153 4302 0 1 3 | |
40 712814 712680 4988 4524 152 4303 0 1 3 | |
40 712854 712680 4988 4525 151 4304 0 1 3 | |
41 712895 712680 4988 4526 150 4305 0 1 3 | |
40 712935 712680 4988 4527 149 4306 0 1 3 | |
39 712974 712680 4988 4528 148 4307 0 1 3 | |
40 713014 712680 4988 4529 147 4308 0 1 3 | |
40 713054 712680 4988 4530 146 4309 0 1 3 | |
38 713092 712680 4988 4531 145 4310 0 1 3 | |
40 713132 712680 4988 4532 144 4311 0 1 3 | |
41 713173 712680 4988 4533 143 4312 0 1 3 | |
39 713212 712680 4988 4534 142 4313 0 1 3 | |
39 713251 712680 4988 4535 141 4314 0 1 3 | |
41 713292 712680 4988 4536 140 4315 0 1 3 | |
40 713332 712680 4988 4537 139 4316 0 1 3 | |
39 713371 712680 4988 4538 138 4317 0 1 3 | |
65 713436 712680 4988 4539 137 4318 0 1 3 | |
42 713478 712680 4988 4540 136 4319 0 1 3 | |
43 713521 712680 5986 4541 135 4276 0 1 3 | |
41 713562 712680 5986 4542 134 4277 0 1 3 | |
39 713601 712680 5986 4543 133 4278 0 1 3 | |
92 713693 713686 5986 4544 132 4279 0 1 3 | |
49 713742 713686 5986 4545 175 4280 0 1 3 | |
45 713787 713686 5986 4546 174 4281 0 1 3 | |
41 713828 713686 5986 4547 173 4282 0 1 3 | |
40 713868 713686 5986 4548 172 4283 0 1 3 | |
43 713911 713686 5986 4549 171 4284 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 713950 713686 5986 4550 170 4285 0 1 3 | |
44 713994 713686 5986 4551 169 4286 0 1 3 | |
41 714035 713686 5986 4552 168 4287 0 1 3 | |
40 714075 713686 5986 4553 167 4288 0 1 3 | |
40 714115 713686 5986 4554 166 4289 0 1 3 | |
42 714157 713686 5986 4555 165 4290 0 1 3 | |
40 714197 713686 5986 4556 164 4291 0 1 3 | |
39 714236 713686 5986 4557 163 4292 0 1 3 | |
41 714277 713686 5986 4558 162 4293 0 1 3 | |
40 714317 713686 5986 4559 161 4294 0 1 3 | |
38 714355 713686 5986 4560 160 4295 0 1 3 | |
64 714419 713686 5986 4561 159 4296 0 1 3 | |
44 714463 713686 5986 4562 158 4297 0 1 3 | |
41 714504 713686 5986 4563 157 4298 0 1 3 | |
42 714546 713686 6984 4564 156 4255 0 1 3 | |
40 714586 713686 6984 4565 155 4256 0 1 3 | |
40 714626 713686 6984 4566 154 4257 0 1 3 | |
90 714716 714700 6984 4567 197 4258 0 1 3 | |
45 714761 714700 6984 4568 196 4259 0 1 3 | |
42 714803 714700 6984 4569 195 4260 0 1 3 | |
39 714842 714700 6984 4570 194 4261 0 1 3 | |
40 714882 714700 6984 4571 193 4262 0 1 3 | |
42 714924 714700 6984 4572 192 4263 0 1 3 | |
40 714964 714700 6984 4573 191 4264 0 1 3 | |
39 715003 714700 6984 4574 190 4265 0 1 3 | |
42 715045 714700 6984 4575 189 4266 0 1 3 | |
40 715085 714700 6984 4576 188 4267 0 1 3 | |
39 715124 714700 6984 4577 187 4268 0 1 3 | |
40 715164 714700 6984 4578 186 4269 0 1 3 | |
66 715230 714700 6984 4579 185 4270 0 1 3 | |
45 715275 714700 6984 4580 184 4271 0 1 3 | |
41 715316 714700 6984 4581 183 4272 0 1 3 | |
39 715355 714700 6984 4582 182 4273 0 1 3 | |
66 715421 714700 6984 4583 181 4274 0 1 3 | |
46 715467 714700 6984 4584 180 4275 0 1 3 | |
44 715511 714700 6984 4585 179 4276 0 1 3 | |
41 715552 714700 7981 4586 178 4233 0 1 3 | |
40 715592 714700 7981 4587 177 4234 0 1 3 | |
40 715632 714700 7981 4588 176 4235 0 1 3 | |
95 715727 715712 8004 4589 219 4235 0 1 3 | |
45 715772 715712 8004 4590 218 4236 0 1 3 | |
42 715814 715712 8004 4591 217 4237 0 1 3 | |
40 715854 715712 8004 4592 216 4238 0 1 3 | |
41 715895 715712 8004 4593 215 4239 0 1 3 | |
41 715936 715712 8004 4594 214 4240 0 1 3 | |
39 715975 715712 8004 4595 213 4241 0 1 3 | |
40 716015 715712 8004 4596 212 4242 0 1 3 | |
41 716056 715712 8004 4597 211 4243 0 1 3 | |
39 716095 715712 8004 4598 210 4244 0 1 3 | |
38 716133 715712 8004 4599 209 4245 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 716173 715712 8004 4600 208 4246 0 1 3 | |
43 716216 715712 8004 4601 207 4247 0 1 3 | |
39 716255 715712 8004 4602 206 4248 0 1 3 | |
41 716296 715712 8004 4603 205 4249 0 1 3 | |
40 716336 715712 8004 4604 204 4250 0 1 3 | |
40 716376 715712 8004 4605 203 4251 0 1 3 | |
66 716442 715712 8004 4606 202 4252 0 1 3 | |
43 716485 715712 8004 4607 201 4253 0 1 3 | |
43 716528 715712 9002 4608 200 4210 0 1 3 | |
39 716567 715712 9002 4609 199 4211 0 1 3 | |
39 716606 715712 9002 4610 198 4212 0 1 3 | |
86 716692 716686 9002 4611 197 4213 0 1 3 | |
48 716740 716686 9002 4612 240 4214 0 1 3 | |
44 716784 716686 9002 4613 239 4215 0 1 3 | |
40 716824 716686 9002 4614 238 4216 0 1 3 | |
41 716865 716686 9002 4615 237 4217 0 1 3 | |
41 716906 716686 9002 4616 236 4218 0 1 3 | |
38 716944 716686 9002 4617 235 4219 0 1 3 | |
40 716984 716686 9002 4618 234 4220 0 1 3 | |
41 717025 716686 9002 4619 233 4221 0 1 3 | |
39 717064 716686 9002 4620 232 4222 0 1 3 | |
40 717104 716686 9002 4621 231 4223 0 1 3 | |
40 717144 716686 9002 4622 230 4224 0 1 3 | |
39 717183 716686 9002 4623 229 4225 0 1 3 | |
39 717222 716686 9002 4624 228 4226 0 1 3 | |
42 717264 716686 9002 4625 227 4227 0 1 3 | |
39 717303 716686 9002 4626 226 4228 0 1 3 | |
40 717343 716686 9002 4627 225 4229 0 1 3 | |
40 717383 716686 9002 4628 224 4230 0 1 3 | |
67 717450 716686 9002 4629 223 4231 0 1 3 | |
40 717490 716686 9002 4630 222 4232 0 1 3 | |
43 717533 716686 10000 4631 221 4189 0 1 3 | |
41 717574 716686 10000 4632 220 4190 0 1 3 | |
40 717614 716686 10000 4633 219 4191 0 1 3 | |
87 717701 717687 10000 4634 263 4192 0 1 3 | |
46 717747 717687 10000 4635 262 4193 0 1 3 | |
43 717790 717687 10000 4636 261 4194 0 1 3 | |
39 717829 717687 10000 4637 260 4195 0 1 3 | |
39 717868 717687 10000 4638 259 4196 0 1 3 | |
42 717910 717687 10000 4639 258 4197 0 1 3 | |
39 717949 717687 10000 4640 257 4198 0 1 3 | |
38 717987 717687 10000 4641 256 4199 0 1 3 | |
42 718029 717687 10000 4642 255 4200 0 1 3 | |
39 718068 717687 10000 4643 254 4201 0 1 3 | |
39 718107 717687 10000 4644 253 4202 0 1 3 | |
40 718147 717687 10000 4645 252 4203 0 1 3 | |
40 718187 717687 10000 4646 251 4204 0 1 3 | |
39 718226 717687 10000 4647 250 4205 0 1 3 | |
40 718266 717687 10000 4648 249 4206 0 1 3 | |
41 718307 717687 10000 4649 248 4207 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 718346 717687 10000 4650 247 4208 0 1 3 | |
66 718412 717687 10000 4651 246 4209 0 1 3 | |
46 718458 717687 10000 4652 245 4210 0 1 3 | |
41 718499 717687 10000 4653 244 4211 0 1 3 | |
42 718541 717687 10997 4654 243 4168 0 1 3 | |
39 718580 717687 10997 4655 242 4169 0 1 3 | |
40 718620 717687 10997 4656 241 4170 0 1 3 | |
90 718710 718695 10997 4657 284 4171 0 1 3 | |
45 718755 718695 10997 4658 283 4172 0 1 3 | |
44 718799 718695 10997 4659 282 4173 0 1 3 | |
40 718839 718695 10997 4660 281 4174 0 1 3 | |
39 718878 718695 10997 4661 280 4175 0 1 3 | |
41 718919 718695 10997 4662 279 4176 0 1 3 | |
40 718959 718695 10997 4663 278 4177 0 1 3 | |
39 718998 718695 10997 4664 277 4178 0 1 3 | |
41 719039 718695 10997 4665 276 4179 0 1 3 | |
40 719079 718695 10997 4666 275 4180 0 1 3 | |
39 719118 718695 10997 4667 274 4181 0 1 3 | |
40 719158 718695 10997 4668 273 4182 0 1 3 | |
41 719199 718695 10997 4669 272 4183 0 1 3 | |
40 719239 718695 10997 4670 271 4184 0 1 3 | |
40 719279 718695 10997 4671 270 4185 0 1 3 | |
40 719319 718695 10997 4672 269 4186 0 1 3 | |
87 719406 718695 10997 4673 268 4187 0 1 3 | |
52 719458 718695 10997 4674 267 4188 0 1 3 | |
43 719501 718695 10997 4675 266 4189 0 1 3 | |
43 719544 718695 11995 4676 265 4146 0 1 3 | |
41 719585 718695 11995 4677 264 4147 0 1 3 | |
39 719624 718695 11995 4678 263 4148 0 1 3 | |
90 719714 719699 11995 4679 306 4149 0 1 3 | |
47 719761 719699 11995 4680 305 4150 0 1 3 | |
42 719803 719699 11995 4681 304 4151 0 1 3 | |
40 719843 719699 11995 4682 303 4152 0 1 3 | |
40 719883 719699 11995 4683 302 4153 0 1 3 | |
42 719925 719699 11995 4684 301 4154 0 1 3 | |
41 719966 719699 11995 4685 300 4155 0 1 3 | |
40 720006 719699 11995 4686 299 4156 0 1 3 | |
41 720047 719699 11995 4687 298 4157 0 1 3 | |
40 720087 719699 11995 4688 297 4158 0 1 3 | |
40 720127 719699 11995 4689 296 4159 0 1 3 | |
41 720168 719699 11995 4690 295 4160 0 1 3 | |
39 720207 719699 11995 4691 294 4161 0 1 3 | |
40 720247 719699 11995 4692 293 4162 0 1 3 | |
41 720288 719699 11995 4693 292 4163 0 1 3 | |
40 720328 719699 11995 4694 291 4164 0 1 3 | |
39 720367 719699 11995 4695 290 4165 0 1 3 | |
69 720436 719699 11995 4696 289 4166 0 1 3 | |
44 720480 719699 11995 4697 288 4167 0 1 3 | |
62 720542 719699 12993 4698 287 4124 0 1 3 | |
44 720586 719699 12993 4699 286 4125 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
42 720628 719699 12993 4700 285 4126 0 1 3 | |
94 720722 720706 12993 4701 328 4127 0 1 3 | |
45 720767 720706 12993 4702 327 4128 0 1 3 | |
88 720855 720706 12993 4703 326 4129 0 1 3 | |
45 720900 720706 12993 4704 325 4130 0 1 3 | |
41 720941 720706 12993 4705 324 4131 0 1 3 | |
41 720982 720706 12993 4706 323 4132 0 1 3 | |
40 721022 720706 12993 4707 322 4133 0 1 3 | |
39 721061 720706 12993 4708 321 4134 0 1 3 | |
39 721100 720706 12993 4709 320 4135 0 1 3 | |
41 721141 720706 12993 4710 319 4136 0 1 3 | |
40 721181 720706 12993 4711 318 4137 0 1 3 | |
40 721221 720706 12993 4712 317 4138 0 1 3 | |
40 721261 720706 12993 4713 316 4139 0 1 3 | |
39 721300 720706 12993 4714 315 4140 0 1 3 | |
41 721341 720706 12993 4715 314 4141 0 1 3 | |
39 721380 720706 12993 4716 313 4142 0 1 3 | |
70 721450 720706 12993 4717 312 4143 0 1 3 | |
43 721493 720706 12993 4718 311 4144 0 1 3 | |
43 721536 720706 13990 4719 310 4101 0 1 3 | |
40 721576 720706 13990 4720 309 4102 0 1 3 | |
39 721615 720706 13990 4721 308 4103 0 1 3 | |
89 721704 721688 13990 4722 351 4104 0 1 3 | |
46 721750 721688 13990 4723 350 4105 0 1 3 | |
42 721792 721688 13990 4724 349 4106 0 1 3 | |
40 721832 721688 13990 4725 348 4107 0 1 3 | |
39 721871 721688 13990 4726 347 4108 0 1 3 | |
41 721912 721688 13990 4727 346 4109 0 1 3 | |
40 721952 721688 13990 4728 345 4110 0 1 3 | |
38 721990 721688 13990 4729 344 4111 0 1 3 | |
41 722031 721688 13990 4730 343 4112 0 1 3 | |
40 722071 721688 13990 4731 342 4113 0 1 3 | |
40 722111 721688 13990 4732 341 4114 0 1 3 | |
40 722151 721688 13990 4733 340 4115 0 1 3 | |
41 722192 721688 13990 4734 339 4116 0 1 3 | |
39 722231 721688 13990 4735 338 4117 0 1 3 | |
41 722272 721688 13990 4736 337 4118 0 1 3 | |
39 722311 721688 13990 4737 336 4119 0 1 3 | |
39 722350 721688 13990 4738 335 4120 0 1 3 | |
63 722413 721688 13990 4739 334 4121 0 1 3 | |
45 722458 721688 13990 4740 333 4122 0 1 3 | |
42 722500 721688 13990 4741 332 4123 0 1 3 | |
42 722542 721688 14988 4742 331 4080 0 1 3 | |
39 722581 721688 14988 4743 330 4081 0 1 3 | |
40 722621 721688 14988 4744 329 4082 0 1 3 | |
92 722713 722697 14988 4745 372 4083 0 1 3 | |
45 722758 722697 14988 4746 371 4084 0 1 3 | |
42 722800 722697 14988 4747 370 4085 0 1 3 | |
40 722840 722697 14988 4748 369 4086 0 1 3 | |
40 722880 722697 14988 4749 368 4087 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 722921 722697 14988 4750 367 4088 0 1 3 | |
43 722964 722697 14988 4751 366 4089 0 1 3 | |
39 723003 722697 14988 4752 365 4090 0 1 3 | |
41 723044 722697 14988 4753 364 4091 0 1 3 | |
39 723083 722697 14988 4754 363 4092 0 1 3 | |
40 723123 722697 14988 4755 362 4093 0 1 3 | |
41 723164 722697 14988 4756 361 4094 0 1 3 | |
39 723203 722697 14988 4757 360 4095 0 1 3 | |
40 723243 722697 14988 4758 359 4096 0 1 3 | |
41 723284 722697 14988 4759 358 4097 0 1 3 | |
40 723324 722697 14988 4760 357 4098 0 1 3 | |
40 723364 722697 14988 4761 356 4099 0 1 3 | |
65 723429 722697 14988 4762 355 4100 0 1 3 | |
46 723475 722697 14988 4763 354 4101 0 1 3 | |
42 723517 722697 15986 4764 353 4058 0 1 3 | |
72 723589 722697 15986 4765 352 4059 0 1 3 | |
44 723633 722697 15986 4766 351 4060 0 1 3 | |
102 723735 723720 15986 4767 394 4061 0 1 3 | |
46 723781 723720 15986 4768 393 4062 0 1 3 | |
41 723822 723720 15986 4769 392 4063 0 1 3 | |
40 723862 723720 15986 4770 391 4064 0 1 3 | |
41 723903 723720 15986 4771 390 4065 0 1 3 | |
40 723943 723720 15986 4772 389 4066 0 1 3 | |
39 723982 723720 15986 4773 388 4067 0 1 3 | |
41 724023 723720 15986 4774 387 4068 0 1 3 | |
40 724063 723720 15986 4775 386 4069 0 1 3 | |
40 724103 723720 15986 4776 385 4070 0 1 3 | |
40 724143 723720 15986 4777 384 4071 0 1 3 | |
39 724182 723720 15986 4778 383 4072 0 1 3 | |
40 724222 723720 15986 4779 382 4073 0 1 3 | |
40 724262 723720 15986 4780 381 4074 0 1 3 | |
40 724302 723720 15986 4781 380 4075 0 1 3 | |
40 724342 723720 15986 4782 379 4076 0 1 3 | |
38 724380 723720 15986 4783 378 4077 0 1 3 | |
69 724449 723720 15986 4784 377 4078 0 1 3 | |
43 724492 723720 15986 4785 376 4079 0 1 3 | |
43 724535 723720 16984 4786 375 4036 0 1 3 | |
41 724576 723720 16984 4787 374 4037 0 1 3 | |
40 724616 723720 16984 4788 373 4038 0 1 3 | |
85 724701 724686 16984 4789 416 4039 0 1 3 | |
46 724747 724686 16984 4790 415 4040 0 1 3 | |
41 724788 724686 16984 4791 414 4041 0 1 3 | |
41 724829 724686 16984 4792 413 4042 0 1 3 | |
40 724869 724686 16984 4793 412 4043 0 1 3 | |
42 724911 724686 16984 4794 411 4044 0 1 3 | |
39 724950 724686 16984 4795 410 4045 0 1 3 | |
40 724990 724686 16984 4796 409 4046 0 1 3 | |
40 725030 724686 16984 4797 408 4047 0 1 3 | |
41 725071 724686 16984 4798 407 4048 0 1 3 | |
39 725110 724686 16984 4799 406 4049 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 725150 724686 16984 4800 405 4050 0 1 3 | |
43 725193 724686 16984 4801 404 4051 0 1 3 | |
39 725232 724686 16984 4802 403 4052 0 1 3 | |
41 725273 724686 16984 4803 402 4053 0 1 3 | |
39 725312 724686 16984 4804 401 4054 0 1 3 | |
40 725352 724686 16984 4805 400 4055 0 1 3 | |
64 725416 724686 16984 4806 399 4056 0 1 3 | |
46 725462 724686 16984 4807 398 4057 0 1 3 | |
40 725502 724686 16984 4808 397 4058 0 1 3 | |
42 725544 724686 17981 4809 396 4015 0 1 3 | |
41 725585 724686 17981 4810 395 4016 0 1 3 | |
39 725624 724686 17981 4811 394 4017 0 1 3 | |
88 725712 725696 18004 4812 437 4017 0 1 3 | |
45 725757 725696 18004 4813 436 4018 0 1 3 | |
42 725799 725696 18004 4814 435 4019 0 1 3 | |
40 725839 725696 18004 4815 434 4020 0 1 3 | |
40 725879 725696 18004 4816 433 4021 0 1 3 | |
40 725919 725696 18004 4817 432 4022 0 1 3 | |
40 725959 725696 18004 4818 431 4023 0 1 3 | |
40 725999 725696 18004 4819 430 4024 0 1 3 | |
41 726040 725696 18004 4820 429 4025 0 1 3 | |
40 726080 725696 18004 4821 428 4026 0 1 3 | |
39 726119 725696 18004 4822 427 4027 0 1 3 | |
41 726160 725696 18004 4823 426 4028 0 1 3 | |
40 726200 725696 18004 4824 425 4029 0 1 3 | |
39 726239 725696 18004 4825 424 4030 0 1 3 | |
41 726280 725696 18004 4826 423 4031 0 1 3 | |
41 726321 725696 18004 4827 422 4032 0 1 3 | |
39 726360 725696 18004 4828 421 4033 0 1 3 | |
64 726424 725696 18004 4829 420 4034 0 1 3 | |
45 726469 725696 18004 4830 419 4035 0 1 3 | |
40 726509 725696 18004 4831 418 4036 0 1 3 | |
43 726552 725696 19002 4832 417 3993 0 1 3 | |
40 726592 725696 19002 4833 416 3994 0 1 3 | |
40 726632 725696 19002 4834 415 3995 0 1 3 | |
92 726724 726710 19002 4835 458 3996 0 1 3 | |
45 726769 726710 19002 4836 457 3997 0 1 3 | |
41 726810 726710 19002 4837 456 3998 0 1 3 | |
41 726851 726710 19002 4838 455 3999 0 1 3 | |
41 726892 726710 19002 4839 454 4000 0 1 3 | |
39 726931 726710 19002 4840 453 4001 0 1 3 | |
40 726971 726710 19002 4841 452 4002 0 1 3 | |
42 727013 726710 19002 4842 451 4003 0 1 3 | |
40 727053 726710 19002 4843 450 4004 0 1 3 | |
39 727092 726710 19002 4844 449 4005 0 1 3 | |
40 727132 726710 19002 4845 448 4006 0 1 3 | |
41 727173 726710 19002 4846 447 4007 0 1 3 | |
39 727212 726710 19002 4847 446 4008 0 1 3 | |
40 727252 726710 19002 4848 445 4009 0 1 3 | |
40 727292 726710 19002 4849 444 4010 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 727331 726710 19002 4850 443 4011 0 1 3 | |
43 727374 726710 19002 4851 442 4012 0 1 3 | |
64 727438 726710 19002 4852 441 4013 0 1 3 | |
44 727482 726710 19002 4853 440 4014 0 1 3 | |
43 727525 726710 20000 4854 439 3971 0 1 3 | |
41 727566 726710 20000 4855 438 3972 0 1 3 | |
39 727605 726710 20000 4856 437 3973 0 1 3 | |
84 727689 727683 20000 4857 436 3974 0 1 3 | |
5166 732855 732827 24988 4858 700 3755 0 1 3 | |
62 732917 732827 24988 4859 699 3756 0 1 3 | |
43 732960 732827 24988 4860 698 3757 0 1 3 | |
41 733001 732827 24988 4861 697 3758 0 1 3 | |
42 733043 732827 24988 4862 696 3759 0 1 3 | |
40 733083 732827 24988 4863 695 3760 0 1 3 | |
39 733122 732827 24988 4864 694 3761 0 1 3 | |
40 733162 732827 24988 4865 693 3762 0 1 3 | |
40 733202 732827 24988 4866 692 3763 0 1 3 | |
40 733242 732827 24988 4867 691 3764 0 1 3 | |
40 733282 732827 24988 4868 690 3765 0 1 3 | |
41 733323 732827 24988 4869 689 3766 0 1 3 | |
39 733362 732827 24988 4870 688 3767 0 1 3 | |
75 733437 732827 24988 4871 687 3768 0 1 3 | |
45 733482 732827 24988 4872 686 3769 0 1 3 | |
45 733527 732827 25986 4873 685 3726 0 1 3 | |
41 733568 732827 25986 4874 684 3727 0 1 3 | |
41 733609 732827 25986 4875 683 3728 0 1 3 | |
94 733703 733698 25986 4876 682 3729 0 1 3 | |
50 733753 733698 25986 4877 725 3730 0 1 3 | |
43 733796 733698 25986 4878 724 3731 0 1 3 | |
41 733837 733698 25986 4879 723 3732 0 1 3 | |
40 733877 733698 25986 4880 722 3733 0 1 3 | |
41 733918 733698 25986 4881 721 3734 0 1 3 | |
39 733957 733698 25986 4882 720 3735 0 1 3 | |
41 733998 733698 25986 4883 719 3736 0 1 3 | |
41 734039 733698 25986 4884 718 3737 0 1 3 | |
40 734079 733698 25986 4885 717 3738 0 1 3 | |
39 734118 733698 25986 4886 716 3739 0 1 3 | |
41 734159 733698 25986 4887 715 3740 0 1 3 | |
39 734198 733698 25986 4888 714 3741 0 1 3 | |
40 734238 733698 25986 4889 713 3742 0 1 3 | |
41 734279 733698 25986 4890 712 3743 0 1 3 | |
39 734318 733698 25986 4891 711 3744 0 1 3 | |
40 734358 733698 25986 4892 710 3745 0 1 3 | |
64 734422 733698 25986 4893 709 3746 0 1 3 | |
45 734467 733698 25986 4894 708 3747 0 1 3 | |
43 734510 733698 25986 4895 707 3748 0 1 3 | |
42 734552 733698 26984 4896 706 3705 0 1 3 | |
41 734593 733698 26984 4897 705 3706 0 1 3 | |
40 734633 733698 26984 4898 704 3707 0 1 3 | |
90 734723 734709 26984 4899 747 3708 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
44 734767 734709 26984 4900 746 3709 0 1 3 | |
47 734814 734709 26984 4901 745 3710 0 1 3 | |
40 734854 734709 26984 4902 744 3711 0 1 3 | |
41 734895 734709 26984 4903 743 3712 0 1 3 | |
41 734936 734709 26984 4904 742 3713 0 1 3 | |
39 734975 734709 26984 4905 741 3714 0 1 3 | |
40 735015 734709 26984 4906 740 3715 0 1 3 | |
41 735056 734709 26984 4907 739 3716 0 1 3 | |
40 735096 734709 26984 4908 738 3717 0 1 3 | |
39 735135 734709 26984 4909 737 3718 0 1 3 | |
41 735176 734709 26984 4910 736 3719 0 1 3 | |
39 735215 734709 26984 4911 735 3720 0 1 3 | |
39 735254 734709 26984 4912 734 3721 0 1 3 | |
41 735295 734709 26984 4913 733 3722 0 1 3 | |
40 735335 734709 26984 4914 732 3723 0 1 3 | |
40 735375 734709 26984 4915 731 3724 0 1 3 | |
67 735442 734709 26984 4916 730 3725 0 1 3 | |
43 735485 734709 26984 4917 729 3726 0 1 3 | |
43 735528 734709 27981 4918 728 3683 0 1 3 | |
40 735568 734709 27981 4919 727 3684 0 1 3 | |
39 735607 734709 27981 4920 726 3685 0 1 3 | |
86 735693 735687 28004 4921 725 3685 0 1 3 | |
49 735742 735687 28004 4922 768 3686 0 1 3 | |
44 735786 735687 28004 4923 767 3687 0 1 3 | |
42 735828 735687 28004 4924 766 3688 0 1 3 | |
40 735868 735687 28004 4925 765 3689 0 1 3 | |
41 735909 735687 28004 4926 764 3690 0 1 3 | |
39 735948 735687 28004 4927 763 3691 0 1 3 | |
40 735988 735687 28004 4928 762 3692 0 1 3 | |
40 736028 735687 28004 4929 761 3693 0 1 3 | |
40 736068 735687 28004 4930 760 3694 0 1 3 | |
39 736107 735687 28004 4931 759 3695 0 1 3 | |
40 736147 735687 28004 4932 758 3696 0 1 3 | |
40 736187 735687 28004 4933 757 3697 0 1 3 | |
39 736226 735687 28004 4934 756 3698 0 1 3 | |
40 736266 735687 28004 4935 755 3699 0 1 3 | |
40 736306 735687 28004 4936 754 3700 0 1 3 | |
39 736345 735687 28004 4937 753 3701 0 1 3 | |
39 736384 735687 28004 4938 752 3702 0 1 3 | |
75 736459 735687 28004 4939 751 3703 0 1 3 | |
41 736500 735687 28004 4940 750 3704 0 1 3 | |
65 736565 735687 29002 4941 749 3661 0 1 3 | |
42 736607 735687 29002 4942 748 3662 0 1 3 | |
89 736696 736690 29002 4943 747 3663 0 1 3 | |
47 736743 736690 29002 4944 790 3664 0 1 3 | |
44 736787 736690 29002 4945 789 3665 0 1 3 | |
41 736828 736690 29002 4946 788 3666 0 1 3 | |
39 736867 736690 29002 4947 787 3667 0 1 3 | |
41 736908 736690 29002 4948 786 3668 0 1 3 | |
39 736947 736690 29002 4949 785 3669 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 736986 736690 29002 4950 784 3670 0 1 3 | |
73 737059 736690 29002 4951 783 3671 0 1 3 | |
44 737103 736690 29002 4952 782 3672 0 1 3 | |
42 737145 736690 29002 4953 781 3673 0 1 3 | |
41 737186 736690 29002 4954 780 3674 0 1 3 | |
40 737226 736690 29002 4955 779 3675 0 1 3 | |
40 737266 736690 29002 4956 778 3676 0 1 3 | |
40 737306 736690 29002 4957 777 3677 0 1 3 | |
39 737345 736690 29002 4958 776 3678 0 1 3 | |
39 737384 736690 29002 4959 775 3679 0 1 3 | |
71 737455 736690 29002 4960 774 3680 0 1 3 | |
43 737498 736690 29002 4961 773 3681 0 1 3 | |
42 737540 736690 30000 4962 772 3638 0 1 3 | |
41 737581 736690 30000 4963 771 3639 0 1 3 | |
39 737620 736690 30000 4964 770 3640 0 1 3 | |
92 737712 737697 30000 4965 814 3641 0 1 3 | |
46 737758 737697 30000 4966 813 3642 0 1 3 | |
42 737800 737697 30000 4967 812 3643 0 1 3 | |
41 737841 737697 30000 4968 811 3644 0 1 3 | |
39 737880 737697 30000 4969 810 3645 0 1 3 | |
41 737921 737697 30000 4970 809 3646 0 1 3 | |
40 737961 737697 30000 4971 808 3647 0 1 3 | |
39 738000 737697 30000 4972 807 3648 0 1 3 | |
41 738041 737697 30000 4973 806 3649 0 1 3 | |
40 738081 737697 30000 4974 805 3650 0 1 3 | |
39 738120 737697 30000 4975 804 3651 0 1 3 | |
41 738161 737697 30000 4976 803 3652 0 1 3 | |
39 738200 737697 30000 4977 802 3653 0 1 3 | |
41 738241 737697 30000 4978 801 3654 0 1 3 | |
40 738281 737697 30000 4979 800 3655 0 1 3 | |
39 738320 737697 30000 4980 799 3656 0 1 3 | |
40 738360 737697 30000 4981 798 3657 0 1 3 | |
64 738424 737697 30000 4982 797 3658 0 1 3 | |
45 738469 737697 30000 4983 796 3659 0 1 3 | |
42 738511 737697 30000 4984 795 3660 0 1 3 | |
43 738554 737697 30997 4985 794 3617 0 1 3 | |
41 738595 737697 30997 4986 793 3618 0 1 3 | |
39 738634 737697 30997 4987 792 3619 0 1 3 | |
89 738723 738709 30997 4988 835 3620 0 1 3 | |
46 738769 738709 30997 4989 834 3621 0 1 3 | |
41 738810 738709 30997 4990 833 3622 0 1 3 | |
40 738850 738709 30997 4991 832 3623 0 1 3 | |
40 738890 738709 30997 4992 831 3624 0 1 3 | |
40 738930 738709 30997 4993 830 3625 0 1 3 | |
40 738970 738709 30997 4994 829 3626 0 1 3 | |
40 739010 738709 30997 4995 828 3627 0 1 3 | |
42 739052 738709 30997 4996 827 3628 0 1 3 | |
39 739091 738709 30997 4997 826 3629 0 1 3 | |
39 739130 738709 30997 4998 825 3630 0 1 3 | |
41 739171 738709 30997 4999 824 3631 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 739210 738709 30997 5000 823 3632 0 1 3 | |
43 739253 738709 30997 5001 822 3633 0 1 3 | |
42 739295 738709 30997 5002 821 3634 0 1 3 | |
39 739334 738709 30997 5003 820 3635 0 1 3 | |
40 739374 738709 30997 5004 819 3636 0 1 3 | |
66 739440 738709 30997 5005 818 3637 0 1 3 | |
43 739483 738709 30997 5006 817 3638 0 1 3 | |
43 739526 738709 31995 5007 816 3595 0 1 3 | |
40 739566 738709 31995 5008 815 3596 0 1 3 | |
39 739605 738709 31995 5009 814 3597 0 1 3 | |
85 739690 739683 31995 5010 813 3598 0 1 3 | |
50 739740 739683 31995 5011 856 3599 0 1 3 | |
44 739784 739683 31995 5012 855 3600 0 1 3 | |
41 739825 739683 31995 5013 854 3601 0 1 3 | |
40 739865 739683 31995 5014 853 3602 0 1 3 | |
40 739905 739683 31995 5015 852 3603 0 1 3 | |
39 739944 739683 31995 5016 851 3604 0 1 3 | |
39 739983 739683 31995 5017 850 3605 0 1 3 | |
41 740024 739683 31995 5018 849 3606 0 1 3 | |
40 740064 739683 31995 5019 848 3607 0 1 3 | |
40 740104 739683 31995 5020 847 3608 0 1 3 | |
41 740145 739683 31995 5021 846 3609 0 1 3 | |
40 740185 739683 31995 5022 845 3610 0 1 3 | |
39 740224 739683 31995 5023 844 3611 0 1 3 | |
40 740264 739683 31995 5024 843 3612 0 1 3 | |
39 740303 739683 31995 5025 842 3613 0 1 3 | |
39 740342 739683 31995 5026 841 3614 0 1 3 | |
40 740382 739683 31995 5027 840 3615 0 1 3 | |
66 740448 739683 31995 5028 839 3616 0 1 3 | |
42 740490 739683 31995 5029 838 3617 0 1 3 | |
43 740533 739683 32993 5030 837 3574 0 1 3 | |
40 740573 739683 32993 5031 836 3575 0 1 3 | |
39 740612 739683 32993 5032 835 3576 0 1 3 | |
89 740701 740671 32993 5033 878 3577 0 1 3 | |
48 740749 740671 32993 5034 877 3578 0 1 3 | |
104 740853 740671 32993 5035 876 3579 0 1 3 | |
49 740902 740671 32993 5036 875 3580 0 1 3 | |
42 740944 740671 32993 5037 874 3581 0 1 3 | |
41 740985 740671 32993 5038 873 3582 0 1 3 | |
40 741025 740671 32993 5039 872 3583 0 1 3 | |
41 741066 740671 32993 5040 871 3584 0 1 3 | |
40 741106 740671 32993 5041 870 3585 0 1 3 | |
42 741148 740671 32993 5042 869 3586 0 1 3 | |
40 741188 740671 32993 5043 868 3587 0 1 3 | |
71 741259 740671 32993 5044 867 3588 0 1 3 | |
45 741304 740671 32993 5045 866 3589 0 1 3 | |
41 741345 740671 32993 5046 865 3590 0 1 3 | |
40 741385 740671 32993 5047 864 3591 0 1 3 | |
74 741459 740671 32993 5048 863 3592 0 1 3 | |
42 741501 740671 32993 5049 862 3593 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
43 741544 740671 33990 5050 861 3550 0 1 3 | |
44 741588 740671 33990 5051 860 3551 0 1 3 | |
39 741627 740671 33990 5052 859 3552 0 1 3 | |
99 741726 741709 33990 5053 902 3553 0 1 3 | |
46 741772 741709 33990 5054 901 3554 0 1 3 | |
41 741813 741709 33990 5055 900 3555 0 1 3 | |
41 741854 741709 33990 5056 899 3556 0 1 3 | |
41 741895 741709 33990 5057 898 3557 0 1 3 | |
40 741935 741709 33990 5058 897 3558 0 1 3 | |
38 741973 741709 33990 5059 896 3559 0 1 3 | |
41 742014 741709 33990 5060 895 3560 0 1 3 | |
40 742054 741709 33990 5061 894 3561 0 1 3 | |
40 742094 741709 33990 5062 893 3562 0 1 3 | |
40 742134 741709 33990 5063 892 3563 0 1 3 | |
40 742174 741709 33990 5064 891 3564 0 1 3 | |
39 742213 741709 33990 5065 890 3565 0 1 3 | |
39 742252 741709 33990 5066 889 3566 0 1 3 | |
40 742292 741709 33990 5067 888 3567 0 1 3 | |
40 742332 741709 33990 5068 887 3568 0 1 3 | |
39 742371 741709 33990 5069 886 3569 0 1 3 | |
67 742438 741709 33990 5070 885 3570 0 1 3 | |
44 742482 741709 33990 5071 884 3571 0 1 3 | |
43 742525 741709 34988 5072 883 3528 0 1 3 | |
41 742566 741709 34988 5073 882 3529 0 1 3 | |
40 742606 741709 34988 5074 881 3530 0 1 3 | |
101 742707 742699 34988 5075 880 3531 0 1 3 | |
49 742756 742699 34988 5076 923 3532 0 1 3 | |
44 742800 742699 34988 5077 922 3533 0 1 3 | |
41 742841 742699 34988 5078 921 3534 0 1 3 | |
40 742881 742699 34988 5079 920 3535 0 1 3 | |
41 742922 742699 34988 5080 919 3536 0 1 3 | |
39 742961 742699 34988 5081 918 3537 0 1 3 | |
40 743001 742699 34988 5082 917 3538 0 1 3 | |
41 743042 742699 34988 5083 916 3539 0 1 3 | |
39 743081 742699 34988 5084 915 3540 0 1 3 | |
39 743120 742699 34988 5085 914 3541 0 1 3 | |
41 743161 742699 34988 5086 913 3542 0 1 3 | |
39 743200 742699 34988 5087 912 3543 0 1 3 | |
39 743239 742699 34988 5088 911 3544 0 1 3 | |
41 743280 742699 34988 5089 910 3545 0 1 3 | |
39 743319 742699 34988 5090 909 3546 0 1 3 | |
39 743358 742699 34988 5091 908 3547 0 1 3 | |
63 743421 742699 34988 5092 907 3548 0 1 3 | |
46 743467 742699 34988 5093 906 3549 0 1 3 | |
41 743508 742699 34988 5094 905 3550 0 1 3 | |
43 743551 742699 35986 5095 904 3507 0 1 3 | |
39 743590 742699 35986 5096 903 3508 0 1 3 | |
40 743630 742699 35986 5097 902 3509 0 1 3 | |
92 743722 743705 35986 5098 945 3510 0 1 3 | |
45 743767 743705 35986 5099 944 3511 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 743808 743705 35986 5100 943 3512 0 1 3 | |
43 743851 743705 35986 5101 942 3513 0 1 3 | |
42 743893 743705 35986 5102 941 3514 0 1 3 | |
40 743933 743705 35986 5103 940 3515 0 1 3 | |
40 743973 743705 35986 5104 939 3516 0 1 3 | |
41 744014 743705 35986 5105 938 3517 0 1 3 | |
39 744053 743705 35986 5106 937 3518 0 1 3 | |
39 744092 743705 35986 5107 936 3519 0 1 3 | |
40 744132 743705 35986 5108 935 3520 0 1 3 | |
41 744173 743705 35986 5109 934 3521 0 1 3 | |
39 744212 743705 35986 5110 933 3522 0 1 3 | |
39 744251 743705 35986 5111 932 3523 0 1 3 | |
40 744291 743705 35986 5112 931 3524 0 1 3 | |
39 744330 743705 35986 5113 930 3525 0 1 3 | |
41 744371 743705 35986 5114 929 3526 0 1 3 | |
70 744441 743705 35986 5115 928 3527 0 1 3 | |
44 744485 743705 35986 5116 927 3528 0 1 3 | |
61 744546 743705 36984 5117 926 3485 0 1 3 | |
43 744589 743705 36984 5118 925 3486 0 1 3 | |
41 744630 743705 36984 5119 924 3487 0 1 3 | |
89 744719 744704 36984 5120 967 3488 0 1 3 | |
46 744765 744704 36984 5121 966 3489 0 1 3 | |
41 744806 744704 36984 5122 965 3490 0 1 3 | |
40 744846 744704 36984 5123 964 3491 0 1 3 | |
39 744885 744704 36984 5124 963 3492 0 1 3 | |
42 744927 744704 36984 5125 962 3493 0 1 3 | |
40 744967 744704 36984 5126 961 3494 0 1 3 | |
39 745006 744704 36984 5127 960 3495 0 1 3 | |
41 745047 744704 36984 5128 959 3496 0 1 3 | |
40 745087 744704 36984 5129 958 3497 0 1 3 | |
39 745126 744704 36984 5130 957 3498 0 1 3 | |
42 745168 744704 36984 5131 956 3499 0 1 3 | |
39 745207 744704 36984 5132 955 3500 0 1 3 | |
39 745246 744704 36984 5133 954 3501 0 1 3 | |
41 745287 744704 36984 5134 953 3502 0 1 3 | |
40 745327 744704 36984 5135 952 3503 0 1 3 | |
97 745424 744704 36984 5136 951 3504 0 1 3 | |
49 745473 744704 36984 5137 950 3505 0 1 3 | |
62 745535 744704 36984 5138 949 3506 0 1 3 | |
48 745583 744704 37981 5139 948 3463 0 1 3 | |
41 745624 744704 37981 5140 947 3464 0 1 3 | |
91 745715 745700 38004 5141 990 3464 0 1 3 | |
46 745761 745700 38004 5142 989 3465 0 1 3 | |
44 745805 745700 38004 5143 988 3466 0 1 3 | |
40 745845 745700 38004 5144 987 3467 0 1 3 | |
39 745884 745700 38004 5145 986 3468 0 1 3 | |
41 745925 745700 38004 5146 985 3469 0 1 3 | |
40 745965 745700 38004 5147 984 3470 0 1 3 | |
39 746004 745700 38004 5148 983 3471 0 1 3 | |
41 746045 745700 38004 5149 982 3472 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 746085 745700 38004 5150 981 3473 0 1 3 | |
44 746129 745700 38004 5151 980 3474 0 1 3 | |
42 746171 745700 38004 5152 979 3475 0 1 3 | |
40 746211 745700 38004 5153 978 3476 0 1 3 | |
40 746251 745700 38004 5154 977 3477 0 1 3 | |
41 746292 745700 38004 5155 976 3478 0 1 3 | |
40 746332 745700 38004 5156 975 3479 0 1 3 | |
39 746371 745700 38004 5157 974 3480 0 1 3 | |
66 746437 745700 38004 5158 973 3481 0 1 3 | |
43 746480 745700 38004 5159 972 3482 0 1 3 | |
43 746523 745700 39002 5160 971 3439 0 1 3 | |
40 746563 745700 39002 5161 970 3440 0 1 3 | |
40 746603 745700 39002 5162 969 3441 0 1 3 | |
79 746682 745700 39002 5163 968 3442 0 1 3 | |
54 746736 746688 39002 5164 1011 3443 0 1 3 | |
42 746778 746688 39002 5165 1010 3444 0 1 3 | |
41 746819 746688 39002 5166 1009 3445 0 1 3 | |
40 746859 746688 39002 5167 1008 3446 0 1 3 | |
40 746899 746688 39002 5168 1007 3447 0 1 3 | |
41 746940 746688 39002 5169 1006 3448 0 1 3 | |
40 746980 746688 39002 5170 1005 3449 0 1 3 | |
41 747021 746688 39002 5171 1004 3450 0 1 3 | |
40 747061 746688 39002 5172 1003 3451 0 1 3 | |
39 747100 746688 39002 5173 1002 3452 0 1 3 | |
40 747140 746688 39002 5174 1001 3453 0 1 3 | |
40 747180 746688 39002 5175 1000 3454 0 1 3 | |
40 747220 746688 39002 5176 999 3455 0 1 3 | |
40 747260 746688 39002 5177 998 3456 0 1 3 | |
41 747301 746688 39002 5178 997 3457 0 1 3 | |
39 747340 746688 39002 5179 996 3458 0 1 3 | |
39 747379 746688 39002 5180 995 3459 0 1 3 | |
65 747444 746688 39002 5181 994 3460 0 1 3 | |
42 747486 746688 39002 5182 993 3461 0 1 3 | |
43 747529 746688 40000 5183 992 3418 0 1 3 | |
40 747569 746688 40000 5184 991 3419 0 1 3 | |
39 747608 746688 40000 5185 990 3420 0 1 3 | |
86 747694 747688 40000 5186 989 3421 0 1 3 | |
50 747744 747688 40000 5187 1033 3422 0 1 3 | |
44 747788 747688 40000 5188 1032 3423 0 1 3 | |
40 747828 747688 40000 5189 1031 3424 0 1 3 | |
41 747869 747688 40000 5190 1030 3425 0 1 3 | |
42 747911 747688 40000 5191 1029 3426 0 1 3 | |
40 747951 747688 40000 5192 1028 3427 0 1 3 | |
39 747990 747688 40000 5193 1027 3428 0 1 3 | |
41 748031 747688 40000 5194 1026 3429 0 1 3 | |
41 748072 747688 40000 5195 1025 3430 0 1 3 | |
40 748112 747688 40000 5196 1024 3431 0 1 3 | |
40 748152 747688 40000 5197 1023 3432 0 1 3 | |
40 748192 747688 40000 5198 1022 3433 0 1 3 | |
40 748232 747688 40000 5199 1021 3434 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 748272 747688 40000 5200 1020 3435 0 1 3 | |
42 748314 747688 40000 5201 1019 3436 0 1 3 | |
40 748354 747688 40000 5202 1018 3437 0 1 3 | |
63 748417 747688 40000 5203 1017 3438 0 1 3 | |
46 748463 747688 40000 5204 1016 3439 0 1 3 | |
42 748505 747688 40000 5205 1015 3440 0 1 3 | |
43 748548 747688 40997 5206 1014 3397 0 1 3 | |
40 748588 747688 40997 5207 1013 3398 0 1 3 | |
39 748627 747688 40997 5208 1012 3399 0 1 3 | |
89 748716 748700 40997 5209 1055 3400 0 1 3 | |
44 748760 748700 40997 5210 1054 3401 0 1 3 | |
42 748802 748700 40997 5211 1053 3402 0 1 3 | |
41 748843 748700 40997 5212 1052 3403 0 1 3 | |
39 748882 748700 40997 5213 1051 3404 0 1 3 | |
40 748922 748700 40997 5214 1050 3405 0 1 3 | |
40 748962 748700 40997 5215 1049 3406 0 1 3 | |
40 749002 748700 40997 5216 1048 3407 0 1 3 | |
42 749044 748700 40997 5217 1047 3408 0 1 3 | |
41 749085 748700 40997 5218 1046 3409 0 1 3 | |
39 749124 748700 40997 5219 1045 3410 0 1 3 | |
42 749166 748700 40997 5220 1044 3411 0 1 3 | |
40 749206 748700 40997 5221 1043 3412 0 1 3 | |
39 749245 748700 40997 5222 1042 3413 0 1 3 | |
41 749286 748700 40997 5223 1041 3414 0 1 3 | |
39 749325 748700 40997 5224 1040 3415 0 1 3 | |
39 749364 748700 40997 5225 1039 3416 0 1 3 | |
64 749428 748700 40997 5226 1038 3417 0 1 3 | |
70 749498 748700 40997 5227 1037 3418 0 1 3 | |
49 749547 748700 41995 5228 1036 3375 0 1 3 | |
41 749588 748700 41995 5229 1035 3376 0 1 3 | |
40 749628 748700 41995 5230 1034 3377 0 1 3 | |
95 749723 749708 41995 5231 1077 3378 0 1 3 | |
47 749770 749708 41995 5232 1076 3379 0 1 3 | |
41 749811 749708 41995 5233 1075 3380 0 1 3 | |
41 749852 749708 41995 5234 1074 3381 0 1 3 | |
40 749892 749708 41995 5235 1073 3382 0 1 3 | |
41 749933 749708 41995 5236 1072 3383 0 1 3 | |
40 749973 749708 41995 5237 1071 3384 0 1 3 | |
39 750012 749708 41995 5238 1070 3385 0 1 3 | |
40 750052 749708 41995 5239 1069 3386 0 1 3 | |
40 750092 749708 41995 5240 1068 3387 0 1 3 | |
40 750132 749708 41995 5241 1067 3388 0 1 3 | |
40 750172 749708 41995 5242 1066 3389 0 1 3 | |
40 750212 749708 41995 5243 1065 3390 0 1 3 | |
40 750252 749708 41995 5244 1064 3391 0 1 3 | |
40 750292 749708 41995 5245 1063 3392 0 1 3 | |
39 750331 749708 41995 5246 1062 3393 0 1 3 | |
39 750370 749708 41995 5247 1061 3394 0 1 3 | |
67 750437 749708 41995 5248 1060 3395 0 1 3 | |
44 750481 749708 41995 5249 1059 3396 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
43 750524 749708 42993 5250 1058 3353 0 1 3 | |
43 750567 749708 42993 5251 1057 3354 0 1 3 | |
41 750608 749708 42993 5252 1056 3355 0 1 3 | |
83 750691 750685 42993 5253 1055 3356 0 1 3 | |
49 750740 750685 42993 5254 1098 3357 0 1 3 | |
85 750825 750685 42993 5255 1097 3358 0 1 3 | |
48 750873 750685 42993 5256 1096 3359 0 1 3 | |
44 750917 750685 42993 5257 1095 3360 0 1 3 | |
41 750958 750685 42993 5258 1094 3361 0 1 3 | |
39 750997 750685 42993 5259 1093 3362 0 1 3 | |
42 751039 750685 42993 5260 1092 3363 0 1 3 | |
39 751078 750685 42993 5261 1091 3364 0 1 3 | |
39 751117 750685 42993 5262 1090 3365 0 1 3 | |
41 751158 750685 42993 5263 1089 3366 0 1 3 | |
40 751198 750685 42993 5264 1088 3367 0 1 3 | |
40 751238 750685 42993 5265 1087 3368 0 1 3 | |
40 751278 750685 42993 5266 1086 3369 0 1 3 | |
40 751318 750685 42993 5267 1085 3370 0 1 3 | |
39 751357 750685 42993 5268 1084 3371 0 1 3 | |
66 751423 750685 42993 5269 1083 3372 0 1 3 | |
45 751468 750685 42993 5270 1082 3373 0 1 3 | |
42 751510 750685 42993 5271 1081 3374 0 1 3 | |
42 751552 750685 43990 5272 1080 3331 0 1 3 | |
40 751592 750685 43990 5273 1079 3332 0 1 3 | |
39 751631 750685 43990 5274 1078 3333 0 1 3 | |
95 751726 751710 43990 5275 1121 3334 0 1 3 | |
45 751771 751710 43990 5276 1120 3335 0 1 3 | |
41 751812 751710 43990 5277 1119 3336 0 1 3 | |
39 751851 751710 43990 5278 1118 3337 0 1 3 | |
40 751891 751710 43990 5279 1117 3338 0 1 3 | |
40 751931 751710 43990 5280 1116 3339 0 1 3 | |
39 751970 751710 43990 5281 1115 3340 0 1 3 | |
39 752009 751710 43990 5282 1114 3341 0 1 3 | |
41 752050 751710 43990 5283 1113 3342 0 1 3 | |
40 752090 751710 43990 5284 1112 3343 0 1 3 | |
40 752130 751710 43990 5285 1111 3344 0 1 3 | |
40 752170 751710 43990 5286 1110 3345 0 1 3 | |
40 752210 751710 43990 5287 1109 3346 0 1 3 | |
40 752250 751710 43990 5288 1108 3347 0 1 3 | |
41 752291 751710 43990 5289 1107 3348 0 1 3 | |
40 752331 751710 43990 5290 1106 3349 0 1 3 | |
40 752371 751710 43990 5291 1105 3350 0 1 3 | |
70 752441 751710 43990 5292 1104 3351 0 1 3 | |
43 752484 751710 43990 5293 1103 3352 0 1 3 | |
62 752546 751710 44988 5294 1102 3309 0 1 3 | |
44 752590 751710 44988 5295 1101 3310 0 1 3 | |
41 752631 751710 44988 5296 1100 3311 0 1 3 | |
90 752721 752706 44988 5297 1143 3312 0 1 3 | |
45 752766 752706 44988 5298 1142 3313 0 1 3 | |
41 752807 752706 44988 5299 1141 3314 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 752847 752706 44988 5300 1140 3315 0 1 3 | |
45 752892 752706 44988 5301 1139 3316 0 1 3 | |
42 752934 752706 44988 5302 1138 3317 0 1 3 | |
39 752973 752706 44988 5303 1137 3318 0 1 3 | |
41 753014 752706 44988 5304 1136 3319 0 1 3 | |
40 753054 752706 44988 5305 1135 3320 0 1 3 | |
40 753094 752706 44988 5306 1134 3321 0 1 3 | |
39 753133 752706 44988 5307 1133 3322 0 1 3 | |
42 753175 752706 44988 5308 1132 3323 0 1 3 | |
40 753215 752706 44988 5309 1131 3324 0 1 3 | |
40 753255 752706 44988 5310 1130 3325 0 1 3 | |
40 753295 752706 44988 5311 1129 3326 0 1 3 | |
40 753335 752706 44988 5312 1128 3327 0 1 3 | |
40 753375 752706 44988 5313 1127 3328 0 1 3 | |
66 753441 752706 44988 5314 1126 3329 0 1 3 | |
45 753486 752706 44988 5315 1125 3330 0 1 3 | |
42 753528 752706 45986 5316 1124 3287 0 1 3 | |
73 753601 752706 45986 5317 1123 3288 0 1 3 | |
89 753690 752706 45986 5318 1122 3289 0 1 3 | |
55 753745 753696 45986 5319 1165 3290 0 1 3 | |
45 753790 753696 45986 5320 1164 3291 0 1 3 | |
41 753831 753696 45986 5321 1163 3292 0 1 3 | |
40 753871 753696 45986 5322 1162 3293 0 1 3 | |
42 753913 753696 45986 5323 1161 3294 0 1 3 | |
39 753952 753696 45986 5324 1160 3295 0 1 3 | |
40 753992 753696 45986 5325 1159 3296 0 1 3 | |
41 754033 753696 45986 5326 1158 3297 0 1 3 | |
39 754072 753696 45986 5327 1157 3298 0 1 3 | |
39 754111 753696 45986 5328 1156 3299 0 1 3 | |
41 754152 753696 45986 5329 1155 3300 0 1 3 | |
39 754191 753696 45986 5330 1154 3301 0 1 3 | |
40 754231 753696 45986 5331 1153 3302 0 1 3 | |
41 754272 753696 45986 5332 1152 3303 0 1 3 | |
40 754312 753696 45986 5333 1151 3304 0 1 3 | |
39 754351 753696 45986 5334 1150 3305 0 1 3 | |
61 754412 753696 45986 5335 1149 3306 0 1 3 | |
47 754459 753696 45986 5336 1148 3307 0 1 3 | |
41 754500 753696 45986 5337 1147 3308 0 1 3 | |
43 754543 753696 46984 5338 1146 3265 0 1 3 | |
40 754583 753696 46984 5339 1145 3266 0 1 3 | |
40 754623 753696 46984 5340 1144 3267 0 1 3 | |
92 754715 754699 46984 5341 1187 3268 0 1 3 | |
45 754760 754699 46984 5342 1186 3269 0 1 3 | |
43 754803 754699 46984 5343 1185 3270 0 1 3 | |
40 754843 754699 46984 5344 1184 3271 0 1 3 | |
40 754883 754699 46984 5345 1183 3272 0 1 3 | |
41 754924 754699 46984 5346 1182 3273 0 1 3 | |
41 754965 754699 46984 5347 1181 3274 0 1 3 | |
40 755005 754699 46984 5348 1180 3275 0 1 3 | |
41 755046 754699 46984 5349 1179 3276 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 755087 754699 46984 5350 1178 3277 0 1 3 | |
42 755129 754699 46984 5351 1177 3278 0 1 3 | |
42 755171 754699 46984 5352 1176 3279 0 1 3 | |
40 755211 754699 46984 5353 1175 3280 0 1 3 | |
39 755250 754699 46984 5354 1174 3281 0 1 3 | |
41 755291 754699 46984 5355 1173 3282 0 1 3 | |
40 755331 754699 46984 5356 1172 3283 0 1 3 | |
38 755369 754699 46984 5357 1171 3284 0 1 3 | |
66 755435 754699 46984 5358 1170 3285 0 1 3 | |
42 755477 754699 46984 5359 1169 3286 0 1 3 | |
43 755520 754699 47981 5360 1168 3243 0 1 3 | |
41 755561 754699 47981 5361 1167 3244 0 1 3 | |
40 755601 754699 47981 5362 1166 3245 0 1 3 | |
41 755642 754699 47981 5363 1165 3246 0 1 3 | |
88 755730 755683 48004 5364 1208 3246 0 1 3 | |
44 755774 755683 48004 5365 1207 3247 0 1 3 | |
41 755815 755683 48004 5366 1206 3248 0 1 3 | |
40 755855 755683 48004 5367 1205 3249 0 1 3 | |
41 755896 755683 48004 5368 1204 3250 0 1 3 | |
40 755936 755683 48004 5369 1203 3251 0 1 3 | |
40 755976 755683 48004 5370 1202 3252 0 1 3 | |
40 756016 755683 48004 5371 1201 3253 0 1 3 | |
41 756057 755683 48004 5372 1200 3254 0 1 3 | |
39 756096 755683 48004 5373 1199 3255 0 1 3 | |
39 756135 755683 48004 5374 1198 3256 0 1 3 | |
42 756177 755683 48004 5375 1197 3257 0 1 3 | |
39 756216 755683 48004 5376 1196 3258 0 1 3 | |
39 756255 755683 48004 5377 1195 3259 0 1 3 | |
41 756296 755683 48004 5378 1194 3260 0 1 3 | |
40 756336 755683 48004 5379 1193 3261 0 1 3 | |
40 756376 755683 48004 5380 1192 3262 0 1 3 | |
64 756440 755683 48004 5381 1191 3263 0 1 3 | |
43 756483 755683 48004 5382 1190 3264 0 1 3 | |
43 756526 755683 49002 5383 1189 3221 0 1 3 | |
41 756567 755683 49002 5384 1188 3222 0 1 3 | |
40 756607 755683 49002 5385 1187 3223 0 1 3 | |
79 756686 755683 49002 5386 1186 3224 0 1 3 | |
53 756739 756692 49002 5387 1229 3225 0 1 3 | |
44 756783 756692 49002 5388 1228 3226 0 1 3 | |
41 756824 756692 49002 5389 1227 3227 0 1 3 | |
40 756864 756692 49002 5390 1226 3228 0 1 3 | |
41 756905 756692 49002 5391 1225 3229 0 1 3 | |
41 756946 756692 49002 5392 1224 3230 0 1 3 | |
40 756986 756692 49002 5393 1223 3231 0 1 3 | |
39 757025 756692 49002 5394 1222 3232 0 1 3 | |
40 757065 756692 49002 5395 1221 3233 0 1 3 | |
40 757105 756692 49002 5396 1220 3234 0 1 3 | |
41 757146 756692 49002 5397 1219 3235 0 1 3 | |
40 757186 756692 49002 5398 1218 3236 0 1 3 | |
40 757226 756692 49002 5399 1217 3237 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 757267 756692 49002 5400 1216 3238 0 1 3 | |
42 757309 756692 49002 5401 1215 3239 0 1 3 | |
39 757348 756692 49002 5402 1214 3240 0 1 3 | |
39 757387 756692 49002 5403 1213 3241 0 1 3 | |
68 757455 756692 49002 5404 1212 3242 0 1 3 | |
42 757497 756692 49002 5405 1211 3243 0 1 3 | |
43 757540 756692 50000 5406 1210 3200 0 1 3 | |
40 757580 756692 50000 5407 1209 3201 0 1 3 | |
109 757689 756692 50000 5408 1208 3202 0 1 3 | |
56 757745 757696 50000 5409 1252 3203 0 1 3 | |
45 757790 757696 50000 5410 1251 3204 0 1 3 | |
40 757830 757696 50000 5411 1250 3205 0 1 3 | |
40 757870 757696 50000 5412 1249 3206 0 1 3 | |
41 757911 757696 50000 5413 1248 3207 0 1 3 | |
40 757951 757696 50000 5414 1247 3208 0 1 3 | |
39 757990 757696 50000 5415 1246 3209 0 1 3 | |
40 758030 757696 50000 5416 1245 3210 0 1 3 | |
40 758070 757696 50000 5417 1244 3211 0 1 3 | |
41 758111 757696 50000 5418 1243 3212 0 1 3 | |
41 758152 757696 50000 5419 1242 3213 0 1 3 | |
40 758192 757696 50000 5420 1241 3214 0 1 3 | |
40 758232 757696 50000 5421 1240 3215 0 1 3 | |
40 758272 757696 50000 5422 1239 3216 0 1 3 | |
40 758312 757696 50000 5423 1238 3217 0 1 3 | |
39 758351 757696 50000 5424 1237 3218 0 1 3 | |
61 758412 757696 50000 5425 1236 3219 0 1 3 | |
48 758460 757696 50000 5426 1235 3220 0 1 3 | |
41 758501 757696 50000 5427 1234 3221 0 1 3 | |
43 758544 757696 50997 5428 1233 3178 0 1 3 | |
40 758584 757696 50997 5429 1232 3179 0 1 3 | |
40 758624 757696 50997 5430 1231 3180 0 1 3 | |
91 758715 758699 50997 5431 1274 3181 0 1 3 | |
44 758759 758699 50997 5432 1273 3182 0 1 3 | |
43 758802 758699 50997 5433 1272 3183 0 1 3 | |
41 758843 758699 50997 5434 1271 3184 0 1 3 | |
40 758883 758699 50997 5435 1270 3185 0 1 3 | |
42 758925 758699 50997 5436 1269 3186 0 1 3 | |
39 758964 758699 50997 5437 1268 3187 0 1 3 | |
39 759003 758699 50997 5438 1267 3188 0 1 3 | |
41 759044 758699 50997 5439 1266 3189 0 1 3 | |
39 759083 758699 50997 5440 1265 3190 0 1 3 | |
40 759123 758699 50997 5441 1264 3191 0 1 3 | |
40 759163 758699 50997 5442 1263 3192 0 1 3 | |
41 759204 758699 50997 5443 1262 3193 0 1 3 | |
39 759243 758699 50997 5444 1261 3194 0 1 3 | |
41 759284 758699 50997 5445 1260 3195 0 1 3 | |
40 759324 758699 50997 5446 1259 3196 0 1 3 | |
39 759363 758699 50997 5447 1258 3197 0 1 3 | |
63 759426 758699 50997 5448 1257 3198 0 1 3 | |
45 759471 758699 50997 5449 1256 3199 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 759511 758699 50997 5450 1255 3200 0 1 3 | |
46 759557 758699 51995 5451 1254 3157 0 1 3 | |
40 759597 758699 51995 5452 1253 3158 0 1 3 | |
40 759637 758699 51995 5453 1252 3159 0 1 3 | |
88 759725 759711 51995 5454 1295 3160 0 1 3 | |
47 759772 759711 51995 5455 1294 3161 0 1 3 | |
41 759813 759711 51995 5456 1293 3162 0 1 3 | |
40 759853 759711 51995 5457 1292 3163 0 1 3 | |
40 759893 759711 51995 5458 1291 3164 0 1 3 | |
40 759933 759711 51995 5459 1290 3165 0 1 3 | |
38 759971 759711 51995 5460 1289 3166 0 1 3 | |
40 760011 759711 51995 5461 1288 3167 0 1 3 | |
40 760051 759711 51995 5462 1287 3168 0 1 3 | |
39 760090 759711 51995 5463 1286 3169 0 1 3 | |
39 760129 759711 51995 5464 1285 3170 0 1 3 | |
42 760171 759711 51995 5465 1284 3171 0 1 3 | |
39 760210 759711 51995 5466 1283 3172 0 1 3 | |
40 760250 759711 51995 5467 1282 3173 0 1 3 | |
41 760291 759711 51995 5468 1281 3174 0 1 3 | |
40 760331 759711 51995 5469 1280 3175 0 1 3 | |
40 760371 759711 51995 5470 1279 3176 0 1 3 | |
69 760440 759711 51995 5471 1278 3177 0 1 3 | |
43 760483 759711 51995 5472 1277 3178 0 1 3 | |
63 760546 759711 52993 5473 1276 3135 0 1 3 | |
45 760591 759711 52993 5474 1275 3136 0 1 3 | |
42 760633 759711 52993 5475 1274 3137 0 1 3 | |
91 760724 760708 52993 5476 1317 3138 0 1 3 | |
45 760769 760708 52993 5477 1316 3139 0 1 3 | |
89 760858 760708 52993 5478 1315 3140 0 1 3 | |
45 760903 760708 52993 5479 1314 3141 0 1 3 | |
40 760943 760708 52993 5480 1313 3142 0 1 3 | |
40 760983 760708 52993 5481 1312 3143 0 1 3 | |
41 761024 760708 52993 5482 1311 3144 0 1 3 | |
39 761063 760708 52993 5483 1310 3145 0 1 3 | |
39 761102 760708 52993 5484 1309 3146 0 1 3 | |
41 761143 760708 52993 5485 1308 3147 0 1 3 | |
40 761183 760708 52993 5486 1307 3148 0 1 3 | |
40 761223 760708 52993 5487 1306 3149 0 1 3 | |
39 761262 760708 52993 5488 1305 3150 0 1 3 | |
41 761303 760708 52993 5489 1304 3151 0 1 3 | |
40 761343 760708 52993 5490 1303 3152 0 1 3 | |
40 761383 760708 52993 5491 1302 3153 0 1 3 | |
68 761451 760708 52993 5492 1301 3154 0 1 3 | |
42 761493 760708 52993 5493 1300 3155 0 1 3 | |
43 761536 760708 53990 5494 1299 3112 0 1 3 | |
40 761576 760708 53990 5495 1298 3113 0 1 3 | |
40 761616 760708 53990 5496 1297 3114 0 1 3 | |
89 761705 761688 53990 5497 1340 3115 0 1 3 | |
47 761752 761688 53990 5498 1339 3116 0 1 3 | |
72 761824 761688 53990 5499 1338 3117 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
45 761869 761688 53990 5500 1337 3118 0 1 3 | |
48 761917 761688 53990 5501 1336 3119 0 1 3 | |
41 761958 761688 53990 5502 1335 3120 0 1 3 | |
39 761997 761688 53990 5503 1334 3121 0 1 3 | |
42 762039 761688 53990 5504 1333 3122 0 1 3 | |
39 762078 761688 53990 5505 1332 3123 0 1 3 | |
40 762118 761688 53990 5506 1331 3124 0 1 3 | |
40 762158 761688 53990 5507 1330 3125 0 1 3 | |
40 762198 761688 53990 5508 1329 3126 0 1 3 | |
38 762236 761688 53990 5509 1328 3127 0 1 3 | |
40 762276 761688 53990 5510 1327 3128 0 1 3 | |
40 762316 761688 53990 5511 1326 3129 0 1 3 | |
40 762356 761688 53990 5512 1325 3130 0 1 3 | |
65 762421 761688 53990 5513 1324 3131 0 1 3 | |
47 762468 761688 53990 5514 1323 3132 0 1 3 | |
40 762508 761688 53990 5515 1322 3133 0 1 3 | |
42 762550 761688 54988 5516 1321 3090 0 1 3 | |
40 762590 761688 54988 5517 1320 3091 0 1 3 | |
40 762630 761688 54988 5518 1319 3092 0 1 3 | |
92 762722 762706 54988 5519 1362 3093 0 1 3 | |
47 762769 762706 54988 5520 1361 3094 0 1 3 | |
41 762810 762706 54988 5521 1360 3095 0 1 3 | |
41 762851 762706 54988 5522 1359 3096 0 1 3 | |
42 762893 762706 54988 5523 1358 3097 0 1 3 | |
40 762933 762706 54988 5524 1357 3098 0 1 3 | |
39 762972 762706 54988 5525 1356 3099 0 1 3 | |
39 763011 762706 54988 5526 1355 3100 0 1 3 | |
41 763052 762706 54988 5527 1354 3101 0 1 3 | |
38 763090 762706 54988 5528 1353 3102 0 1 3 | |
39 763129 762706 54988 5529 1352 3103 0 1 3 | |
41 763170 762706 54988 5530 1351 3104 0 1 3 | |
39 763209 762706 54988 5531 1350 3105 0 1 3 | |
38 763247 762706 54988 5532 1349 3106 0 1 3 | |
41 763288 762706 54988 5533 1348 3107 0 1 3 | |
39 763327 762706 54988 5534 1347 3108 0 1 3 | |
39 763366 762706 54988 5535 1346 3109 0 1 3 | |
63 763429 762706 54988 5536 1345 3110 0 1 3 | |
45 763474 762706 54988 5537 1344 3111 0 1 3 | |
40 763514 762706 54988 5538 1343 3112 0 1 3 | |
42 763556 762706 55986 5539 1342 3069 0 1 3 | |
40 763596 762706 55986 5540 1341 3070 0 1 3 | |
39 763635 762706 55986 5541 1340 3071 0 1 3 | |
87 763722 763707 55986 5542 1383 3072 0 1 3 | |
46 763768 763707 55986 5543 1382 3073 0 1 3 | |
42 763810 763707 55986 5544 1381 3074 0 1 3 | |
41 763851 763707 55986 5545 1380 3075 0 1 3 | |
41 763892 763707 55986 5546 1379 3076 0 1 3 | |
41 763933 763707 55986 5547 1378 3077 0 1 3 | |
39 763972 763707 55986 5548 1377 3078 0 1 3 | |
39 764011 763707 55986 5549 1376 3079 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 764051 763707 55986 5550 1375 3080 0 1 3 | |
43 764094 763707 55986 5551 1374 3081 0 1 3 | |
41 764135 763707 55986 5552 1373 3082 0 1 3 | |
40 764175 763707 55986 5553 1372 3083 0 1 3 | |
40 764215 763707 55986 5554 1371 3084 0 1 3 | |
40 764255 763707 55986 5555 1370 3085 0 1 3 | |
40 764295 763707 55986 5556 1369 3086 0 1 3 | |
40 764335 763707 55986 5557 1368 3087 0 1 3 | |
39 764374 763707 55986 5558 1367 3088 0 1 3 | |
65 764439 763707 55986 5559 1366 3089 0 1 3 | |
44 764483 763707 55986 5560 1365 3090 0 1 3 | |
43 764526 763707 56984 5561 1364 3047 0 1 3 | |
42 764568 763707 56984 5562 1363 3048 0 1 3 | |
40 764608 763707 56984 5563 1362 3049 0 1 3 | |
82 764690 764683 56984 5564 1361 3050 0 1 3 | |
50 764740 764683 56984 5565 1404 3051 0 1 3 | |
45 764785 764683 56984 5566 1403 3052 0 1 3 | |
41 764826 764683 56984 5567 1402 3053 0 1 3 | |
39 764865 764683 56984 5568 1401 3054 0 1 3 | |
42 764907 764683 56984 5569 1400 3055 0 1 3 | |
39 764946 764683 56984 5570 1399 3056 0 1 3 | |
40 764986 764683 56984 5571 1398 3057 0 1 3 | |
41 765027 764683 56984 5572 1397 3058 0 1 3 | |
39 765066 764683 56984 5573 1396 3059 0 1 3 | |
40 765106 764683 56984 5574 1395 3060 0 1 3 | |
40 765146 764683 56984 5575 1394 3061 0 1 3 | |
40 765186 764683 56984 5576 1393 3062 0 1 3 | |
39 765225 764683 56984 5577 1392 3063 0 1 3 | |
41 765266 764683 56984 5578 1391 3064 0 1 3 | |
40 765306 764683 56984 5579 1390 3065 0 1 3 | |
39 765345 764683 56984 5580 1389 3066 0 1 3 | |
40 765385 764683 56984 5581 1388 3067 0 1 3 | |
67 765452 764683 56984 5582 1387 3068 0 1 3 | |
42 765494 764683 56984 5583 1386 3069 0 1 3 | |
43 765537 764683 57981 5584 1385 3026 0 1 3 | |
41 765578 764683 57981 5585 1384 3027 0 1 3 | |
39 765617 764683 57981 5586 1383 3028 0 1 3 | |
88 765705 765689 58004 5587 1426 3028 0 1 3 | |
46 765751 765689 58004 5588 1425 3029 0 1 3 | |
69 765820 765689 58004 5589 1424 3030 0 1 3 | |
45 765865 765689 58004 5590 1423 3031 0 1 3 | |
43 765908 765689 58004 5591 1422 3032 0 1 3 | |
39 765947 765689 58004 5592 1421 3033 0 1 3 | |
41 765988 765689 58004 5593 1420 3034 0 1 3 | |
41 766029 765689 58004 5594 1419 3035 0 1 3 | |
40 766069 765689 58004 5595 1418 3036 0 1 3 | |
40 766109 765689 58004 5596 1417 3037 0 1 3 | |
40 766149 765689 58004 5597 1416 3038 0 1 3 | |
40 766189 765689 58004 5598 1415 3039 0 1 3 | |
39 766228 765689 58004 5599 1414 3040 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 766268 765689 58004 5600 1413 3041 0 1 3 | |
43 766311 765689 58004 5601 1412 3042 0 1 3 | |
41 766352 765689 58004 5602 1411 3043 0 1 3 | |
61 766413 765689 58004 5603 1410 3044 0 1 3 | |
48 766461 765689 58004 5604 1409 3045 0 1 3 | |
41 766502 765689 58004 5605 1408 3046 0 1 3 | |
43 766545 765689 59002 5606 1407 3003 0 1 3 | |
40 766585 765689 59002 5607 1406 3004 0 1 3 | |
40 766625 765689 59002 5608 1405 3005 0 1 3 | |
92 766717 766702 59002 5609 1448 3006 0 1 3 | |
45 766762 766702 59002 5610 1447 3007 0 1 3 | |
44 766806 766702 59002 5611 1446 3008 0 1 3 | |
41 766847 766702 59002 5612 1445 3009 0 1 3 | |
40 766887 766702 59002 5613 1444 3010 0 1 3 | |
41 766928 766702 59002 5614 1443 3011 0 1 3 | |
40 766968 766702 59002 5615 1442 3012 0 1 3 | |
39 767007 766702 59002 5616 1441 3013 0 1 3 | |
40 767047 766702 59002 5617 1440 3014 0 1 3 | |
40 767087 766702 59002 5618 1439 3015 0 1 3 | |
40 767127 766702 59002 5619 1438 3016 0 1 3 | |
41 767168 766702 59002 5620 1437 3017 0 1 3 | |
39 767207 766702 59002 5621 1436 3018 0 1 3 | |
39 767246 766702 59002 5622 1435 3019 0 1 3 | |
41 767287 766702 59002 5623 1434 3020 0 1 3 | |
40 767327 766702 59002 5624 1433 3021 0 1 3 | |
40 767367 766702 59002 5625 1432 3022 0 1 3 | |
63 767430 766702 59002 5626 1431 3023 0 1 3 | |
45 767475 766702 59002 5627 1430 3024 0 1 3 | |
43 767518 766702 59002 5628 1429 3025 0 1 3 | |
41 767559 766702 60000 5629 1428 2982 0 1 3 | |
40 767599 766702 60000 5630 1427 2983 0 1 3 | |
39 767638 766702 60000 5631 1426 2984 0 1 3 | |
88 767726 767712 60000 5632 1470 2985 0 1 3 | |
46 767772 767712 60000 5633 1469 2986 0 1 3 | |
42 767814 767712 60000 5634 1468 2987 0 1 3 | |
40 767854 767712 60000 5635 1467 2988 0 1 3 | |
41 767895 767712 60000 5636 1466 2989 0 1 3 | |
41 767936 767712 60000 5637 1465 2990 0 1 3 | |
40 767976 767712 60000 5638 1464 2991 0 1 3 | |
41 768017 767712 60000 5639 1463 2992 0 1 3 | |
39 768056 767712 60000 5640 1462 2993 0 1 3 | |
40 768096 767712 60000 5641 1461 2994 0 1 3 | |
40 768136 767712 60000 5642 1460 2995 0 1 3 | |
41 768177 767712 60000 5643 1459 2996 0 1 3 | |
40 768217 767712 60000 5644 1458 2997 0 1 3 | |
39 768256 767712 60000 5645 1457 2998 0 1 3 | |
39 768295 767712 60000 5646 1456 2999 0 1 3 | |
39 768334 767712 60000 5647 1455 3000 0 1 3 | |
39 768373 767712 60000 5648 1454 3001 0 1 3 | |
71 768444 767712 60000 5649 1453 3002 0 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
44 768488 767712 60000 5650 1452 3003 0 1 3 | |
65 768553 767712 60997 5651 1451 2960 0 1 3 | |
45 768598 767712 60997 5652 1450 2961 0 1 3 | |
41 768639 767712 60997 5653 1449 2962 0 1 3 | |
94 768733 768718 60997 5654 1492 2963 0 1 3 | |
45 768778 768718 60997 5655 1491 2964 4 1 3 | |
42 768820 768718 60997 5656 1490 2965 4 1 3 | |
40 768860 768718 60997 5657 1489 2966 4 1 3 | |
41 768901 768718 60997 5658 1488 2967 4 1 3 | |
40 768941 768718 60997 5659 1487 2968 4 1 3 | |
39 768980 768718 60997 5660 1486 2969 4 1 3 | |
41 769021 768718 60997 5661 1485 2970 4 1 3 | |
40 769061 768718 60997 5662 1484 2971 4 1 3 | |
40 769101 768718 60997 5663 1483 2972 4 1 3 | |
39 769140 768718 60997 5664 1482 2973 4 1 3 | |
40 769180 768718 60997 5665 1481 2974 4 1 3 | |
40 769220 768718 60997 5666 1480 2975 4 1 3 | |
39 769259 768718 60997 5667 1479 2976 4 1 3 | |
40 769299 768718 60997 5668 1478 2977 4 1 3 | |
40 769339 768718 60997 5669 1477 2978 4 1 3 | |
39 769378 768718 60997 5670 1476 2979 4 1 3 | |
66 769444 768718 60997 5671 1475 2980 4 1 3 | |
43 769487 768718 60997 5672 1474 2981 4 1 3 | |
43 769530 768718 61995 5673 1473 2938 4 1 3 | |
40 769570 768718 61995 5674 1472 2939 4 1 3 | |
41 769611 768718 61995 5675 1471 2940 4 1 3 | |
84 769695 769689 61995 5676 1470 2941 4 1 3 | |
48 769743 769689 61995 5677 1513 2942 4 1 3 | |
43 769786 769689 61995 5678 1512 2943 4 1 3 | |
41 769827 769689 61995 5679 1511 2944 4 1 3 | |
66 769893 769689 61995 5680 1510 2945 4 1 3 | |
44 769937 769689 61995 5681 1509 2946 4 1 3 | |
40 769977 769689 61995 5682 1508 2947 4 1 3 | |
42 770019 769689 61995 5683 1507 2948 4 1 3 | |
40 770059 769689 61995 5684 1506 2949 4 1 3 | |
39 770098 769689 61995 5685 1505 2950 4 1 3 | |
40 770138 769689 61995 5686 1504 2951 4 1 3 | |
41 770179 769689 61995 5687 1503 2952 4 1 3 | |
39 770218 769689 61995 5688 1502 2953 4 1 3 | |
39 770257 769689 61995 5689 1501 2954 4 1 3 | |
41 770298 769689 61995 5690 1500 2955 4 1 3 | |
40 770338 769689 61995 5691 1499 2956 4 1 3 | |
39 770377 769689 61995 5692 1498 2957 4 1 3 | |
68 770445 769689 61995 5693 1497 2958 4 1 3 | |
44 770489 769689 61995 5694 1496 2959 4 1 3 | |
43 770532 769689 62993 5695 1495 2916 4 1 3 | |
42 770574 769689 62993 5696 1494 2917 4 1 3 | |
39 770613 769689 62993 5697 1493 2918 4 1 3 | |
91 770704 770697 62993 5698 1492 2919 4 1 3 | |
48 770752 770697 62993 5699 1535 2920 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
94 770846 770697 62993 5700 1534 2921 4 1 3 | |
50 770896 770697 62993 5701 1533 2922 4 1 3 | |
42 770938 770697 62993 5702 1532 2923 4 1 3 | |
39 770977 770697 62993 5703 1531 2924 4 1 3 | |
41 771018 770697 62993 5704 1530 2925 4 1 3 | |
40 771058 770697 62993 5705 1529 2926 4 1 3 | |
39 771097 770697 62993 5706 1528 2927 4 1 3 | |
39 771136 770697 62993 5707 1527 2928 4 1 3 | |
40 771176 770697 62993 5708 1526 2929 4 1 3 | |
40 771216 770697 62993 5709 1525 2930 4 1 3 | |
40 771256 770697 62993 5710 1524 2931 4 1 3 | |
41 771297 770697 62993 5711 1523 2932 4 1 3 | |
39 771336 770697 62993 5712 1522 2933 4 1 3 | |
39 771375 770697 62993 5713 1521 2934 4 1 3 | |
69 771444 770697 62993 5714 1520 2935 4 1 3 | |
44 771488 770697 62993 5715 1519 2936 4 1 3 | |
43 771531 770697 63990 5716 1518 2893 4 1 3 | |
40 771571 770697 63990 5717 1517 2894 4 1 3 | |
40 771611 770697 63990 5718 1516 2895 4 1 3 | |
87 771698 771692 63990 5719 1515 2896 4 1 3 | |
50 771748 771692 63990 5720 1558 2897 4 1 3 | |
45 771793 771692 63990 5721 1557 2898 4 1 3 | |
41 771834 771692 63990 5722 1556 2899 4 1 3 | |
39 771873 771692 63990 5723 1555 2900 4 1 3 | |
43 771916 771692 63990 5724 1554 2901 4 1 3 | |
40 771956 771692 63990 5725 1553 2902 4 1 3 | |
39 771995 771692 63990 5726 1552 2903 4 1 3 | |
42 772037 771692 63990 5727 1551 2904 4 1 3 | |
39 772076 771692 63990 5728 1550 2905 4 1 3 | |
41 772117 771692 63990 5729 1549 2906 4 1 3 | |
41 772158 771692 63990 5730 1548 2907 4 1 3 | |
39 772197 771692 63990 5731 1547 2908 4 1 3 | |
39 772236 771692 63990 5732 1546 2909 4 1 3 | |
41 772277 771692 63990 5733 1545 2910 4 1 3 | |
40 772317 771692 63990 5734 1544 2911 4 1 3 | |
40 772357 771692 63990 5735 1543 2912 4 1 3 | |
62 772419 771692 63990 5736 1542 2913 4 1 3 | |
47 772466 771692 63990 5737 1541 2914 4 1 3 | |
41 772507 771692 63990 5738 1540 2915 4 1 3 | |
42 772549 771692 64988 5739 1539 2872 4 1 3 | |
40 772589 771692 64988 5740 1538 2873 4 1 3 | |
40 772629 771692 64988 5741 1537 2874 4 1 3 | |
92 772721 772704 64988 5742 1580 2875 4 1 3 | |
47 772768 772704 64988 5743 1579 2876 4 1 3 | |
42 772810 772704 64988 5744 1578 2877 4 1 3 | |
39 772849 772704 64988 5745 1577 2878 4 1 3 | |
41 772890 772704 64988 5746 1576 2879 4 1 3 | |
41 772931 772704 64988 5747 1575 2880 4 1 3 | |
39 772970 772704 64988 5748 1574 2881 4 1 3 | |
40 773010 772704 64988 5749 1573 2882 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 773050 772704 64988 5750 1572 2883 4 1 3 | |
43 773093 772704 64988 5751 1571 2884 4 1 3 | |
41 773134 772704 64988 5752 1570 2885 4 1 3 | |
41 773175 772704 64988 5753 1569 2886 4 1 3 | |
41 773216 772704 64988 5754 1568 2887 4 1 3 | |
39 773255 772704 64988 5755 1567 2888 4 1 3 | |
42 773297 772704 64988 5756 1566 2889 4 1 3 | |
40 773337 772704 64988 5757 1565 2890 4 1 3 | |
39 773376 772704 64988 5758 1564 2891 4 1 3 | |
68 773444 772704 64988 5759 1563 2892 4 1 3 | |
44 773488 772704 64988 5760 1562 2893 4 1 3 | |
43 773531 772704 65986 5761 1561 2850 4 1 3 | |
41 773572 772704 65986 5762 1560 2851 4 1 3 | |
40 773612 772704 65986 5763 1559 2852 4 1 3 | |
91 773703 773676 65986 5764 1602 2853 4 1 3 | |
48 773751 773676 65986 5765 1601 2854 4 1 3 | |
44 773795 773676 65986 5766 1600 2855 4 1 3 | |
40 773835 773676 65986 5767 1599 2856 4 1 3 | |
40 773875 773676 65986 5768 1598 2857 4 1 3 | |
41 773916 773676 65986 5769 1597 2858 4 1 3 | |
72 773988 773676 65986 5770 1596 2859 4 1 3 | |
44 774032 773676 65986 5771 1595 2860 4 1 3 | |
42 774074 773676 65986 5772 1594 2861 4 1 3 | |
40 774114 773676 65986 5773 1593 2862 4 1 3 | |
41 774155 773676 65986 5774 1592 2863 4 1 3 | |
40 774195 773676 65986 5775 1591 2864 4 1 3 | |
39 774234 773676 65986 5776 1590 2865 4 1 3 | |
41 774275 773676 65986 5777 1589 2866 4 1 3 | |
41 774316 773676 65986 5778 1588 2867 4 1 3 | |
39 774355 773676 65986 5779 1587 2868 4 1 3 | |
64 774419 773676 65986 5780 1586 2869 4 1 3 | |
49 774468 773676 65986 5781 1585 2870 4 1 3 | |
41 774509 773676 65986 5782 1584 2871 4 1 3 | |
42 774551 773676 66984 5783 1583 2828 4 1 3 | |
41 774592 773676 66984 5784 1582 2829 4 1 3 | |
40 774632 773676 66984 5785 1581 2830 4 1 3 | |
89 774721 774705 66984 5786 1624 2831 4 1 3 | |
47 774768 774705 66984 5787 1623 2832 4 1 3 | |
41 774809 774705 66984 5788 1622 2833 4 1 3 | |
40 774849 774705 66984 5789 1621 2834 4 1 3 | |
39 774888 774705 66984 5790 1620 2835 4 1 3 | |
40 774928 774705 66984 5791 1619 2836 4 1 3 | |
41 774969 774705 66984 5792 1618 2837 4 1 3 | |
39 775008 774705 66984 5793 1617 2838 4 1 3 | |
41 775049 774705 66984 5794 1616 2839 4 1 3 | |
40 775089 774705 66984 5795 1615 2840 4 1 3 | |
40 775129 774705 66984 5796 1614 2841 4 1 3 | |
40 775169 774705 66984 5797 1613 2842 4 1 3 | |
41 775210 774705 66984 5798 1612 2843 4 1 3 | |
40 775250 774705 66984 5799 1611 2844 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
42 775292 774705 66984 5800 1610 2845 4 1 3 | |
43 775335 774705 66984 5801 1609 2846 4 1 3 | |
39 775374 774705 66984 5802 1608 2847 4 1 3 | |
67 775441 774705 66984 5803 1607 2848 4 1 3 | |
45 775486 774705 66984 5804 1606 2849 4 1 3 | |
43 775529 774705 67981 5805 1605 2806 4 1 3 | |
41 775570 774705 67981 5806 1604 2807 4 1 3 | |
40 775610 774705 67981 5807 1603 2808 4 1 3 | |
85 775695 775688 68004 5808 1602 2808 4 1 3 | |
50 775745 775688 68004 5809 1645 2809 4 1 3 | |
44 775789 775688 68004 5810 1644 2810 4 1 3 | |
40 775829 775688 68004 5811 1643 2811 4 1 3 | |
41 775870 775688 68004 5812 1642 2812 4 1 3 | |
40 775910 775688 68004 5813 1641 2813 4 1 3 | |
40 775950 775688 68004 5814 1640 2814 4 1 3 | |
39 775989 775688 68004 5815 1639 2815 4 1 3 | |
41 776030 775688 68004 5816 1638 2816 4 1 3 | |
40 776070 775688 68004 5817 1637 2817 4 1 3 | |
39 776109 775688 68004 5818 1636 2818 4 1 3 | |
41 776150 775688 68004 5819 1635 2819 4 1 3 | |
40 776190 775688 68004 5820 1634 2820 4 1 3 | |
39 776229 775688 68004 5821 1633 2821 4 1 3 | |
41 776270 775688 68004 5822 1632 2822 4 1 3 | |
39 776309 775688 68004 5823 1631 2823 4 1 3 | |
40 776349 775688 68004 5824 1630 2824 4 1 3 | |
39 776388 775688 68004 5825 1629 2825 4 1 3 | |
71 776459 775688 68004 5826 1628 2826 4 1 3 | |
43 776502 775688 68004 5827 1627 2827 4 1 3 | |
64 776566 775688 69002 5828 1626 2784 4 1 3 | |
42 776608 775688 69002 5829 1625 2785 4 1 3 | |
84 776692 776685 69002 5830 1624 2786 4 1 3 | |
49 776741 776685 69002 5831 1667 2787 4 1 3 | |
44 776785 776685 69002 5832 1666 2788 4 1 3 | |
42 776827 776685 69002 5833 1665 2789 4 1 3 | |
40 776867 776685 69002 5834 1664 2790 4 1 3 | |
42 776909 776685 69002 5835 1663 2791 4 1 3 | |
39 776948 776685 69002 5836 1662 2792 4 1 3 | |
40 776988 776685 69002 5837 1661 2793 4 1 3 | |
41 777029 776685 69002 5838 1660 2794 4 1 3 | |
40 777069 776685 69002 5839 1659 2795 4 1 3 | |
41 777110 776685 69002 5840 1658 2796 4 1 3 | |
40 777150 776685 69002 5841 1657 2797 4 1 3 | |
40 777190 776685 69002 5842 1656 2798 4 1 3 | |
39 777229 776685 69002 5843 1655 2799 4 1 3 | |
41 777270 776685 69002 5844 1654 2800 4 1 3 | |
40 777310 776685 69002 5845 1653 2801 4 1 3 | |
40 777350 776685 69002 5846 1652 2802 4 1 3 | |
39 777389 776685 69002 5847 1651 2803 4 1 3 | |
67 777456 776685 69002 5848 1650 2804 4 1 3 | |
42 777498 776685 69002 5849 1649 2805 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
44 777542 776685 70000 5850 1648 2762 4 1 3 | |
43 777585 776685 70000 5851 1647 2763 4 1 3 | |
40 777625 776685 70000 5852 1646 2764 4 1 3 | |
90 777715 777699 70000 5853 1690 2765 4 1 3 | |
47 777762 777699 70000 5854 1689 2766 4 1 3 | |
44 777806 777699 70000 5855 1688 2767 4 1 3 | |
40 777846 777699 70000 5856 1687 2768 4 1 3 | |
39 777885 777699 70000 5857 1686 2769 4 1 3 | |
42 777927 777699 70000 5858 1685 2770 4 1 3 | |
40 777967 777699 70000 5859 1684 2771 4 1 3 | |
65 778032 777699 70000 5860 1683 2772 4 1 3 | |
43 778075 777699 70000 5861 1682 2773 4 1 3 | |
40 778115 777699 70000 5862 1681 2774 4 1 3 | |
42 778157 777699 70000 5863 1680 2775 4 1 3 | |
40 778197 777699 70000 5864 1679 2776 4 1 3 | |
39 778236 777699 70000 5865 1678 2777 4 1 3 | |
42 778278 777699 70000 5866 1677 2778 4 1 3 | |
40 778318 777699 70000 5867 1676 2779 4 1 3 | |
40 778358 777699 70000 5868 1675 2780 4 1 3 | |
65 778423 777699 70000 5869 1674 2781 4 1 3 | |
47 778470 777699 70000 5870 1673 2782 4 1 3 | |
41 778511 777699 70000 5871 1672 2783 4 1 3 | |
44 778555 777699 70997 5872 1671 2740 4 1 3 | |
41 778596 777699 70997 5873 1670 2741 4 1 3 | |
40 778636 777699 70997 5874 1669 2742 4 1 3 | |
95 778731 778715 70997 5875 1712 2743 4 1 3 | |
46 778777 778715 70997 5876 1711 2744 4 1 3 | |
42 778819 778715 70997 5877 1710 2745 4 1 3 | |
41 778860 778715 70997 5878 1709 2746 4 1 3 | |
41 778901 778715 70997 5879 1708 2747 4 1 3 | |
39 778940 778715 70997 5880 1707 2748 4 1 3 | |
40 778980 778715 70997 5881 1706 2749 4 1 3 | |
40 779020 778715 70997 5882 1705 2750 4 1 3 | |
40 779060 778715 70997 5883 1704 2751 4 1 3 | |
40 779100 778715 70997 5884 1703 2752 4 1 3 | |
40 779140 778715 70997 5885 1702 2753 4 1 3 | |
40 779180 778715 70997 5886 1701 2754 4 1 3 | |
40 779220 778715 70997 5887 1700 2755 4 1 3 | |
40 779260 778715 70997 5888 1699 2756 4 1 3 | |
41 779301 778715 70997 5889 1698 2757 4 1 3 | |
39 779340 778715 70997 5890 1697 2758 4 1 3 | |
40 779380 778715 70997 5891 1696 2759 4 1 3 | |
65 779445 778715 70997 5892 1695 2760 4 1 3 | |
44 779489 778715 70997 5893 1694 2761 4 1 3 | |
42 779531 778715 71995 5894 1693 2718 4 1 3 | |
40 779571 778715 71995 5895 1692 2719 4 1 3 | |
40 779611 778715 71995 5896 1691 2720 4 1 3 | |
83 779694 779687 71995 5897 1690 2721 4 1 3 | |
50 779744 779687 71995 5898 1733 2722 4 1 3 | |
45 779789 779687 71995 5899 1732 2723 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 779829 779687 71995 5900 1731 2724 4 1 3 | |
43 779872 779687 71995 5901 1730 2725 4 1 3 | |
43 779915 779687 71995 5902 1729 2726 4 1 3 | |
40 779955 779687 71995 5903 1728 2727 4 1 3 | |
39 779994 779687 71995 5904 1727 2728 4 1 3 | |
40 780034 779687 71995 5905 1726 2729 4 1 3 | |
39 780073 779687 71995 5906 1725 2730 4 1 3 | |
40 780113 779687 71995 5907 1724 2731 4 1 3 | |
41 780154 779687 71995 5908 1723 2732 4 1 3 | |
39 780193 779687 71995 5909 1722 2733 4 1 3 | |
40 780233 779687 71995 5910 1721 2734 4 1 3 | |
41 780274 779687 71995 5911 1720 2735 4 1 3 | |
40 780314 779687 71995 5912 1719 2736 4 1 3 | |
39 780353 779687 71995 5913 1718 2737 4 1 3 | |
39 780392 779687 71995 5914 1717 2738 4 1 3 | |
67 780459 779687 71995 5915 1716 2739 4 1 3 | |
42 780501 779687 71995 5916 1715 2740 4 1 3 | |
43 780544 779687 72993 5917 1714 2697 4 1 3 | |
40 780584 779687 72993 5918 1713 2698 4 1 3 | |
39 780623 779687 72993 5919 1712 2699 4 1 3 | |
86 780709 780693 72993 5920 1755 2700 4 1 3 | |
47 780756 780693 72993 5921 1754 2701 4 1 3 | |
87 780843 780693 72993 5922 1753 2702 4 1 3 | |
46 780889 780693 72993 5923 1752 2703 4 1 3 | |
41 780930 780693 72993 5924 1751 2704 4 1 3 | |
40 780970 780693 72993 5925 1750 2705 4 1 3 | |
39 781009 780693 72993 5926 1749 2706 4 1 3 | |
42 781051 780693 72993 5927 1748 2707 4 1 3 | |
39 781090 780693 72993 5928 1747 2708 4 1 3 | |
40 781130 780693 72993 5929 1746 2709 4 1 3 | |
41 781171 780693 72993 5930 1745 2710 4 1 3 | |
39 781210 780693 72993 5931 1744 2711 4 1 3 | |
39 781249 780693 72993 5932 1743 2712 4 1 3 | |
42 781291 780693 72993 5933 1742 2713 4 1 3 | |
39 781330 780693 72993 5934 1741 2714 4 1 3 | |
40 781370 780693 72993 5935 1740 2715 4 1 3 | |
65 781435 780693 72993 5936 1739 2716 4 1 3 | |
45 781480 780693 72993 5937 1738 2717 4 1 3 | |
43 781523 780693 73990 5938 1737 2674 4 1 3 | |
41 781564 780693 73990 5939 1736 2675 4 1 3 | |
40 781604 780693 73990 5940 1735 2676 4 1 3 | |
40 781644 780693 73990 5941 1734 2677 4 1 3 | |
96 781740 781690 73990 5942 1777 2678 4 1 3 | |
44 781784 781690 73990 5943 1776 2679 4 1 3 | |
42 781826 781690 73990 5944 1775 2680 4 1 3 | |
39 781865 781690 73990 5945 1774 2681 4 1 3 | |
42 781907 781690 73990 5946 1773 2682 4 1 3 | |
40 781947 781690 73990 5947 1772 2683 4 1 3 | |
39 781986 781690 73990 5948 1771 2684 4 1 3 | |
42 782028 781690 73990 5949 1770 2685 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 782068 781690 73990 5950 1769 2686 4 1 3 | |
76 782144 781690 73990 5951 1768 2687 4 1 3 | |
44 782188 781690 73990 5952 1767 2688 4 1 3 | |
42 782230 781690 73990 5953 1766 2689 4 1 3 | |
41 782271 781690 73990 5954 1765 2690 4 1 3 | |
40 782311 781690 73990 5955 1764 2691 4 1 3 | |
41 782352 781690 73990 5956 1763 2692 4 1 3 | |
40 782392 781690 73990 5957 1762 2693 4 1 3 | |
71 782463 781690 73990 5958 1761 2694 4 1 3 | |
41 782504 781690 73990 5959 1760 2695 4 1 3 | |
43 782547 781690 74988 5960 1759 2652 4 1 3 | |
42 782589 781690 74988 5961 1758 2653 4 1 3 | |
40 782629 781690 74988 5962 1757 2654 4 1 3 | |
96 782725 782708 74988 5963 1800 2655 4 1 3 | |
46 782771 782708 74988 5964 1799 2656 4 1 3 | |
43 782814 782708 74988 5965 1798 2657 4 1 3 | |
40 782854 782708 74988 5966 1797 2658 4 1 3 | |
40 782894 782708 74988 5967 1796 2659 4 1 3 | |
40 782934 782708 74988 5968 1795 2660 4 1 3 | |
39 782973 782708 74988 5969 1794 2661 4 1 3 | |
40 783013 782708 74988 5970 1793 2662 4 1 3 | |
41 783054 782708 74988 5971 1792 2663 4 1 3 | |
41 783095 782708 74988 5972 1791 2664 4 1 3 | |
39 783134 782708 74988 5973 1790 2665 4 1 3 | |
41 783175 782708 74988 5974 1789 2666 4 1 3 | |
40 783215 782708 74988 5975 1788 2667 4 1 3 | |
39 783254 782708 74988 5976 1787 2668 4 1 3 | |
41 783295 782708 74988 5977 1786 2669 4 1 3 | |
40 783335 782708 74988 5978 1785 2670 4 1 3 | |
40 783375 782708 74988 5979 1784 2671 4 1 3 | |
65 783440 782708 74988 5980 1783 2672 4 1 3 | |
45 783485 782708 74988 5981 1782 2673 4 1 3 | |
42 783527 782708 75986 5982 1781 2630 4 1 3 | |
41 783568 782708 75986 5983 1780 2631 4 1 3 | |
41 783609 782708 75986 5984 1779 2632 4 1 3 | |
83 783692 782708 75986 5985 1778 2633 4 1 3 | |
54 783746 783698 75986 5986 1821 2634 4 1 3 | |
44 783790 783698 75986 5987 1820 2635 4 1 3 | |
41 783831 783698 75986 5988 1819 2636 4 1 3 | |
40 783871 783698 75986 5989 1818 2637 4 1 3 | |
42 783913 783698 75986 5990 1817 2638 4 1 3 | |
39 783952 783698 75986 5991 1816 2639 4 1 3 | |
40 783992 783698 75986 5992 1815 2640 4 1 3 | |
41 784033 783698 75986 5993 1814 2641 4 1 3 | |
40 784073 783698 75986 5994 1813 2642 4 1 3 | |
40 784113 783698 75986 5995 1812 2643 4 1 3 | |
41 784154 783698 75986 5996 1811 2644 4 1 3 | |
41 784195 783698 75986 5997 1810 2645 4 1 3 | |
40 784235 783698 75986 5998 1809 2646 4 1 3 | |
40 784275 783698 75986 5999 1808 2647 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
42 784317 783698 75986 6000 1807 2648 4 1 3 | |
43 784360 783698 75986 6001 1806 2649 4 1 3 | |
68 784428 783698 75986 6002 1805 2650 4 1 3 | |
45 784473 783698 75986 6003 1804 2651 4 1 3 | |
42 784515 783698 75986 6004 1803 2652 4 1 3 | |
65 784580 783698 76984 6005 1802 2609 4 1 3 | |
42 784622 783698 76984 6006 1801 2610 4 1 3 | |
85 784707 784691 76984 6007 1844 2611 4 1 3 | |
46 784753 784691 76984 6008 1843 2612 4 1 3 | |
43 784796 784691 76984 6009 1842 2613 4 1 3 | |
41 784837 784691 76984 6010 1841 2614 4 1 3 | |
40 784877 784691 76984 6011 1840 2615 4 1 3 | |
41 784918 784691 76984 6012 1839 2616 4 1 3 | |
40 784958 784691 76984 6013 1838 2617 4 1 3 | |
40 784998 784691 76984 6014 1837 2618 4 1 3 | |
42 785040 784691 76984 6015 1836 2619 4 1 3 | |
40 785080 784691 76984 6016 1835 2620 4 1 3 | |
39 785119 784691 76984 6017 1834 2621 4 1 3 | |
42 785161 784691 76984 6018 1833 2622 4 1 3 | |
39 785200 784691 76984 6019 1832 2623 4 1 3 | |
40 785240 784691 76984 6020 1831 2624 4 1 3 | |
40 785280 784691 76984 6021 1830 2625 4 1 3 | |
39 785319 784691 76984 6022 1829 2626 4 1 3 | |
40 785359 784691 76984 6023 1828 2627 4 1 3 | |
62 785421 784691 76984 6024 1827 2628 4 1 3 | |
47 785468 784691 76984 6025 1826 2629 4 1 3 | |
41 785509 784691 76984 6026 1825 2630 4 1 3 | |
43 785552 784691 77981 6027 1824 2587 4 1 3 | |
39 785591 784691 77981 6028 1823 2588 4 1 3 | |
40 785631 784691 77981 6029 1822 2589 4 1 3 | |
91 785722 785706 78004 6030 1865 2589 4 1 3 | |
47 785769 785706 78004 6031 1864 2590 4 1 3 | |
41 785810 785706 78004 6032 1863 2591 4 1 3 | |
41 785851 785706 78004 6033 1862 2592 4 1 3 | |
40 785891 785706 78004 6034 1861 2593 4 1 3 | |
42 785933 785706 78004 6035 1860 2594 4 1 3 | |
39 785972 785706 78004 6036 1859 2595 4 1 3 | |
41 786013 785706 78004 6037 1858 2596 4 1 3 | |
40 786053 785706 78004 6038 1857 2597 4 1 3 | |
40 786093 785706 78004 6039 1856 2598 4 1 3 | |
39 786132 785706 78004 6040 1855 2599 4 1 3 | |
42 786174 785706 78004 6041 1854 2600 4 1 3 | |
66 786240 785706 78004 6042 1853 2601 4 1 3 | |
44 786284 785706 78004 6043 1852 2602 4 1 3 | |
43 786327 785706 78004 6044 1851 2603 4 1 3 | |
40 786367 785706 78004 6045 1850 2604 4 1 3 | |
67 786434 785706 78004 6046 1849 2605 4 1 3 | |
44 786478 785706 78004 6047 1848 2606 4 1 3 | |
44 786522 785706 78004 6048 1847 2607 4 1 3 | |
41 786563 785706 79002 6049 1846 2564 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 786603 785706 79002 6050 1845 2565 4 1 3 | |
44 786647 785706 79002 6051 1844 2566 4 1 3 | |
97 786744 786695 79002 6052 1887 2567 4 1 3 | |
44 786788 786695 79002 6053 1886 2568 4 1 3 | |
41 786829 786695 79002 6054 1885 2569 4 1 3 | |
41 786870 786695 79002 6055 1884 2570 4 1 3 | |
41 786911 786695 79002 6056 1883 2571 4 1 3 | |
39 786950 786695 79002 6057 1882 2572 4 1 3 | |
40 786990 786695 79002 6058 1881 2573 4 1 3 | |
41 787031 786695 79002 6059 1880 2574 4 1 3 | |
40 787071 786695 79002 6060 1879 2575 4 1 3 | |
40 787111 786695 79002 6061 1878 2576 4 1 3 | |
40 787151 786695 79002 6062 1877 2577 4 1 3 | |
39 787190 786695 79002 6063 1876 2578 4 1 3 | |
40 787230 786695 79002 6064 1875 2579 4 1 3 | |
39 787269 786695 79002 6065 1874 2580 4 1 3 | |
40 787309 786695 79002 6066 1873 2581 4 1 3 | |
40 787349 786695 79002 6067 1872 2582 4 1 3 | |
39 787388 786695 79002 6068 1871 2583 4 1 3 | |
68 787456 786695 79002 6069 1870 2584 4 1 3 | |
43 787499 786695 79002 6070 1869 2585 4 1 3 | |
42 787541 786695 80000 6071 1868 2542 4 1 3 | |
40 787581 786695 80000 6072 1867 2543 4 1 3 | |
39 787620 786695 80000 6073 1866 2544 4 1 3 | |
87 787707 787691 80000 6074 1910 2545 4 1 3 | |
46 787753 787691 80000 6075 1909 2546 4 1 3 | |
45 787798 787691 80000 6076 1908 2547 4 1 3 | |
41 787839 787691 80000 6077 1907 2548 4 1 3 | |
40 787879 787691 80000 6078 1906 2549 4 1 3 | |
41 787920 787691 80000 6079 1905 2550 4 1 3 | |
40 787960 787691 80000 6080 1904 2551 4 1 3 | |
40 788000 787691 80000 6081 1903 2552 4 1 3 | |
42 788042 787691 80000 6082 1902 2553 4 1 3 | |
39 788081 787691 80000 6083 1901 2554 4 1 3 | |
39 788120 787691 80000 6084 1900 2555 4 1 3 | |
41 788161 787691 80000 6085 1899 2556 4 1 3 | |
40 788201 787691 80000 6086 1898 2557 4 1 3 | |
40 788241 787691 80000 6087 1897 2558 4 1 3 | |
40 788281 787691 80000 6088 1896 2559 4 1 3 | |
40 788321 787691 80000 6089 1895 2560 4 1 3 | |
39 788360 787691 80000 6090 1894 2561 4 1 3 | |
64 788424 787691 80000 6091 1893 2562 4 1 3 | |
45 788469 787691 80000 6092 1892 2563 4 1 3 | |
41 788510 787691 80000 6093 1891 2564 4 1 3 | |
42 788552 787691 80997 6094 1890 2521 4 1 3 | |
41 788593 787691 80997 6095 1889 2522 4 1 3 | |
39 788632 787691 80997 6096 1888 2523 4 1 3 | |
88 788720 788705 80997 6097 1931 2524 4 1 3 | |
45 788765 788705 80997 6098 1930 2525 4 1 3 | |
43 788808 788705 80997 6099 1929 2526 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 788849 788705 80997 6100 1928 2527 4 1 3 | |
42 788891 788705 80997 6101 1927 2528 4 1 3 | |
42 788933 788705 80997 6102 1926 2529 4 1 3 | |
39 788972 788705 80997 6103 1925 2530 4 1 3 | |
39 789011 788705 80997 6104 1924 2531 4 1 3 | |
42 789053 788705 80997 6105 1923 2532 4 1 3 | |
39 789092 788705 80997 6106 1922 2533 4 1 3 | |
40 789132 788705 80997 6107 1921 2534 4 1 3 | |
41 789173 788705 80997 6108 1920 2535 4 1 3 | |
40 789213 788705 80997 6109 1919 2536 4 1 3 | |
40 789253 788705 80997 6110 1918 2537 4 1 3 | |
41 789294 788705 80997 6111 1917 2538 4 1 3 | |
40 789334 788705 80997 6112 1916 2539 4 1 3 | |
40 789374 788705 80997 6113 1915 2540 4 1 3 | |
64 789438 788705 80997 6114 1914 2541 4 1 3 | |
45 789483 788705 80997 6115 1913 2542 4 1 3 | |
43 789526 788705 81995 6116 1912 2499 4 1 3 | |
42 789568 788705 81995 6117 1911 2500 4 1 3 | |
40 789608 788705 81995 6118 1910 2501 4 1 3 | |
81 789689 788705 81995 6119 1909 2502 4 1 3 | |
54 789743 789695 81995 6120 1952 2503 4 1 3 | |
44 789787 789695 81995 6121 1951 2504 4 1 3 | |
40 789827 789695 81995 6122 1950 2505 4 1 3 | |
40 789867 789695 81995 6123 1949 2506 4 1 3 | |
41 789908 789695 81995 6124 1948 2507 4 1 3 | |
39 789947 789695 81995 6125 1947 2508 4 1 3 | |
39 789986 789695 81995 6126 1946 2509 4 1 3 | |
41 790027 789695 81995 6127 1945 2510 4 1 3 | |
39 790066 789695 81995 6128 1944 2511 4 1 3 | |
40 790106 789695 81995 6129 1943 2512 4 1 3 | |
40 790146 789695 81995 6130 1942 2513 4 1 3 | |
40 790186 789695 81995 6131 1941 2514 4 1 3 | |
63 790249 789695 81995 6132 1940 2515 4 1 3 | |
45 790294 789695 81995 6133 1939 2516 4 1 3 | |
41 790335 789695 81995 6134 1938 2517 4 1 3 | |
40 790375 789695 81995 6135 1937 2518 4 1 3 | |
68 790443 789695 81995 6136 1936 2519 4 1 3 | |
44 790487 789695 81995 6137 1935 2520 4 1 3 | |
44 790531 789695 82993 6138 1934 2477 4 1 3 | |
40 790571 789695 82993 6139 1933 2478 4 1 3 | |
40 790611 789695 82993 6140 1932 2479 4 1 3 | |
81 790692 789695 82993 6141 1931 2480 4 1 3 | |
54 790746 790698 82993 6142 1974 2481 4 1 3 | |
84 790830 790698 82993 6143 1973 2482 4 1 3 | |
48 790878 790698 82993 6144 1972 2483 4 1 3 | |
43 790921 790698 82993 6145 1971 2484 4 1 3 | |
41 790962 790698 82993 6146 1970 2485 4 1 3 | |
41 791003 790698 82993 6147 1969 2486 4 1 3 | |
41 791044 790698 82993 6148 1968 2487 4 1 3 | |
41 791085 790698 82993 6149 1967 2488 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 791124 790698 82993 6150 1966 2489 4 1 3 | |
44 791168 790698 82993 6151 1965 2490 4 1 3 | |
41 791209 790698 82993 6152 1964 2491 4 1 3 | |
39 791248 790698 82993 6153 1963 2492 4 1 3 | |
43 791291 790698 82993 6154 1962 2493 4 1 3 | |
40 791331 790698 82993 6155 1961 2494 4 1 3 | |
39 791370 790698 82993 6156 1960 2495 4 1 3 | |
66 791436 790698 82993 6157 1959 2496 4 1 3 | |
44 791480 790698 82993 6158 1958 2497 4 1 3 | |
44 791524 790698 83990 6159 1957 2454 4 1 3 | |
41 791565 790698 83990 6160 1956 2455 4 1 3 | |
40 791605 790698 83990 6161 1955 2456 4 1 3 | |
41 791646 790698 83990 6162 1954 2457 4 1 3 | |
98 791744 791693 83990 6163 1997 2458 4 1 3 | |
45 791789 791693 83990 6164 1996 2459 4 1 3 | |
41 791830 791693 83990 6165 1995 2460 4 1 3 | |
40 791870 791693 83990 6166 1994 2461 4 1 3 | |
42 791912 791693 83990 6167 1993 2462 4 1 3 | |
40 791952 791693 83990 6168 1992 2463 4 1 3 | |
39 791991 791693 83990 6169 1991 2464 4 1 3 | |
40 792031 791693 83990 6170 1990 2465 4 1 3 | |
39 792070 791693 83990 6171 1989 2466 4 1 3 | |
41 792111 791693 83990 6172 1988 2467 4 1 3 | |
41 792152 791693 83990 6173 1987 2468 4 1 3 | |
41 792193 791693 83990 6174 1986 2469 4 1 3 | |
39 792232 791693 83990 6175 1985 2470 4 1 3 | |
41 792273 791693 83990 6176 1984 2471 4 1 3 | |
40 792313 791693 83990 6177 1983 2472 4 1 3 | |
39 792352 791693 83990 6178 1982 2473 4 1 3 | |
40 792392 791693 83990 6179 1981 2474 4 1 3 | |
73 792465 791693 83990 6180 1980 2475 4 1 3 | |
42 792507 791693 83990 6181 1979 2476 4 1 3 | |
63 792570 791693 84988 6182 1978 2433 4 1 3 | |
44 792614 791693 84988 6183 1977 2434 4 1 3 | |
85 792699 792693 84988 6184 1976 2435 4 1 3 | |
47 792746 792693 84988 6185 2019 2436 4 1 3 | |
45 792791 792693 84988 6186 2018 2437 4 1 3 | |
40 792831 792693 84988 6187 2017 2438 4 1 3 | |
40 792871 792693 84988 6188 2016 2439 4 1 3 | |
40 792911 792693 84988 6189 2015 2440 4 1 3 | |
40 792951 792693 84988 6190 2014 2441 4 1 3 | |
39 792990 792693 84988 6191 2013 2442 4 1 3 | |
41 793031 792693 84988 6192 2012 2443 4 1 3 | |
40 793071 792693 84988 6193 2011 2444 4 1 3 | |
41 793112 792693 84988 6194 2010 2445 4 1 3 | |
40 793152 792693 84988 6195 2009 2446 4 1 3 | |
39 793191 792693 84988 6196 2008 2447 4 1 3 | |
39 793230 792693 84988 6197 2007 2448 4 1 3 | |
41 793271 792693 84988 6198 2006 2449 4 1 3 | |
40 793311 792693 84988 6199 2005 2450 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 793350 792693 84988 6200 2004 2451 4 1 3 | |
43 793393 792693 84988 6201 2003 2452 4 1 3 | |
68 793461 792693 84988 6202 2002 2453 4 1 3 | |
42 793503 792693 84988 6203 2001 2454 4 1 3 | |
43 793546 792693 85986 6204 2000 2411 4 1 3 | |
40 793586 792693 85986 6205 1999 2412 4 1 3 | |
39 793625 792693 85986 6206 1998 2413 4 1 3 | |
92 793717 793701 85986 6207 2041 2414 4 1 3 | |
47 793764 793701 85986 6208 2040 2415 4 1 3 | |
44 793808 793701 85986 6209 2039 2416 4 1 3 | |
40 793848 793701 85986 6210 2038 2417 4 1 3 | |
40 793888 793701 85986 6211 2037 2418 4 1 3 | |
42 793930 793701 85986 6212 2036 2419 4 1 3 | |
39 793969 793701 85986 6213 2035 2420 4 1 3 | |
40 794009 793701 85986 6214 2034 2421 4 1 3 | |
42 794051 793701 85986 6215 2033 2422 4 1 3 | |
40 794091 793701 85986 6216 2032 2423 4 1 3 | |
39 794130 793701 85986 6217 2031 2424 4 1 3 | |
42 794172 793701 85986 6218 2030 2425 4 1 3 | |
39 794211 793701 85986 6219 2029 2426 4 1 3 | |
40 794251 793701 85986 6220 2028 2427 4 1 3 | |
42 794293 793701 85986 6221 2027 2428 4 1 3 | |
68 794361 793701 85986 6222 2026 2429 4 1 3 | |
70 794431 793701 85986 6223 2025 2430 4 1 3 | |
47 794478 793701 85986 6224 2024 2431 4 1 3 | |
44 794522 793701 85986 6225 2023 2432 4 1 3 | |
41 794563 793701 86984 6226 2022 2389 4 1 3 | |
40 794603 793701 86984 6227 2021 2390 4 1 3 | |
39 794642 793701 86984 6228 2020 2391 4 1 3 | |
97 794739 794723 86984 6229 2063 2392 4 1 3 | |
44 794783 794723 86984 6230 2062 2393 4 1 3 | |
41 794824 794723 86984 6231 2061 2394 4 1 3 | |
41 794865 794723 86984 6232 2060 2395 4 1 3 | |
41 794906 794723 86984 6233 2059 2396 4 1 3 | |
40 794946 794723 86984 6234 2058 2397 4 1 3 | |
41 794987 794723 86984 6235 2057 2398 4 1 3 | |
41 795028 794723 86984 6236 2056 2399 4 1 3 | |
40 795068 794723 86984 6237 2055 2400 4 1 3 | |
40 795108 794723 86984 6238 2054 2401 4 1 3 | |
40 795148 794723 86984 6239 2053 2402 4 1 3 | |
42 795190 794723 86984 6240 2052 2403 4 1 3 | |
39 795229 794723 86984 6241 2051 2404 4 1 3 | |
39 795268 794723 86984 6242 2050 2405 4 1 3 | |
41 795309 794723 86984 6243 2049 2406 4 1 3 | |
40 795349 794723 86984 6244 2048 2407 4 1 3 | |
39 795388 794723 86984 6245 2047 2408 4 1 3 | |
67 795455 794723 86984 6246 2046 2409 4 1 3 | |
43 795498 794723 86984 6247 2045 2410 4 1 3 | |
42 795540 794723 87981 6248 2044 2367 4 1 3 | |
41 795581 794723 87981 6249 2043 2368 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 795620 794723 87981 6250 2042 2369 4 1 3 | |
88 795708 795693 88004 6251 2085 2369 4 1 3 | |
47 795755 795693 88004 6252 2084 2370 4 1 3 | |
44 795799 795693 88004 6253 2083 2371 4 1 3 | |
40 795839 795693 88004 6254 2082 2372 4 1 3 | |
40 795879 795693 88004 6255 2081 2373 4 1 3 | |
42 795921 795693 88004 6256 2080 2374 4 1 3 | |
39 795960 795693 88004 6257 2079 2375 4 1 3 | |
40 796000 795693 88004 6258 2078 2376 4 1 3 | |
42 796042 795693 88004 6259 2077 2377 4 1 3 | |
40 796082 795693 88004 6260 2076 2378 4 1 3 | |
40 796122 795693 88004 6261 2075 2379 4 1 3 | |
41 796163 795693 88004 6262 2074 2380 4 1 3 | |
41 796204 795693 88004 6263 2073 2381 4 1 3 | |
39 796243 795693 88004 6264 2072 2382 4 1 3 | |
41 796284 795693 88004 6265 2071 2383 4 1 3 | |
40 796324 795693 88004 6266 2070 2384 4 1 3 | |
39 796363 795693 88004 6267 2069 2385 4 1 3 | |
63 796426 795693 88004 6268 2068 2386 4 1 3 | |
47 796473 795693 88004 6269 2067 2387 4 1 3 | |
40 796513 795693 88004 6270 2066 2388 4 1 3 | |
43 796556 795693 89002 6271 2065 2345 4 1 3 | |
40 796596 795693 89002 6272 2064 2346 4 1 3 | |
41 796637 795693 89002 6273 2063 2347 4 1 3 | |
88 796725 796710 89002 6274 2106 2348 4 1 3 | |
46 796771 796710 89002 6275 2105 2349 4 1 3 | |
42 796813 796710 89002 6276 2104 2350 4 1 3 | |
40 796853 796710 89002 6277 2103 2351 4 1 3 | |
41 796894 796710 89002 6278 2102 2352 4 1 3 | |
41 796935 796710 89002 6279 2101 2353 4 1 3 | |
40 796975 796710 89002 6280 2100 2354 4 1 3 | |
40 797015 796710 89002 6281 2099 2355 4 1 3 | |
41 797056 796710 89002 6282 2098 2356 4 1 3 | |
40 797096 796710 89002 6283 2097 2357 4 1 3 | |
39 797135 796710 89002 6284 2096 2358 4 1 3 | |
40 797175 796710 89002 6285 2095 2359 4 1 3 | |
40 797215 796710 89002 6286 2094 2360 4 1 3 | |
40 797255 796710 89002 6287 2093 2361 4 1 3 | |
40 797295 796710 89002 6288 2092 2362 4 1 3 | |
39 797334 796710 89002 6289 2091 2363 4 1 3 | |
40 797374 796710 89002 6290 2090 2364 4 1 3 | |
65 797439 796710 89002 6291 2089 2365 4 1 3 | |
45 797484 796710 89002 6292 2088 2366 4 1 3 | |
44 797528 796710 90000 6293 2087 2323 4 1 3 | |
41 797569 796710 90000 6294 2086 2324 4 1 3 | |
40 797609 796710 90000 6295 2085 2325 4 1 3 | |
79 797688 796710 90000 6296 2084 2326 4 1 3 | |
54 797742 797695 90000 6297 2128 2327 4 1 3 | |
43 797785 797695 90000 6298 2127 2328 4 1 3 | |
41 797826 797695 90000 6299 2126 2329 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 797866 797695 90000 6300 2125 2330 4 1 3 | |
44 797910 797695 90000 6301 2124 2331 4 1 3 | |
40 797950 797695 90000 6302 2123 2332 4 1 3 | |
40 797990 797695 90000 6303 2122 2333 4 1 3 | |
40 798030 797695 90000 6304 2121 2334 4 1 3 | |
40 798070 797695 90000 6305 2120 2335 4 1 3 | |
39 798109 797695 90000 6306 2119 2336 4 1 3 | |
41 798150 797695 90000 6307 2118 2337 4 1 3 | |
41 798191 797695 90000 6308 2117 2338 4 1 3 | |
39 798230 797695 90000 6309 2116 2339 4 1 3 | |
40 798270 797695 90000 6310 2115 2340 4 1 3 | |
41 798311 797695 90000 6311 2114 2341 4 1 3 | |
39 798350 797695 90000 6312 2113 2342 4 1 3 | |
473 798823 798799 90997 6313 2156 2299 4 1 3 | |
55 798878 798799 90997 6314 2155 2300 4 1 3 | |
44 798922 798799 90997 6315 2154 2301 4 1 3 | |
40 798962 798799 90997 6316 2153 2302 4 1 3 | |
39 799001 798799 90997 6317 2152 2303 4 1 3 | |
41 799042 798799 90997 6318 2151 2304 4 1 3 | |
41 799083 798799 90997 6319 2150 2305 4 1 3 | |
40 799123 798799 90997 6320 2149 2306 4 1 3 | |
41 799164 798799 90997 6321 2148 2307 4 1 3 | |
41 799205 798799 90997 6322 2147 2308 4 1 3 | |
40 799245 798799 90997 6323 2146 2309 4 1 3 | |
40 799285 798799 90997 6324 2145 2310 4 1 3 | |
40 799325 798799 90997 6325 2144 2311 4 1 3 | |
39 799364 798799 90997 6326 2143 2312 4 1 3 | |
74 799438 798799 90997 6327 2142 2313 4 1 3 | |
46 799484 798799 90997 6328 2141 2314 4 1 3 | |
44 799528 798799 91995 6329 2140 2271 4 1 3 | |
41 799569 798799 91995 6330 2139 2272 4 1 3 | |
40 799609 798799 91995 6331 2138 2273 4 1 3 | |
86 799695 798799 91995 6332 2137 2274 4 1 3 | |
56 799751 799701 91995 6333 2180 2275 4 1 3 | |
44 799795 799701 91995 6334 2179 2276 4 1 3 | |
41 799836 799701 91995 6335 2178 2277 4 1 3 | |
40 799876 799701 91995 6336 2177 2278 4 1 3 | |
41 799917 799701 91995 6337 2176 2279 4 1 3 | |
40 799957 799701 91995 6338 2175 2280 4 1 3 | |
40 799997 799701 91995 6339 2174 2281 4 1 3 | |
41 800038 799701 91995 6340 2173 2282 4 1 3 | |
39 800077 799701 91995 6341 2172 2283 4 1 3 | |
38 800115 799701 91995 6342 2171 2284 4 1 3 | |
41 800156 799701 91995 6343 2170 2285 4 1 3 | |
40 800196 799701 91995 6344 2169 2286 4 1 3 | |
40 800236 799701 91995 6345 2168 2287 4 1 3 | |
41 800277 799701 91995 6346 2167 2288 4 1 3 | |
40 800317 799701 91995 6347 2166 2289 4 1 3 | |
40 800357 799701 91995 6348 2165 2290 4 1 3 | |
82 800439 799701 91995 6349 2164 2291 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
52 800491 799701 91995 6350 2163 2292 4 1 3 | |
69 800560 799701 92993 6351 2162 2249 4 1 3 | |
45 800605 799701 92993 6352 2161 2250 4 1 3 | |
43 800648 799701 92993 6353 2160 2251 4 1 3 | |
95 800743 800692 92993 6354 2203 2252 4 1 3 | |
94 800837 800692 92993 6355 2202 2253 4 1 3 | |
49 800886 800692 92993 6356 2201 2254 4 1 3 | |
43 800929 800692 92993 6357 2200 2255 4 1 3 | |
41 800970 800692 92993 6358 2199 2256 4 1 3 | |
39 801009 800692 92993 6359 2198 2257 4 1 3 | |
41 801050 800692 92993 6360 2197 2258 4 1 3 | |
40 801090 800692 92993 6361 2196 2259 4 1 3 | |
40 801130 800692 92993 6362 2195 2260 4 1 3 | |
41 801171 800692 92993 6363 2194 2261 4 1 3 | |
40 801211 800692 92993 6364 2193 2262 4 1 3 | |
38 801249 800692 92993 6365 2192 2263 4 1 3 | |
41 801290 800692 92993 6366 2191 2264 4 1 3 | |
41 801331 800692 92993 6367 2190 2265 4 1 3 | |
39 801370 800692 92993 6368 2189 2266 4 1 3 | |
66 801436 800692 92993 6369 2188 2267 4 1 3 | |
46 801482 800692 92993 6370 2187 2268 4 1 3 | |
43 801525 800692 92993 6371 2186 2269 4 1 3 | |
40 801565 800692 93990 6372 2185 2226 4 1 3 | |
39 801604 800692 93990 6373 2184 2227 4 1 3 | |
41 801645 800692 93990 6374 2183 2228 4 1 3 | |
95 801740 801724 93990 6375 2226 2229 4 1 3 | |
45 801785 801724 93990 6376 2225 2230 4 1 3 | |
40 801825 801724 93990 6377 2224 2231 4 1 3 | |
40 801865 801724 93990 6378 2223 2232 4 1 3 | |
40 801905 801724 93990 6379 2222 2233 4 1 3 | |
40 801945 801724 93990 6380 2221 2234 4 1 3 | |
39 801984 801724 93990 6381 2220 2235 4 1 3 | |
40 802024 801724 93990 6382 2219 2236 4 1 3 | |
39 802063 801724 93990 6383 2218 2237 4 1 3 | |
40 802103 801724 93990 6384 2217 2238 4 1 3 | |
39 802142 801724 93990 6385 2216 2239 4 1 3 | |
40 802182 801724 93990 6386 2215 2240 4 1 3 | |
41 802223 801724 93990 6387 2214 2241 4 1 3 | |
39 802262 801724 93990 6388 2213 2242 4 1 3 | |
41 802303 801724 93990 6389 2212 2243 4 1 3 | |
39 802342 801724 93990 6390 2211 2244 4 1 3 | |
39 802381 801724 93990 6391 2210 2245 4 1 3 | |
66 802447 801724 93990 6392 2209 2246 4 1 3 | |
44 802491 801724 93990 6393 2208 2247 4 1 3 | |
42 802533 801724 94988 6394 2207 2204 4 1 3 | |
42 802575 801724 94988 6395 2206 2205 4 1 3 | |
41 802616 801724 94988 6396 2205 2206 4 1 3 | |
88 802704 802697 94988 6397 2204 2207 4 1 3 | |
48 802752 802697 94988 6398 2247 2208 4 1 3 | |
44 802796 802697 94988 6399 2246 2209 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 802836 802697 94988 6400 2245 2210 4 1 3 | |
44 802880 802697 94988 6401 2244 2211 4 1 3 | |
42 802922 802697 94988 6402 2243 2212 4 1 3 | |
75 802997 802697 94988 6403 2242 2213 4 1 3 | |
46 803043 802697 94988 6404 2241 2214 4 1 3 | |
42 803085 802697 94988 6405 2240 2215 4 1 3 | |
41 803126 802697 94988 6406 2239 2216 4 1 3 | |
42 803168 802697 94988 6407 2238 2217 4 1 3 | |
40 803208 802697 94988 6408 2237 2218 4 1 3 | |
40 803248 802697 94988 6409 2236 2219 4 1 3 | |
42 803290 802697 94988 6410 2235 2220 4 1 3 | |
40 803330 802697 94988 6411 2234 2221 4 1 3 | |
40 803370 802697 94988 6412 2233 2222 4 1 3 | |
68 803438 802697 94988 6413 2232 2223 4 1 3 | |
45 803483 802697 94988 6414 2231 2224 4 1 3 | |
43 803526 802697 95986 6415 2230 2181 4 1 3 | |
41 803567 802697 95986 6416 2229 2182 4 1 3 | |
41 803608 802697 95986 6417 2228 2183 4 1 3 | |
41 803649 802697 95986 6418 2227 2184 4 1 3 | |
97 803746 803696 95986 6419 2270 2185 4 1 3 | |
45 803791 803696 95986 6420 2269 2186 4 1 3 | |
42 803833 803696 95986 6421 2268 2187 4 1 3 | |
39 803872 803696 95986 6422 2267 2188 4 1 3 | |
40 803912 803696 95986 6423 2266 2189 4 1 3 | |
41 803953 803696 95986 6424 2265 2190 4 1 3 | |
40 803993 803696 95986 6425 2264 2191 4 1 3 | |
40 804033 803696 95986 6426 2263 2192 4 1 3 | |
40 804073 803696 95986 6427 2262 2193 4 1 3 | |
40 804113 803696 95986 6428 2261 2194 4 1 3 | |
41 804154 803696 95986 6429 2260 2195 4 1 3 | |
40 804194 803696 95986 6430 2259 2196 4 1 3 | |
40 804234 803696 95986 6431 2258 2197 4 1 3 | |
40 804274 803696 95986 6432 2257 2198 4 1 3 | |
39 804313 803696 95986 6433 2256 2199 4 1 3 | |
40 804353 803696 95986 6434 2255 2200 4 1 3 | |
40 804393 803696 95986 6435 2254 2201 4 1 3 | |
68 804461 803696 95986 6436 2253 2202 4 1 3 | |
43 804504 803696 95986 6437 2252 2203 4 1 3 | |
45 804549 803696 96984 6438 2251 2160 4 1 3 | |
40 804589 803696 96984 6439 2250 2161 4 1 3 | |
40 804629 803696 96984 6440 2249 2162 4 1 3 | |
92 804721 804705 96984 6441 2292 2163 4 1 3 | |
46 804767 804705 96984 6442 2291 2164 4 1 3 | |
43 804810 804705 96984 6443 2290 2165 4 1 3 | |
40 804850 804705 96984 6444 2289 2166 4 1 3 | |
39 804889 804705 96984 6445 2288 2167 4 1 3 | |
40 804929 804705 96984 6446 2287 2168 4 1 3 | |
40 804969 804705 96984 6447 2286 2169 4 1 3 | |
39 805008 804705 96984 6448 2285 2170 4 1 3 | |
41 805049 804705 96984 6449 2284 2171 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 805089 804705 96984 6450 2283 2172 4 1 3 | |
43 805132 804705 96984 6451 2282 2173 4 1 3 | |
41 805173 804705 96984 6452 2281 2174 4 1 3 | |
40 805213 804705 96984 6453 2280 2175 4 1 3 | |
39 805252 804705 96984 6454 2279 2176 4 1 3 | |
41 805293 804705 96984 6455 2278 2177 4 1 3 | |
39 805332 804705 96984 6456 2277 2178 4 1 3 | |
40 805372 804705 96984 6457 2276 2179 4 1 3 | |
64 805436 804705 96984 6458 2275 2180 4 1 3 | |
46 805482 804705 96984 6459 2274 2181 4 1 3 | |
43 805525 804705 97981 6460 2273 2138 4 1 3 | |
42 805567 804705 97981 6461 2272 2139 4 1 3 | |
40 805607 804705 97981 6462 2271 2140 4 1 3 | |
40 805647 804705 97981 6463 2270 2141 4 1 3 | |
90 805737 805723 98004 6464 2313 2141 4 1 3 | |
45 805782 805723 98004 6465 2312 2142 4 1 3 | |
41 805823 805723 98004 6466 2311 2143 4 1 3 | |
40 805863 805723 98004 6467 2310 2144 4 1 3 | |
42 805905 805723 98004 6468 2309 2145 4 1 3 | |
39 805944 805723 98004 6469 2308 2146 4 1 3 | |
40 805984 805723 98004 6470 2307 2147 4 1 3 | |
40 806024 805723 98004 6471 2306 2148 4 1 3 | |
39 806063 805723 98004 6472 2305 2149 4 1 3 | |
39 806102 805723 98004 6473 2304 2150 4 1 3 | |
40 806142 805723 98004 6474 2303 2151 4 1 3 | |
40 806182 805723 98004 6475 2302 2152 4 1 3 | |
40 806222 805723 98004 6476 2301 2153 4 1 3 | |
39 806261 805723 98004 6477 2300 2154 4 1 3 | |
40 806301 805723 98004 6478 2299 2155 4 1 3 | |
39 806340 805723 98004 6479 2298 2156 4 1 3 | |
40 806380 805723 98004 6480 2297 2157 4 1 3 | |
66 806446 805723 98004 6481 2296 2158 4 1 3 | |
43 806489 805723 98004 6482 2295 2159 4 1 3 | |
42 806531 805723 99002 6483 2294 2116 4 1 3 | |
41 806572 805723 99002 6484 2293 2117 4 1 3 | |
40 806612 805723 99002 6485 2292 2118 4 1 3 | |
88 806700 805723 99002 6486 2291 2119 4 1 3 | |
52 806752 806681 99002 6487 2334 2120 4 1 3 | |
45 806797 806681 99002 6488 2333 2121 4 1 3 | |
42 806839 806681 99002 6489 2332 2122 4 1 3 | |
40 806879 806681 99002 6490 2331 2123 4 1 3 | |
40 806919 806681 99002 6491 2330 2124 4 1 3 | |
40 806959 806681 99002 6492 2329 2125 4 1 3 | |
39 806998 806681 99002 6493 2328 2126 4 1 3 | |
41 807039 806681 99002 6494 2327 2127 4 1 3 | |
66 807105 806681 99002 6495 2326 2128 4 1 3 | |
45 807150 806681 99002 6496 2325 2129 4 1 3 | |
41 807191 806681 99002 6497 2324 2130 4 1 3 | |
40 807231 806681 99002 6498 2323 2131 4 1 3 | |
39 807270 806681 99002 6499 2322 2132 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
42 807312 806681 99002 6500 2321 2133 4 1 3 | |
42 807354 806681 99002 6501 2320 2134 4 1 3 | |
40 807394 806681 99002 6502 2319 2135 4 1 3 | |
71 807465 806681 99002 6503 2318 2136 4 1 3 | |
40 807505 806681 99002 6504 2317 2137 4 1 3 | |
44 807549 806681 100000 6505 2316 2094 4 1 3 | |
41 807590 806681 100000 6506 2315 2095 4 1 3 | |
40 807630 806681 100000 6507 2314 2096 4 1 3 | |
93 807723 807707 100000 6508 2358 2097 4 1 3 | |
47 807770 807707 100000 6509 2357 2098 4 1 3 | |
44 807814 807707 100000 6510 2356 2099 4 1 3 | |
40 807854 807707 100000 6511 2355 2100 4 1 3 | |
40 807894 807707 100000 6512 2354 2101 4 1 3 | |
40 807934 807707 100000 6513 2353 2102 4 1 3 | |
40 807974 807707 100000 6514 2352 2103 4 1 3 | |
40 808014 807707 100000 6515 2351 2104 4 1 3 | |
41 808055 807707 100000 6516 2350 2105 4 1 3 | |
40 808095 807707 100000 6517 2349 2106 4 1 3 | |
39 808134 807707 100000 6518 2348 2107 4 1 3 | |
42 808176 807707 100000 6519 2347 2108 4 1 3 | |
40 808216 807707 100000 6520 2346 2109 4 1 3 | |
39 808255 807707 100000 6521 2345 2110 4 1 3 | |
41 808296 807707 100000 6522 2344 2111 4 1 3 | |
39 808335 807707 100000 6523 2343 2112 4 1 3 | |
40 808375 807707 100000 6524 2342 2113 4 1 3 | |
70 808445 807707 100000 6525 2341 2114 4 1 3 | |
44 808489 807707 100000 6526 2340 2115 4 1 3 | |
62 808551 807707 100997 6527 2339 2072 4 1 3 | |
45 808596 807707 100997 6528 2338 2073 4 1 3 | |
41 808637 807707 100997 6529 2337 2074 4 1 3 | |
89 808726 808710 100997 6530 2380 2075 4 1 3 | |
47 808773 808710 100997 6531 2379 2076 4 1 3 | |
41 808814 808710 100997 6532 2378 2077 4 1 3 | |
41 808855 808710 100997 6533 2377 2078 4 1 3 | |
40 808895 808710 100997 6534 2376 2079 4 1 3 | |
41 808936 808710 100997 6535 2375 2080 4 1 3 | |
40 808976 808710 100997 6536 2374 2081 4 1 3 | |
38 809014 808710 100997 6537 2373 2082 4 1 3 | |
41 809055 808710 100997 6538 2372 2083 4 1 3 | |
39 809094 808710 100997 6539 2371 2084 4 1 3 | |
39 809133 808710 100997 6540 2370 2085 4 1 3 | |
41 809174 808710 100997 6541 2369 2086 4 1 3 | |
39 809213 808710 100997 6542 2368 2087 4 1 3 | |
40 809253 808710 100997 6543 2367 2088 4 1 3 | |
40 809293 808710 100997 6544 2366 2089 4 1 3 | |
40 809333 808710 100997 6545 2365 2090 4 1 3 | |
39 809372 808710 100997 6546 2364 2091 4 1 3 | |
64 809436 808710 100997 6547 2363 2092 4 1 3 | |
44 809480 808710 100997 6548 2362 2093 4 1 3 | |
43 809523 808710 100997 6549 2361 2094 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 809564 808710 101995 6550 2360 2051 4 1 3 | |
42 809606 808710 101995 6551 2359 2052 4 1 3 | |
42 809648 808710 101995 6552 2358 2053 4 1 3 | |
90 809738 809689 101995 6553 2401 2054 4 1 3 | |
44 809782 809689 101995 6554 2400 2055 4 1 3 | |
40 809822 809689 101995 6555 2399 2056 4 1 3 | |
40 809862 809689 101995 6556 2398 2057 4 1 3 | |
41 809903 809689 101995 6557 2397 2058 4 1 3 | |
40 809943 809689 101995 6558 2396 2059 4 1 3 | |
39 809982 809689 101995 6559 2395 2060 4 1 3 | |
40 810022 809689 101995 6560 2394 2061 4 1 3 | |
40 810062 809689 101995 6561 2393 2062 4 1 3 | |
40 810102 809689 101995 6562 2392 2063 4 1 3 | |
39 810141 809689 101995 6563 2391 2064 4 1 3 | |
41 810182 809689 101995 6564 2390 2065 4 1 3 | |
40 810222 809689 101995 6565 2389 2066 4 1 3 | |
40 810262 809689 101995 6566 2388 2067 4 1 3 | |
40 810302 809689 101995 6567 2387 2068 4 1 3 | |
39 810341 809689 101995 6568 2386 2069 4 1 3 | |
40 810381 809689 101995 6569 2385 2070 4 1 3 | |
65 810446 809689 101995 6570 2384 2071 4 1 3 | |
43 810489 809689 101995 6571 2383 2072 4 1 3 | |
43 810532 809689 102993 6572 2382 2029 4 1 3 | |
41 810573 809689 102993 6573 2381 2030 4 1 3 | |
38 810611 809689 102993 6574 2380 2031 4 1 3 | |
79 810690 809689 102993 6575 2379 2032 4 1 3 | |
56 810746 810696 102993 6576 2422 2033 4 1 3 | |
85 810831 810696 102993 6577 2421 2034 4 1 3 | |
48 810879 810696 102993 6578 2420 2035 4 1 3 | |
43 810922 810696 102993 6579 2419 2036 4 1 3 | |
41 810963 810696 102993 6580 2418 2037 4 1 3 | |
39 811002 810696 102993 6581 2417 2038 4 1 3 | |
41 811043 810696 102993 6582 2416 2039 4 1 3 | |
70 811113 810696 102993 6583 2415 2040 4 1 3 | |
45 811158 810696 102993 6584 2414 2041 4 1 3 | |
41 811199 810696 102993 6585 2413 2042 4 1 3 | |
39 811238 810696 102993 6586 2412 2043 4 1 3 | |
40 811278 810696 102993 6587 2411 2044 4 1 3 | |
40 811318 810696 102993 6588 2410 2045 4 1 3 | |
39 811357 810696 102993 6589 2409 2046 4 1 3 | |
65 811422 810696 102993 6590 2408 2047 4 1 3 | |
50 811472 810696 102993 6591 2407 2048 4 1 3 | |
42 811514 810696 102993 6592 2406 2049 4 1 3 | |
43 811557 810696 103990 6593 2405 2006 4 1 3 | |
40 811597 810696 103990 6594 2404 2007 4 1 3 | |
40 811637 810696 103990 6595 2403 2008 4 1 3 | |
94 811731 811715 103990 6596 2446 2009 4 1 3 | |
47 811778 811715 103990 6597 2445 2010 4 1 3 | |
42 811820 811715 103990 6598 2444 2011 4 1 3 | |
40 811860 811715 103990 6599 2443 2012 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 811901 811715 103990 6600 2442 2013 4 1 3 | |
43 811944 811715 103990 6601 2441 2014 4 1 3 | |
40 811984 811715 103990 6602 2440 2015 4 1 3 | |
41 812025 811715 103990 6603 2439 2016 4 1 3 | |
40 812065 811715 103990 6604 2438 2017 4 1 3 | |
40 812105 811715 103990 6605 2437 2018 4 1 3 | |
40 812145 811715 103990 6606 2436 2019 4 1 3 | |
40 812185 811715 103990 6607 2435 2020 4 1 3 | |
40 812225 811715 103990 6608 2434 2021 4 1 3 | |
39 812264 811715 103990 6609 2433 2022 4 1 3 | |
41 812305 811715 103990 6610 2432 2023 4 1 3 | |
40 812345 811715 103990 6611 2431 2024 4 1 3 | |
39 812384 811715 103990 6612 2430 2025 4 1 3 | |
65 812449 811715 103990 6613 2429 2026 4 1 3 | |
44 812493 811715 103990 6614 2428 2027 4 1 3 | |
43 812536 811715 104988 6615 2427 1984 4 1 3 | |
40 812576 811715 104988 6616 2426 1985 4 1 3 | |
41 812617 811715 104988 6617 2425 1986 4 1 3 | |
87 812704 812698 104988 6618 2424 1987 4 1 3 | |
50 812754 812698 104988 6619 2467 1988 4 1 3 | |
44 812798 812698 104988 6620 2466 1989 4 1 3 | |
41 812839 812698 104988 6621 2465 1990 4 1 3 | |
40 812879 812698 104988 6622 2464 1991 4 1 3 | |
42 812921 812698 104988 6623 2463 1992 4 1 3 | |
40 812961 812698 104988 6624 2462 1993 4 1 3 | |
39 813000 812698 104988 6625 2461 1994 4 1 3 | |
41 813041 812698 104988 6626 2460 1995 4 1 3 | |
41 813082 812698 104988 6627 2459 1996 4 1 3 | |
39 813121 812698 104988 6628 2458 1997 4 1 3 | |
40 813161 812698 104988 6629 2457 1998 4 1 3 | |
40 813201 812698 104988 6630 2456 1999 4 1 3 | |
39 813240 812698 104988 6631 2455 2000 4 1 3 | |
40 813280 812698 104988 6632 2454 2001 4 1 3 | |
39 813319 812698 104988 6633 2453 2002 4 1 3 | |
39 813358 812698 104988 6634 2452 2003 4 1 3 | |
60 813418 812698 104988 6635 2451 2004 4 1 3 | |
48 813466 812698 104988 6636 2450 2005 4 1 3 | |
41 813507 812698 104988 6637 2449 2006 4 1 3 | |
43 813550 812698 105986 6638 2448 1963 4 1 3 | |
41 813591 812698 105986 6639 2447 1964 4 1 3 | |
40 813631 812698 105986 6640 2446 1965 4 1 3 | |
90 813721 813705 105986 6641 2489 1966 4 1 3 | |
45 813766 813705 105986 6642 2488 1967 4 1 3 | |
43 813809 813705 105986 6643 2487 1968 4 1 3 | |
40 813849 813705 105986 6644 2486 1969 4 1 3 | |
40 813889 813705 105986 6645 2485 1970 4 1 3 | |
42 813931 813705 105986 6646 2484 1971 4 1 3 | |
40 813971 813705 105986 6647 2483 1972 4 1 3 | |
39 814010 813705 105986 6648 2482 1973 4 1 3 | |
41 814051 813705 105986 6649 2481 1974 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 814091 813705 105986 6650 2480 1975 4 1 3 | |
42 814133 813705 105986 6651 2479 1976 4 1 3 | |
42 814175 813705 105986 6652 2478 1977 4 1 3 | |
39 814214 813705 105986 6653 2477 1978 4 1 3 | |
40 814254 813705 105986 6654 2476 1979 4 1 3 | |
41 814295 813705 105986 6655 2475 1980 4 1 3 | |
40 814335 813705 105986 6656 2474 1981 4 1 3 | |
39 814374 813705 105986 6657 2473 1982 4 1 3 | |
64 814438 813705 105986 6658 2472 1983 4 1 3 | |
45 814483 813705 105986 6659 2471 1984 4 1 3 | |
44 814527 813705 106984 6660 2470 1941 4 1 3 | |
40 814567 813705 106984 6661 2469 1942 4 1 3 | |
40 814607 813705 106984 6662 2468 1943 4 1 3 | |
41 814648 813705 106984 6663 2467 1944 4 1 3 | |
92 814740 814725 106984 6664 2510 1945 4 1 3 | |
44 814784 814725 106984 6665 2509 1946 4 1 3 | |
41 814825 814725 106984 6666 2508 1947 4 1 3 | |
41 814866 814725 106984 6667 2507 1948 4 1 3 | |
41 814907 814725 106984 6668 2506 1949 4 1 3 | |
39 814946 814725 106984 6669 2505 1950 4 1 3 | |
40 814986 814725 106984 6670 2504 1951 4 1 3 | |
68 815054 814725 106984 6671 2503 1952 4 1 3 | |
43 815097 814725 106984 6672 2502 1953 4 1 3 | |
40 815137 814725 106984 6673 2501 1954 4 1 3 | |
42 815179 814725 106984 6674 2500 1955 4 1 3 | |
40 815219 814725 106984 6675 2499 1956 4 1 3 | |
39 815258 814725 106984 6676 2498 1957 4 1 3 | |
41 815299 814725 106984 6677 2497 1958 4 1 3 | |
39 815338 814725 106984 6678 2496 1959 4 1 3 | |
39 815377 814725 106984 6679 2495 1960 4 1 3 | |
69 815446 814725 106984 6680 2494 1961 4 1 3 | |
45 815491 814725 106984 6681 2493 1962 4 1 3 | |
45 815536 814725 107981 6682 2492 1919 4 1 3 | |
41 815577 814725 107981 6683 2491 1920 4 1 3 | |
40 815617 814725 107981 6684 2490 1921 4 1 3 | |
90 815707 815701 108004 6685 2489 1921 4 1 3 | |
49 815756 815701 108004 6686 2532 1922 4 1 3 | |
44 815800 815701 108004 6687 2531 1923 4 1 3 | |
40 815840 815701 108004 6688 2530 1924 4 1 3 | |
40 815880 815701 108004 6689 2529 1925 4 1 3 | |
41 815921 815701 108004 6690 2528 1926 4 1 3 | |
40 815961 815701 108004 6691 2527 1927 4 1 3 | |
40 816001 815701 108004 6692 2526 1928 4 1 3 | |
40 816041 815701 108004 6693 2525 1929 4 1 3 | |
40 816081 815701 108004 6694 2524 1930 4 1 3 | |
39 816120 815701 108004 6695 2523 1931 4 1 3 | |
41 816161 815701 108004 6696 2522 1932 4 1 3 | |
39 816200 815701 108004 6697 2521 1933 4 1 3 | |
39 816239 815701 108004 6698 2520 1934 4 1 3 | |
41 816280 815701 108004 6699 2519 1935 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 816319 815701 108004 6700 2518 1936 4 1 3 | |
43 816362 815701 108004 6701 2517 1937 4 1 3 | |
68 816430 815701 108004 6702 2516 1938 4 1 3 | |
46 816476 815701 108004 6703 2515 1939 4 1 3 | |
42 816518 815701 108004 6704 2514 1940 4 1 3 | |
65 816583 815701 109002 6705 2513 1897 4 1 3 | |
42 816625 815701 109002 6706 2512 1898 4 1 3 | |
85 816710 816695 109002 6707 2555 1899 4 1 3 | |
48 816758 816695 109002 6708 2554 1900 4 1 3 | |
44 816802 816695 109002 6709 2553 1901 4 1 3 | |
40 816842 816695 109002 6710 2552 1902 4 1 3 | |
39 816881 816695 109002 6711 2551 1903 4 1 3 | |
41 816922 816695 109002 6712 2550 1904 4 1 3 | |
41 816963 816695 109002 6713 2549 1905 4 1 3 | |
39 817002 816695 109002 6714 2548 1906 4 1 3 | |
42 817044 816695 109002 6715 2547 1907 4 1 3 | |
40 817084 816695 109002 6716 2546 1908 4 1 3 | |
38 817122 816695 109002 6717 2545 1909 4 1 3 | |
41 817163 816695 109002 6718 2544 1910 4 1 3 | |
40 817203 816695 109002 6719 2543 1911 4 1 3 | |
39 817242 816695 109002 6720 2542 1912 4 1 3 | |
40 817282 816695 109002 6721 2541 1913 4 1 3 | |
40 817322 816695 109002 6722 2540 1914 4 1 3 | |
39 817361 816695 109002 6723 2539 1915 4 1 3 | |
60 817421 816695 109002 6724 2538 1916 4 1 3 | |
48 817469 816695 109002 6725 2537 1917 4 1 3 | |
41 817510 816695 109002 6726 2536 1918 4 1 3 | |
44 817554 816695 110000 6727 2535 1875 4 1 3 | |
40 817594 816695 110000 6728 2534 1876 4 1 3 | |
39 817633 816695 110000 6729 2533 1877 4 1 3 | |
92 817725 817709 110000 6730 2577 1878 4 1 3 | |
45 817770 817709 110000 6731 2576 1879 4 1 3 | |
44 817814 817709 110000 6732 2575 1880 4 1 3 | |
40 817854 817709 110000 6733 2574 1881 4 1 3 | |
40 817894 817709 110000 6734 2573 1882 4 1 3 | |
42 817936 817709 110000 6735 2572 1883 4 1 3 | |
39 817975 817709 110000 6736 2571 1884 4 1 3 | |
40 818015 817709 110000 6737 2570 1885 4 1 3 | |
42 818057 817709 110000 6738 2569 1886 4 1 3 | |
39 818096 817709 110000 6739 2568 1887 4 1 3 | |
40 818136 817709 110000 6740 2567 1888 4 1 3 | |
40 818176 817709 110000 6741 2566 1889 4 1 3 | |
39 818215 817709 110000 6742 2565 1890 4 1 3 | |
39 818254 817709 110000 6743 2564 1891 4 1 3 | |
42 818296 817709 110000 6744 2563 1892 4 1 3 | |
40 818336 817709 110000 6745 2562 1893 4 1 3 | |
40 818376 817709 110000 6746 2561 1894 4 1 3 | |
64 818440 817709 110000 6747 2560 1895 4 1 3 | |
44 818484 817709 110000 6748 2559 1896 4 1 3 | |
43 818527 817709 110000 6749 2558 1897 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 818567 817709 110997 6750 2557 1854 4 1 3 | |
42 818609 817709 110997 6751 2556 1855 4 1 3 | |
42 818651 817709 110997 6752 2555 1856 4 1 3 | |
90 818741 818692 110997 6753 2598 1857 4 1 3 | |
44 818785 818692 110997 6754 2597 1858 4 1 3 | |
41 818826 818692 110997 6755 2596 1859 4 1 3 | |
41 818867 818692 110997 6756 2595 1860 4 1 3 | |
41 818908 818692 110997 6757 2594 1861 4 1 3 | |
39 818947 818692 110997 6758 2593 1862 4 1 3 | |
63 819010 818692 110997 6759 2592 1863 4 1 3 | |
45 819055 818692 110997 6760 2591 1864 4 1 3 | |
40 819095 818692 110997 6761 2590 1865 4 1 3 | |
40 819135 818692 110997 6762 2589 1866 4 1 3 | |
40 819175 818692 110997 6763 2588 1867 4 1 3 | |
40 819215 818692 110997 6764 2587 1868 4 1 3 | |
39 819254 818692 110997 6765 2586 1869 4 1 3 | |
40 819294 818692 110997 6766 2585 1870 4 1 3 | |
41 819335 818692 110997 6767 2584 1871 4 1 3 | |
39 819374 818692 110997 6768 2583 1872 4 1 3 | |
67 819441 818692 110997 6769 2582 1873 4 1 3 | |
44 819485 818692 110997 6770 2581 1874 4 1 3 | |
43 819528 818692 111995 6771 2580 1831 4 1 3 | |
40 819568 818692 111995 6772 2579 1832 4 1 3 | |
41 819609 818692 111995 6773 2578 1833 4 1 3 | |
41 819650 818692 111995 6774 2577 1834 4 1 3 | |
93 819743 819694 111995 6775 2620 1835 4 1 3 | |
44 819787 819694 111995 6776 2619 1836 4 1 3 | |
41 819828 819694 111995 6777 2618 1837 4 1 3 | |
40 819868 819694 111995 6778 2617 1838 4 1 3 | |
40 819908 819694 111995 6779 2616 1839 4 1 3 | |
40 819948 819694 111995 6780 2615 1840 4 1 3 | |
39 819987 819694 111995 6781 2614 1841 4 1 3 | |
40 820027 819694 111995 6782 2613 1842 4 1 3 | |
41 820068 819694 111995 6783 2612 1843 4 1 3 | |
40 820108 819694 111995 6784 2611 1844 4 1 3 | |
39 820147 819694 111995 6785 2610 1845 4 1 3 | |
41 820188 819694 111995 6786 2609 1846 4 1 3 | |
39 820227 819694 111995 6787 2608 1847 4 1 3 | |
39 820266 819694 111995 6788 2607 1848 4 1 3 | |
41 820307 819694 111995 6789 2606 1849 4 1 3 | |
40 820347 819694 111995 6790 2605 1850 4 1 3 | |
39 820386 819694 111995 6791 2604 1851 4 1 3 | |
66 820452 819694 111995 6792 2603 1852 4 1 3 | |
44 820496 819694 111995 6793 2602 1853 4 1 3 | |
42 820538 819694 112993 6794 2601 1810 4 1 3 | |
40 820578 819694 112993 6795 2600 1811 4 1 3 | |
40 820618 819694 112993 6796 2599 1812 4 1 3 | |
85 820703 820697 112993 6797 2598 1813 4 1 3 | |
48 820751 820697 112993 6798 2641 1814 4 1 3 | |
88 820839 820697 112993 6799 2640 1815 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
46 820885 820697 112993 6800 2639 1816 4 1 3 | |
47 820932 820697 112993 6801 2638 1817 4 1 3 | |
42 820974 820697 112993 6802 2637 1818 4 1 3 | |
41 821015 820697 112993 6803 2636 1819 4 1 3 | |
42 821057 820697 112993 6804 2635 1820 4 1 3 | |
40 821097 820697 112993 6805 2634 1821 4 1 3 | |
39 821136 820697 112993 6806 2633 1822 4 1 3 | |
40 821176 820697 112993 6807 2632 1823 4 1 3 | |
40 821216 820697 112993 6808 2631 1824 4 1 3 | |
39 821255 820697 112993 6809 2630 1825 4 1 3 | |
41 821296 820697 112993 6810 2629 1826 4 1 3 | |
39 821335 820697 112993 6811 2628 1827 4 1 3 | |
40 821375 820697 112993 6812 2627 1828 4 1 3 | |
66 821441 820697 112993 6813 2626 1829 4 1 3 | |
46 821487 820697 112993 6814 2625 1830 4 1 3 | |
44 821531 820697 113990 6815 2624 1787 4 1 3 | |
40 821571 820697 113990 6816 2623 1788 4 1 3 | |
40 821611 820697 113990 6817 2622 1789 4 1 3 | |
41 821652 820697 113990 6818 2621 1790 4 1 3 | |
95 821747 821699 113990 6819 2664 1791 4 1 3 | |
44 821791 821699 113990 6820 2663 1792 4 1 3 | |
42 821833 821699 113990 6821 2662 1793 4 1 3 | |
39 821872 821699 113990 6822 2661 1794 4 1 3 | |
42 821914 821699 113990 6823 2660 1795 4 1 3 | |
39 821953 821699 113990 6824 2659 1796 4 1 3 | |
39 821992 821699 113990 6825 2658 1797 4 1 3 | |
41 822033 821699 113990 6826 2657 1798 4 1 3 | |
41 822074 821699 113990 6827 2656 1799 4 1 3 | |
39 822113 821699 113990 6828 2655 1800 4 1 3 | |
41 822154 821699 113990 6829 2654 1801 4 1 3 | |
40 822194 821699 113990 6830 2653 1802 4 1 3 | |
39 822233 821699 113990 6831 2652 1803 4 1 3 | |
39 822272 821699 113990 6832 2651 1804 4 1 3 | |
41 822313 821699 113990 6833 2650 1805 4 1 3 | |
39 822352 821699 113990 6834 2649 1806 4 1 3 | |
39 822391 821699 113990 6835 2648 1807 4 1 3 | |
67 822458 821699 113990 6836 2647 1808 4 1 3 | |
43 822501 821699 113990 6837 2646 1809 4 1 3 | |
43 822544 821699 114988 6838 2645 1766 4 1 3 | |
40 822584 821699 114988 6839 2644 1767 4 1 3 | |
39 822623 821699 114988 6840 2643 1768 4 1 3 | |
85 822708 822702 114988 6841 2642 1769 4 1 3 | |
49 822757 822702 114988 6842 2685 1770 4 1 3 | |
43 822800 822702 114988 6843 2684 1771 4 1 3 | |
41 822841 822702 114988 6844 2683 1772 4 1 3 | |
40 822881 822702 114988 6845 2682 1773 4 1 3 | |
41 822922 822702 114988 6846 2681 1774 4 1 3 | |
41 822963 822702 114988 6847 2680 1775 4 1 3 | |
40 823003 822702 114988 6848 2679 1776 4 1 3 | |
70 823073 822702 114988 6849 2678 1777 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
44 823117 822702 114988 6850 2677 1778 4 1 3 | |
45 823162 822702 114988 6851 2676 1779 4 1 3 | |
41 823203 822702 114988 6852 2675 1780 4 1 3 | |
39 823242 822702 114988 6853 2674 1781 4 1 3 | |
41 823283 822702 114988 6854 2673 1782 4 1 3 | |
40 823323 822702 114988 6855 2672 1783 4 1 3 | |
39 823362 822702 114988 6856 2671 1784 4 1 3 | |
64 823426 822702 114988 6857 2670 1785 4 1 3 | |
46 823472 822702 114988 6858 2669 1786 4 1 3 | |
42 823514 822702 114988 6859 2668 1787 4 1 3 | |
43 823557 822702 115986 6860 2667 1744 4 1 3 | |
40 823597 822702 115986 6861 2666 1745 4 1 3 | |
40 823637 822702 115986 6862 2665 1746 4 1 3 | |
96 823733 823717 115986 6863 2708 1747 4 1 3 | |
48 823781 823717 115986 6864 2707 1748 4 1 3 | |
41 823822 823717 115986 6865 2706 1749 4 1 3 | |
40 823862 823717 115986 6866 2705 1750 4 1 3 | |
40 823902 823717 115986 6867 2704 1751 4 1 3 | |
41 823943 823717 115986 6868 2703 1752 4 1 3 | |
40 823983 823717 115986 6869 2702 1753 4 1 3 | |
40 824023 823717 115986 6870 2701 1754 4 1 3 | |
41 824064 823717 115986 6871 2700 1755 4 1 3 | |
40 824104 823717 115986 6872 2699 1756 4 1 3 | |
39 824143 823717 115986 6873 2698 1757 4 1 3 | |
42 824185 823717 115986 6874 2697 1758 4 1 3 | |
39 824224 823717 115986 6875 2696 1759 4 1 3 | |
40 824264 823717 115986 6876 2695 1760 4 1 3 | |
41 824305 823717 115986 6877 2694 1761 4 1 3 | |
40 824345 823717 115986 6878 2693 1762 4 1 3 | |
40 824385 823717 115986 6879 2692 1763 4 1 3 | |
70 824455 823717 115986 6880 2691 1764 4 1 3 | |
44 824499 823717 115986 6881 2690 1765 4 1 3 | |
62 824561 823717 116984 6882 2689 1722 4 1 3 | |
44 824605 823717 116984 6883 2688 1723 4 1 3 | |
40 824645 823717 116984 6884 2687 1724 4 1 3 | |
94 824739 824724 116984 6885 2730 1725 4 1 3 | |
45 824784 824724 116984 6886 2729 1726 4 1 3 | |
41 824825 824724 116984 6887 2728 1727 4 1 3 | |
40 824865 824724 116984 6888 2727 1728 4 1 3 | |
41 824906 824724 116984 6889 2726 1729 4 1 3 | |
39 824945 824724 116984 6890 2725 1730 4 1 3 | |
40 824985 824724 116984 6891 2724 1731 4 1 3 | |
41 825026 824724 116984 6892 2723 1732 4 1 3 | |
39 825065 824724 116984 6893 2722 1733 4 1 3 | |
40 825105 824724 116984 6894 2721 1734 4 1 3 | |
39 825144 824724 116984 6895 2720 1735 4 1 3 | |
41 825185 824724 116984 6896 2719 1736 4 1 3 | |
39 825224 824724 116984 6897 2718 1737 4 1 3 | |
40 825264 824724 116984 6898 2717 1738 4 1 3 | |
40 825304 824724 116984 6899 2716 1739 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 825344 824724 116984 6900 2715 1740 4 1 3 | |
43 825387 824724 116984 6901 2714 1741 4 1 3 | |
65 825452 824724 116984 6902 2713 1742 4 1 3 | |
44 825496 824724 116984 6903 2712 1743 4 1 3 | |
41 825537 824724 117981 6904 2711 1700 4 1 3 | |
41 825578 824724 117981 6905 2710 1701 4 1 3 | |
39 825617 824724 117981 6906 2709 1702 4 1 3 | |
85 825702 825694 118004 6907 2708 1702 4 1 3 | |
49 825751 825694 118004 6908 2751 1703 4 1 3 | |
45 825796 825694 118004 6909 2750 1704 4 1 3 | |
40 825836 825694 118004 6910 2749 1705 4 1 3 | |
40 825876 825694 118004 6911 2748 1706 4 1 3 | |
42 825918 825694 118004 6912 2747 1707 4 1 3 | |
40 825958 825694 118004 6913 2746 1708 4 1 3 | |
39 825997 825694 118004 6914 2745 1709 4 1 3 | |
41 826038 825694 118004 6915 2744 1710 4 1 3 | |
40 826078 825694 118004 6916 2743 1711 4 1 3 | |
39 826117 825694 118004 6917 2742 1712 4 1 3 | |
40 826157 825694 118004 6918 2741 1713 4 1 3 | |
39 826196 825694 118004 6919 2740 1714 4 1 3 | |
40 826236 825694 118004 6920 2739 1715 4 1 3 | |
40 826276 825694 118004 6921 2738 1716 4 1 3 | |
40 826316 825694 118004 6922 2737 1717 4 1 3 | |
40 826356 825694 118004 6923 2736 1718 4 1 3 | |
39 826395 825694 118004 6924 2735 1719 4 1 3 | |
67 826462 825694 118004 6925 2734 1720 4 1 3 | |
42 826504 825694 118004 6926 2733 1721 4 1 3 | |
43 826547 825694 119002 6927 2732 1678 4 1 3 | |
41 826588 825694 119002 6928 2731 1679 4 1 3 | |
40 826628 825694 119002 6929 2730 1680 4 1 3 | |
85 826713 826697 119002 6930 2773 1681 4 1 3 | |
46 826759 826697 119002 6931 2772 1682 4 1 3 | |
44 826803 826697 119002 6932 2771 1683 4 1 3 | |
40 826843 826697 119002 6933 2770 1684 4 1 3 | |
40 826883 826697 119002 6934 2769 1685 4 1 3 | |
41 826924 826697 119002 6935 2768 1686 4 1 3 | |
39 826963 826697 119002 6936 2767 1687 4 1 3 | |
66 827029 826697 119002 6937 2766 1688 4 1 3 | |
43 827072 826697 119002 6938 2765 1689 4 1 3 | |
40 827112 826697 119002 6939 2764 1690 4 1 3 | |
41 827153 826697 119002 6940 2763 1691 4 1 3 | |
40 827193 826697 119002 6941 2762 1692 4 1 3 | |
39 827232 826697 119002 6942 2761 1693 4 1 3 | |
40 827272 826697 119002 6943 2760 1694 4 1 3 | |
40 827312 826697 119002 6944 2759 1695 4 1 3 | |
39 827351 826697 119002 6945 2758 1696 4 1 3 | |
39 827390 826697 119002 6946 2757 1697 4 1 3 | |
69 827459 826697 119002 6947 2756 1698 4 1 3 | |
44 827503 826697 119002 6948 2755 1699 4 1 3 | |
44 827547 826697 120000 6949 2754 1656 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 827587 826697 120000 6950 2753 1657 4 1 3 | |
42 827629 826697 120000 6951 2752 1658 4 1 3 | |
92 827721 827705 120000 6952 2796 1659 4 1 3 | |
46 827767 827705 120000 6953 2795 1660 4 1 3 | |
43 827810 827705 120000 6954 2794 1661 4 1 3 | |
40 827850 827705 120000 6955 2793 1662 4 1 3 | |
41 827891 827705 120000 6956 2792 1663 4 1 3 | |
41 827932 827705 120000 6957 2791 1664 4 1 3 | |
41 827973 827705 120000 6958 2790 1665 4 1 3 | |
40 828013 827705 120000 6959 2789 1666 4 1 3 | |
41 828054 827705 120000 6960 2788 1667 4 1 3 | |
38 828092 827705 120000 6961 2787 1668 4 1 3 | |
40 828132 827705 120000 6962 2786 1669 4 1 3 | |
40 828172 827705 120000 6963 2785 1670 4 1 3 | |
40 828212 827705 120000 6964 2784 1671 4 1 3 | |
39 828251 827705 120000 6965 2783 1672 4 1 3 | |
40 828291 827705 120000 6966 2782 1673 4 1 3 | |
40 828331 827705 120000 6967 2781 1674 4 1 3 | |
39 828370 827705 120000 6968 2780 1675 4 1 3 | |
63 828433 827705 120000 6969 2779 1676 4 1 3 | |
46 828479 827705 120000 6970 2778 1677 4 1 3 | |
41 828520 827705 120000 6971 2777 1678 4 1 3 | |
43 828563 827705 120997 6972 2776 1635 4 1 3 | |
39 828602 827705 120997 6973 2775 1636 4 1 3 | |
40 828642 827705 120997 6974 2774 1637 4 1 3 | |
100 828742 828725 120997 6975 2817 1638 4 1 3 | |
45 828787 828725 120997 6976 2816 1639 4 1 3 | |
41 828828 828725 120997 6977 2815 1640 4 1 3 | |
41 828869 828725 120997 6978 2814 1641 4 1 3 | |
41 828910 828725 120997 6979 2813 1642 4 1 3 | |
41 828951 828725 120997 6980 2812 1643 4 1 3 | |
40 828991 828725 120997 6981 2811 1644 4 1 3 | |
40 829031 828725 120997 6982 2810 1645 4 1 3 | |
40 829071 828725 120997 6983 2809 1646 4 1 3 | |
40 829111 828725 120997 6984 2808 1647 4 1 3 | |
41 829152 828725 120997 6985 2807 1648 4 1 3 | |
40 829192 828725 120997 6986 2806 1649 4 1 3 | |
40 829232 828725 120997 6987 2805 1650 4 1 3 | |
39 829271 828725 120997 6988 2804 1651 4 1 3 | |
41 829312 828725 120997 6989 2803 1652 4 1 3 | |
39 829351 828725 120997 6990 2802 1653 4 1 3 | |
39 829390 828725 120997 6991 2801 1654 4 1 3 | |
66 829456 828725 120997 6992 2800 1655 4 1 3 | |
43 829499 828725 120997 6993 2799 1656 4 1 3 | |
43 829542 828725 121995 6994 2798 1613 4 1 3 | |
41 829583 828725 121995 6995 2797 1614 4 1 3 | |
39 829622 828725 121995 6996 2796 1615 4 1 3 | |
84 829706 829700 121995 6997 2795 1616 4 1 3 | |
48 829754 829700 121995 6998 2838 1617 4 1 3 | |
44 829798 829700 121995 6999 2837 1618 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 829839 829700 121995 7000 2836 1619 4 1 3 | |
44 829883 829700 121995 7001 2835 1620 4 1 3 | |
43 829926 829700 121995 7002 2834 1621 4 1 3 | |
39 829965 829700 121995 7003 2833 1622 4 1 3 | |
40 830005 829700 121995 7004 2832 1623 4 1 3 | |
41 830046 829700 121995 7005 2831 1624 4 1 3 | |
40 830086 829700 121995 7006 2830 1625 4 1 3 | |
40 830126 829700 121995 7007 2829 1626 4 1 3 | |
40 830166 829700 121995 7008 2828 1627 4 1 3 | |
40 830206 829700 121995 7009 2827 1628 4 1 3 | |
39 830245 829700 121995 7010 2826 1629 4 1 3 | |
40 830285 829700 121995 7011 2825 1630 4 1 3 | |
39 830324 829700 121995 7012 2824 1631 4 1 3 | |
40 830364 829700 121995 7013 2823 1632 4 1 3 | |
63 830427 829700 121995 7014 2822 1633 4 1 3 | |
47 830474 829700 121995 7015 2821 1634 4 1 3 | |
41 830515 829700 121995 7016 2820 1635 4 1 3 | |
42 830557 829700 122993 7017 2819 1592 4 1 3 | |
41 830598 829700 122993 7018 2818 1593 4 1 3 | |
39 830637 829700 122993 7019 2817 1594 4 1 3 | |
88 830725 830710 122993 7020 2860 1595 4 1 3 | |
45 830770 830710 122993 7021 2859 1596 4 1 3 | |
90 830860 830710 122993 7022 2858 1597 4 1 3 | |
45 830905 830710 122993 7023 2857 1598 4 1 3 | |
42 830947 830710 122993 7024 2856 1599 4 1 3 | |
69 831016 830710 122993 7025 2855 1600 4 1 3 | |
47 831063 830710 122993 7026 2854 1601 4 1 3 | |
41 831104 830710 122993 7027 2853 1602 4 1 3 | |
40 831144 830710 122993 7028 2852 1603 4 1 3 | |
43 831187 830710 122993 7029 2851 1604 4 1 3 | |
40 831227 830710 122993 7030 2850 1605 4 1 3 | |
39 831266 830710 122993 7031 2849 1606 4 1 3 | |
42 831308 830710 122993 7032 2848 1607 4 1 3 | |
40 831348 830710 122993 7033 2847 1608 4 1 3 | |
39 831387 830710 122993 7034 2846 1609 4 1 3 | |
69 831456 830710 122993 7035 2845 1610 4 1 3 | |
44 831500 830710 122993 7036 2844 1611 4 1 3 | |
43 831543 830710 123990 7037 2843 1568 4 1 3 | |
41 831584 830710 123990 7038 2842 1569 4 1 3 | |
40 831624 830710 123990 7039 2841 1570 4 1 3 | |
92 831716 831710 123990 7040 2840 1571 4 1 3 | |
49 831765 831710 123990 7041 2883 1572 4 1 3 | |
44 831809 831710 123990 7042 2882 1573 4 1 3 | |
40 831849 831710 123990 7043 2881 1574 4 1 3 | |
40 831889 831710 123990 7044 2880 1575 4 1 3 | |
42 831931 831710 123990 7045 2879 1576 4 1 3 | |
40 831971 831710 123990 7046 2878 1577 4 1 3 | |
39 832010 831710 123990 7047 2877 1578 4 1 3 | |
41 832051 831710 123990 7048 2876 1579 4 1 3 | |
40 832091 831710 123990 7049 2875 1580 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 832130 831710 123990 7050 2874 1581 4 1 3 | |
44 832174 831710 123990 7051 2873 1582 4 1 3 | |
40 832214 831710 123990 7052 2872 1583 4 1 3 | |
40 832254 831710 123990 7053 2871 1584 4 1 3 | |
41 832295 831710 123990 7054 2870 1585 4 1 3 | |
39 832334 831710 123990 7055 2869 1586 4 1 3 | |
40 832374 831710 123990 7056 2868 1587 4 1 3 | |
67 832441 831710 123990 7057 2867 1588 4 1 3 | |
45 832486 831710 123990 7058 2866 1589 4 1 3 | |
60 832546 831710 123990 7059 2865 1590 4 1 3 | |
47 832593 831710 124988 7060 2864 1547 4 1 3 | |
41 832634 831710 124988 7061 2863 1548 4 1 3 | |
91 832725 832710 124988 7062 2906 1549 4 1 3 | |
45 832770 832710 124988 7063 2905 1550 4 1 3 | |
42 832812 832710 124988 7064 2904 1551 4 1 3 | |
40 832852 832710 124988 7065 2903 1552 4 1 3 | |
39 832891 832710 124988 7066 2902 1553 4 1 3 | |
41 832932 832710 124988 7067 2901 1554 4 1 3 | |
39 832971 832710 124988 7068 2900 1555 4 1 3 | |
39 833010 832710 124988 7069 2899 1556 4 1 3 | |
41 833051 832710 124988 7070 2898 1557 4 1 3 | |
41 833092 832710 124988 7071 2897 1558 4 1 3 | |
39 833131 832710 124988 7072 2896 1559 4 1 3 | |
41 833172 832710 124988 7073 2895 1560 4 1 3 | |
40 833212 832710 124988 7074 2894 1561 4 1 3 | |
39 833251 832710 124988 7075 2893 1562 4 1 3 | |
41 833292 832710 124988 7076 2892 1563 4 1 3 | |
39 833331 832710 124988 7077 2891 1564 4 1 3 | |
40 833371 832710 124988 7078 2890 1565 4 1 3 | |
63 833434 832710 124988 7079 2889 1566 4 1 3 | |
44 833478 832710 124988 7080 2888 1567 4 1 3 | |
42 833520 832710 124988 7081 2887 1568 4 1 3 | |
42 833562 832710 125986 7082 2886 1525 4 1 3 | |
40 833602 832710 125986 7083 2885 1526 4 1 3 | |
40 833642 832710 125986 7084 2884 1527 4 1 3 | |
93 833735 833719 125986 7085 2927 1528 4 1 3 | |
45 833780 833719 125986 7086 2926 1529 4 1 3 | |
42 833822 833719 125986 7087 2925 1530 4 1 3 | |
39 833861 833719 125986 7088 2924 1531 4 1 3 | |
41 833902 833719 125986 7089 2923 1532 4 1 3 | |
40 833942 833719 125986 7090 2922 1533 4 1 3 | |
40 833982 833719 125986 7091 2921 1534 4 1 3 | |
39 834021 833719 125986 7092 2920 1535 4 1 3 | |
41 834062 833719 125986 7093 2919 1536 4 1 3 | |
39 834101 833719 125986 7094 2918 1537 4 1 3 | |
39 834140 833719 125986 7095 2917 1538 4 1 3 | |
41 834181 833719 125986 7096 2916 1539 4 1 3 | |
39 834220 833719 125986 7097 2915 1540 4 1 3 | |
39 834259 833719 125986 7098 2914 1541 4 1 3 | |
41 834300 833719 125986 7099 2913 1542 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 834339 833719 125986 7100 2912 1543 4 1 3 | |
41 834380 833719 125986 7101 2911 1544 4 1 3 | |
68 834448 833719 125986 7102 2910 1545 4 1 3 | |
43 834491 833719 125986 7103 2909 1546 4 1 3 | |
43 834534 833719 126984 7104 2908 1503 4 1 3 | |
41 834575 833719 126984 7105 2907 1504 4 1 3 | |
41 834616 833719 126984 7106 2906 1505 4 1 3 | |
79 834695 833719 126984 7107 2905 1506 4 1 3 | |
54 834749 834701 126984 7108 2948 1507 4 1 3 | |
43 834792 834701 126984 7109 2947 1508 4 1 3 | |
41 834833 834701 126984 7110 2946 1509 4 1 3 | |
39 834872 834701 126984 7111 2945 1510 4 1 3 | |
41 834913 834701 126984 7112 2944 1511 4 1 3 | |
40 834953 834701 126984 7113 2943 1512 4 1 3 | |
66 835019 834701 126984 7114 2942 1513 4 1 3 | |
47 835066 834701 126984 7115 2941 1514 4 1 3 | |
41 835107 834701 126984 7116 2940 1515 4 1 3 | |
40 835147 834701 126984 7117 2939 1516 4 1 3 | |
41 835188 834701 126984 7118 2938 1517 4 1 3 | |
41 835229 834701 126984 7119 2937 1518 4 1 3 | |
39 835268 834701 126984 7120 2936 1519 4 1 3 | |
41 835309 834701 126984 7121 2935 1520 4 1 3 | |
40 835349 834701 126984 7122 2934 1521 4 1 3 | |
40 835389 834701 126984 7123 2933 1522 4 1 3 | |
67 835456 834701 126984 7124 2932 1523 4 1 3 | |
44 835500 834701 126984 7125 2931 1524 4 1 3 | |
44 835544 834701 127981 7126 2930 1481 4 1 3 | |
40 835584 834701 127981 7127 2929 1482 4 1 3 | |
41 835625 834701 127981 7128 2928 1483 4 1 3 | |
89 835714 835707 128004 7129 2927 1483 4 1 3 | |
48 835762 835707 128004 7130 2970 1484 4 1 3 | |
43 835805 835707 128004 7131 2969 1485 4 1 3 | |
40 835845 835707 128004 7132 2968 1486 4 1 3 | |
40 835885 835707 128004 7133 2967 1487 4 1 3 | |
42 835927 835707 128004 7134 2966 1488 4 1 3 | |
40 835967 835707 128004 7135 2965 1489 4 1 3 | |
40 836007 835707 128004 7136 2964 1490 4 1 3 | |
42 836049 835707 128004 7137 2963 1491 4 1 3 | |
39 836088 835707 128004 7138 2962 1492 4 1 3 | |
39 836127 835707 128004 7139 2961 1493 4 1 3 | |
41 836168 835707 128004 7140 2960 1494 4 1 3 | |
39 836207 835707 128004 7141 2959 1495 4 1 3 | |
39 836246 835707 128004 7142 2958 1496 4 1 3 | |
42 836288 835707 128004 7143 2957 1497 4 1 3 | |
39 836327 835707 128004 7144 2956 1498 4 1 3 | |
39 836366 835707 128004 7145 2955 1499 4 1 3 | |
62 836428 835707 128004 7146 2954 1500 4 1 3 | |
47 836475 835707 128004 7147 2953 1501 4 1 3 | |
42 836517 835707 128004 7148 2952 1502 4 1 3 | |
43 836560 835707 129002 7149 2951 1459 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 836599 835707 129002 7150 2950 1460 4 1 3 | |
44 836643 835707 129002 7151 2949 1461 4 1 3 | |
92 836735 836718 129002 7152 2992 1462 4 1 3 | |
46 836781 836718 129002 7153 2991 1463 4 1 3 | |
42 836823 836718 129002 7154 2990 1464 4 1 3 | |
41 836864 836718 129002 7155 2989 1465 4 1 3 | |
40 836904 836718 129002 7156 2988 1466 4 1 3 | |
40 836944 836718 129002 7157 2987 1467 4 1 3 | |
39 836983 836718 129002 7158 2986 1468 4 1 3 | |
39 837022 836718 129002 7159 2985 1469 4 1 3 | |
41 837063 836718 129002 7160 2984 1470 4 1 3 | |
40 837103 836718 129002 7161 2983 1471 4 1 3 | |
40 837143 836718 129002 7162 2982 1472 4 1 3 | |
40 837183 836718 129002 7163 2981 1473 4 1 3 | |
40 837223 836718 129002 7164 2980 1474 4 1 3 | |
39 837262 836718 129002 7165 2979 1475 4 1 3 | |
41 837303 836718 129002 7166 2978 1476 4 1 3 | |
39 837342 836718 129002 7167 2977 1477 4 1 3 | |
38 837380 836718 129002 7168 2976 1478 4 1 3 | |
66 837446 836718 129002 7169 2975 1479 4 1 3 | |
44 837490 836718 129002 7170 2974 1480 4 1 3 | |
42 837532 836718 130000 7171 2973 1437 4 1 3 | |
41 837573 836718 130000 7172 2972 1438 4 1 3 | |
40 837613 836718 130000 7173 2971 1439 4 1 3 | |
41 837654 836718 130000 7174 2970 1440 4 1 3 | |
89 837743 837696 130000 7175 3014 1441 4 1 3 | |
44 837787 837696 130000 7176 3013 1442 4 1 3 | |
42 837829 837696 130000 7177 3012 1443 4 1 3 | |
39 837868 837696 130000 7178 3011 1444 4 1 3 | |
41 837909 837696 130000 7179 3010 1445 4 1 3 | |
40 837949 837696 130000 7180 3009 1446 4 1 3 | |
40 837989 837696 130000 7181 3008 1447 4 1 3 | |
40 838029 837696 130000 7182 3007 1448 4 1 3 | |
40 838069 837696 130000 7183 3006 1449 4 1 3 | |
40 838109 837696 130000 7184 3005 1450 4 1 3 | |
39 838148 837696 130000 7185 3004 1451 4 1 3 | |
40 838188 837696 130000 7186 3003 1452 4 1 3 | |
39 838227 837696 130000 7187 3002 1453 4 1 3 | |
40 838267 837696 130000 7188 3001 1454 4 1 3 | |
41 838308 837696 130000 7189 3000 1455 4 1 3 | |
39 838347 837696 130000 7190 2999 1456 4 1 3 | |
40 838387 837696 130000 7191 2998 1457 4 1 3 | |
65 838452 837696 130000 7192 2997 1458 4 1 3 | |
43 838495 837696 130000 7193 2996 1459 4 1 3 | |
43 838538 837696 130997 7194 2995 1416 4 1 3 | |
41 838579 837696 130997 7195 2994 1417 4 1 3 | |
41 838620 837696 130997 7196 2993 1418 4 1 3 | |
84 838704 838698 130997 7197 2992 1419 4 1 3 | |
48 838752 838698 130997 7198 3035 1420 4 1 3 | |
44 838796 838698 130997 7199 3034 1421 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 838837 838698 130997 7200 3033 1422 4 1 3 | |
43 838880 838698 130997 7201 3032 1423 4 1 3 | |
65 838945 838698 130997 7202 3031 1424 4 1 3 | |
42 838987 838698 130997 7203 3030 1425 4 1 3 | |
42 839029 838698 130997 7204 3029 1426 4 1 3 | |
42 839071 838698 130997 7205 3028 1427 4 1 3 | |
40 839111 838698 130997 7206 3027 1428 4 1 3 | |
40 839151 838698 130997 7207 3026 1429 4 1 3 | |
40 839191 838698 130997 7208 3025 1430 4 1 3 | |
40 839231 838698 130997 7209 3024 1431 4 1 3 | |
40 839271 838698 130997 7210 3023 1432 4 1 3 | |
41 839312 838698 130997 7211 3022 1433 4 1 3 | |
39 839351 838698 130997 7212 3021 1434 4 1 3 | |
40 839391 838698 130997 7213 3020 1435 4 1 3 | |
68 839459 838698 130997 7214 3019 1436 4 1 3 | |
42 839501 838698 130997 7215 3018 1437 4 1 3 | |
42 839543 838698 131995 7216 3017 1394 4 1 3 | |
40 839583 838698 131995 7217 3016 1395 4 1 3 | |
40 839623 838698 131995 7218 3015 1396 4 1 3 | |
86 839709 839703 131995 7219 3014 1397 4 1 3 | |
49 839758 839703 131995 7220 3057 1398 4 1 3 | |
44 839802 839703 131995 7221 3056 1399 4 1 3 | |
41 839843 839703 131995 7222 3055 1400 4 1 3 | |
39 839882 839703 131995 7223 3054 1401 4 1 3 | |
42 839924 839703 131995 7224 3053 1402 4 1 3 | |
40 839964 839703 131995 7225 3052 1403 4 1 3 | |
39 840003 839703 131995 7226 3051 1404 4 1 3 | |
43 840046 839703 131995 7227 3050 1405 4 1 3 | |
40 840086 839703 131995 7228 3049 1406 4 1 3 | |
39 840125 839703 131995 7229 3048 1407 4 1 3 | |
41 840166 839703 131995 7230 3047 1408 4 1 3 | |
39 840205 839703 131995 7231 3046 1409 4 1 3 | |
39 840244 839703 131995 7232 3045 1410 4 1 3 | |
42 840286 839703 131995 7233 3044 1411 4 1 3 | |
39 840325 839703 131995 7234 3043 1412 4 1 3 | |
39 840364 839703 131995 7235 3042 1413 4 1 3 | |
65 840429 839703 131995 7236 3041 1414 4 1 3 | |
47 840476 839703 131995 7237 3040 1415 4 1 3 | |
41 840517 839703 131995 7238 3039 1416 4 1 3 | |
65 840582 839703 132993 7239 3038 1373 4 1 3 | |
43 840625 839703 132993 7240 3037 1374 4 1 3 | |
90 840715 840685 132993 7241 3080 1375 4 1 3 | |
47 840762 840685 132993 7242 3079 1376 4 1 3 | |
101 840863 840685 132993 7243 3078 1377 4 1 3 | |
47 840910 840685 132993 7244 3077 1378 4 1 3 | |
42 840952 840685 132993 7245 3076 1379 4 1 3 | |
41 840993 840685 132993 7246 3075 1380 4 1 3 | |
40 841033 840685 132993 7247 3074 1381 4 1 3 | |
39 841072 840685 132993 7248 3073 1382 4 1 3 | |
40 841112 840685 132993 7249 3072 1383 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 841153 840685 132993 7250 3071 1384 4 1 3 | |
43 841196 840685 132993 7251 3070 1385 4 1 3 | |
40 841236 840685 132993 7252 3069 1386 4 1 3 | |
41 841277 840685 132993 7253 3068 1387 4 1 3 | |
40 841317 840685 132993 7254 3067 1388 4 1 3 | |
39 841356 840685 132993 7255 3066 1389 4 1 3 | |
40 841396 840685 132993 7256 3065 1390 4 1 3 | |
70 841466 840685 132993 7257 3064 1391 4 1 3 | |
43 841509 840685 132993 7258 3063 1392 4 1 3 | |
44 841553 840685 133990 7259 3062 1349 4 1 3 | |
41 841594 840685 133990 7260 3061 1350 4 1 3 | |
39 841633 840685 133990 7261 3060 1351 4 1 3 | |
96 841729 841713 133990 7262 3103 1352 4 1 3 | |
48 841777 841713 133990 7263 3102 1353 4 1 3 | |
41 841818 841713 133990 7264 3101 1354 4 1 3 | |
40 841858 841713 133990 7265 3100 1355 4 1 3 | |
39 841897 841713 133990 7266 3099 1356 4 1 3 | |
41 841938 841713 133990 7267 3098 1357 4 1 3 | |
39 841977 841713 133990 7268 3097 1358 4 1 3 | |
38 842015 841713 133990 7269 3096 1359 4 1 3 | |
42 842057 841713 133990 7270 3095 1360 4 1 3 | |
38 842095 841713 133990 7271 3094 1361 4 1 3 | |
40 842135 841713 133990 7272 3093 1362 4 1 3 | |
40 842175 841713 133990 7273 3092 1363 4 1 3 | |
40 842215 841713 133990 7274 3091 1364 4 1 3 | |
38 842253 841713 133990 7275 3090 1365 4 1 3 | |
41 842294 841713 133990 7276 3089 1366 4 1 3 | |
40 842334 841713 133990 7277 3088 1367 4 1 3 | |
38 842372 841713 133990 7278 3087 1368 4 1 3 | |
63 842435 841713 133990 7279 3086 1369 4 1 3 | |
47 842482 841713 133990 7280 3085 1370 4 1 3 | |
41 842523 841713 133990 7281 3084 1371 4 1 3 | |
43 842566 841713 134988 7282 3083 1328 4 1 3 | |
40 842606 841713 134988 7283 3082 1329 4 1 3 | |
40 842646 841713 134988 7284 3081 1330 4 1 3 | |
90 842736 842721 134988 7285 3124 1331 4 1 3 | |
46 842782 842721 134988 7286 3123 1332 4 1 3 | |
41 842823 842721 134988 7287 3122 1333 4 1 3 | |
40 842863 842721 134988 7288 3121 1334 4 1 3 | |
41 842904 842721 134988 7289 3120 1335 4 1 3 | |
40 842944 842721 134988 7290 3119 1336 4 1 3 | |
39 842983 842721 134988 7291 3118 1337 4 1 3 | |
74 843057 842721 134988 7292 3117 1338 4 1 3 | |
45 843102 842721 134988 7293 3116 1339 4 1 3 | |
41 843143 842721 134988 7294 3115 1340 4 1 3 | |
42 843185 842721 134988 7295 3114 1341 4 1 3 | |
40 843225 842721 134988 7296 3113 1342 4 1 3 | |
40 843265 842721 134988 7297 3112 1343 4 1 3 | |
41 843306 842721 134988 7298 3111 1344 4 1 3 | |
39 843345 842721 134988 7299 3110 1345 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 843384 842721 134988 7300 3109 1346 4 1 3 | |
73 843457 842721 134988 7301 3108 1347 4 1 3 | |
44 843501 842721 134988 7302 3107 1348 4 1 3 | |
43 843544 842721 135986 7303 3106 1305 4 1 3 | |
41 843585 842721 135986 7304 3105 1306 4 1 3 | |
40 843625 842721 135986 7305 3104 1307 4 1 3 | |
90 843715 843709 135986 7306 3103 1308 4 1 3 | |
46 843761 843709 135986 7307 3146 1309 4 1 3 | |
43 843804 843709 135986 7308 3145 1310 4 1 3 | |
42 843846 843709 135986 7309 3144 1311 4 1 3 | |
39 843885 843709 135986 7310 3143 1312 4 1 3 | |
42 843927 843709 135986 7311 3142 1313 4 1 3 | |
39 843966 843709 135986 7312 3141 1314 4 1 3 | |
40 844006 843709 135986 7313 3140 1315 4 1 3 | |
41 844047 843709 135986 7314 3139 1316 4 1 3 | |
39 844086 843709 135986 7315 3138 1317 4 1 3 | |
39 844125 843709 135986 7316 3137 1318 4 1 3 | |
41 844166 843709 135986 7317 3136 1319 4 1 3 | |
40 844206 843709 135986 7318 3135 1320 4 1 3 | |
39 844245 843709 135986 7319 3134 1321 4 1 3 | |
41 844286 843709 135986 7320 3133 1322 4 1 3 | |
40 844326 843709 135986 7321 3132 1323 4 1 3 | |
40 844366 843709 135986 7322 3131 1324 4 1 3 | |
63 844429 843709 135986 7323 3130 1325 4 1 3 | |
45 844474 843709 135986 7324 3129 1326 4 1 3 | |
41 844515 843709 135986 7325 3128 1327 4 1 3 | |
42 844557 843709 136984 7326 3127 1284 4 1 3 | |
41 844598 843709 136984 7327 3126 1285 4 1 3 | |
39 844637 843709 136984 7328 3125 1286 4 1 3 | |
92 844729 844714 136984 7329 3168 1287 4 1 3 | |
45 844774 844714 136984 7330 3167 1288 4 1 3 | |
43 844817 844714 136984 7331 3166 1289 4 1 3 | |
41 844858 844714 136984 7332 3165 1290 4 1 3 | |
39 844897 844714 136984 7333 3164 1291 4 1 3 | |
41 844938 844714 136984 7334 3163 1292 4 1 3 | |
40 844978 844714 136984 7335 3162 1293 4 1 3 | |
39 845017 844714 136984 7336 3161 1294 4 1 3 | |
41 845058 844714 136984 7337 3160 1295 4 1 3 | |
39 845097 844714 136984 7338 3159 1296 4 1 3 | |
39 845136 844714 136984 7339 3158 1297 4 1 3 | |
41 845177 844714 136984 7340 3157 1298 4 1 3 | |
39 845216 844714 136984 7341 3156 1299 4 1 3 | |
40 845256 844714 136984 7342 3155 1300 4 1 3 | |
41 845297 844714 136984 7343 3154 1301 4 1 3 | |
40 845337 844714 136984 7344 3153 1302 4 1 3 | |
40 845377 844714 136984 7345 3152 1303 4 1 3 | |
64 845441 844714 136984 7346 3151 1304 4 1 3 | |
45 845486 844714 136984 7347 3150 1305 4 1 3 | |
42 845528 844714 136984 7348 3149 1306 4 1 3 | |
41 845569 844714 137981 7349 3148 1263 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 845609 844714 137981 7350 3147 1264 4 1 3 | |
43 845652 844714 137981 7351 3146 1265 4 1 3 | |
93 845745 845730 138004 7352 3189 1265 4 1 3 | |
44 845789 845730 138004 7353 3188 1266 4 1 3 | |
41 845830 845730 138004 7354 3187 1267 4 1 3 | |
40 845870 845730 138004 7355 3186 1268 4 1 3 | |
41 845911 845730 138004 7356 3185 1269 4 1 3 | |
40 845951 845730 138004 7357 3184 1270 4 1 3 | |
40 845991 845730 138004 7358 3183 1271 4 1 3 | |
40 846031 845730 138004 7359 3182 1272 4 1 3 | |
40 846071 845730 138004 7360 3181 1273 4 1 3 | |
40 846111 845730 138004 7361 3180 1274 4 1 3 | |
40 846151 845730 138004 7362 3179 1275 4 1 3 | |
40 846191 845730 138004 7363 3178 1276 4 1 3 | |
39 846230 845730 138004 7364 3177 1277 4 1 3 | |
39 846269 845730 138004 7365 3176 1278 4 1 3 | |
41 846310 845730 138004 7366 3175 1279 4 1 3 | |
39 846349 845730 138004 7367 3174 1280 4 1 3 | |
41 846390 845730 138004 7368 3173 1281 4 1 3 | |
65 846455 845730 138004 7369 3172 1282 4 1 3 | |
44 846499 845730 138004 7370 3171 1283 4 1 3 | |
43 846542 845730 139002 7371 3170 1240 4 1 3 | |
41 846583 845730 139002 7372 3169 1241 4 1 3 | |
40 846623 845730 139002 7373 3168 1242 4 1 3 | |
87 846710 846704 139002 7374 3167 1243 4 1 3 | |
49 846759 846704 139002 7375 3210 1244 4 1 3 | |
44 846803 846704 139002 7376 3209 1245 4 1 3 | |
41 846844 846704 139002 7377 3208 1246 4 1 3 | |
40 846884 846704 139002 7378 3207 1247 4 1 3 | |
42 846926 846704 139002 7379 3206 1248 4 1 3 | |
67 846993 846704 139002 7380 3205 1249 4 1 3 | |
45 847038 846704 139002 7381 3204 1250 4 1 3 | |
40 847078 846704 139002 7382 3203 1251 4 1 3 | |
39 847117 846704 139002 7383 3202 1252 4 1 3 | |
41 847158 846704 139002 7384 3201 1253 4 1 3 | |
41 847199 846704 139002 7385 3200 1254 4 1 3 | |
39 847238 846704 139002 7386 3199 1255 4 1 3 | |
41 847279 846704 139002 7387 3198 1256 4 1 3 | |
40 847319 846704 139002 7388 3197 1257 4 1 3 | |
39 847358 846704 139002 7389 3196 1258 4 1 3 | |
39 847397 846704 139002 7390 3195 1259 4 1 3 | |
71 847468 846704 139002 7391 3194 1260 4 1 3 | |
43 847511 846704 139002 7392 3193 1261 4 1 3 | |
43 847554 846704 140000 7393 3192 1218 4 1 3 | |
39 847593 846704 140000 7394 3191 1219 4 1 3 | |
40 847633 846704 140000 7395 3190 1220 4 1 3 | |
89 847722 847706 140000 7396 3234 1221 4 1 3 | |
46 847768 847706 140000 7397 3233 1222 4 1 3 | |
42 847810 847706 140000 7398 3232 1223 4 1 3 | |
41 847851 847706 140000 7399 3231 1224 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 847891 847706 140000 7400 3230 1225 4 1 3 | |
44 847935 847706 140000 7401 3229 1226 4 1 3 | |
39 847974 847706 140000 7402 3228 1227 4 1 3 | |
40 848014 847706 140000 7403 3227 1228 4 1 3 | |
40 848054 847706 140000 7404 3226 1229 4 1 3 | |
40 848094 847706 140000 7405 3225 1230 4 1 3 | |
39 848133 847706 140000 7406 3224 1231 4 1 3 | |
41 848174 847706 140000 7407 3223 1232 4 1 3 | |
39 848213 847706 140000 7408 3222 1233 4 1 3 | |
40 848253 847706 140000 7409 3221 1234 4 1 3 | |
41 848294 847706 140000 7410 3220 1235 4 1 3 | |
39 848333 847706 140000 7411 3219 1236 4 1 3 | |
41 848374 847706 140000 7412 3218 1237 4 1 3 | |
66 848440 847706 140000 7413 3217 1238 4 1 3 | |
47 848487 847706 140000 7414 3216 1239 4 1 3 | |
61 848548 847706 140000 7415 3215 1240 4 1 3 | |
46 848594 847706 140997 7416 3214 1197 4 1 3 | |
42 848636 847706 140997 7417 3213 1198 4 1 3 | |
93 848729 848713 140997 7418 3256 1199 4 1 3 | |
45 848774 848713 140997 7419 3255 1200 4 1 3 | |
43 848817 848713 140997 7420 3254 1201 4 1 3 | |
42 848859 848713 140997 7421 3253 1202 4 1 3 | |
39 848898 848713 140997 7422 3252 1203 4 1 3 | |
42 848940 848713 140997 7423 3251 1204 4 1 3 | |
41 848981 848713 140997 7424 3250 1205 4 1 3 | |
40 849021 848713 140997 7425 3249 1206 4 1 3 | |
40 849061 848713 140997 7426 3248 1207 4 1 3 | |
41 849102 848713 140997 7427 3247 1208 4 1 3 | |
40 849142 848713 140997 7428 3246 1209 4 1 3 | |
41 849183 848713 140997 7429 3245 1210 4 1 3 | |
40 849223 848713 140997 7430 3244 1211 4 1 3 | |
38 849261 848713 140997 7431 3243 1212 4 1 3 | |
42 849303 848713 140997 7432 3242 1213 4 1 3 | |
40 849343 848713 140997 7433 3241 1214 4 1 3 | |
39 849382 848713 140997 7434 3240 1215 4 1 3 | |
65 849447 848713 140997 7435 3239 1216 4 1 3 | |
45 849492 848713 140997 7436 3238 1217 4 1 3 | |
42 849534 848713 141995 7437 3237 1174 4 1 3 | |
40 849574 848713 141995 7438 3236 1175 4 1 3 | |
40 849614 848713 141995 7439 3235 1176 4 1 3 | |
41 849655 848713 141995 7440 3234 1177 4 1 3 | |
93 849748 849699 141995 7441 3277 1178 4 1 3 | |
44 849792 849699 141995 7442 3276 1179 4 1 3 | |
41 849833 849699 141995 7443 3275 1180 4 1 3 | |
40 849873 849699 141995 7444 3274 1181 4 1 3 | |
40 849913 849699 141995 7445 3273 1182 4 1 3 | |
40 849953 849699 141995 7446 3272 1183 4 1 3 | |
40 849993 849699 141995 7447 3271 1184 4 1 3 | |
41 850034 849699 141995 7448 3270 1185 4 1 3 | |
40 850074 849699 141995 7449 3269 1186 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 850114 849699 141995 7450 3268 1187 4 1 3 | |
43 850157 849699 141995 7451 3267 1188 4 1 3 | |
41 850198 849699 141995 7452 3266 1189 4 1 3 | |
40 850238 849699 141995 7453 3265 1190 4 1 3 | |
41 850279 849699 141995 7454 3264 1191 4 1 3 | |
39 850318 849699 141995 7455 3263 1192 4 1 3 | |
39 850357 849699 141995 7456 3262 1193 4 1 3 | |
39 850396 849699 141995 7457 3261 1194 4 1 3 | |
68 850464 849699 141995 7458 3260 1195 4 1 3 | |
42 850506 849699 141995 7459 3259 1196 4 1 3 | |
43 850549 849699 142993 7460 3258 1153 4 1 3 | |
41 850590 849699 142993 7461 3257 1154 4 1 3 | |
40 850630 849699 142993 7462 3256 1155 4 1 3 | |
85 850715 850700 142993 7463 3299 1156 4 1 3 | |
48 850763 850700 142993 7464 3298 1157 4 1 3 | |
92 850855 850700 142993 7465 3297 1158 4 1 3 | |
45 850900 850700 142993 7466 3296 1159 4 1 3 | |
43 850943 850700 142993 7467 3295 1160 4 1 3 | |
72 851015 850700 142993 7468 3294 1161 4 1 3 | |
46 851061 850700 142993 7469 3293 1162 4 1 3 | |
42 851103 850700 142993 7470 3292 1163 4 1 3 | |
40 851143 850700 142993 7471 3291 1164 4 1 3 | |
40 851183 850700 142993 7472 3290 1165 4 1 3 | |
41 851224 850700 142993 7473 3289 1166 4 1 3 | |
40 851264 850700 142993 7474 3288 1167 4 1 3 | |
40 851304 850700 142993 7475 3287 1168 4 1 3 | |
40 851344 850700 142993 7476 3286 1169 4 1 3 | |
40 851384 850700 142993 7477 3285 1170 4 1 3 | |
72 851456 850700 142993 7478 3284 1171 4 1 3 | |
44 851500 850700 142993 7479 3283 1172 4 1 3 | |
43 851543 850700 143990 7480 3282 1129 4 1 3 | |
40 851583 850700 143990 7481 3281 1130 4 1 3 | |
40 851623 850700 143990 7482 3280 1131 4 1 3 | |
90 851713 851707 143990 7483 3279 1132 4 1 3 | |
47 851760 851707 143990 7484 3322 1133 4 1 3 | |
44 851804 851707 143990 7485 3321 1134 4 1 3 | |
41 851845 851707 143990 7486 3320 1135 4 1 3 | |
40 851885 851707 143990 7487 3319 1136 4 1 3 | |
42 851927 851707 143990 7488 3318 1137 4 1 3 | |
40 851967 851707 143990 7489 3317 1138 4 1 3 | |
39 852006 851707 143990 7490 3316 1139 4 1 3 | |
41 852047 851707 143990 7491 3315 1140 4 1 3 | |
40 852087 851707 143990 7492 3314 1141 4 1 3 | |
39 852126 851707 143990 7493 3313 1142 4 1 3 | |
40 852166 851707 143990 7494 3312 1143 4 1 3 | |
39 852205 851707 143990 7495 3311 1144 4 1 3 | |
40 852245 851707 143990 7496 3310 1145 4 1 3 | |
41 852286 851707 143990 7497 3309 1146 4 1 3 | |
40 852326 851707 143990 7498 3308 1147 4 1 3 | |
39 852365 851707 143990 7499 3307 1148 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
61 852426 851707 143990 7500 3306 1149 4 1 3 | |
51 852477 851707 143990 7501 3305 1150 4 1 3 | |
42 852519 851707 143990 7502 3304 1151 4 1 3 | |
43 852562 851707 144988 7503 3303 1108 4 1 3 | |
40 852602 851707 144988 7504 3302 1109 4 1 3 | |
40 852642 851707 144988 7505 3301 1110 4 1 3 | |
92 852734 852718 144988 7506 3344 1111 4 1 3 | |
47 852781 852718 144988 7507 3343 1112 4 1 3 | |
41 852822 852718 144988 7508 3342 1113 4 1 3 | |
40 852862 852718 144988 7509 3341 1114 4 1 3 | |
39 852901 852718 144988 7510 3340 1115 4 1 3 | |
41 852942 852718 144988 7511 3339 1116 4 1 3 | |
40 852982 852718 144988 7512 3338 1117 4 1 3 | |
39 853021 852718 144988 7513 3337 1118 4 1 3 | |
41 853062 852718 144988 7514 3336 1119 4 1 3 | |
40 853102 852718 144988 7515 3335 1120 4 1 3 | |
39 853141 852718 144988 7516 3334 1121 4 1 3 | |
41 853182 852718 144988 7517 3333 1122 4 1 3 | |
40 853222 852718 144988 7518 3332 1123 4 1 3 | |
40 853262 852718 144988 7519 3331 1124 4 1 3 | |
40 853302 852718 144988 7520 3330 1125 4 1 3 | |
40 853342 852718 144988 7521 3329 1126 4 1 3 | |
39 853381 852718 144988 7522 3328 1127 4 1 3 | |
65 853446 852718 144988 7523 3327 1128 4 1 3 | |
46 853492 852718 144988 7524 3326 1129 4 1 3 | |
43 853535 852718 145986 7525 3325 1086 4 1 3 | |
42 853577 852718 145986 7526 3324 1087 4 1 3 | |
40 853617 852718 145986 7527 3323 1088 4 1 3 | |
81 853698 852718 145986 7528 3322 1089 4 1 3 | |
53 853751 853704 145986 7529 3365 1090 4 1 3 | |
43 853794 853704 145986 7530 3364 1091 4 1 3 | |
41 853835 853704 145986 7531 3363 1092 4 1 3 | |
40 853875 853704 145986 7532 3362 1093 4 1 3 | |
40 853915 853704 145986 7533 3361 1094 4 1 3 | |
40 853955 853704 145986 7534 3360 1095 4 1 3 | |
40 853995 853704 145986 7535 3359 1096 4 1 3 | |
41 854036 853704 145986 7536 3358 1097 4 1 3 | |
40 854076 853704 145986 7537 3357 1098 4 1 3 | |
39 854115 853704 145986 7538 3356 1099 4 1 3 | |
40 854155 853704 145986 7539 3355 1100 4 1 3 | |
40 854195 853704 145986 7540 3354 1101 4 1 3 | |
40 854235 853704 145986 7541 3353 1102 4 1 3 | |
40 854275 853704 145986 7542 3352 1103 4 1 3 | |
40 854315 853704 145986 7543 3351 1104 4 1 3 | |
40 854355 853704 145986 7544 3350 1105 4 1 3 | |
39 854394 853704 145986 7545 3349 1106 4 1 3 | |
66 854460 853704 145986 7546 3348 1107 4 1 3 | |
43 854503 853704 145986 7547 3347 1108 4 1 3 | |
43 854546 853704 146984 7548 3346 1065 4 1 3 | |
41 854587 853704 146984 7549 3345 1066 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 854626 853704 146984 7550 3344 1067 4 1 3 | |
90 854716 854699 146984 7551 3387 1068 4 1 3 | |
48 854764 854699 146984 7552 3386 1069 4 1 3 | |
43 854807 854699 146984 7553 3385 1070 4 1 3 | |
41 854848 854699 146984 7554 3384 1071 4 1 3 | |
40 854888 854699 146984 7555 3383 1072 4 1 3 | |
66 854954 854699 146984 7556 3382 1073 4 1 3 | |
43 854997 854699 146984 7557 3381 1074 4 1 3 | |
42 855039 854699 146984 7558 3380 1075 4 1 3 | |
40 855079 854699 146984 7559 3379 1076 4 1 3 | |
40 855119 854699 146984 7560 3378 1077 4 1 3 | |
41 855160 854699 146984 7561 3377 1078 4 1 3 | |
40 855200 854699 146984 7562 3376 1079 4 1 3 | |
39 855239 854699 146984 7563 3375 1080 4 1 3 | |
41 855280 854699 146984 7564 3374 1081 4 1 3 | |
39 855319 854699 146984 7565 3373 1082 4 1 3 | |
39 855358 854699 146984 7566 3372 1083 4 1 3 | |
40 855398 854699 146984 7567 3371 1084 4 1 3 | |
72 855470 854699 146984 7568 3370 1085 4 1 3 | |
41 855511 854699 146984 7569 3369 1086 4 1 3 | |
44 855555 854699 147981 7570 3368 1043 4 1 3 | |
40 855595 854699 147981 7571 3367 1044 4 1 3 | |
40 855635 854699 147981 7572 3366 1045 4 1 3 | |
91 855726 855711 148004 7573 3409 1045 4 1 3 | |
46 855772 855711 148004 7574 3408 1046 4 1 3 | |
43 855815 855711 148004 7575 3407 1047 4 1 3 | |
41 855856 855711 148004 7576 3406 1048 4 1 3 | |
39 855895 855711 148004 7577 3405 1049 4 1 3 | |
42 855937 855711 148004 7578 3404 1050 4 1 3 | |
40 855977 855711 148004 7579 3403 1051 4 1 3 | |
39 856016 855711 148004 7580 3402 1052 4 1 3 | |
41 856057 855711 148004 7581 3401 1053 4 1 3 | |
40 856097 855711 148004 7582 3400 1054 4 1 3 | |
39 856136 855711 148004 7583 3399 1055 4 1 3 | |
42 856178 855711 148004 7584 3398 1056 4 1 3 | |
40 856218 855711 148004 7585 3397 1057 4 1 3 | |
39 856257 855711 148004 7586 3396 1058 4 1 3 | |
41 856298 855711 148004 7587 3395 1059 4 1 3 | |
40 856338 855711 148004 7588 3394 1060 4 1 3 | |
39 856377 855711 148004 7589 3393 1061 4 1 3 | |
66 856443 855711 148004 7590 3392 1062 4 1 3 | |
46 856489 855711 148004 7591 3391 1063 4 1 3 | |
61 856550 855711 149002 7592 3390 1020 4 1 3 | |
48 856598 855711 149002 7593 3389 1021 4 1 3 | |
41 856639 855711 149002 7594 3388 1022 4 1 3 | |
93 856732 856716 149002 7595 3431 1023 4 1 3 | |
47 856779 856716 149002 7596 3430 1024 4 1 3 | |
41 856820 856716 149002 7597 3429 1025 4 1 3 | |
40 856860 856716 149002 7598 3428 1026 4 1 3 | |
40 856900 856716 149002 7599 3427 1027 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
42 856942 856716 149002 7600 3426 1028 4 1 3 | |
42 856984 856716 149002 7601 3425 1029 4 1 3 | |
40 857024 856716 149002 7602 3424 1030 4 1 3 | |
40 857064 856716 149002 7603 3423 1031 4 1 3 | |
40 857104 856716 149002 7604 3422 1032 4 1 3 | |
39 857143 856716 149002 7605 3421 1033 4 1 3 | |
40 857183 856716 149002 7606 3420 1034 4 1 3 | |
40 857223 856716 149002 7607 3419 1035 4 1 3 | |
38 857261 856716 149002 7608 3418 1036 4 1 3 | |
41 857302 856716 149002 7609 3417 1037 4 1 3 | |
41 857343 856716 149002 7610 3416 1038 4 1 3 | |
39 857382 856716 149002 7611 3415 1039 4 1 3 | |
73 857455 856716 149002 7612 3414 1040 4 1 3 | |
44 857499 856716 149002 7613 3413 1041 4 1 3 | |
43 857542 856716 150000 7614 3412 998 4 1 3 | |
41 857583 856716 150000 7615 3411 999 4 1 3 | |
39 857622 856716 150000 7616 3410 1000 4 1 3 | |
88 857710 857703 150000 7617 3409 1001 4 1 3 | |
50 857760 857703 150000 7618 3453 1002 4 1 3 | |
43 857803 857703 150000 7619 3452 1003 4 1 3 | |
41 857844 857703 150000 7620 3451 1004 4 1 3 | |
40 857884 857703 150000 7621 3450 1005 4 1 3 | |
41 857925 857703 150000 7622 3449 1006 4 1 3 | |
40 857965 857703 150000 7623 3448 1007 4 1 3 | |
40 858005 857703 150000 7624 3447 1008 4 1 3 | |
40 858045 857703 150000 7625 3446 1009 4 1 3 | |
40 858085 857703 150000 7626 3445 1010 4 1 3 | |
39 858124 857703 150000 7627 3444 1011 4 1 3 | |
40 858164 857703 150000 7628 3443 1012 4 1 3 | |
40 858204 857703 150000 7629 3442 1013 4 1 3 | |
39 858243 857703 150000 7630 3441 1014 4 1 3 | |
41 858284 857703 150000 7631 3440 1015 4 1 3 | |
40 858324 857703 150000 7632 3439 1016 4 1 3 | |
40 858364 857703 150000 7633 3438 1017 4 1 3 | |
59 858423 857703 150000 7634 3437 1018 4 1 3 | |
49 858472 857703 150000 7635 3436 1019 4 1 3 | |
42 858514 857703 150000 7636 3435 1020 4 1 3 | |
42 858556 857703 150997 7637 3434 977 4 1 3 | |
40 858596 857703 150997 7638 3433 978 4 1 3 | |
40 858636 857703 150997 7639 3432 979 4 1 3 | |
87 858723 858708 150997 7640 3475 980 4 1 3 | |
45 858768 858708 150997 7641 3474 981 4 1 3 | |
42 858810 858708 150997 7642 3473 982 4 1 3 | |
40 858850 858708 150997 7643 3472 983 4 1 3 | |
40 858890 858708 150997 7644 3471 984 4 1 3 | |
41 858931 858708 150997 7645 3470 985 4 1 3 | |
65 858996 858708 150997 7646 3469 986 4 1 3 | |
45 859041 858708 150997 7647 3468 987 4 1 3 | |
41 859082 858708 150997 7648 3467 988 4 1 3 | |
40 859122 858708 150997 7649 3466 989 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 859163 858708 150997 7650 3465 990 4 1 3 | |
43 859206 858708 150997 7651 3464 991 4 1 3 | |
40 859246 858708 150997 7652 3463 992 4 1 3 | |
40 859286 858708 150997 7653 3462 993 4 1 3 | |
41 859327 858708 150997 7654 3461 994 4 1 3 | |
40 859367 858708 150997 7655 3460 995 4 1 3 | |
63 859430 858708 150997 7656 3459 996 4 1 3 | |
47 859477 858708 150997 7657 3458 997 4 1 3 | |
42 859519 858708 150997 7658 3457 998 4 1 3 | |
44 859563 858708 151995 7659 3456 955 4 1 3 | |
41 859604 858708 151995 7660 3455 956 4 1 3 | |
40 859644 858708 151995 7661 3454 957 4 1 3 | |
91 859735 859719 151995 7662 3497 958 4 1 3 | |
47 859782 859719 151995 7663 3496 959 4 1 3 | |
41 859823 859719 151995 7664 3495 960 4 1 3 | |
39 859862 859719 151995 7665 3494 961 4 1 3 | |
41 859903 859719 151995 7666 3493 962 4 1 3 | |
41 859944 859719 151995 7667 3492 963 4 1 3 | |
40 859984 859719 151995 7668 3491 964 4 1 3 | |
39 860023 859719 151995 7669 3490 965 4 1 3 | |
40 860063 859719 151995 7670 3489 966 4 1 3 | |
40 860103 859719 151995 7671 3488 967 4 1 3 | |
40 860143 859719 151995 7672 3487 968 4 1 3 | |
41 860184 859719 151995 7673 3486 969 4 1 3 | |
38 860222 859719 151995 7674 3485 970 4 1 3 | |
39 860261 859719 151995 7675 3484 971 4 1 3 | |
41 860302 859719 151995 7676 3483 972 4 1 3 | |
40 860342 859719 151995 7677 3482 973 4 1 3 | |
40 860382 859719 151995 7678 3481 974 4 1 3 | |
65 860447 859719 151995 7679 3480 975 4 1 3 | |
44 860491 859719 151995 7680 3479 976 4 1 3 | |
41 860532 859719 151995 7681 3478 977 4 1 3 | |
41 860573 859719 152993 7682 3477 934 4 1 3 | |
39 860612 859719 152993 7683 3476 935 4 1 3 | |
39 860651 859719 152993 7684 3475 936 4 1 3 | |
91 860742 860726 152993 7685 3518 937 4 1 3 | |
82 860824 860726 152993 7686 3517 938 4 1 3 | |
49 860873 860726 152993 7687 3516 939 4 1 3 | |
44 860917 860726 152993 7688 3515 940 4 1 3 | |
40 860957 860726 152993 7689 3514 941 4 1 3 | |
40 860997 860726 152993 7690 3513 942 4 1 3 | |
41 861038 860726 152993 7691 3512 943 4 1 3 | |
40 861078 860726 152993 7692 3511 944 4 1 3 | |
39 861117 860726 152993 7693 3510 945 4 1 3 | |
40 861157 860726 152993 7694 3509 946 4 1 3 | |
40 861197 860726 152993 7695 3508 947 4 1 3 | |
39 861236 860726 152993 7696 3507 948 4 1 3 | |
39 861275 860726 152993 7697 3506 949 4 1 3 | |
41 861316 860726 152993 7698 3505 950 4 1 3 | |
39 861355 860726 152993 7699 3504 951 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
38 861393 860726 152993 7700 3503 952 4 1 3 | |
72 861465 860726 152993 7701 3502 953 4 1 3 | |
44 861509 860726 152993 7702 3501 954 4 1 3 | |
44 861553 860726 153990 7703 3500 911 4 1 3 | |
40 861593 860726 153990 7704 3499 912 4 1 3 | |
40 861633 860726 153990 7705 3498 913 4 1 3 | |
92 861725 861709 153990 7706 3541 914 4 1 3 | |
46 861771 861709 153990 7707 3540 915 4 1 3 | |
44 861815 861709 153990 7708 3539 916 4 1 3 | |
40 861855 861709 153990 7709 3538 917 4 1 3 | |
40 861895 861709 153990 7710 3537 918 4 1 3 | |
40 861935 861709 153990 7711 3536 919 4 1 3 | |
39 861974 861709 153990 7712 3535 920 4 1 3 | |
40 862014 861709 153990 7713 3534 921 4 1 3 | |
41 862055 861709 153990 7714 3533 922 4 1 3 | |
39 862094 861709 153990 7715 3532 923 4 1 3 | |
39 862133 861709 153990 7716 3531 924 4 1 3 | |
41 862174 861709 153990 7717 3530 925 4 1 3 | |
40 862214 861709 153990 7718 3529 926 4 1 3 | |
39 862253 861709 153990 7719 3528 927 4 1 3 | |
39 862292 861709 153990 7720 3527 928 4 1 3 | |
40 862332 861709 153990 7721 3526 929 4 1 3 | |
38 862370 861709 153990 7722 3525 930 4 1 3 | |
63 862433 861709 153990 7723 3524 931 4 1 3 | |
45 862478 861709 153990 7724 3523 932 4 1 3 | |
41 862519 861709 153990 7725 3522 933 4 1 3 | |
43 862562 861709 154988 7726 3521 890 4 1 3 | |
41 862603 861709 154988 7727 3520 891 4 1 3 | |
40 862643 861709 154988 7728 3519 892 4 1 3 | |
90 862733 862718 154988 7729 3562 893 4 1 3 | |
46 862779 862718 154988 7730 3561 894 4 1 3 | |
41 862820 862718 154988 7731 3560 895 4 1 3 | |
41 862861 862718 154988 7732 3559 896 4 1 3 | |
40 862901 862718 154988 7733 3558 897 4 1 3 | |
42 862943 862718 154988 7734 3557 898 4 1 3 | |
39 862982 862718 154988 7735 3556 899 4 1 3 | |
10336 873318 873289 164988 7736 3996 459 4 1 3 | |
65 873383 873289 164988 7737 3995 460 4 1 3 | |
96 873479 873289 164988 7738 3994 461 4 1 3 | |
44 873523 873289 164988 7739 3993 462 4 1 3 | |
72 873595 873289 165986 7740 3992 419 4 1 3 | |
43 873638 873289 165986 7741 3991 420 4 1 3 | |
119 873757 873703 165986 7742 4034 421 4 1 3 | |
49 873806 873703 165986 7743 4033 422 4 1 3 | |
40 873846 873703 165986 7744 4032 423 4 1 3 | |
39 873885 873703 165986 7745 4031 424 4 1 3 | |
42 873927 873703 165986 7746 4030 425 4 1 3 | |
39 873966 873703 165986 7747 4029 426 4 1 3 | |
41 874007 873703 165986 7748 4028 427 4 1 3 | |
40 874047 873703 165986 7749 4027 428 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 874088 873703 165986 7750 4026 429 4 1 3 | |
44 874132 873703 165986 7751 4025 430 4 1 3 | |
42 874174 873703 165986 7752 4024 431 4 1 3 | |
39 874213 873703 165986 7753 4023 432 4 1 3 | |
39 874252 873703 165986 7754 4022 433 4 1 3 | |
41 874293 873703 165986 7755 4021 434 4 1 3 | |
38 874331 873703 165986 7756 4020 435 4 1 3 | |
39 874370 873703 165986 7757 4019 436 4 1 3 | |
66 874436 873703 165986 7758 4018 437 4 1 3 | |
46 874482 873703 165986 7759 4017 438 4 1 3 | |
41 874523 873703 165986 7760 4016 439 4 1 3 | |
42 874565 873703 166984 7761 4015 396 4 1 3 | |
40 874605 873703 166984 7762 4014 397 4 1 3 | |
40 874645 873703 166984 7763 4013 398 4 1 3 | |
90 874735 874720 166984 7764 4056 399 4 1 3 | |
44 874779 874720 166984 7765 4055 400 4 1 3 | |
44 874823 874720 166984 7766 4054 401 4 1 3 | |
40 874863 874720 166984 7767 4053 402 4 1 3 | |
39 874902 874720 166984 7768 4052 403 4 1 3 | |
42 874944 874720 166984 7769 4051 404 4 1 3 | |
39 874983 874720 166984 7770 4050 405 4 1 3 | |
40 875023 874720 166984 7771 4049 406 4 1 3 | |
41 875064 874720 166984 7772 4048 407 4 1 3 | |
39 875103 874720 166984 7773 4047 408 4 1 3 | |
39 875142 874720 166984 7774 4046 409 4 1 3 | |
42 875184 874720 166984 7775 4045 410 4 1 3 | |
39 875223 874720 166984 7776 4044 411 4 1 3 | |
39 875262 874720 166984 7777 4043 412 4 1 3 | |
41 875303 874720 166984 7778 4042 413 4 1 3 | |
39 875342 874720 166984 7779 4041 414 4 1 3 | |
39 875381 874720 166984 7780 4040 415 4 1 3 | |
65 875446 874720 166984 7781 4039 416 4 1 3 | |
45 875491 874720 166984 7782 4038 417 4 1 3 | |
43 875534 874720 166984 7783 4037 418 4 1 3 | |
42 875576 874720 167981 7784 4036 375 4 1 3 | |
39 875615 874720 167981 7785 4035 376 4 1 3 | |
39 875654 874720 167981 7786 4034 377 4 1 3 | |
95 875749 875734 168004 7787 4077 377 4 1 3 | |
44 875793 875734 168004 7788 4076 378 4 1 3 | |
42 875835 875734 168004 7789 4075 379 4 1 3 | |
39 875874 875734 168004 7790 4074 380 4 1 3 | |
41 875915 875734 168004 7791 4073 381 4 1 3 | |
38 875953 875734 168004 7792 4072 382 4 1 3 | |
38 875991 875734 168004 7793 4071 383 4 1 3 | |
40 876031 875734 168004 7794 4070 384 4 1 3 | |
40 876071 875734 168004 7795 4069 385 4 1 3 | |
39 876110 875734 168004 7796 4068 386 4 1 3 | |
39 876149 875734 168004 7797 4067 387 4 1 3 | |
41 876190 875734 168004 7798 4066 388 4 1 3 | |
40 876230 875734 168004 7799 4065 389 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
39 876269 875734 168004 7800 4064 390 4 1 3 | |
44 876313 875734 168004 7801 4063 391 4 1 3 | |
40 876353 875734 168004 7802 4062 392 4 1 3 | |
39 876392 875734 168004 7803 4061 393 4 1 3 | |
66 876458 875734 168004 7804 4060 394 4 1 3 | |
45 876503 875734 168004 7805 4059 395 4 1 3 | |
43 876546 875734 169002 7806 4058 352 4 1 3 | |
39 876585 875734 169002 7807 4057 353 4 1 3 | |
40 876625 875734 169002 7808 4056 354 4 1 3 | |
84 876709 876702 169002 7809 4055 355 4 1 3 | |
49 876758 876702 169002 7810 4098 356 4 1 3 | |
42 876800 876702 169002 7811 4097 357 4 1 3 | |
41 876841 876702 169002 7812 4096 358 4 1 3 | |
40 876881 876702 169002 7813 4095 359 4 1 3 | |
42 876923 876702 169002 7814 4094 360 4 1 3 | |
40 876963 876702 169002 7815 4093 361 4 1 3 | |
40 877003 876702 169002 7816 4092 362 4 1 3 | |
39 877042 876702 169002 7817 4091 363 4 1 3 | |
40 877082 876702 169002 7818 4090 364 4 1 3 | |
39 877121 876702 169002 7819 4089 365 4 1 3 | |
41 877162 876702 169002 7820 4088 366 4 1 3 | |
39 877201 876702 169002 7821 4087 367 4 1 3 | |
40 877241 876702 169002 7822 4086 368 4 1 3 | |
38 877279 876702 169002 7823 4085 369 4 1 3 | |
42 877321 876702 169002 7824 4084 370 4 1 3 | |
40 877361 876702 169002 7825 4083 371 4 1 3 | |
98 877459 876702 169002 7826 4082 372 4 1 3 | |
46 877505 876702 169002 7827 4081 373 4 1 3 | |
45 877550 876702 170000 7828 4080 330 4 1 3 | |
41 877591 876702 170000 7829 4079 331 4 1 3 | |
39 877630 876702 170000 7830 4078 332 4 1 3 | |
91 877721 877715 170000 7831 4077 333 4 1 3 | |
49 877770 877715 170000 7832 4121 334 4 1 3 | |
45 877815 877715 170000 7833 4120 335 4 1 3 | |
40 877855 877715 170000 7834 4119 336 4 1 3 | |
40 877895 877715 170000 7835 4118 337 4 1 3 | |
41 877936 877715 170000 7836 4117 338 4 1 3 | |
40 877976 877715 170000 7837 4116 339 4 1 3 | |
39 878015 877715 170000 7838 4115 340 4 1 3 | |
42 878057 877715 170000 7839 4114 341 4 1 3 | |
39 878096 877715 170000 7840 4113 342 4 1 3 | |
40 878136 877715 170000 7841 4112 343 4 1 3 | |
43 878179 877715 170000 7842 4111 344 4 1 3 | |
40 878219 877715 170000 7843 4110 345 4 1 3 | |
39 878258 877715 170000 7844 4109 346 4 1 3 | |
40 878298 877715 170000 7845 4108 347 4 1 3 | |
41 878339 877715 170000 7846 4107 348 4 1 3 | |
39 878378 877715 170000 7847 4106 349 4 1 3 | |
64 878442 877715 170000 7848 4105 350 4 1 3 | |
47 878489 877715 170000 7849 4104 351 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 878530 877715 170000 7850 4103 352 4 1 3 | |
46 878576 877715 170997 7851 4102 309 4 1 3 | |
40 878616 877715 170997 7852 4101 310 4 1 3 | |
41 878657 877715 170997 7853 4100 311 4 1 3 | |
94 878751 878736 170997 7854 4143 312 4 1 3 | |
44 878795 878736 170997 7855 4142 313 4 1 3 | |
41 878836 878736 170997 7856 4141 314 4 1 3 | |
40 878876 878736 170997 7857 4140 315 4 1 3 | |
41 878917 878736 170997 7858 4139 316 4 1 3 | |
40 878957 878736 170997 7859 4138 317 4 1 3 | |
40 878997 878736 170997 7860 4137 318 4 1 3 | |
40 879037 878736 170997 7861 4136 319 4 1 3 | |
40 879077 878736 170997 7862 4135 320 4 1 3 | |
39 879116 878736 170997 7863 4134 321 4 1 3 | |
40 879156 878736 170997 7864 4133 322 4 1 3 | |
40 879196 878736 170997 7865 4132 323 4 1 3 | |
39 879235 878736 170997 7866 4131 324 4 1 3 | |
39 879274 878736 170997 7867 4130 325 4 1 3 | |
40 879314 878736 170997 7868 4129 326 4 1 3 | |
40 879354 878736 170997 7869 4128 327 4 1 3 | |
38 879392 878736 170997 7870 4127 328 4 1 3 | |
66 879458 878736 170997 7871 4126 329 4 1 3 | |
44 879502 878736 170997 7872 4125 330 4 1 3 | |
43 879545 878736 171995 7873 4124 287 4 1 3 | |
41 879586 878736 171995 7874 4123 288 4 1 3 | |
39 879625 878736 171995 7875 4122 289 4 1 3 | |
83 879708 879701 171995 7876 4121 290 4 1 3 | |
48 879756 879701 171995 7877 4164 291 4 1 3 | |
43 879799 879701 171995 7878 4163 292 4 1 3 | |
42 879841 879701 171995 7879 4162 293 4 1 3 | |
40 879881 879701 171995 7880 4161 294 4 1 3 | |
41 879922 879701 171995 7881 4160 295 4 1 3 | |
39 879961 879701 171995 7882 4159 296 4 1 3 | |
40 880001 879701 171995 7883 4158 297 4 1 3 | |
39 880040 879701 171995 7884 4157 298 4 1 3 | |
41 880081 879701 171995 7885 4156 299 4 1 3 | |
39 880120 879701 171995 7886 4155 300 4 1 3 | |
40 880160 879701 171995 7887 4154 301 4 1 3 | |
40 880200 879701 171995 7888 4153 302 4 1 3 | |
39 880239 879701 171995 7889 4152 303 4 1 3 | |
41 880280 879701 171995 7890 4151 304 4 1 3 | |
40 880320 879701 171995 7891 4150 305 4 1 3 | |
40 880360 879701 171995 7892 4149 306 4 1 3 | |
39 880399 879701 171995 7893 4148 307 4 1 3 | |
70 880469 879701 171995 7894 4147 308 4 1 3 | |
43 880512 879701 171995 7895 4146 309 4 1 3 | |
64 880576 879701 172993 7896 4145 266 4 1 3 | |
44 880620 879701 172993 7897 4144 267 4 1 3 | |
79 880699 879701 172993 7898 4143 268 4 1 3 | |
55 880754 880705 172993 7899 4186 269 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
118 880872 880705 172993 7900 4185 270 4 1 3 | |
52 880924 880705 172993 7901 4184 271 4 1 3 | |
42 880966 880705 172993 7902 4183 272 4 1 3 | |
40 881006 880705 172993 7903 4182 273 4 1 3 | |
41 881047 880705 172993 7904 4181 274 4 1 3 | |
40 881087 880705 172993 7905 4180 275 4 1 3 | |
39 881126 880705 172993 7906 4179 276 4 1 3 | |
40 881166 880705 172993 7907 4178 277 4 1 3 | |
40 881206 880705 172993 7908 4177 278 4 1 3 | |
40 881246 880705 172993 7909 4176 279 4 1 3 | |
40 881286 880705 172993 7910 4175 280 4 1 3 | |
40 881326 880705 172993 7911 4174 281 4 1 3 | |
39 881365 880705 172993 7912 4173 282 4 1 3 | |
40 881405 880705 172993 7913 4172 283 4 1 3 | |
71 881476 880705 172993 7914 4171 284 4 1 3 | |
43 881519 880705 172993 7915 4170 285 4 1 3 | |
42 881561 880705 173990 7916 4169 242 4 1 3 | |
73 881634 880705 173990 7917 4168 243 4 1 3 | |
103 881737 881721 173990 7918 4211 244 4 1 3 | |
48 881785 881721 173990 7919 4210 245 4 1 3 | |
42 881827 881721 173990 7920 4209 246 4 1 3 | |
40 881867 881721 173990 7921 4208 247 4 1 3 | |
42 881909 881721 173990 7922 4207 248 4 1 3 | |
39 881948 881721 173990 7923 4206 249 4 1 3 | |
39 881987 881721 173990 7924 4205 250 4 1 3 | |
40 882027 881721 173990 7925 4204 251 4 1 3 | |
41 882068 881721 173990 7926 4203 252 4 1 3 | |
40 882108 881721 173990 7927 4202 253 4 1 3 | |
40 882148 881721 173990 7928 4201 254 4 1 3 | |
39 882187 881721 173990 7929 4200 255 4 1 3 | |
39 882226 881721 173990 7930 4199 256 4 1 3 | |
39 882265 881721 173990 7931 4198 257 4 1 3 | |
42 882307 881721 173990 7932 4197 258 4 1 3 | |
40 882347 881721 173990 7933 4196 259 4 1 3 | |
39 882386 881721 173990 7934 4195 260 4 1 3 | |
68 882454 881721 173990 7935 4194 261 4 1 3 | |
45 882499 881721 173990 7936 4193 262 4 1 3 | |
43 882542 881721 174988 7937 4192 219 4 1 3 | |
40 882582 881721 174988 7938 4191 220 4 1 3 | |
40 882622 881721 174988 7939 4190 221 4 1 3 | |
82 882704 881721 174988 7940 4189 222 4 1 3 | |
54 882758 882709 174988 7941 4232 223 4 1 3 | |
43 882801 882709 174988 7942 4231 224 4 1 3 | |
41 882842 882709 174988 7943 4230 225 4 1 3 | |
41 882883 882709 174988 7944 4229 226 4 1 3 | |
40 882923 882709 174988 7945 4228 227 4 1 3 | |
41 882964 882709 174988 7946 4227 228 4 1 3 | |
39 883003 882709 174988 7947 4226 229 4 1 3 | |
41 883044 882709 174988 7948 4225 230 4 1 3 | |
39 883083 882709 174988 7949 4224 231 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 883123 882709 174988 7950 4223 232 4 1 3 | |
42 883165 882709 174988 7951 4222 233 4 1 3 | |
41 883206 882709 174988 7952 4221 234 4 1 3 | |
40 883246 882709 174988 7953 4220 235 4 1 3 | |
40 883286 882709 174988 7954 4219 236 4 1 3 | |
40 883326 882709 174988 7955 4218 237 4 1 3 | |
39 883365 882709 174988 7956 4217 238 4 1 3 | |
39 883404 882709 174988 7957 4216 239 4 1 3 | |
68 883472 882709 174988 7958 4215 240 4 1 3 | |
41 883513 882709 174988 7959 4214 241 4 1 3 | |
42 883555 882709 175986 7960 4213 198 4 1 3 | |
40 883595 882709 175986 7961 4212 199 4 1 3 | |
40 883635 882709 175986 7962 4211 200 4 1 3 | |
88 883723 883707 175986 7963 4254 201 4 1 3 | |
47 883770 883707 175986 7964 4253 202 4 1 3 | |
43 883813 883707 175986 7965 4252 203 4 1 3 | |
40 883853 883707 175986 7966 4251 204 4 1 3 | |
39 883892 883707 175986 7967 4250 205 4 1 3 | |
42 883934 883707 175986 7968 4249 206 4 1 3 | |
40 883974 883707 175986 7969 4248 207 4 1 3 | |
40 884014 883707 175986 7970 4247 208 4 1 3 | |
41 884055 883707 175986 7971 4246 209 4 1 3 | |
40 884095 883707 175986 7972 4245 210 4 1 3 | |
39 884134 883707 175986 7973 4244 211 4 1 3 | |
40 884174 883707 175986 7974 4243 212 4 1 3 | |
41 884215 883707 175986 7975 4242 213 4 1 3 | |
40 884255 883707 175986 7976 4241 214 4 1 3 | |
41 884296 883707 175986 7977 4240 215 4 1 3 | |
40 884336 883707 175986 7978 4239 216 4 1 3 | |
40 884376 883707 175986 7979 4238 217 4 1 3 | |
63 884439 883707 175986 7980 4237 218 4 1 3 | |
45 884484 883707 175986 7981 4236 219 4 1 3 | |
41 884525 883707 175986 7982 4235 220 4 1 3 | |
42 884567 883707 176984 7983 4234 177 4 1 3 | |
40 884607 883707 176984 7984 4233 178 4 1 3 | |
39 884646 883707 176984 7985 4232 179 4 1 3 | |
88 884734 884719 176984 7986 4275 180 4 1 3 | |
45 884779 884719 176984 7987 4274 181 4 1 3 | |
43 884822 884719 176984 7988 4273 182 4 1 3 | |
40 884862 884719 176984 7989 4272 183 4 1 3 | |
41 884903 884719 176984 7990 4271 184 4 1 3 | |
42 884945 884719 176984 7991 4270 185 4 1 3 | |
39 884984 884719 176984 7992 4269 186 4 1 3 | |
39 885023 884719 176984 7993 4268 187 4 1 3 | |
41 885064 884719 176984 7994 4267 188 4 1 3 | |
39 885103 884719 176984 7995 4266 189 4 1 3 | |
39 885142 884719 176984 7996 4265 190 4 1 3 | |
40 885182 884719 176984 7997 4264 191 4 1 3 | |
40 885222 884719 176984 7998 4263 192 4 1 3 | |
40 885262 884719 176984 7999 4262 193 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
41 885303 884719 176984 8000 4261 194 4 1 3 | |
43 885346 884719 176984 8001 4260 195 4 1 3 | |
40 885386 884719 176984 8002 4259 196 4 1 3 | |
66 885452 884719 176984 8003 4258 197 4 1 3 | |
44 885496 884719 176984 8004 4257 198 4 1 3 | |
42 885538 884719 177981 8005 4256 155 4 1 3 | |
41 885579 884719 177981 8006 4255 156 4 1 3 | |
67 885646 884719 177981 8007 4254 157 4 1 3 | |
114 885760 885742 178004 8008 4297 157 4 1 3 | |
48 885808 885742 178004 8009 4296 158 4 1 3 | |
41 885849 885742 178004 8010 4295 159 4 1 3 | |
40 885889 885742 178004 8011 4294 160 4 1 3 | |
41 885930 885742 178004 8012 4293 161 4 1 3 | |
40 885970 885742 178004 8013 4292 162 4 1 3 | |
39 886009 885742 178004 8014 4291 163 4 1 3 | |
40 886049 885742 178004 8015 4290 164 4 1 3 | |
39 886088 885742 178004 8016 4289 165 4 1 3 | |
40 886128 885742 178004 8017 4288 166 4 1 3 | |
41 886169 885742 178004 8018 4287 167 4 1 3 | |
39 886208 885742 178004 8019 4286 168 4 1 3 | |
40 886248 885742 178004 8020 4285 169 4 1 3 | |
41 886289 885742 178004 8021 4284 170 4 1 3 | |
40 886329 885742 178004 8022 4283 171 4 1 3 | |
39 886368 885742 178004 8023 4282 172 4 1 3 | |
62 886430 885742 178004 8024 4281 173 4 1 3 | |
47 886477 885742 178004 8025 4280 174 4 1 3 | |
41 886518 885742 178004 8026 4279 175 4 1 3 | |
43 886561 885742 179002 8027 4278 132 4 1 3 | |
39 886600 885742 179002 8028 4277 133 4 1 3 | |
39 886639 885742 179002 8029 4276 134 4 1 3 | |
92 886731 886715 179002 8030 4319 135 4 1 3 | |
47 886778 886715 179002 8031 4318 136 4 1 3 | |
44 886822 886715 179002 8032 4317 137 4 1 3 | |
41 886863 886715 179002 8033 4316 138 4 1 3 | |
39 886902 886715 179002 8034 4315 139 4 1 3 | |
42 886944 886715 179002 8035 4314 140 4 1 3 | |
39 886983 886715 179002 8036 4313 141 4 1 3 | |
40 887023 886715 179002 8037 4312 142 4 1 3 | |
42 887065 886715 179002 8038 4311 143 4 1 3 | |
39 887104 886715 179002 8039 4310 144 4 1 3 | |
39 887143 886715 179002 8040 4309 145 4 1 3 | |
40 887183 886715 179002 8041 4308 146 4 1 3 | |
39 887222 886715 179002 8042 4307 147 4 1 3 | |
40 887262 886715 179002 8043 4306 148 4 1 3 | |
41 887303 886715 179002 8044 4305 149 4 1 3 | |
40 887343 886715 179002 8045 4304 150 4 1 3 | |
40 887383 886715 179002 8046 4303 151 4 1 3 | |
63 887446 886715 179002 8047 4302 152 4 1 3 | |
44 887490 886715 179002 8048 4301 153 4 1 3 | |
44 887534 886715 179002 8049 4300 154 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
40 887574 886715 180000 8050 4299 111 4 1 3 | |
43 887617 886715 180000 8051 4298 112 4 1 3 | |
42 887659 886715 180000 8052 4297 113 4 1 3 | |
93 887752 887701 180000 8053 4341 114 4 1 3 | |
45 887797 887701 180000 8054 4340 115 4 1 3 | |
41 887838 887701 180000 8055 4339 116 4 1 3 | |
40 887878 887701 180000 8056 4338 117 4 1 3 | |
40 887918 887701 180000 8057 4337 118 4 1 3 | |
40 887958 887701 180000 8058 4336 119 4 1 3 | |
39 887997 887701 180000 8059 4335 120 4 1 3 | |
41 888038 887701 180000 8060 4334 121 4 1 3 | |
40 888078 887701 180000 8061 4333 122 4 1 3 | |
39 888117 887701 180000 8062 4332 123 4 1 3 | |
39 888156 887701 180000 8063 4331 124 4 1 3 | |
41 888197 887701 180000 8064 4330 125 4 1 3 | |
40 888237 887701 180000 8065 4329 126 4 1 3 | |
40 888277 887701 180000 8066 4328 127 4 1 3 | |
40 888317 887701 180000 8067 4327 128 4 1 3 | |
40 888357 887701 180000 8068 4326 129 4 1 3 | |
39 888396 887701 180000 8069 4325 130 4 1 3 | |
68 888464 887701 180000 8070 4324 131 4 1 3 | |
43 888507 887701 180000 8071 4323 132 4 1 3 | |
62 888569 887701 180997 8072 4322 89 4 1 3 | |
44 888613 887701 180997 8073 4321 90 4 1 3 | |
42 888655 887701 180997 8074 4320 91 4 1 3 | |
91 888746 888731 180997 8075 4363 92 4 1 3 | |
45 888791 888731 180997 8076 4362 93 4 1 3 | |
40 888831 888731 180997 8077 4361 94 4 1 3 | |
41 888872 888731 180997 8078 4360 95 4 1 3 | |
40 888912 888731 180997 8079 4359 96 4 1 3 | |
40 888952 888731 180997 8080 4358 97 4 1 3 | |
40 888992 888731 180997 8081 4357 98 4 1 3 | |
38 889030 888731 180997 8082 4356 99 4 1 3 | |
41 889071 888731 180997 8083 4355 100 4 1 3 | |
39 889110 888731 180997 8084 4354 101 4 1 3 | |
40 889150 888731 180997 8085 4353 102 4 1 3 | |
40 889190 888731 180997 8086 4352 103 4 1 3 | |
39 889229 888731 180997 8087 4351 104 4 1 3 | |
40 889269 888731 180997 8088 4350 105 4 1 3 | |
41 889310 888731 180997 8089 4349 106 4 1 3 | |
39 889349 888731 180997 8090 4348 107 4 1 3 | |
39 889388 888731 180997 8091 4347 108 4 1 3 | |
64 889452 888731 180997 8092 4346 109 4 1 3 | |
44 889496 888731 180997 8093 4345 110 4 1 3 | |
42 889538 888731 181995 8094 4344 67 4 1 3 | |
40 889578 888731 181995 8095 4343 68 4 1 3 | |
40 889618 888731 181995 8096 4342 69 4 1 3 | |
41 889659 888731 181995 8097 4341 70 4 1 3 | |
88 889747 88alsa-time-test: tests/alsa-time-test.c:244: main: Assertion `(unsigned) avail <= buffer_size' failed. | |
9733 181995 8098 4384 71 4 1 3 | |
74 889821 889733 181995 8099 4383 72 4 1 3 | |
Elapsed CPU ALSA Pos Samples avail delay revents handled state | |
44 889865 889733 181995 8100 4382 73 4 1 3 | |
45 889910 889733 181995 8101 4381 74 4 1 3 | |
42 889952 889733 181995 8102 4380 75 4 1 3 | |
41 889993 889733 181995 8103 4379 76 4 1 3 | |
41 890034 889733 181995 8104 4378 77 4 1 3 | |
39 890073 889733 181995 8105 4377 78 4 1 3 | |
40 890113 889733 181995 8106 4376 79 4 1 3 | |
39 890152 889733 181995 8107 4375 80 4 1 3 | |
42 890194 889733 181995 8108 4374 81 4 1 3 | |
40 890234 889733 181995 8109 4373 82 4 1 3 | |
38 890272 889733 181995 8110 4372 83 4 1 3 | |
42 890314 889733 181995 8111 4371 84 4 1 3 | |
39 890353 889733 181995 8112 4370 85 4 1 3 | |
39 890392 889733 181995 8113 4369 86 4 1 3 | |
68 890460 889733 181995 8114 4368 87 4 1 3 | |
43 890503 889733 181995 8115 4367 88 4 1 3 | |
43 890546 889733 182993 8116 4366 45 4 1 3 | |
40 890586 889733 182993 8117 4365 46 4 1 3 | |
40 890626 889733 182993 8118 4364 47 4 1 3 | |
90 890716 890708 182993 8119 4363 48 4 1 3 | |
49 890765 890708 182993 8120 4406 49 4 1 3 | |
90 890855 890708 182993 8121 4405 50 4 1 3 | |
43 890898 890708 182993 8122 4404 51 4 1 3 | |
42 890940 890708 182993 8123 4403 52 4 1 3 | |
40 890980 890708 182993 8124 4402 53 4 1 3 | |
40 891020 890708 182993 8125 4401 54 4 1 3 | |
41 891061 890708 182993 8126 4400 55 4 1 3 | |
39 891100 890708 182993 8127 4399 56 4 1 3 | |
39 891139 890708 182993 8128 4398 57 4 1 3 | |
41 891180 890708 182993 8129 4397 58 4 1 3 | |
40 891220 890708 182993 8130 4396 59 4 1 3 | |
39 891259 890708 182993 8131 4395 60 4 1 3 | |
41 891300 890708 182993 8132 4394 61 4 1 3 | |
39 891339 890708 182993 8133 4393 62 4 1 3 | |
39 891378 890708 182993 8134 4392 63 4 1 3 | |
66 891444 890708 182993 8135 4391 64 4 1 3 | |
45 891489 890708 182993 8136 4390 65 4 1 3 | |
42 891531 890708 182993 8137 4389 66 4 1 3 | |
43 891574 890708 183990 8138 4388 23 4 1 3 | |
40 891614 890708 183990 8139 4387 24 4 1 3 | |
39 891653 890708 183990 8140 4386 25 4 1 3 | |
97 891750 891734 183990 8141 4429 26 4 1 3 |
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