counter.v

`default_nettype none

module top
(
 output [7:0] out,
 output       nenable,
 inout        irq,
 input        spi_cs,
 input        spi_clk,
 input        spi_di,
 inout        spi_do,
 inout        i2c_scl,
 inout        i2c_sda,
 output [2:0] led_rgb
 );

   wire       clk;

SB_HFOSC #(.CLKHF_DIV("0b01"))
osc(.CLKHFPU(1),
    .CLKHFEN(1'b1),
    .CLKHF(clk));


   reg [7:0]  reset_counter;
   wire       reset;

initial reset_counter = 0;
assign reset = ~&reset_counter;

always @(posedge clk)
  if (reset)
    reset_counter <= reset_counter + 1;


   reg [25:0]  counter;

always @(posedge clk)
  if (reset)
    counter <= 0;
  else
    counter <= counter + 1;


assign out = counter[17:10];
assign led_rgb = counter[25:22];
assign nenable = reset;

endmodule