regfile.v

module regfile #(parameter WIDTH = 32, COUNT = 16, ADDR_WIDTH = 4) (
  output reg [WIDTH - 1:0] data_out,
  input clk,
  input reset,
  input write,
  input [ADDR_WIDTH - 1:0] addr,
  input [WIDTH - 1:0] data_in);

  reg [WIDTH - 1:0] registers[COUNT - 1:0];

  always @(posedge clk) begin
    data_out <= registers[addr];
    if (write) begin
      registers[addr] <= data_in;
    end
  end
endmodule