Skip to content

Instantly share code, notes, and snippets.

@corecode
Created February 21, 2019 23:23
Show Gist options
  • Save corecode/669fdcb31090543b35fc4cc90ba27880 to your computer and use it in GitHub Desktop.
Save corecode/669fdcb31090543b35fc4cc90ba27880 to your computer and use it in GitHub Desktop.
// ******************************************************************************
// iCEcube Netlister
// Version: 2017.08.27940
// Build Date: Sep 12 2017 08:25:46
// File Generated: Feb 20 2019 00:33:11
// Purpose: Post-Route Verilog/VHDL netlist for timing simulation
// Copyright (C) 2006-2010 by Lattice Semiconductor Corp. All rights reserved.
// ******************************************************************************
// Verilog file for cell "top" view "INTERFACE"
module top (
y,
b,
a);
output y;
input b;
input a;
wire N__163;
wire N__162;
wire N__161;
wire N__154;
wire N__153;
wire N__152;
wire N__145;
wire N__144;
wire N__143;
wire N__126;
wire N__123;
wire N__120;
wire N__117;
wire N__114;
wire N__111;
wire N__108;
wire N__105;
wire N__102;
wire N__99;
wire N__96;
wire N__93;
wire N__90;
wire N__87;
wire N__84;
wire N__81;
wire N__78;
wire N__75;
wire N__72;
wire N__69;
wire VCCG0;
wire GNDG0;
wire y_padLegalizeSB_DFFNet;
wire internalOscilatorOutputNet;
wire b_c;
wire a_c;
wire y_c;
wire _gnd_net_;
defparam a_pad_iopad.IO_STANDARD="SB_LVCMOS";
defparam a_pad_iopad.PULLUP=1'b0;
IO_PAD a_pad_iopad (
.OE(N__163),
.DIN(N__162),
.DOUT(N__161),
.PACKAGEPIN(a));
defparam a_pad_preio.PIN_TYPE=6'b000001;
defparam a_pad_preio.NEG_TRIGGER=1'b0;
PRE_IO a_pad_preio (
.PADOEN(N__163),
.PADOUT(N__162),
.PADIN(N__161),
.CLOCKENABLE(),
.DIN0(a_c),
.DIN1(),
.DOUT0(),
.DOUT1(),
.INPUTCLK(),
.LATCHINPUTVALUE(),
.OUTPUTCLK(),
.OUTPUTENABLE());
defparam b_pad_iopad.IO_STANDARD="SB_LVCMOS";
defparam b_pad_iopad.PULLUP=1'b0;
IO_PAD b_pad_iopad (
.OE(N__154),
.DIN(N__153),
.DOUT(N__152),
.PACKAGEPIN(b));
defparam b_pad_preio.PIN_TYPE=6'b000001;
defparam b_pad_preio.NEG_TRIGGER=1'b0;
PRE_IO b_pad_preio (
.PADOEN(N__154),
.PADOUT(N__153),
.PADIN(N__152),
.CLOCKENABLE(),
.DIN0(b_c),
.DIN1(),
.DOUT0(),
.DOUT1(),
.INPUTCLK(),
.LATCHINPUTVALUE(),
.OUTPUTCLK(),
.OUTPUTENABLE());
defparam y_pad_iopad.IO_STANDARD="SB_LVCMOS";
defparam y_pad_iopad.PULLUP=1'b0;
IO_PAD y_pad_iopad (
.OE(N__145),
.DIN(N__144),
.DOUT(N__143),
.PACKAGEPIN(y));
defparam y_pad_preio.PIN_TYPE=6'b101001;
defparam y_pad_preio.NEG_TRIGGER=1'b0;
PRE_IO y_pad_preio (
.PADOEN(N__145),
.PADOUT(N__144),
.PADIN(N__143),
.CLOCKENABLE(),
.DIN0(),
.DIN1(),
.DOUT0(N__81),
.DOUT1(),
.INPUTCLK(),
.LATCHINPUTVALUE(),
.OUTPUTCLK(),
.OUTPUTENABLE(N__126));
IoInMux I__28 (
.O(N__126),
.I(N__123));
LocalMux I__27 (
.O(N__123),
.I(y_padLegalizeSB_DFFNet));
ClkMux I__26 (
.O(N__120),
.I(N__117));
LocalMux I__25 (
.O(N__117),
.I(N__114));
Span4Mux_s2_v I__24 (
.O(N__114),
.I(N__111));
Sp12to4 I__23 (
.O(N__111),
.I(N__108));
Span12Mux_h I__22 (
.O(N__108),
.I(N__105));
Span12Mux_h I__21 (
.O(N__105),
.I(N__102));
Odrv12 I__20 (
.O(N__102),
.I(internalOscilatorOutputNet));
InMux I__19 (
.O(N__99),
.I(N__96));
LocalMux I__18 (
.O(N__96),
.I(b_c));
InMux I__17 (
.O(N__93),
.I(N__90));
LocalMux I__16 (
.O(N__90),
.I(N__87));
Span4Mux_h I__15 (
.O(N__87),
.I(N__84));
Odrv4 I__14 (
.O(N__84),
.I(a_c));
IoInMux I__13 (
.O(N__81),
.I(N__78));
LocalMux I__12 (
.O(N__78),
.I(N__75));
Span12Mux_s0_v I__11 (
.O(N__75),
.I(N__72));
Span12Mux_h I__10 (
.O(N__72),
.I(N__69));
Odrv12 I__9 (
.O(N__69),
.I(y_c));
SMCCLK internalOscilator (
.CLK(internalOscilatorOutputNet));
VCC VCC (
.Y(VCCG0));
GND GND (
.Y(GNDG0));
GND GND_Inst (
.Y(_gnd_net_));
defparam y_padLegalizeSB_DFF_LC_5_1_0.C_ON=1'b0;
defparam y_padLegalizeSB_DFF_LC_5_1_0.SEQ_MODE=4'b1000;
defparam y_padLegalizeSB_DFF_LC_5_1_0.LUT_INIT=16'b1111111111111111;
LogicCell40 y_padLegalizeSB_DFF_LC_5_1_0 (
.in0(_gnd_net_),
.in1(_gnd_net_),
.in2(_gnd_net_),
.in3(_gnd_net_),
.lcout(y_padLegalizeSB_DFFNet),
.ltout(),
.carryin(_gnd_net_),
.carryout(),
.clk(N__120),
.ce(),
.sr(_gnd_net_));
defparam a_I_0_2_lut_LC_18_1_0.C_ON=1'b0;
defparam a_I_0_2_lut_LC_18_1_0.SEQ_MODE=4'b0000;
defparam a_I_0_2_lut_LC_18_1_0.LUT_INIT=16'b1111111110101010;
LogicCell40 a_I_0_2_lut_LC_18_1_0 (
.in0(N__99),
.in1(_gnd_net_),
.in2(_gnd_net_),
.in3(N__93),
.lcout(y_c),
.ltout(),
.carryin(_gnd_net_),
.carryout(),
.clk(_gnd_net_),
.ce(),
.sr(_gnd_net_));
endmodule // top
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment