VHDL Code

gistfile1.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

entity Nexys2TopLevel is
Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
       seg : out STD_LOGIC_VECTOR (6 downto 0);
       dp  : out STD_LOGIC;
       an  : out STD_LOGIC_VECTOR (3 downto 0);
       clk : in STD_LOGIC;
       sw  : in STD_LOGIC_VECTOR (7 downto 0);
       btn : in STD_LOGIC_VECTOR (3 downto 0));
end Nexys2TopLevel;

architecture bevahorial of Nexys2TopLevel is
--DIVISION CORE
component DIVISION_CORE
	port (
	clk: IN std_logic;
	rfd: OUT std_logic;
	sclr: IN std_logic;
	dividend: IN std_logic_VECTOR(31 downto 0);
	divisor: IN std_logic_VECTOR(31 downto 0);
	quotient: OUT std_logic_VECTOR(31 downto 0);
	fractional: OUT std_logic_VECTOR(31 downto 0));
end component;
--DIVISION CORE

--SQUARE ROOT CORE
component Square_Root_Core
	port (
	x_in: IN std_logic_VECTOR(31 downto 0);
	nd: IN std_logic;
	x_out: OUT std_logic_VECTOR(16 downto 0);
	rdy: OUT std_logic;
	clk: IN std_logic;
	sclr: IN std_logic);
end component;
--SQUARE ROOT CORE

--BASIC SIGNAL INITIALIZATION
signal rst: STD_LOGIC;
signal count : STD_LOGIC_vector(9 downto 0);
signal counter : STD_LOGIC_vector(15 downto 0);
signal an_sig  : STD_LOGIC_VECTOR (3 downto 0);
signal digit1  : STD_LOGIC_VECTOR (7 downto 0);
signal digit2  : STD_LOGIC_VECTOR (7 downto 0);
signal digit3  : STD_LOGIC_VECTOR (7 downto 0);
signal digit4  : STD_LOGIC_VECTOR (7 downto 0);
signal clockINV: STD_LOGIC;
--BASIC SIGNAL INITIALIZATION

--DIVISION SIGNALS
signal	rfd_sig: std_logic;
signal	dividend_sig: std_logic_VECTOR(31 downto 0);
signal	divisor_sig: std_logic_VECTOR(31 downto 0);
signal	quotient_sig: std_logic_VECTOR(31 downto 0);
signal	fractional_sig: std_logic_VECTOR(31 downto 0);
signal sclr_sig_DIV: std_logic;
--DIVISION SIGNALS

--Square Root Signals
signal x_in_sig:  std_logic_VECTOR(31 downto 0);
signal	nd_sig:    std_logic;
signal	x_out_sig: std_logic_VECTOR(16 downto 0);
signal	rdy_sig:   std_logic;
signal sclr_sig_ROOT: std_logic;
--Square Root Signals

--RAM INITIALIZATION
type rom_type is array (0 to 4) of std_logic_vector(31 downto 0);
signal ROM: rom_type := 
(
X"00000008", X"00000004", X"00000005", X"0000000C", X"00000082"
);
--RAM INITIALIZATION

--ROM signals
signal we : std_logic;
signal en : std_logic;
signal addr:std_logic_vector(5 downto 0);
signal di : std_logic_vector(15 downto 0);
signal do : std_logic_vector(15 downto 0);
--ROM signals

--Prime Find Signals
signal test_value             : std_logic_vector (31 downto 0);
signal loop_output_quotient   : std_logic_vector (31 downto 0);
signal loop_output_fractional : std_logic_vector (31 downto 0);
signal ROM_INDEX              : std_logic_vector (15 downto 0);
signal loop_value             : std_logic_vector (31 downto 0);
signal found                  : std_logic;
signal output_prime           : std_logic_vector (15 downto 0);

signal test_value_integer            : integer:=0;
signal loop_output_quotient_integer  : integer:=0;
signal loop_output_fractional_integer: integer:=0;
signal dividend_sig_integer          : integer:=0;
signal ROM_INDEX_integer             : integer:=0;
signal loop_value_integer            : integer:=0;

signal ROM_INDEX_vector : std_logic_vector (15 downto 0);
signal loop_value_vector: std_logic_vector (31 downto 0);
--Prime Find Signals
begin
  
--BASIC CONTROL SIGNALS
rst<= btn(0);
an <= an_sig;
--BASIC CONTROL SIGNALS

--DIVISION CORE
U0: DIVISION_CORE port map (
  clk => clk,
  rfd => rfd_sig,
  sclr => sclr_sig_DIV,
  
	dividend => dividend_sig,
	divisor => divisor_sig,
	quotient => quotient_sig,
	fractional => fractional_sig); 
--DIVISON CORE

--SQUARE ROOT CORE
U1: Square_Root_Core port map (
			x_in => x_in_sig,
			nd => nd_sig, 
			x_out => x_out_sig,
			rdy => rdy_sig,
			clk => clk,
			sclr => sclr_sig_ROOT);
--ND specifies if the core has new data input
--RDY specifies if the core has a data output ready
--SQUARE ROOT CORE

--Version A
calculate_if_prime_version_A: process(clk, rst)
--variable ROM_INDEX: integer range 0 to 4:=0;
--variable loop_value: integer:=0;
begin
  if (rst = '1') then
    ROM_INDEX <= (others=>'0');
    loop_value <= (others=>'0');
    found<='0';
    --ROM_INDEX  :=0;
    --loop_value :=0;
    
  --elsif(clk'event and clk= '1') then
  elsif(clk'event and clk= '1' and found='0') then  
      sclr_sig_DIV <= '1';
      sclr_sig_DIV <= '0';
      
      --vector type value
      --ROM_INDEX_vector  <= conv_std_logic_vector(ROM_INDEX,16);
      --loop_value_vector <= conv_std_logic_vector(loop_value,32);
      --vector type value
      
      test_value <= ROM(conv_integer(ROM_INDEX));
      --test_value <= ROM(ROM_INDEX);
      
      dividend_sig <= test_value;
      divisor_sig  <= loop_value;
      --divisor <= loop_value_vector;
    
      loop_output_quotient   <= quotient_sig;
      loop_output_fractional <= fractional_sig;
    
      --interger type value
      test_value_integer            <= conv_integer(test_value);
      dividend_sig_integer          <= conv_integer(dividend_sig);
      loop_output_quotient_integer  <= conv_integer(loop_output_quotient);
      loop_output_fractional_integer<= conv_integer(loop_output_fractional);
      loop_value_integer            <= conv_integer(loop_value);
      ROM_INDEX_integer             <= conv_integer(ROM_INDEX);
      --integer type value
      
      --Things that would be cleared
      --dividend_sig
      --divisor_sig
      --loop_output_quotient
      --loop_output_fractional
      
    --CASE 1
    if (loop_value_integer = 0 or loop_value_integer = 1) then
      loop_value <= loop_value+'1';
    --we skip the values of 0 and 1 because we don't want to test the
    --values, because 0 dividied by anything is void, and divided by 1
    --is itself, which we don't want that result
    --CASE 1
    
    --CASE 2
    elsif (test_value_integer = 0 or test_value_integer = 1) then
        ROM_INDEX <= ROM_INDEX+'1';
        --We don't test for 1, because anything divided by 1 is still 1
        --And We don't test for 0, because anything divided by 0 is a type of
        --overflow
    --CASE 2
    
    --CASE 3
    elsif (loop_value_integer = test_value_integer) then
        --output_prime <= ROM_INDEX;
        counter <= ROM_INDEX;
        found <= '1';
        --If the loop value is equal to the dividend signal, it means
        --that it is a prime, because it passed all the other tests
    --CASE 3
    
    --CASE 4
    elsif (loop_output_quotient_integer < test_value_integer
       and loop_output_fractional_integer = 0) then
        --NOT A PRIME
        ROM_INDEX <= ROM_INDEX+'1';
        loop_value <= (others=>'0');
        --If it has no fractional value, and if the quotent is greater than 0 or less than 0
        --and have a frational integer of 0, means that a number, which is not itself
        --has been successfully divided into a whole value, which is then NOT A PRIME
        
    --CASE 4
    
    --CASE 5
    elsif (loop_output_quotient_integer < test_value_integer
      and  loop_output_fractional_integer > 0) then
        --NOT YET A PRIME
        loop_value <= loop_value+'1';
        --If there are fractional values, we don't know whether it
        --is a prime or not, we need to test until the last value
    --CASE 5
    
    end if;
  end if;
end process;

SHOW_VALUE_IN_ROM_I: process (clk, rst)
  begin
    if (rst = '1') then
        counter <= (others=>'0');
    elsif (clk'event and clk= '1') then
        --counter <= output_prime;
    end if;
end process;
--Version A

activateAnode:process(clk, rst)
   begin
     if(rst = '1') then
      an_sig <= "1110";--May have problem
     elsif(clk'event and clk= '1') then
       if (count = 0) then
         an_sig <=an_sig(2 downto 0)& an_sig(3);
      else an_sig <=an_sig;
     end if;
   end if;
end process;

pickDigit:process(clk, rst)
  begin
    if(rst = '1') then
    led <= (others => '0');
    seg <= (others => '1');
    dp  <= '1';
    elsif(clk'event and clk= '1') then
      led <= sw; --LED will start responding
      case an_sig(3 downto 0) is
        when "1110" => seg <= digit1(7 downto 1); dp<= digit1(0);
        when "1101" => seg <= digit2(7 downto 1); dp<= digit2(0);
        when "1011" => seg <= digit3(7 downto 1); dp<= digit3(0);
        when "0111" => seg <= digit4(7 downto 1); dp<= digit4(0);
        when others => seg <= "1111111"; dp<= '1' ;
      end case;
    end if;
end process;

--ROM
--ROM_CONTROL: process(clk)
--  begin
--    if (clk'event and clk= '1') then
--      if (en = '1') then
--        if (we = '1') then
--          ROM_I(conv_integer(addr))<=di;
--        end if;
--        do <= ROM(conv_integer(addr));
--      end if;
--    end if;
--end process;
--ROM

--TRADITIONAL MODEL: DO NOT REMOVE
--process (<clock>,<async_reset>)
--begin 
--   if <async_reset> = '1' then
--      <statements>;
--   elsif (<clock>'event and <clock> = '1') then
--      if <sync_reset> = '1' then
--         <statements>;
--      else
--         <statements>;
--      end if;
--   end if;
--end process;
--TRADITIONAL MODEL: DO NOT REMOVE

--7 SEGMENT DISPLAY
digitMap1:process(clk)
begin
--digit 1
case counter(3 downto 0) is
  when "0000" => digit1 <= "10000001"; --0 and the dot is off
  when "0001" => digit1 <= "11110011"; --1 and the dot is off
  when "0010" => digit1 <= "01001001"; --2 and the dot is off
  when "0011" => digit1 <= "01100001"; --3 and the dot is off
  when "0100" => digit1 <= "00110011"; --4 and the dot is off
  when "0101" => digit1 <= "00100101"; --5 and the dot is off
  when "0110" => digit1 <= "00000101"; --6 and the dot is off
  when "0111" => digit1 <= "11110001"; --7 and the dot is off
  when "1000" => digit1 <= "00000001"; --8 and the dot is off
  when "1001" => digit1 <= "00100001"; --9 and the dot is off
  when "1010" => digit1 <= "00010000"; --A and the dot is on
  when "1011" => digit1 <= "00000000"; --B and the dot is on
  when "1100" => digit1 <= "10001100"; --C and the dot is on
  when "1101" => digit1 <= "10000000"; --D and the dot is on
  when "1110" => digit1 <= "00001100"; --E and the dot is on
  when "1111" => digit1 <= "00011100"; --F and the dot is on
  when others => digit1 <= "11111111"; --Dark and the dot is off
end case;
end process;

digitMap2:process(clk)
  begin
  --digit 2
  case counter(7 downto 4) is 
  when "0000" => digit2<= "10000001"; --0 and the dot is off 
  when "0001" => digit2 <= "11110011"; --1 and the dot is off 
  when "0010" => digit2 <= "01001001"; --2 and the dot is off 
  when "0011" => digit2 <= "01100001"; --3 and the dot is off 
  when "0100" => digit2 <= "00110011"; --4 and the dot is off 
  when "0101" => digit2 <= "00100101"; --5 and the dot is off 
  when "0110" => digit2 <= "00000101"; --6 and the dot is off 
  when "0111" => digit2 <= "11110001"; --7 and the dot is off 
  when "1000" => digit2 <= "00000001"; --8 and the dot is off 
  when "1001" => digit2 <= "00100001"; --9 and the dot is off 
  when "1010" => digit2 <= "00010000"; --A and the dot is on
  when "1011" => digit2 <= "00000000"; --B and the dot is on
  when "1100" => digit2 <= "10001100"; --C and the dot is on
  when "1101" => digit2 <= "10000000"; --D and the dot is on
  when "1110" => digit2 <= "00001100"; --E and the dot is on
  when "1111" => digit2 <= "00011100"; --F and the dot is on
  when others => digit2 <= "11111111"; --Dark and the dot is off
  end case;
end process;

digitMap3:process(clk)
begin
--digit 3
case counter(11 downto 8) is
  when "0000" => digit3 <= "10000001"; --0 and the dot is off
  when "0001" => digit3 <= "11110011"; --1 and the dot is off
  when "0010" => digit3 <= "01001001"; --2 and the dot is off
  when "0011" => digit3 <= "01100001"; --3 and the dot is off
  when "0100" => digit3 <= "00110011"; --4 and the dot is off
  when "0101" => digit3 <= "00100101"; --5 and the dot is off
  when "0110" => digit3 <= "00000101"; --6 and the dot is off
  when "0111" => digit3 <= "11110001"; --7 and the dot is off
  when "1000" => digit3 <= "00000001"; --8 and the dot is off
  when "1001" => digit3 <= "00100001"; --9 and the dot is off
  when "1010" => digit3 <= "00010000"; --A and the dot is on
  when "1011" => digit3 <= "00000000"; --B and the dot is on
  when "1100" => digit3 <= "10001100"; --C and the dot is on
  when "1101" => digit3 <= "10000000"; --D and the dot is on
  when "1110" => digit3 <= "00001100"; --E and the dot is on
  when "1111" => digit3 <= "00011100"; --F and the dot is on
  when others => digit3 <= "11111111"; --Dark and the dot is off
end case;
end process;

digitMap4:process(clk)
begin
--digit 4
case counter(15 downto 12) is
  when "0000" => digit4 <= "10000001"; --0 and the dot is off
  when "0001" => digit4 <= "11110011"; --1 and the dot is off
  when "0010" => digit4 <= "01001001"; --2 and the dot is off
  when "0011" => digit4 <= "01100001"; --3 and the dot is off
  when "0100" => digit4 <= "00110011"; --4 and the dot is off
  when "0101" => digit4 <= "00100101"; --5 and the dot is off
  when "0110" => digit4 <= "00000101"; --6 and the dot is off
  when "0111" => digit4 <= "11110001"; --7 and the dot is off
  when "1000" => digit4 <= "00000001"; --8 and the dot is off
  when "1001" => digit4 <= "00100001"; --9 and the dot is off
  when "1010" => digit4 <= "00010000"; --A and the dot is on
  when "1011" => digit4 <= "00000000"; --B and the dot is on
  when "1100" => digit4 <= "10001100"; --C and the dot is on
  when "1101" => digit4 <= "10000000"; --D and the dot is on
  when "1110" => digit4 <= "00001100"; --E and the dot is on
  when "1111" => digit4 <= "00011100"; --F and the dot is on
  when others => digit4 <= "11111111"; --Dark and the dot is off
end case;
end process;
--7 SEGMENT DISPLAY
end bevahorial;