Last active
October 29, 2019 09:49
-
-
Save lwhsu/743286ead8c33bed61764d80b3a008ca to your computer and use it in GitHub Desktop.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
# This is a shell archive. Save it in a file, remove anything before | |
# this line, and then unpack it by entering "sh file". Note, it may | |
# create directories; files and directories will be owned by you and | |
# have default permissions. | |
# | |
# This archive contains: | |
# | |
# riscv-isa-sim | |
# riscv-isa-sim/pkg-descr | |
# riscv-isa-sim/distinfo | |
# riscv-isa-sim/pkg-plist | |
# riscv-isa-sim/Makefile | |
# | |
echo c - riscv-isa-sim | |
mkdir -p riscv-isa-sim > /dev/null 2>&1 | |
echo x - riscv-isa-sim/pkg-descr | |
sed 's/^X//' >riscv-isa-sim/pkg-descr << 'e20f4d002f42839deb45f56282cb5a07' | |
XSpike, a RISC-V ISA Simulator | |
X | |
XThe RISC-V ISA Simulator implements a functional model of one or more RISC-V | |
Xprocessors. | |
X | |
XWWW: https://github.com/riscv/riscv-isa-sim | |
e20f4d002f42839deb45f56282cb5a07 | |
echo x - riscv-isa-sim/distinfo | |
sed 's/^X//' >riscv-isa-sim/distinfo << 'add7ce79b7618cfddd4f6478e578a4c2' | |
XTIMESTAMP = 1572317773 | |
XSHA256 (riscv-riscv-isa-sim-v1.0.0_GH0.tar.gz) = 7ad7f2bac701ab01a469a7ed07075ae1509e3a617da107ef364eebf21d3324a8 | |
XSIZE (riscv-riscv-isa-sim-v1.0.0_GH0.tar.gz) = 283500 | |
add7ce79b7618cfddd4f6478e578a4c2 | |
echo x - riscv-isa-sim/pkg-plist | |
sed 's/^X//' >riscv-isa-sim/pkg-plist << '868ab0f2a67d340c235801147aec4a0a' | |
Xbin/elf2hex | |
Xbin/spike | |
Xbin/spike-dasm | |
Xbin/termios-xspike | |
Xbin/xspike | |
Xinclude/fesvr/context.h | |
Xinclude/fesvr/device.h | |
Xinclude/fesvr/dtm.h | |
Xinclude/fesvr/elf.h | |
Xinclude/fesvr/elfloader.h | |
Xinclude/fesvr/htif.h | |
Xinclude/fesvr/htif_hexwriter.h | |
Xinclude/fesvr/htif_pthread.h | |
Xinclude/fesvr/memif.h | |
Xinclude/fesvr/option_parser.h | |
Xinclude/fesvr/rfb.h | |
Xinclude/fesvr/syscall.h | |
Xinclude/fesvr/term.h | |
Xinclude/fesvr/tsi.h | |
Xlib/libfesvr.a | |
Xlibdata/pkgconfig/riscv-dummy_rocc.pc | |
Xlibdata/pkgconfig/riscv-fesvr.pc | |
Xlibdata/pkgconfig/riscv-riscv.pc | |
Xlibdata/pkgconfig/riscv-softfloat.pc | |
Xlibdata/pkgconfig/riscv-spike_main.pc | |
868ab0f2a67d340c235801147aec4a0a | |
echo x - riscv-isa-sim/Makefile | |
sed 's/^X//' >riscv-isa-sim/Makefile << 'ab0ea866d70fea1862c8aa030cf75948' | |
X# $FreeBSD: head/emulators/riscv-isa-sim/Makefile 507372 2019-07-26 20:46:53Z gerald $ | |
X | |
XPORTNAME= riscv-isa-sim | |
XPORTVERSION= 1.0.0 | |
XDISTVERSIONPREFIX=v | |
XCATEGORIES= emulators | |
X | |
XMAINTAINER= lwhsu@FreeBSD.org | |
XCOMMENT= Spike, a RISC-V ISA Simulator | |
X | |
XLICENSE= BSD3CLAUSE | |
X | |
XBUILD_DEPENDS= ${LOCALBASE}/bin/ar:devel/binutils | |
X | |
XUSES= compiler:c++11-lang gmake shebangfix | |
X | |
XUSE_GITHUB= yes | |
XGH_ACCOUNT= riscv | |
X | |
XHAS_CONFIGURE= yes | |
XCONFIGURE_ENV= AR=${LOCALBASE}/bin/ar | |
X | |
XSHEBANG_FILES= scripts/vcs-version.sh | |
X | |
XSTRIP_FILES= bin/elf2hex \ | |
X bin/spike \ | |
X bin/spike-dasm \ | |
X bin/termios-xspike \ | |
X bin/xspike | |
X | |
Xpost-install: | |
X. for f in ${STRIP_FILES} | |
X ${STRIP_CMD} ${STAGEDIR}${PREFIX}/${f} | |
X. endfor | |
X | |
X.include <bsd.port.mk> | |
ab0ea866d70fea1862c8aa030cf75948 | |
exit | |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment