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AdamSLevy / keybase.md
Created August 24, 2016 00:03
Keybase identity proof

Keybase proof

I hereby claim:

  • I am adamslevy on github.
  • I am adamslevy (https://keybase.io/adamslevy) on keybase.
  • I have a public key ASBgnQRWdoIE9dz8Rf1_Tshz-LgC2Mi2FjA0bjZR4hW0SQo

To claim this, I am signing this object:

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AdamSLevy / git_submodules_best_practices.md
Last active August 25, 2016 05:48
Git Submodules Best Practices

#Git Submodules Best Practices

This document outlines some basic policies that should be followed by teams using git submodules in thier projects.

Guidelines

Always branch before making changes to a submodule.

Go into the submodule and branch before making changes to it.

Rationale

Unless the super project happens to be pointing to the latest commit in the submodule's tree, the submodule is checked out to a commit in the detached head state. This means that changes and

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AdamSLevy / gitflow-breakdown.md
Created September 13, 2016 00:18 — forked from JamesMGreene/gitflow-breakdown.md
A comparison of using `git flow` commands versus raw `git` commands.

Initialize

gitflow git
git flow init git init
git commit --allow-empty -m "Initial commit"
git checkout -b develop master

Connect to the remote repository

coreboot-d1ef71a romstage Thu Mar 3 12:23:28 PST 2016 starting...
bist: 0x00000000
tsc_low: 0x0003e404
tsc_hi: 0x00000000
CONFIG_MMCONF_BASE_ADDRESS: 0xe0000000
Using: FSP 1.1
FSP TempRamInit successful
FSP_INFO_HEADER: fff6e094
00:00.0 Host bridge: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series SoC Transaction Register (rev 35)
Subsystem: Intel Corporation Device 7270
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Kernel driver in use: iosf_mbi_pci
00:02.0 VGA compatible controller: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Integrated Graphics Controller (rev 35) (prog-if 00 [VGA controller])
Subsystem: Intel Corporation Device 7270
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
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AdamSLevy / github_rsa.pub
Created October 3, 2016 18:18
Arch Box GitHub Public Key
ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAACAQDMWBqrhXpnQ/LAJMrEg5r2J5ujPq4sj4jCgEMrXx23Wm46+XgEfCuPCtNYqyrYH7i4qtM26oZhnfoW7JH0vOjcXhRPLZ35vwH5xc3pdw7y/mnxYgYvwKHtHyVxiJPhsm6cRSb/giP5R3fhgFtrad4uT/rH5VwhopJtwzQdnyIdQYqw4rh82oZwYveLW0+wcCy5TzlDTYhtz7Hy+GzPUdzG7snqHol2qg1UckEwjA55aotG8qocIF8vDnK95AE5YoaakM76EuOKSaskgPdUTNTgiaZudbxhJGLsyoV9k/5YTSD2TjVdHTs0F1sdZkRencwwI4agN4NMt9SyTKf6WaVzlT3wlGVSijF3Gs6iooXgeXnGQqg/ap/uv7uuGCqk8ug+SYluTJmVfDtvlZjxenUndHAh3+9nJJcYqgkPT0G5TSNZmwn9J0tVYjwF3TC8lQ9GT4qnERulVOlwcA3iPSoYo4kw8JVRq2LPGmhYYd1nwQHxTpQZME0YxI0/l/WPql12pJv5TPQPagbbn4vzG8x6qUOAkfgAgoh4oBSVvSdZ6bW6sxaWrjnsVoWUn83oThPZHGxi0SMKAL4HObN/cBLzHBT0Pjmq8y58TId7M4C2Ls49ZTYPmfhRIZvV4ZHShqS3HZAzWUnP9GQUzl+1i/Ic4qc44Rju6xfp+UOtVYxR1Q== theadamlevy@gmail.com
flashrom v0.9.9-r1955 on Linux 4.7.5-1-ARCH (x86_64)
flashrom is free software, get the source code at https://flashrom.org
Calibrating delay loop... OK.
coreboot table found at 0x7cc13000.
Found chipset "Intel Braswell".
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with it,
then please email a report to flashrom@flashrom.org including a verbose (-V) log.
Thank you!
# Copyright (C) 2014 Infinite Automation Systems Inc. All rights reserved.
# @author Matthew Lohbihler
###############################################################################
# TO OVERRIDE VALUES IN THIS FILE...
#
# Do not change the values in this file, because when you upgrade your core
# your changes will be overwritten. Instead, create a new file called
# <MA_HOME>/overrides/properties/env.properties and override properties
# there. The overrides directory will never be overwritten by an upgrade, so
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AdamSLevy / -
Created January 29, 2017 07:08
00:00.0 Host bridge: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series SoC Transaction Register (rev 35)
00:02.0 VGA compatible controller: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Integrated Graphics Controller (rev 35)
00:0b.0 Signal processing controller: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series Power Management Controller (rev 35)
00:14.0 USB controller: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series USB xHCI Controller (rev 35)
00:1b.0 Audio device: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series High Definition Audio Controller (rev 35)
00:1c.0 PCI bridge: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series PCI Express Port #1 (rev 35)
00:1c.2 PCI bridge: Intel Corporation Atom/Celeron/Pentium Processor x5-E8000/J3xxx/N3xxx Series PCI Express Port #3 (rev 35)
00:1f.0 ISA bridge: Intel Corporation Atom/Celeron/Pentium Processor x5-