c5g.vhd

-- Baseline pineout
-- This is some base pinout file for the C5G, aka the terasic cyclone v gx starter kit board, because the one from terasic is verilog.
-- Some features are just not usable with this file. Don't assume it works or it is reliable.

library ieee;
use ieee.std_logic_1164.all;

entity baseline_c5gx is
	-- 1.2V ADC
	port (
--			ADC_CONVST, ADC_SCK, ADC_SDI : out std_logic;
--			ADC_SDO : out std_logic;
			
	-- 2.5V AUDio
--			AUD_ADCDAT : in std_logic; -- ADC data
--			AUD_ADCLRCK : inout std_logic; -- ADC LRCK?
--			AUD_BCLK : inout std_logic; -- BCLK?
--			AUD_DACDAT : out std_logic; -- DAC data
--			AUD_DACLRCK : inout std_logic; -- DAC LRCK
--			AUD_XCK : out std_logic; -- XCK
	
	-- Clocks
--			CLOCK_125_p : in std_logic; -- LVDS 125MHz clock
--			CLOCK_50_B5B : in std_logic; -- 3.3V LVTTL
--			CLOCK_50_B6A : in std_logic;
			CLOCK_50_B7A : in std_logic; -- 2.5V
--			CLOCK_50_B8A : in std_logic;
	
	-- Buttons and switches
--			CPU_RESET_n : in std_logic; -- 3.3V LVTTL
--			KEY : in std_logic_vector(3 downto 0); -- 1.2V
			SW : in std_logic_vector(9 downto 0); -- 1.2V
	
	-- 1.2V HSUL DDR2LP
--			DDR2LP_CA : out std_logic_vector(9 downto 0);
--			DDR2LP_CKE : out std_logic_vector(1 downto 0);
--			DDR2LP_CK_n : out std_logic; -- 1.2V differential HSUL
--			DDR2LP_CK_p : out std_logic; -- 1.2V differential HSUL
--			DDR2LP_CS_n : out std_logic_vector(1 downto 0);
--			DDR2LP_DM : out std_logic_vector(3 downto 0);
--			DDR2LP_DQ : inout std_logic_vector(31 downto 0);
--			DDR2LP_DQS_n : inout std_logic_vector(3 downto 0); -- 1.2V differential HSUL
--			DDR2LP_DQS_p : inout std_logic_vector(3 downto 0); -- 1.2V differential HSUL
--			DDR2LP_OCT_RZQ : in std_logic; -- 1.2V

	-- 1.2V HEXadecimal displays
--			HEX0, HEX1, HEX2, HEX3 : out std_logic_vector(6 downto 0);
			
	-- 2.5V LEDs
--			LEDG : out std_logic_vector(7 downto 0);
			LEDR : out std_logic_vector(9 downto 0)
			
	-- 1.5V PCML REFCLK
--			REFCLK_p0, REFCLK_p1 : in std_logic;
		
	-- HDMI
--			HDMI_TX_CLK : out std_logic;
--			HDMI_TX_D : out std_logic_vector(23 downto 0);
--			HDMI_TX_DE : out std_logic;
--			HDMI_TX_HS : out std_logic;
--			HDMI_TX_INT : in std_logic; -- HDMI INTerrupt, for vsync and stuff?
--			HDMI_TX_VS : out std_logic;
	
	-- 2.5V I2C
--			I2C_SCL : out std_logic;
--			I2C_SDA : inout std_logic;

	-- 3.3V LVTTL SD
--			SD_CLK : out std_logic;
--			SD_CMD : inout std_logic;
--			SD_DAT : inout std_logic_vector(3 downto 0);
	
	-- 1.5V PCML SMA
--			SMA_GXB_RX_p : in std_logic;
--			SMA_GXB_TX_p : out std_logic;

	-- 3.3V LVTTL SRAM
--			SRAM_A : out std_logic_vector(17 downto 0);
--			SRAM_CE_n : out std_logic;
--			SRAM_D : inout std_logic_vector(15 downto 0);
--			SRAM_LB_n : out std_logic;
--			SRAM_OE_n : out std_logic;
--			SRAM_UB_n : out std_logic;
--			SRAM_WE_n : out std_logic;
	
	-- 2.5V UART
--			UART_RX : in std_logic;
--			UART_TX : out std_logic
	);
end entity;

architecture baseline_c5gx_arch of baseline_c5gx is

begin

	process(CLOCK_50_B7A)
	begin
		if rising_edge(CLOCK_50_B7A) then
			LEDR <= SW;
		end if;
	end process;
end architecture;