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Fabien Marteau Martoni

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Martoni / multsum.scala
Created February 15, 2021 14:57
Chisel multiplication of 2 UInt with same size. Serial addition way of multiplication.
package multsum
import chisel3._
import chisel3.util._
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
import chisel3.formal.Formal
/* Unsigned multiplication */
class MultSum(val bsize: Int = 16) extends Module with Formal {
val io = IO(new Bundle {
@Martoni
Martoni / cic_filter.scala
Last active March 11, 2021 07:29
PDM CIC Filter in Chisel
import chisel3._
import chisel3.util._
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
class CICFilter(val bsize: Int = 16,
val rising: Boolean = true, //currently only one channel
val cicstages: Int = 3,
val cicrate: Int = 23,
val cicdelay: Int = 1) extends Module{
val io = IO(new Bundle {
@Martoni
Martoni / SimplePWM.scala
Created March 23, 2021 10:30
Simple Chisel PWM
import chisel3._
import chisel3.util._
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
class SimplePWM(val insize: Int = 16) extends Module {
val io = IO(new Bundle {
val inval = Flipped(Decoupled(UInt(insize.W)))
val pwm_o = Output(Bool())
})
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Martoni / TMDS_PLLVR.v
Created March 4, 2022 07:57
GbHDMI project generated by Chisel GbHdmi module. With Gowin synthesis error
//Copyright (C)2014-2020 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//GOWIN Version: V1.9.7.01Beta
//Part Number: GW1NSR-LV4CQN48PC7/I6
//Device: GW1NSR-4C
//Created Time: Tue Nov 03 14:39:26 2020
module TMDS_PLLVR (clkout, lock, clkoutd, clkin);
@Martoni
Martoni / patch.py
Created July 22, 2022 14:47 — forked from pepijndevos/patch.py
Gowin IDE patcher
#!/usr/bin/python3
import os
import re
import subprocess
import mmap
def patch(filename : str, bytes):
subprocess.run(["cp",filename, filename + '_patched'])
with open(filename + "_patched", "r+b") as f: