diff --git a/src/cmd/compile/internal/amd64/ssa.go b/src/cmd/compile/internal/amd64/ssa.go | |
index 307cdc5e83..dc1ab4161a 100644 | |
--- a/src/cmd/compile/internal/amd64/ssa.go | |
+++ b/src/cmd/compile/internal/amd64/ssa.go | |
@@ -149,6 +149,17 @@ func duff(size int64) (int64, int64) { | |
func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) { | |
switch v.Op { | |
+ case ssa.OpAMD64FMASD: | |
+ p := s.Prog(v.Op.Asm()) | |
+ p.From.Type = obj.TYPE_REG | |
+ p.From.Reg = v.Args[2].Reg() | |
+ p.To.Type = obj.TYPE_REG | |
+ p.To.Reg = v.Reg() | |
+ p.SetFrom3(obj.Addr{Type: obj.TYPE_REG, Reg: v.Args[1].Reg()}) | |
+ if v.Reg() != v.Args[0].Reg() { | |
+ v.Fatalf("input[0] and output not in same register %s", v.LongString()) | |
+ } | |
+ | |
case ssa.OpAMD64ADDQ, ssa.OpAMD64ADDL: | |
r := v.Reg() | |
r1 := v.Args[0].Reg() | |
diff --git a/src/cmd/compile/internal/ssa/gen/AMD64.rules b/src/cmd/compile/internal/ssa/gen/AMD64.rules | |
index dd71ccaf5e..681fa4e511 100644 | |
--- a/src/cmd/compile/internal/ssa/gen/AMD64.rules | |
+++ b/src/cmd/compile/internal/ssa/gen/AMD64.rules | |
@@ -2427,3 +2427,5 @@ | |
&& validValAndOff(0,off) | |
&& clobber(l) -> | |
@l.Block (CMP(Q|L|W|B)constload {sym} [makeValAndOff(0,off)] ptr mem) | |
+ | |
+(ADDSD (MULSD x y) z) -> (FMASD z x y) | |
\ No newline at end of file | |
diff --git a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go | |
index 5a8634abd1..14402771ea 100644 | |
--- a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go | |
+++ b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go | |
@@ -143,6 +143,7 @@ func init() { | |
fp01 = regInfo{inputs: nil, outputs: fponly} | |
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly} | |
+ fp31 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly} | |
fp21load = regInfo{inputs: []regMask{fp, gpspsb, 0}, outputs: fponly} | |
fpgp = regInfo{inputs: fponly, outputs: gponly} | |
gpfp = regInfo{inputs: gponly, outputs: fponly} | |
@@ -167,6 +168,8 @@ func init() { | |
{name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true}, // fp32 div | |
{name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true}, // fp64 div | |
+ {name: "FMASD", argLength: 3, reg: fp31, resultInArg0: true, asm: "VFMADD231SD"}, // fp64 fma | |
+ | |
{name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // fp32 load | |
{name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // fp64 load | |
{name: "MOVSSconst", reg: fp01, asm: "MOVSS", aux: "Float32", rematerializeable: true}, // fp32 constant |
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