Skip to content

Instantly share code, notes, and snippets.

View Th3Fanbus's full-sized avatar
🔥
overheating

Angel Pons Th3Fanbus

🔥
overheating
View GitHub Profile
@Th3Fanbus
Th3Fanbus / finder.cpp
Created January 22, 2019 20:21
What the hell did I make? I don't remember what this was...
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <iterator>
#include <algorithm>
const std::string folder = "DUMP/";
const std::vector<std::string> filenames = {
"010216CD-9C09-4EB5-B7DA-D0A2865092D4_1281.ROM",
Non-zero if the kernel has been tainted. Numeric values, which can be
ORed together. The letters are seen in "Tainted" line of Oops reports.
1 (P): A module with a non-GPL license has been loaded, this
includes modules with no license.
Set by modutils >= 2.4.9 and module-init-tools.
2 (F): A module was force loaded by insmod -f.
Set by modutils >= 2.4.9 and module-init-tools.
4 (S): Unsafe SMP processors: SMP with CPUs not designed for SMP.
8 (R): A module was forcibly unloaded from the system by rmmod -f.
@Th3Fanbus
Th3Fanbus / intel_inside.txt
Created August 15, 2019 02:03
Intel Inside ASCII art
..-+osyhhdmmNNNMMMNNNmmdhhys+:.
.:+shdNMMMMMMMMMNNmdddddddddmNNMMMMMMMMMMmhs\.
.:oymMMMMMmdyso/:` `\+shmMMMMMMNh+.
.:ohNMMNdyo/-` `\smMMMMMmo.
./ymMMdy+:` `+hMMMMMh:
:smMds/` `oNMMMMh.
.ho:` `yMMMMN:
/mmmm\ \MMMMM|
/NNNNh dMMMM+ :MMMMN.
.: /MMMMd .mmmmd dMMMM+ yMMMMs
@Th3Fanbus
Th3Fanbus / linux-phc.log
Created January 30, 2020 18:19
mobile sandy bridge (i3): "CPU not recognized" - Linux PHC
Thread name: mobile sandy bridge (i3): "CPU not recognized" [4 posts]
Post by tliketea at Thu 26. Jul 2012, 12:23:
Howdy,
I followed the linuxsolver tutorial for using PHCTool in 12.04 several times now. Everything seems to be working (no errors), but the GUI tool shows me "CPU not recognized - calculation not available" ...
cat /proc/cpuinfo gives:
int smbus_stub(int slv_addr, int reg, int length, unsigned char *b)
{
struct mrc_params *p = wrapper_params;
unsigned char *spd_data;
switch (slv_addr) {
case FAKE_SPD_ADDR_CH0:
spd_data = p->mainboard.dram_data[0];
break;
case FAKE_SPD_ADDR_CH1:
@Th3Fanbus
Th3Fanbus / lspci_satellite_pro_l70.log
Created October 16, 2020 13:03
lspci of Toshiba Satellite Pro L70-A
usuario@bloodfest ~ $ lspci
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller (rev 06)
00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor PCI Express x16 Controller (rev 06)
00:02.0 VGA compatible controller: Intel Corporation 4th Gen Core Processor Integrated Graphics Controller (rev 06)
00:03.0 Audio device: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor HD Audio Controller (rev 06)
00:14.0 USB controller: Intel Corporation 8 Series/C220 Series Chipset Family USB xHCI (rev 04)
00:16.0 Communication controller: Intel Corporation 8 Series/C220 Series Chipset Family MEI Controller #1 (rev 04)
00:1a.0 USB controller: Intel Corporation 8 Series/C220 Series Chipset Family USB EHCI #2 (rev 04)
00:1b.0 Audio device: Intel Corporation 8 Series/C220 Series Chipset High Definition Audio Controller (rev 04)
00:1c.0 PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI Express Root Port #1 (rev d4)

https://review.coreboot.org/c/coreboot/+/46943 cpu/intel/Makefile.inc: Use correct Kconfig symbols https://review.coreboot.org/c/coreboot/+/46977 sb/intel/lynxpoint: Use common code to generate HPET table https://review.coreboot.org/c/coreboot/+/46719 sb/intel/lynxpoint: Drop unnecessary 'UL' suffix https://review.coreboot.org/c/coreboot/+/46720 {cpu,nb}/intel/haswell: Drop unnecessary 'UL' suffix https://review.coreboot.org/c/coreboot/+/46725 sb/intel/lynxpoint/lpc.c: Simplify PM init sequence https://review.coreboot.org/c/coreboot/+/46726 sb/intel/lynxpoint: Align with Broadwell https://review.coreboot.org/c/coreboot/+/46727 azalia: Treat all negative return values as errors https://review.coreboot.org/c/coreboot/+/46728 azalia: Use 'HDA_GCTL_CRST' macro as unset-mask https://review.coreboot.org/c/coreboot/+/46734 Revert "broadwell: Switch to using common ACPI _SWS code" https://review.coreboot.org/c/coreboot/+/46732 soc/intel/broadwell/gma.c: Align struct with Haswell

@Th3Fanbus
Th3Fanbus / ironlak-scanchains.log
Created January 17, 2021 00:10
Ironlake scan chain accesses
R1D0 [33d] <= 0 (0000)
R500 C0 [b61] <= 0 (0000)
R500 C1 [b61] <= 0 (0000)
R1D0 [151] <= 4 (0004)
R1D0 [142] <= 0 (0000)
R500 C1 [6b3] <= 1 (0001)
R500 C1 [6cf] <= 1 (0001)
R1D0 [33d] <= 0 (0000)
R1D0 [33d] <= 0 (0000)
@Th3Fanbus
Th3Fanbus / long_lspci.log
Created February 2, 2021 22:00
lspci -vvvxxxx on Asus Z10PA-D8
00:00.0 Host bridge: Intel Corporation Xeon E7 v3/Xeon E5 v3/Core i7 DMI2 (rev 02)
Subsystem: Intel Corporation Device 0000
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 0
NUMA node: 0
Capabilities: [90] Express (v2) Root Port (Slot-), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
@Th3Fanbus
Th3Fanbus / how-to-patch-dsdt.txt
Last active April 26, 2021 09:33
How to apply a DSDT override
# Instructions derived from: https://wiki.archlinux.org/index.php/DSDT
########################################################################
# Recompiling it yourself #
# https://wiki.archlinux.org/index.php/DSDT#Recompiling_it_yourself #
########################################################################
# Extract the binary ACPI tables
sudo cat /sys/firmware/acpi/tables/DSDT > dsdt.dat