topEntity.v

/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 1.5.0. DO NOT MODIFY.
*/
`timescale 100fs/100fs
module topEntity
    ( // Inputs
      input  clk // clock
    , input  rst // reset
    , input  en // enable
    , input [1:0] in

      // Outputs
    , output wire [3:0] out
    );
  // i2c/Imperative.hs:(156,1)-(162,17)
  wire  s1;
  // i2c/Imperative.hs:(156,1)-(162,17)
  wire signed [63:0] n;
  // i2c/Imperative.hs:(156,1)-(162,17)
  wire [64:0] a1;
  // i2c/Imperative.hs:(156,1)-(162,17)
  reg [64:0] ds1 = {1'b0,   64'sd0};
  wire [69:0] result;
  wire [1:0] c$app_arg;
  wire [1:0] y_outSDA;
  wire [1:0] y_outSDA1;
  wire [1:0] c$app_arg_0;
  wire [1:0] y_outSCL;
  wire [1:0] y_outSCL1;
  wire [3:0] \w' ;
  wire [3:0] c$w1_case_alt;
  wire [3:0] c$w1_case_alt_0;
  wire [3:0] c$w1_case_alt_1;
  wire [1:0] y_outSDA_0;
  wire [1:0] y_outSCL_0;
  wire [3:0] c$w1_case_alt_2;
  wire [3:0] c$w1_case_alt_3;
  wire [3:0] c$w1_case_alt_4;
  wire [1:0] y_outSDA_1;
  wire [1:0] y_outSCL_1;
  wire [3:0] c$w1_case_alt_5;
  wire [1:0] y_outSDA_2;
  wire [1:0] y_outSCL_2;
  wire [3:0] c$w1_case_alt_6;
  wire [1:0] y_outSDA_3;
  wire [1:0] y_outSCL_3;
  wire [69:0] c$ds3_case_alt;
  wire [69:0] c$ds3_case_alt_0;
  wire [69:0] c$ds3_case_alt_1;
  wire [69:0] c$ds3_case_alt_2;
  wire [69:0] c$ds3_case_alt_3;
  wire signed [63:0] \s'3 ;
  wire [0:0] a4;
  wire [64:0] a3;
  wire  \c$s'_case_alt ;
  wire  \c$s'_case_alt_0 ;
  wire  \c$s'_case_alt_1 ;
  wire  \c$s'_case_alt_2 ;
  wire [0:0] a4_0;
  wire signed [63:0] \s'3_0 ;
  wire [64:0] a3_0;
  wire [0:0] a4_1;
  wire signed [63:0] \s'3_1 ;
  wire [0:0] a4_2;
  wire [64:0] c$ds4_case_alt;
  wire  c$ds4_case_scrut;
  // i2c/Imperative.hs:(175,7)-(191,7)
  wire signed [63:0] x3;
  wire signed [63:0] \s'3_2 ;
  wire [64:0] a3_1;
  wire  \c$s'_case_alt_3 ;
  wire  \s'' ;
  wire [0:0] a1_0;
  wire [64:0] a1_1;
  wire [69:0] result_0;
  wire [1:0] c$app_arg_1;
  // i2c/Imperative.hs:36:3-7
  wire [1:0] y_outSDA_4;
  // i2c/Imperative.hs:36:3-7
  wire [1:0] y_outSDA1_0;
  wire [1:0] c$app_arg_2;
  // i2c/Imperative.hs:36:3-7
  wire [1:0] y_outSCL_4;
  // i2c/Imperative.hs:36:3-7
  wire [1:0] y_outSCL1_0;
  // i2c/Imperative.hs:36:3-7
  wire [3:0] \w'_0 ;
  // i2c/Imperative.hs:36:3-7
  wire [69:0] c$ds3_case_alt_4;
  // i2c/Imperative.hs:36:3-7
  wire [69:0] c$ds3_case_alt_5;
  wire [0:0] y;
  // i2c/Imperative.hs:36:3-7
  wire [0:0] c$ds3_case_alt_6;
  wire [0:0] a1_2;
  wire [64:0] a1_3;
  wire [69:0] result_1;
  wire [1:0] c$app_arg_3;
  wire [1:0] y_outSDA_5;
  wire [1:0] y_outSDA1_1;
  wire [1:0] c$app_arg_4;
  wire [1:0] y_outSCL_5;
  wire [1:0] y_outSCL1_1;
  wire [3:0] \w'_1 ;
  wire [3:0] c$w1_case_alt_7;
  wire [3:0] c$w1_case_alt_8;
  wire [1:0] y_outSDA_6;
  wire [1:0] y_outSCL_6;
  wire [3:0] c$w1_case_alt_9;
  wire [3:0] c$w1_case_alt_10;
  wire [69:0] c$ds3_case_alt_7;
  wire [69:0] c$ds3_case_alt_8;
  wire [69:0] c$ds3_case_alt_9;
  wire [69:0] c$ds3_case_alt_10;
  wire [1:0] c$ds3_app_arg;
  wire [1:0] y_outSDA1_2;
  wire [1:0] c$ds3_app_arg_0;
  wire [1:0] y_outSCL1_2;
  wire [3:0] \w'_2 ;
  wire [69:0] c$ds5_case_alt;
  wire signed [63:0] \s'3_3 ;
  wire [0:0] a4_3;
  wire [64:0] c$ds4_case_alt_0;
  wire  c$ds4_case_scrut_0;
  // i2c/Imperative.hs:(175,7)-(191,7)
  wire signed [63:0] x3_0;
  wire signed [63:0] \s'3_4 ;
  wire [0:0] a4_4;
  wire [0:0] a4_5;
  wire [64:0] c$ds4_case_alt_1;
  // i2c/Imperative.hs:(175,7)-(191,7)
  wire  a1_4;
  wire signed [63:0] \s'3_5 ;
  wire [64:0] a3_2;
  wire [0:0] a4_6;
  wire signed [63:0] \s'3_6 ;
  wire [0:0] a1_5;
  wire [64:0] c$ds4_case_alt_2;
  wire  c$ds4_case_scrut_1;
  // i2c/Imperative.hs:(175,7)-(191,7)
  wire signed [63:0] x3_1;
  wire [64:0] a1_6;
  wire [1:0] a1_7;
  wire [65:0] a1_8;
  wire [70:0] result_2;
  wire [1:0] c$case_alt;
  wire [0:0] c$app_arg_5;
  wire  y_1;
  wire [1:0] a1_9;
  wire [65:0] a1_10;
  wire signed [63:0] c$tte_rhs;
  wire signed [63:0] c$tte_rhs_0;
  wire signed [63:0] c$tte_rhs_1;

  assign out = result[3:0];

  assign s1 = ds1[64:64];

  assign n = $signed(ds1[63:0]);

  assign a1 = result[69:5];

  // register begin
  always @(posedge clk or  posedge  rst) begin : ds1_register
    if ( rst) begin
      ds1 <= {1'b0,   64'sd0};
    end else if (en) begin
      ds1 <= {result[4:4],   $signed(a1[63:0])};
    end
  end
  // register end

  assign result = {c$ds3_case_alt[69:5],
                   c$ds3_case_alt[4:4],   {c$app_arg_0,
                                           c$app_arg}};

  assign c$app_arg = y_outSDA1[1:1] ? y_outSDA1 : y_outSDA;

  assign y_outSDA = c$w1_case_alt[1:0];

  assign y_outSDA1 = \w' [1:0];

  assign c$app_arg_0 = y_outSCL1[1:1] ? y_outSCL1 : y_outSCL;

  assign y_outSCL = c$w1_case_alt[3:2];

  assign y_outSCL1 = \w' [3:2];

  assign \w'  = c$ds3_case_alt[3:0];

  assign c$w1_case_alt = a1_0 ? c$w1_case_alt_0 : {y_outSCL_0,
                                                   y_outSDA_0};

  assign c$w1_case_alt_0 = a4_2 ? c$w1_case_alt_1 : {y_outSCL_0,
                                                     y_outSDA_0};

  assign c$w1_case_alt_1 = {y_outSCL_0,
                            y_outSDA_0};

  assign y_outSDA_0 = c$w1_case_alt_2[1:0];

  assign y_outSCL_0 = c$w1_case_alt_2[3:2];

  assign c$w1_case_alt_2 = a1_0 ? c$w1_case_alt_3 : {y_outSCL_1,
                                                     y_outSDA_1};

  assign c$w1_case_alt_3 = a4_2 ? c$w1_case_alt_4 : {y_outSCL_1,
                                                     y_outSDA_1};

  assign c$w1_case_alt_4 = a4_1 ? {{1'b1,1'd1},
                                   y_outSDA_1} : {y_outSCL_1,   y_outSDA_1};

  assign y_outSDA_1 = c$w1_case_alt_5[1:0];

  assign y_outSCL_1 = c$w1_case_alt_5[3:2];

  assign c$w1_case_alt_5 = {y_outSCL_2,
                            y_outSDA_2};

  assign y_outSDA_2 = c$w1_case_alt_6[1:0];

  assign y_outSCL_2 = c$w1_case_alt_6[3:2];

  assign c$w1_case_alt_6 = a1_0 ? {y_outSCL_3,
                                   {1'b1,1'd1}} : {y_outSCL_3,   y_outSDA_3};

  assign y_outSDA_3 = result_0[1:0];

  assign y_outSCL_3 = result_0[3:2];

  assign c$ds3_case_alt = a1_0 ? c$ds3_case_alt_0 : {{1'd0,
                                                      $signed(a1_1[63:0])},   \c$s'_case_alt ,
                                                     {{1'b0,1'bx},   {1'b0,1'bx}}};

  assign c$ds3_case_alt_0 = a4_2 ? c$ds3_case_alt_1 : {{1'd0,
                                                        \s'3_2 },   \c$s'_case_alt ,   {{1'b0,1'bx},
                                                                                        {1'b0,1'bx}}};

  assign c$ds3_case_alt_1 = a4_1 ? c$ds3_case_alt_2 : {{1'd0,
                                                        \s'3_1 },   \c$s'_case_alt ,   {{1'b0,1'bx},
                                                                                        {1'b0,1'bx}}};

  assign c$ds3_case_alt_2 = a4_0 ? c$ds3_case_alt_3 : {{1'd0,
                                                        \s'3_0 },   \c$s'_case_alt ,   {{1'b0,1'bx},
                                                                                        {1'b0,1'bx}}};

  assign c$ds3_case_alt_3 = a4 ? {{1'd0,
                                   64'sd0},   \c$s'_case_alt ,   {{1'b0,1'bx},
                                                                  {1'b0,1'bx}}} : {{1'd0,   \s'3 },
                                                                                   \c$s'_case_alt ,   {{1'b0,1'bx},
                                                                                                       {1'b0,1'bx}}};

  assign \s'3  = $signed(a3[63:0]);

  assign a4 = a3[64:64];

  assign a3 = {1'd1,   \s'3_0 };

  assign \c$s'_case_alt  = a1_0 ? \c$s'_case_alt_0  : \c$s'_case_alt_3 ;

  assign \c$s'_case_alt_0  = a4_2 ? \c$s'_case_alt_1  : \c$s'_case_alt_3 ;

  assign \c$s'_case_alt_1  = a4_1 ? \c$s'_case_alt_2  : \c$s'_case_alt_3 ;

  assign \c$s'_case_alt_2  = a4_0 ? 1'b1 : \c$s'_case_alt_3 ;

  assign a4_0 = a3_0[64:64];

  assign \s'3_0  = $signed(a3_0[63:0]);

  assign a3_0 = {1'd1,   \s'3_1 };

  assign a4_1 = c$ds4_case_alt[64:64];

  assign \s'3_1  = $signed(c$ds4_case_alt[63:0]);

  assign a4_2 = a3_1[64:64];

  assign c$ds4_case_alt = c$ds4_case_scrut ? {1'd0,
                                              64'sd3} : {1'd1,   \s'3_2 };

  assign c$tte_rhs = (x3 < 64'sd3) ? 64'sd1 : 64'sd0;

  assign c$ds4_case_scrut = c$tte_rhs[0];

  assign x3 = \s'3_2 ;

  assign \s'3_2  = $signed(a3_1[63:0]);

  assign a3_1 = {1'd1,   $signed(a1_1[63:0])};

  assign \c$s'_case_alt_3  = a1_0 ? \s''  : result_0[4:4];

  assign \s''  = result_0[4:4];

  assign a1_0 = a1_1[64:64];

  assign a1_1 = result_0[69:5];

  assign result_0 = {c$ds3_case_alt_4[69:5],
                     c$ds3_case_alt_4[4:4],   {c$app_arg_2,
                                               c$app_arg_1}};

  assign c$app_arg_1 = y_outSDA1_0[1:1] ? y_outSDA1_0 : y_outSDA_4;

  assign y_outSDA_4 = result_2[1:0];

  assign y_outSDA1_0 = \w'_0 [1:0];

  assign c$app_arg_2 = y_outSCL1_0[1:1] ? y_outSCL1_0 : y_outSCL_4;

  assign y_outSCL_4 = result_2[3:2];

  assign y_outSCL1_0 = \w'_0 [3:2];

  assign \w'_0  = c$ds3_case_alt_4[3:0];

  assign c$ds3_case_alt_4 = a1_7[1:1] ? c$ds3_case_alt_5 : {{1'd0,
                                                             $signed(a1_8[63:0])},   result_2[4:4],
                                                            {{1'b0,1'bx},   {1'b0,1'bx}}};

  assign c$ds3_case_alt_5 = y ? {{1'd1,
                                  $signed(a1_8[63:0])},   result_2[4:4],
                                 {{1'b0,1'bx},
                                  {1'b0,1'bx}}} : {{c$ds3_case_alt_6,
                                                    $signed(a1_3[63:0])},   result_1[4:4],
                                                   result_1[3:0]};

  assign y = a1_7[0:0];

  assign c$ds3_case_alt_6 = a1_2 ? 1'd1 : 1'd0;

  assign a1_2 = a1_3[64:64];

  assign a1_3 = result_1[69:5];

  assign result_1 = {c$ds3_case_alt_7[69:5],
                     c$ds3_case_alt_7[4:4],   {c$app_arg_4,
                                               c$app_arg_3}};

  assign c$app_arg_3 = y_outSDA1_1[1:1] ? y_outSDA1_1 : y_outSDA_5;

  assign y_outSDA_5 = c$w1_case_alt_7[1:0];

  assign y_outSDA1_1 = \w'_1 [1:0];

  assign c$app_arg_4 = y_outSCL1_1[1:1] ? y_outSCL1_1 : y_outSCL_5;

  assign y_outSCL_5 = c$w1_case_alt_7[3:2];

  assign y_outSCL1_1 = \w'_1 [3:2];

  assign \w'_1  = c$ds3_case_alt_7[3:0];

  assign c$w1_case_alt_7 = a1_5 ? c$w1_case_alt_8 : {y_outSCL_6,
                                                     y_outSDA_6};

  assign c$w1_case_alt_8 = {y_outSCL_6,
                            y_outSDA_6};

  assign y_outSDA_6 = c$w1_case_alt_9[1:0];

  assign y_outSCL_6 = c$w1_case_alt_9[3:2];

  assign c$w1_case_alt_9 = a1_5 ? c$w1_case_alt_10 : {{1'b0,1'bx},
                                                      {1'b1,1'd0}};

  assign c$w1_case_alt_10 = a4_6 ? {{1'b1,1'd0},
                                    {1'b1,1'd0}} : {{1'b0,1'bx},   {1'b1,1'd0}};

  assign c$ds3_case_alt_7 = a1_5 ? c$ds3_case_alt_8 : {{1'd0,
                                                        $signed(a1_6[63:0])},   result_2[4:4],
                                                       {{1'b0,1'bx},   {1'b0,1'bx}}};

  assign c$ds3_case_alt_8 = a4_6 ? c$ds3_case_alt_9 : {{1'd0,
                                                        \s'3_6 },   result_2[4:4],   {{1'b0,1'bx},
                                                                                      {1'b0,1'bx}}};

  assign c$ds3_case_alt_9 = a4_5 ? c$ds3_case_alt_10 : {{1'd0,
                                                         \s'3_5 },   result_2[4:4],   {{1'b0,1'bx},
                                                                                       {1'b0,1'bx}}};

  assign c$ds3_case_alt_10 = a4_4 ? {c$ds5_case_alt[69:5],
                                     c$ds5_case_alt[4:4],   {c$ds3_app_arg_0,
                                                             c$ds3_app_arg}} : {{1'd0,   \s'3_4 },
                                                                                result_2[4:4],   {{1'b0,1'bx},
                                                                                                  {1'b0,1'bx}}};

  assign c$ds3_app_arg = y_outSDA1_2[1:1] ? y_outSDA1_2 : {1'b0,1'bx};

  assign y_outSDA1_2 = \w'_2 [1:0];

  assign c$ds3_app_arg_0 = y_outSCL1_2[1:1] ? y_outSCL1_2 : {1'b0,1'bx};

  assign y_outSCL1_2 = \w'_2 [3:2];

  assign \w'_2  = c$ds5_case_alt[3:0];

  assign c$ds5_case_alt = a4_3 ? {{1'd1,
                                   \s'3_3 },   result_2[4:4],   {{1'b0,1'bx},
                                                                 {1'b0,1'bx}}} : {{1'd0,   \s'3_3 },
                                                                                  result_2[4:4],   {{1'b0,1'bx},
                                                                                                    {1'b0,1'bx}}};

  assign \s'3_3  = $signed(c$ds4_case_alt_0[63:0]);

  assign a4_3 = c$ds4_case_alt_0[64:64];

  assign c$ds4_case_alt_0 = c$ds4_case_scrut_0 ? {1'd0,
                                                  64'sd2} : {1'd1,   \s'3_4 };

  assign c$tte_rhs_0 = (x3_0 < 64'sd2) ? 64'sd1 : 64'sd0;

  assign c$ds4_case_scrut_0 = c$tte_rhs_0[0];

  assign x3_0 = \s'3_4 ;

  assign \s'3_4  = $signed(c$ds4_case_alt_1[63:0]);

  assign a4_4 = c$ds4_case_alt_1[64:64];

  assign a4_5 = a3_2[64:64];

  assign c$ds4_case_alt_1 = a1_4 ? {1'd1,
                                    \s'3_5 } : {1'd0,   \s'3_5 };

  assign a1_4 = in[1:1] == 1'b0;

  assign \s'3_5  = $signed(a3_2[63:0]);

  assign a3_2 = {1'd1,   \s'3_6 };

  assign a4_6 = c$ds4_case_alt_2[64:64];

  assign \s'3_6  = $signed(c$ds4_case_alt_2[63:0]);

  assign a1_5 = a1_6[64:64];

  assign c$ds4_case_alt_2 = c$ds4_case_scrut_1 ? {1'd0,
                                                  64'sd1} : {1'd1,   $signed(a1_6[63:0])};

  assign c$tte_rhs_1 = (x3_1 < 64'sd1) ? 64'sd1 : 64'sd0;

  assign c$ds4_case_scrut_1 = c$tte_rhs_1[0];

  assign x3_1 = $signed(a1_6[63:0]);

  assign a1_6 = {1'd1,   $signed(a1_8[63:0])};

  assign a1_7 = a1_8[65:64];

  assign a1_8 = result_2[70:5];

  assign result_2 = {{c$case_alt,
                      $signed(a1_10[63:0])},   s1,   {{1'b0,1'bx},
                                                      {1'b0,1'bx}}};

  assign c$case_alt = a1_9[1:1] ? {1'b1,c$app_arg_5} : {1'b0,1'bx};

  assign c$app_arg_5 = y_1 ? 1'd0 : 1'd1;

  assign y_1 = a1_9[0:0];

  assign a1_9 = a1_10[65:64];

  assign a1_10 = {{1'b1,s1},   n};


endmodule