Skip to content

Instantly share code, notes, and snippets.

module and48(A,B,C);
input [47:0]A;
input [47:0]B;
output [47:0]C;
// DSP48E1: 48-bit Multi-Functional Arithmetic Block
// 7 Series
// Xilinx HDL Libraries Guide, version 14.7
DSP48E1 #(
// Feature Control Attributes: Data Path Selection
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
clc;
clear;
sample_bits = 12;#smaple bits
fs = 10000; #sample frequency
f = 60; #target frequency
amp= 2^(sample_bits-1);
t = 0:1/fs:1/f;
x = amp*(1+sin(2*pi*f*t));#avoid negative part
static int set_data_flash_base(uint32_t u32DFBA)
{
uint32_t au32Config[2];
if (FMC_ReadConfig(au32Config, 2) < 0) {
printf("\nRead User Config failed!\n");
return -1;
}
if ((!(au32Config[0] & 0x1)) && (au32Config[1] == u32DFBA))
#include <stdio.h>
#include <stdlib.h>
int main(void)
{
int a = 1, b = 2;
printf("a = %d, b= %d\r\n", a, b);
Nano100B_Series_BSP \Library\CMSIS\Lib\ARM
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#define UNUSED(x) (void)(x)
typedef unsigned char uint8_t;
typedef struct
uint8_t (*send)(uint8_t *data, uint8_t len);
uint8_t (*read)(uint8_t *data, uint8_t len);
#define NUM_VA_ARGS_IMPL( \
_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
_11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \
_21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \
_31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \
_41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \
_51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \
_61, _62, N, ...) N
#define NUM_VA_ARGS(...) NUM_VA_ARGS_IMPL(__VA_ARGS__, 63, 62, 61, \
struct
{
uint32_t data:8;
uint32_t _reserve:24;
} b;
#define PACKET_MAX 100
unsigned int packet_count ;
/*if use this compiler will give a warring */
if(packet_count >=PACKET_MAX)
/*use this for alternative */
if(PACKET_MAX - packet_count >=0)
// RF Front End Settings
// Note: The use of these values completely depends on how the PCB is laid out.
// Please see Device Package and Evaluation Module (EM) Board below.
#define RF_FE_DIFFERENTIAL 0
#define RF_FE_SINGLE_ENDED_RFP 1
#define RF_FE_SINGLE_ENDED_RFN 2
#define RF_FE_ANT_DIVERSITY_RFP_FIRST 3
#define RF_FE_ANT_DIVERSITY_RFN_FIRST 4
#define RF_FE_SINGLE_ENDED_RFP_EXT_PINS 5
#define RF_FE_SINGLE_ENDED_RFN_EXT_PINS 6