a46554

clc;
clear;

sample_bits = 12;#smaple bits
fs = 10000;      #sample frequency
f  = 60;         #target frequency

amp= 2^(sample_bits-1);
t  = 0:1/fs:1/f;
x  = amp*(1+sin(2*pi*f*t));#avoid negative part 

a46554

module and48(A,B,C);
input [47:0]A;
input [47:0]B;
output [47:0]C;
// DSP48E1: 48-bit Multi-Functional Arithmetic Block
// 7 Series
// Xilinx HDL Libraries Guide, version 14.7
DSP48E1 #(
// Feature Control Attributes: Data Path Selection
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)