alu.v

module alu #(parameter WIDTH = 32) (
  input clk,
  input reset,
  input [WIDTH - 1:0] a,
  input [WIDTH - 1:0] b,
  input [3:0] op,
  output c_flag,
  output z_flag,
  output s_flag,
  output [WIDTH - 1:0] value);

  reg [WIDTH:0] acc; // result[WIDTH] is carry bit

  assign c_flag = acc[WIDTH];
  assign z_flag = acc[WIDTH - 1:0] == 0;
  assign s_flag = acc[WIDTH - 1];
  assign value  = acc;

  parameter IADD = 4'b0000;
  parameter ISUB = 4'b0001;
  parameter ITEST = 4'b0100;
  parameter ILOR = 4'b0101;
  parameter INOT = 4'b0110;
  parameter INEG = 4'b0111;
  parameter IAND = 4'b1000;
  parameter IOR = 4'b1001;
  parameter IXOR = 4'b1010;
  parameter ISHL = 4'b1011;
  parameter ISHR = 4'b1100;
  parameter IINC = 4'b1110;
  parameter IDEC = 4'b1111;

  always @(posedge clk) begin
    if (reset) begin
      acc <= 0;
    end else
      case (op)
        // add a b = acc; sets c_flag/z_flag/s_flag
        IADD: acc <= { 1'b0, a } + { 1'b0, b };
        // sub a b = acc; sets c_flag/z_flag/s_flag
        ISUB: acc <= { 1'b1, a } - { 1'b0, b };
        // test a b; clears c_flag, sets z_flag/s_flag
        ITEST: acc <= a && b;
        // lor a b; clears c_flag, sets z_flag/s_flag
        ILOR: acc <= a || b;
        // not a; no effect on flags
        INOT: acc <= !a;
        // neg a; no effect on flags
        INEG: acc <= ~a;
        // and a b; clears c_flag, sets z_flag/s_flag
        IAND: acc <= a & b;
        // or a b; clears c_flag, sets z_flag/s_flag
        IOR: acc <= a | b;
        // xor a b; clears c_flag, sets z_flag/s_flag
        IXOR: acc <= a ^ b;
        // shl a; sets c_flag/z_flag/s_flag
        ISHL: acc <= a << 1;
        // shr a; sets c_flag/z_flag/s_flag
        ISHR: acc <= a >> 1;
        // inc a; sets c_flag/z_flag/s_flag
        IINC: acc <= { 1'b0, a } + { 1'b0, 32'b1 };
        // dec a; sets c_flag/z_flag/s_flag
        IDEC: acc <= { 1'b1, a } - { 1'b0, 32'b1 };
      endcase
  end
endmodule