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damageboy/POPCNTButNoBMI2.jitdump.txt

Created August 21, 2018 11:54
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POPCNTButNoBMI2.jitdump.txt
****** START compiling Program:POPCNTButNoBMI2(int):int (MethodHash=622404b0)
Generating code for Unix x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 7e 03 00 00 04 ldsfld 0x4000003
IL_0005 20 00 04 00 00 ldc.i4 0x400
IL_000a 02 ldarg.0
IL_000b 28 12 00 00 0a call 0xA000012
IL_0010 2a ret
Arg #0 passed in register(s) rdi
lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
*************** In compInitDebuggingInfo() for Program:POPCNTButNoBMI2(int):int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 011h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:POPCNTButNoBMI2(int):int
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [000..011)
IL Code Size,Instr 17, 5, Basic Block count 1, Local Variable Num,Ref count 2, 1 for method Program:POPCNTButNoBMI2(int):int
OPTIONS: opts.MinOpts() == false
Basic block list for 'Program:POPCNTButNoBMI2(int):int'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Program:POPCNTButNoBMI2(int):int
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program:POPCNTButNoBMI2(int):int'
[ 0] 0 (0x000) ldsfld 04000003
[ 1] 5 (0x005) ldc.i4 1024
[ 2] 10 (0x00a) ldarg.0
[ 3] 11 (0x00b) call 0A000012 (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT)
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
info.compCompHnd->canTailCall returned false for call [000004]
[000008] ------------ * STMT void (IL 0x000... ???)
[000004] I-C-G------- \--* CALL int GetNthBitOffset.POPCNTButNoBMI2 (exactContextHnd=0x00007FE9BCFC7599)
[000001] ----G------- arg0 +--* FIELD long _bits
[000002] ------------ arg1 +--* CNS_INT int 0x400
[000003] ------------ arg2 \--* LCL_VAR int V00 arg0
[ 1] 16 (0x010) ret
[000011] ------------ * STMT void (IL ???... ???)
[000010] --C--------- \--* RETURN int
[000009] --C--------- \--* RET_EXPR int (inl return from call [000004])
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** In fgInline()
Expanding INLINE_CANDIDATE in statement [000008] in BB01:
[000008] ------------ * STMT void (IL 0x000...0x010)
[000004] I-C-G------- \--* CALL int GetNthBitOffset.POPCNTButNoBMI2 (exactContextHnd=0x00007FE9BCFC7599)
[000001] ----G------- arg0 +--* FIELD long _bits
[000002] ------------ arg1 +--* CNS_INT int 0x400
[000003] ------------ arg2 \--* LCL_VAR int V00 arg0
Argument #0: has global refs
[000001] ----G------- * FIELD long _bits
Argument #1: is a constant
[000002] ------------ * CNS_INT int 0x400
Argument #2: is a local var
[000003] ------------ * LCL_VAR int V00 arg0
INLINER: inlineInfo.tokenLookupContextHandle for GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int set to 0x00007FE9BCFC7599:
Invoking compiler for the inlinee method GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int :
IL to import:
IL_0000 02 ldarg.0
IL_0001 0a stloc.0
IL_0002 04 ldarg.2
IL_0003 0b stloc.1
IL_0004 2b 12 br.s 18 (IL_0018)
IL_0006 04 ldarg.2
IL_0007 0b stloc.1
IL_0008 04 ldarg.2
IL_0009 06 ldloc.0
IL_000a 25 dup
IL_000b 1e ldc.i4.8
IL_000c 58 add
IL_000d 0a stloc.0
IL_000e 4c ldind.i8
IL_000f 28 0d 00 00 0a call 0xA00000D
IL_0014 69 conv.i4
IL_0015 59 sub
IL_0016 10 02 starg.s 0x2
IL_0018 04 ldarg.2
IL_0019 16 ldc.i4.0
IL_001a 30 ea bgt.s -22 (IL_0006)
IL_001c 06 ldloc.0
IL_001d 1e ldc.i4.8
IL_001e 59 sub
IL_001f 0c stloc.2
IL_0020 07 ldloc.1
IL_0021 08 ldloc.2
IL_0022 4b ldind.u4
IL_0023 28 11 00 00 0a call 0xA000011
IL_0028 59 sub
IL_0029 10 02 starg.s 0x2
IL_002b 04 ldarg.2
IL_002c 16 ldc.i4.0
IL_002d 31 06 ble.s 6 (IL_0035)
IL_002f 04 ldarg.2
IL_0030 0b stloc.1
IL_0031 08 ldloc.2
IL_0032 1a ldc.i4.4
IL_0033 58 add
IL_0034 0c stloc.2
IL_0035 08 ldloc.2
IL_0036 4b ldind.u4
IL_0037 0d stloc.3
IL_0038 08 ldloc.2
IL_0039 02 ldarg.0
IL_003a 59 sub
IL_003b 1a ldc.i4.4
IL_003c 5b div
IL_003d 6a conv.i8
IL_003e 1f 20 ldc.i4.s 0x20
IL_0040 6a conv.i8
IL_0041 5a mul
IL_0042 13 04 stloc.s 0x4
IL_0044 2b 1e br.s 30 (IL_0064)
IL_0046 09 ldloc.3
IL_0047 28 12 00 00 0a call 0xA000012
IL_004c 17 ldc.i4.1
IL_004d 58 add
IL_004e 13 05 stloc.s 0x5
IL_0050 11 04 ldloc.s 0x4
IL_0052 11 05 ldloc.s 0x5
IL_0054 6e conv.u8
IL_0055 58 add
IL_0056 13 04 stloc.s 0x4
IL_0058 07 ldloc.1
IL_0059 17 ldc.i4.1
IL_005a 59 sub
IL_005b 0b stloc.1
IL_005c 09 ldloc.3
IL_005d 11 05 ldloc.s 0x5
IL_005f 1f 1f ldc.i4.s 0x1F
IL_0061 5f and
IL_0062 64 shr.un
IL_0063 0d stloc.3
IL_0064 07 ldloc.1
IL_0065 16 ldc.i4.0
IL_0066 30 de bgt.s -34 (IL_0046)
IL_0068 11 04 ldloc.s 0x4
IL_006a 69 conv.i4
IL_006b 17 ldc.i4.1
IL_006c 59 sub
IL_006d 2a ret
INLINER impTokenLookupContextHandle for GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int is 0x00007FE9BCFC7599.
*************** In fgFindBasicBlocks() for GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int
Jump targets:
IL_0006
IL_0018
IL_0035
IL_0046
IL_0064
New Basic Block BB02 [0001] created.
BB02 [000..006)
New Basic Block BB03 [0002] created.
BB03 [006..018)
New Basic Block BB04 [0003] created.
BB04 [018..01C)
New Basic Block BB05 [0004] created.
BB05 [01C..02F)
New Basic Block BB06 [0005] created.
BB06 [02F..035)
New Basic Block BB07 [0006] created.
BB07 [035..046)
New Basic Block BB08 [0007] created.
BB08 [046..064)
New Basic Block BB09 [0008] created.
BB09 [064..068)
New Basic Block BB10 [0009] created.
BB10 [068..06E)
Basic block list for 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001] 1 1 [000..006)-> BB04 (always)
BB03 [0002] 1 1 [006..018) bwd
BB04 [0003] 2 1 [018..01C)-> BB03 ( cond ) bwd
BB05 [0004] 1 1 [01C..02F)-> BB07 ( cond )
BB06 [0005] 1 1 [02F..035)
BB07 [0006] 2 1 [035..046)-> BB09 (always)
BB08 [0007] 1 1 [046..064) bwd
BB09 [0008] 2 1 [064..068)-> BB08 ( cond ) bwd
BB10 [0009] 1 1 [068..06E) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int
impImportBlockPending for BB02
Importing BB02 (PC=000) of 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
[ 0] 0 (0x000) ldarg.0
lvaGrabTemp returning 2 (V02 tmp1) called for Inlining Arg.
[ 1] 1 (0x001) stloc.0
lvaGrabTemp returning 3 (V03 tmp2) (a long lifetime temp) called for Inline stloc first use temp.
[000016] ------------ * STMT void
[000013] ------------ | /--* LCL_VAR long V02 tmp1
[000015] -A---------- \--* ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
[ 0] 2 (0x002) ldarg.2
lvaGrabTemp returning 4 (V04 tmp3) called for Inlining Arg.
[ 1] 3 (0x003) stloc.1
lvaGrabTemp returning 5 (V05 tmp4) (a long lifetime temp) called for Inline stloc first use temp.
[000020] ------------ * STMT void
[000017] ------------ | /--* LCL_VAR int V04 tmp3
[000019] -A---------- \--* ASG int
[000018] D------N---- \--* LCL_VAR int V05 tmp4
[ 0] 4 (0x004) br.s
impImportBlockPending for BB04
Importing BB04 (PC=024) of 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
[ 0] 24 (0x018) ldarg.2
[ 1] 25 (0x019) ldc.i4.0 0
[ 2] 26 (0x01a) bgt.s
[000026] ------------ * STMT void
[000025] ------------ \--* JTRUE void
[000023] ------------ | /--* CNS_INT int 0
[000024] ------------ \--* GT int
[000022] ------------ \--* LCL_VAR int V04 tmp3
impImportBlockPending for BB05
impImportBlockPending for BB03
Importing BB03 (PC=006) of 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
[ 0] 6 (0x006) ldarg.2
[ 1] 7 (0x007) stloc.1
[000031] ------------ * STMT void
[000028] ------------ | /--* LCL_VAR int V04 tmp3
[000030] -A---------- \--* ASG int
[000029] D------N---- \--* LCL_VAR int V05 tmp4
[ 0] 8 (0x008) ldarg.2
[ 1] 9 (0x009) ldloc.0
[ 2] 10 (0x00a) dup
[ 3] 11 (0x00b) ldc.i4.8 8
[ 4] 12 (0x00c) add
[ 3] 13 (0x00d) stloc.0
lvaGrabTemp returning 6 (V06 tmp5) called for impSpillLclRefs.
[000041] ------------ * STMT void
[000033] ------------ | /--* LCL_VAR long V03 tmp2
[000040] -A---------- \--* ASG long
[000039] D------N---- \--* LCL_VAR long V06 tmp5
[000044] ------------ * STMT void
[000036] ------------ | /--* CAST long <- int
[000035] ------------ | | \--* CNS_INT int 8
[000037] ------------ | /--* ADD long
[000034] ------------ | | \--* LCL_VAR long V03 tmp2
[000043] -A---------- \--* ASG long
[000038] D------N---- \--* LCL_VAR long V03 tmp2
[ 2] 14 (0x00e) ldind.i8
[ 2] 15 (0x00f) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 2] 20 (0x014) conv.i4
[ 2] 21 (0x015) sub
[ 1] 22 (0x016) starg.s 2
[000052] ------------ * STMT void
[000047] ---XG------- | /--* CAST int <- long
[000046] ---XG------- | | \--* HWIntrinsic long PopCount
[000045] *--XG------- | | \--* IND long
[000042] ------------ | | \--* LCL_VAR long V06 tmp5
[000048] ---XG------- | /--* SUB int
[000032] ------------ | | \--* LCL_VAR int V04 tmp3
[000051] -A-XG------- \--* ASG int
[000050] D------N---- \--* LCL_VAR int V04 tmp3
impImportBlockPending for BB04
Importing BB05 (PC=028) of 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
[ 0] 28 (0x01c) ldloc.0
[ 1] 29 (0x01d) ldc.i4.8 8
[ 2] 30 (0x01e) sub
[ 1] 31 (0x01f) stloc.2
lvaGrabTemp returning 7 (V07 tmp6) (a long lifetime temp) called for Inline stloc first use temp.
[000060] ------------ * STMT void
[000056] ------------ | /--* CAST long <- int
[000055] ------------ | | \--* CNS_INT int 8
[000057] ------------ | /--* SUB long
[000054] ------------ | | \--* LCL_VAR long V03 tmp2
[000059] -A---------- \--* ASG long
[000058] D------N---- \--* LCL_VAR long V07 tmp6
[ 0] 32 (0x020) ldloc.1
[ 1] 33 (0x021) ldloc.2
[ 2] 34 (0x022) ldind.u4
[ 2] 35 (0x023) call 0A000011
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[ 2] 40 (0x028) sub
[ 1] 41 (0x029) starg.s 2
[000069] ------------ * STMT void
[000064] ---XG------- | /--* HWIntrinsic int PopCount
[000063] *--XG------- | | \--* IND int
[000062] ------------ | | \--* LCL_VAR long V07 tmp6
[000065] ---XG------- | /--* SUB int
[000061] ------------ | | \--* LCL_VAR int V05 tmp4
[000068] -A-XG------- \--* ASG int
[000067] D------N---- \--* LCL_VAR int V04 tmp3
[ 0] 43 (0x02b) ldarg.2
[ 1] 44 (0x02c) ldc.i4.0 0
[ 2] 45 (0x02d) ble.s
[000074] ------------ * STMT void
[000073] ------------ \--* JTRUE void
[000071] ------------ | /--* CNS_INT int 0
[000072] ------------ \--* LE int
[000070] ------------ \--* LCL_VAR int V04 tmp3
impImportBlockPending for BB06
impImportBlockPending for BB07
Importing BB07 (PC=053) of 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
[ 0] 53 (0x035) ldloc.2
[ 1] 54 (0x036) ldind.u4
[ 1] 55 (0x037) stloc.3
lvaGrabTemp returning 8 (V08 tmp7) (a long lifetime temp) called for Inline stloc first use temp.
[000080] ------------ * STMT void
[000077] *--XG------- | /--* IND int
[000076] ------------ | | \--* LCL_VAR long V07 tmp6
[000079] -A-XG------- \--* ASG int
[000078] D------N---- \--* LCL_VAR int V08 tmp7
[ 0] 56 (0x038) ldloc.2
[ 1] 57 (0x039) ldarg.0
[ 2] 58 (0x03a) sub
[ 1] 59 (0x03b) ldc.i4.4 4
[ 2] 60 (0x03c) div
[ 1] 61 (0x03d) conv.i8
[ 1] 62 (0x03e) ldc.i4.s 32
[ 2] 64 (0x040) conv.i8
[ 2] 65 (0x041) mul
[ 1] 66 (0x042) stloc.s 4
lvaGrabTemp returning 9 (V09 tmp8) (a long lifetime temp) called for Inline stloc first use temp.
[000092] ------------ * STMT void
[000088] ------------ | /--* CAST long <- int
[000087] ------------ | | \--* CNS_INT int 32
[000089] ---X-------- | /--* MUL long
[000085] ------------ | | | /--* CAST long <- int
[000084] ------------ | | | | \--* CNS_INT int 4
[000086] ---X-------- | | \--* DIV long
[000082] ------------ | | | /--* LCL_VAR long V02 tmp1
[000083] ------------ | | \--* SUB long
[000081] ------------ | | \--* LCL_VAR long V07 tmp6
[000091] -A-X-------- \--* ASG long
[000090] D------N---- \--* LCL_VAR long V09 tmp8
[ 0] 68 (0x044) br.s
impImportBlockPending for BB09
Importing BB09 (PC=100) of 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
[ 0] 100 (0x064) ldloc.1
[ 1] 101 (0x065) ldc.i4.0 0
[ 2] 102 (0x066) bgt.s
[000098] ------------ * STMT void
[000097] ------------ \--* JTRUE void
[000095] ------------ | /--* CNS_INT int 0
[000096] ------------ \--* GT int
[000094] ------------ \--* LCL_VAR int V05 tmp4
impImportBlockPending for BB10
impImportBlockPending for BB08
Importing BB08 (PC=070) of 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
[ 0] 70 (0x046) ldloc.3
[ 1] 71 (0x047) call 0A000012
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[ 1] 76 (0x04c) ldc.i4.1 1
[ 2] 77 (0x04d) add
[ 1] 78 (0x04e) stloc.s 5
lvaGrabTemp returning 10 (V10 tmp9) (a long lifetime temp) called for Inline stloc first use temp.
[000106] ------------ * STMT void
[000102] ------------ | /--* CNS_INT int 1
[000103] ------------ | /--* ADD int
[000101] ------------ | | \--* HWIntrinsic int TrailingZeroCount
[000100] ------------ | | \--* LCL_VAR int V08 tmp7
[000105] -A---------- \--* ASG int
[000104] D------N---- \--* LCL_VAR int V10 tmp9
[ 0] 80 (0x050) ldloc.s 4
[ 1] 82 (0x052) ldloc.s 5
[ 2] 84 (0x054) conv.u8
[ 2] 85 (0x055) add
[ 1] 86 (0x056) stloc.s 4
[000113] ------------ * STMT void
[000109] ---------U-- | /--* CAST long <- ulong <- uint
[000108] ------------ | | \--* LCL_VAR int V10 tmp9
[000110] ------------ | /--* ADD long
[000107] ------------ | | \--* LCL_VAR long V09 tmp8
[000112] -A---------- \--* ASG long
[000111] D------N---- \--* LCL_VAR long V09 tmp8
[ 0] 88 (0x058) ldloc.1
[ 1] 89 (0x059) ldc.i4.1 1
[ 2] 90 (0x05a) sub
[ 1] 91 (0x05b) stloc.1
[000119] ------------ * STMT void
[000115] ------------ | /--* CNS_INT int 1
[000116] ------------ | /--* SUB int
[000114] ------------ | | \--* LCL_VAR int V05 tmp4
[000118] -A---------- \--* ASG int
[000117] D------N---- \--* LCL_VAR int V05 tmp4
[ 0] 92 (0x05c) ldloc.3
[ 1] 93 (0x05d) ldloc.s 5
[ 2] 95 (0x05f) ldc.i4.s 31
[ 3] 97 (0x061) and
[ 2] 98 (0x062) shr.un
[ 1] 99 (0x063) stloc.3
[000127] ------------ * STMT void
[000122] ------------ | /--* CNS_INT int 31
[000123] ------------ | /--* AND int
[000121] ------------ | | \--* LCL_VAR int V10 tmp9
[000124] ------------ | /--* RSZ int
[000120] ------------ | | \--* LCL_VAR int V08 tmp7
[000126] -A---------- \--* ASG int
[000125] D------N---- \--* LCL_VAR int V08 tmp7
impImportBlockPending for BB09
Importing BB10 (PC=104) of 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
[ 0] 104 (0x068) ldloc.s 4
[ 1] 106 (0x06a) conv.i4
[ 1] 107 (0x06b) ldc.i4.1 1
[ 2] 108 (0x06c) sub
[ 1] 109 (0x06d) ret
Inlinee Return expression (before normalization) =>
[000131] ------------ /--* CNS_INT int 1
[000132] ------------ * SUB int
[000130] ------------ \--* CAST int <- long
[000129] ------------ \--* LCL_VAR long V09 tmp8
Inlinee Return expression (after normalization) =>
[000131] ------------ /--* CNS_INT int 1
[000132] ------------ * SUB int
[000130] ------------ \--* CAST int <- long
[000129] ------------ \--* LCL_VAR long V09 tmp8
Importing BB06 (PC=047) of 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
[ 0] 47 (0x02f) ldarg.2
[ 1] 48 (0x030) stloc.1
[000137] ------------ * STMT void
[000134] ------------ | /--* LCL_VAR int V04 tmp3
[000136] -A---------- \--* ASG int
[000135] D------N---- \--* LCL_VAR int V05 tmp4
[ 0] 49 (0x031) ldloc.2
[ 1] 50 (0x032) ldc.i4.4 4
[ 2] 51 (0x033) add
[ 1] 52 (0x034) stloc.2
[000144] ------------ * STMT void
[000140] ------------ | /--* CAST long <- int
[000139] ------------ | | \--* CNS_INT int 4
[000141] ------------ | /--* ADD long
[000138] ------------ | | \--* LCL_VAR long V07 tmp6
[000143] -A---------- \--* ASG long
[000142] D------N---- \--* LCL_VAR long V07 tmp6
impImportBlockPending for BB07
----------- Statements (and blocks) added due to the inlining of call [000004] -----------
Arguments setup:
[000147] ------------ * STMT void (IL 0x000... ???)
[000001] ----G------- | /--* FIELD long _bits
[000146] -A--G------- \--* ASG long
[000145] D------N---- \--* LCL_VAR long V02 tmp1
[000150] ------------ * STMT void (IL 0x000... ???)
[000003] ------------ | /--* LCL_VAR int V00 arg0
[000149] -A---------- \--* ASG int
[000148] D------N---- \--* LCL_VAR int V04 tmp3
Zero init inlinee locals:
[000154] ------------ * STMT void (IL 0x000... ???)
[000151] ------------ | /--* CNS_INT long 0
[000153] -A---------- \--* ASG long
[000152] D------N---- \--* LCL_VAR long V03 tmp2
[000158] ------------ * STMT void (IL 0x000... ???)
[000155] ------------ | /--* CNS_INT int 0
[000157] -A---------- \--* ASG int
[000156] D------N---- \--* LCL_VAR int V05 tmp4
[000162] ------------ * STMT void (IL 0x000... ???)
[000159] ------------ | /--* CNS_INT long 0
[000161] -A---------- \--* ASG long
[000160] D------N---- \--* LCL_VAR long V07 tmp6
[000166] ------------ * STMT void (IL 0x000... ???)
[000163] ------------ | /--* CNS_INT int 0
[000165] -A---------- \--* ASG int
[000164] D------N---- \--* LCL_VAR int V08 tmp7
[000170] ------------ * STMT void (IL 0x000... ???)
[000167] ------------ | /--* CNS_INT long 0
[000169] -A---------- \--* ASG long
[000168] D------N---- \--* LCL_VAR long V09 tmp8
[000174] ------------ * STMT void (IL 0x000... ???)
[000171] ------------ | /--* CNS_INT int 0
[000173] -A---------- \--* ASG int
[000172] D------N---- \--* LCL_VAR int V10 tmp9
Inlinee method body:New Basic Block BB11 [0010] created.
Convert bbJumpKind of BB10 to BBJ_NONE
fgInlineAppendStatements: no gc ref inline locals.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB02 [0001] 1 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 0.50 [000..001) i bwd
BB04 [0003] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB05 [0004] 1 0.50 [000..001)-> BB07 ( cond ) i
BB06 [0005] 1 0.50 [000..001) i
BB07 [0006] 2 0.50 [000..001)-> BB09 (always) i
BB08 [0007] 1 0.50 [000..001) i bwd
BB09 [0008] 2 0.50 [000..001)-> BB08 ( cond ) i bwd
BB10 [0009] 1 1 [000..001) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB02 [000..001) -> BB04 (always), preds={} succs={BB04}
***** BB02, stmt 1
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] ------------ | /--* LCL_VAR long V02 tmp1
[000015] -A---------- \--* ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 2
[000020] ------------ * STMT void (IL 0x000... ???)
[000017] ------------ | /--* LCL_VAR int V04 tmp3
[000019] -A---------- \--* ASG int
[000018] D------N---- \--* LCL_VAR int V05 tmp4
------------ BB03 [000..001), preds={} succs={BB04}
***** BB03, stmt 3
[000031] ------------ * STMT void (IL 0x000... ???)
[000028] ------------ | /--* LCL_VAR int V04 tmp3
[000030] -A---------- \--* ASG int
[000029] D------N---- \--* LCL_VAR int V05 tmp4
***** BB03, stmt 4
[000041] ------------ * STMT void (IL 0x000... ???)
[000033] ------------ | /--* LCL_VAR long V03 tmp2
[000040] -A---------- \--* ASG long
[000039] D------N---- \--* LCL_VAR long V06 tmp5
***** BB03, stmt 5
[000044] ------------ * STMT void (IL 0x000... ???)
[000036] ------------ | /--* CAST long <- int
[000035] ------------ | | \--* CNS_INT int 8
[000037] ------------ | /--* ADD long
[000034] ------------ | | \--* LCL_VAR long V03 tmp2
[000043] -A---------- \--* ASG long
[000038] D------N---- \--* LCL_VAR long V03 tmp2
***** BB03, stmt 6
[000052] ------------ * STMT void (IL 0x000... ???)
[000047] ---XG------- | /--* CAST int <- long
[000046] ---XG------- | | \--* HWIntrinsic long PopCount
[000045] *--XG------- | | \--* IND long
[000042] ------------ | | \--* LCL_VAR long V06 tmp5
[000048] ---XG------- | /--* SUB int
[000032] ------------ | | \--* LCL_VAR int V04 tmp3
[000051] -A-XG------- \--* ASG int
[000050] D------N---- \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001) -> BB03 (cond), preds={} succs={BB05,BB03}
***** BB04, stmt 7
[000026] ------------ * STMT void (IL 0x000... ???)
[000025] ------------ \--* JTRUE void
[000023] ------------ | /--* CNS_INT int 0
[000024] ------------ \--* GT int
[000022] ------------ \--* LCL_VAR int V04 tmp3
------------ BB05 [000..001) -> BB07 (cond), preds={} succs={BB06,BB07}
***** BB05, stmt 8
[000060] ------------ * STMT void (IL 0x000... ???)
[000056] ------------ | /--* CAST long <- int
[000055] ------------ | | \--* CNS_INT int 8
[000057] ------------ | /--* SUB long
[000054] ------------ | | \--* LCL_VAR long V03 tmp2
[000059] -A---------- \--* ASG long
[000058] D------N---- \--* LCL_VAR long V07 tmp6
***** BB05, stmt 9
[000069] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG------- | /--* HWIntrinsic int PopCount
[000063] *--XG------- | | \--* IND int
[000062] ------------ | | \--* LCL_VAR long V07 tmp6
[000065] ---XG------- | /--* SUB int
[000061] ------------ | | \--* LCL_VAR int V05 tmp4
[000068] -A-XG------- \--* ASG int
[000067] D------N---- \--* LCL_VAR int V04 tmp3
***** BB05, stmt 10
[000074] ------------ * STMT void (IL 0x000... ???)
[000073] ------------ \--* JTRUE void
[000071] ------------ | /--* CNS_INT int 0
[000072] ------------ \--* LE int
[000070] ------------ \--* LCL_VAR int V04 tmp3
------------ BB06 [000..001), preds={} succs={BB07}
***** BB06, stmt 11
[000137] ------------ * STMT void (IL 0x000... ???)
[000134] ------------ | /--* LCL_VAR int V04 tmp3
[000136] -A---------- \--* ASG int
[000135] D------N---- \--* LCL_VAR int V05 tmp4
***** BB06, stmt 12
[000144] ------------ * STMT void (IL 0x000... ???)
[000140] ------------ | /--* CAST long <- int
[000139] ------------ | | \--* CNS_INT int 4
[000141] ------------ | /--* ADD long
[000138] ------------ | | \--* LCL_VAR long V07 tmp6
[000143] -A---------- \--* ASG long
[000142] D------N---- \--* LCL_VAR long V07 tmp6
------------ BB07 [000..001) -> BB09 (always), preds={} succs={BB09}
***** BB07, stmt 13
[000080] ------------ * STMT void (IL 0x000... ???)
[000077] *--XG------- | /--* IND int
[000076] ------------ | | \--* LCL_VAR long V07 tmp6
[000079] -A-XG------- \--* ASG int
[000078] D------N---- \--* LCL_VAR int V08 tmp7
***** BB07, stmt 14
[000092] ------------ * STMT void (IL 0x000... ???)
[000088] ------------ | /--* CAST long <- int
[000087] ------------ | | \--* CNS_INT int 32
[000089] ---X-------- | /--* MUL long
[000085] ------------ | | | /--* CAST long <- int
[000084] ------------ | | | | \--* CNS_INT int 4
[000086] ---X-------- | | \--* DIV long
[000082] ------------ | | | /--* LCL_VAR long V02 tmp1
[000083] ------------ | | \--* SUB long
[000081] ------------ | | \--* LCL_VAR long V07 tmp6
[000091] -A-X-------- \--* ASG long
[000090] D------N---- \--* LCL_VAR long V09 tmp8
------------ BB08 [000..001), preds={} succs={BB09}
***** BB08, stmt 15
[000106] ------------ * STMT void (IL 0x000... ???)
[000102] ------------ | /--* CNS_INT int 1
[000103] ------------ | /--* ADD int
[000101] ------------ | | \--* HWIntrinsic int TrailingZeroCount
[000100] ------------ | | \--* LCL_VAR int V08 tmp7
[000105] -A---------- \--* ASG int
[000104] D------N---- \--* LCL_VAR int V10 tmp9
***** BB08, stmt 16
[000113] ------------ * STMT void (IL 0x000... ???)
[000109] ---------U-- | /--* CAST long <- ulong <- uint
[000108] ------------ | | \--* LCL_VAR int V10 tmp9
[000110] ------------ | /--* ADD long
[000107] ------------ | | \--* LCL_VAR long V09 tmp8
[000112] -A---------- \--* ASG long
[000111] D------N---- \--* LCL_VAR long V09 tmp8
***** BB08, stmt 17
[000119] ------------ * STMT void (IL 0x000... ???)
[000115] ------------ | /--* CNS_INT int 1
[000116] ------------ | /--* SUB int
[000114] ------------ | | \--* LCL_VAR int V05 tmp4
[000118] -A---------- \--* ASG int
[000117] D------N---- \--* LCL_VAR int V05 tmp4
***** BB08, stmt 18
[000127] ------------ * STMT void (IL 0x000... ???)
[000122] ------------ | /--* CNS_INT int 31
[000123] ------------ | /--* AND int
[000121] ------------ | | \--* LCL_VAR int V10 tmp9
[000124] ------------ | /--* RSZ int
[000120] ------------ | | \--* LCL_VAR int V08 tmp7
[000126] -A---------- \--* ASG int
[000125] D------N---- \--* LCL_VAR int V08 tmp7
------------ BB09 [000..001) -> BB08 (cond), preds={} succs={BB10,BB08}
***** BB09, stmt 19
[000098] ------------ * STMT void (IL 0x000... ???)
[000097] ------------ \--* JTRUE void
[000095] ------------ | /--* CNS_INT int 0
[000096] ------------ \--* GT int
[000094] ------------ \--* LCL_VAR int V05 tmp4
------------ BB10 [000..001), preds={} succs={BB11}
-------------------------------------------------------------------------------------------------------------------
Return expression for call at [000004] is
[000131] ------------ /--* CNS_INT int 1
[000132] ------------ * SUB int
[000130] ------------ \--* CAST int <- long
[000129] ------------ \--* LCL_VAR long V09 tmp8
Successfully inlined GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int (110 IL bytes) (depth 1) [aggressive inline attribute]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Program:POPCNTButNoBMI2(int):int' calling 'GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int'
INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute'
Replacing the return expression placeholder [000009] with [000132]
[000009] --C--------- * RET_EXPR int (inl return from call [000132])
Inserting the inline return expression
[000131] ------------ /--* CNS_INT int 1
[000132] ------------ * SUB int
[000130] ------------ \--* CAST int <- long
[000129] ------------ \--* LCL_VAR long V09 tmp8
*************** After fgInline()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 0.50 [000..001) i bwd
BB04 [0003] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB05 [0004] 1 0.50 [000..001)-> BB07 ( cond ) i
BB06 [0005] 1 0.50 [000..001) i
BB07 [0006] 2 0.50 [000..001)-> BB09 (always) i
BB08 [0007] 1 0.50 [000..001) i bwd
BB09 [0008] 2 0.50 [000..001)-> BB08 ( cond ) i bwd
BB10 [0009] 1 1 [000..001) i
BB11 [0010] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011), preds={} succs={BB02}
***** BB01, stmt 1
[000147] ------------ * STMT void (IL 0x000... ???)
[000001] ----G------- | /--* FIELD long _bits
[000146] -A--G------- \--* ASG long
[000145] D------N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000150] ------------ * STMT void (IL 0x000... ???)
[000003] ------------ | /--* LCL_VAR int V00 arg0
[000149] -A---------- \--* ASG int
[000148] D------N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000154] ------------ * STMT void (IL 0x000... ???)
[000151] ------------ | /--* CNS_INT long 0
[000153] -A---------- \--* ASG long
[000152] D------N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000158] ------------ * STMT void (IL 0x000... ???)
[000155] ------------ | /--* CNS_INT int 0
[000157] -A---------- \--* ASG int
[000156] D------N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000162] ------------ * STMT void (IL 0x000... ???)
[000159] ------------ | /--* CNS_INT long 0
[000161] -A---------- \--* ASG long
[000160] D------N---- \--* LCL_VAR long V07 tmp6
***** BB01, stmt 6
[000166] ------------ * STMT void (IL 0x000... ???)
[000163] ------------ | /--* CNS_INT int 0
[000165] -A---------- \--* ASG int
[000164] D------N---- \--* LCL_VAR int V08 tmp7
***** BB01, stmt 7
[000170] ------------ * STMT void (IL 0x000... ???)
[000167] ------------ | /--* CNS_INT long 0
[000169] -A---------- \--* ASG long
[000168] D------N---- \--* LCL_VAR long V09 tmp8
***** BB01, stmt 8
[000174] ------------ * STMT void (IL 0x000... ???)
[000171] ------------ | /--* CNS_INT int 0
[000173] -A---------- \--* ASG int
[000172] D------N---- \--* LCL_VAR int V10 tmp9
------------ BB02 [000..001) -> BB04 (always), preds={} succs={BB04}
***** BB02, stmt 9
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] ------------ | /--* LCL_VAR long V02 tmp1
[000015] -A---------- \--* ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 10
[000020] ------------ * STMT void (IL 0x000... ???)
[000017] ------------ | /--* LCL_VAR int V04 tmp3
[000019] -A---------- \--* ASG int
[000018] D------N---- \--* LCL_VAR int V05 tmp4
------------ BB03 [000..001), preds={} succs={BB04}
***** BB03, stmt 11
[000031] ------------ * STMT void (IL 0x000... ???)
[000028] ------------ | /--* LCL_VAR int V04 tmp3
[000030] -A---------- \--* ASG int
[000029] D------N---- \--* LCL_VAR int V05 tmp4
***** BB03, stmt 12
[000041] ------------ * STMT void (IL 0x000... ???)
[000033] ------------ | /--* LCL_VAR long V03 tmp2
[000040] -A---------- \--* ASG long
[000039] D------N---- \--* LCL_VAR long V06 tmp5
***** BB03, stmt 13
[000044] ------------ * STMT void (IL 0x000... ???)
[000036] ------------ | /--* CAST long <- int
[000035] ------------ | | \--* CNS_INT int 8
[000037] ------------ | /--* ADD long
[000034] ------------ | | \--* LCL_VAR long V03 tmp2
[000043] -A---------- \--* ASG long
[000038] D------N---- \--* LCL_VAR long V03 tmp2
***** BB03, stmt 14
[000052] ------------ * STMT void (IL 0x000... ???)
[000047] ---XG------- | /--* CAST int <- long
[000046] ---XG------- | | \--* HWIntrinsic long PopCount
[000045] *--XG------- | | \--* IND long
[000042] ------------ | | \--* LCL_VAR long V06 tmp5
[000048] ---XG------- | /--* SUB int
[000032] ------------ | | \--* LCL_VAR int V04 tmp3
[000051] -A-XG------- \--* ASG int
[000050] D------N---- \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001) -> BB03 (cond), preds={} succs={BB05,BB03}
***** BB04, stmt 15
[000026] ------------ * STMT void (IL 0x000... ???)
[000025] ------------ \--* JTRUE void
[000023] ------------ | /--* CNS_INT int 0
[000024] ------------ \--* GT int
[000022] ------------ \--* LCL_VAR int V04 tmp3
------------ BB05 [000..001) -> BB07 (cond), preds={} succs={BB06,BB07}
***** BB05, stmt 16
[000060] ------------ * STMT void (IL 0x000... ???)
[000056] ------------ | /--* CAST long <- int
[000055] ------------ | | \--* CNS_INT int 8
[000057] ------------ | /--* SUB long
[000054] ------------ | | \--* LCL_VAR long V03 tmp2
[000059] -A---------- \--* ASG long
[000058] D------N---- \--* LCL_VAR long V07 tmp6
***** BB05, stmt 17
[000069] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG------- | /--* HWIntrinsic int PopCount
[000063] *--XG------- | | \--* IND int
[000062] ------------ | | \--* LCL_VAR long V07 tmp6
[000065] ---XG------- | /--* SUB int
[000061] ------------ | | \--* LCL_VAR int V05 tmp4
[000068] -A-XG------- \--* ASG int
[000067] D------N---- \--* LCL_VAR int V04 tmp3
***** BB05, stmt 18
[000074] ------------ * STMT void (IL 0x000... ???)
[000073] ------------ \--* JTRUE void
[000071] ------------ | /--* CNS_INT int 0
[000072] ------------ \--* LE int
[000070] ------------ \--* LCL_VAR int V04 tmp3
------------ BB06 [000..001), preds={} succs={BB07}
***** BB06, stmt 19
[000137] ------------ * STMT void (IL 0x000... ???)
[000134] ------------ | /--* LCL_VAR int V04 tmp3
[000136] -A---------- \--* ASG int
[000135] D------N---- \--* LCL_VAR int V05 tmp4
***** BB06, stmt 20
[000144] ------------ * STMT void (IL 0x000... ???)
[000140] ------------ | /--* CAST long <- int
[000139] ------------ | | \--* CNS_INT int 4
[000141] ------------ | /--* ADD long
[000138] ------------ | | \--* LCL_VAR long V07 tmp6
[000143] -A---------- \--* ASG long
[000142] D------N---- \--* LCL_VAR long V07 tmp6
------------ BB07 [000..001) -> BB09 (always), preds={} succs={BB09}
***** BB07, stmt 21
[000080] ------------ * STMT void (IL 0x000... ???)
[000077] *--XG------- | /--* IND int
[000076] ------------ | | \--* LCL_VAR long V07 tmp6
[000079] -A-XG------- \--* ASG int
[000078] D------N---- \--* LCL_VAR int V08 tmp7
***** BB07, stmt 22
[000092] ------------ * STMT void (IL 0x000... ???)
[000088] ------------ | /--* CAST long <- int
[000087] ------------ | | \--* CNS_INT int 32
[000089] ---X-------- | /--* MUL long
[000085] ------------ | | | /--* CAST long <- int
[000084] ------------ | | | | \--* CNS_INT int 4
[000086] ---X-------- | | \--* DIV long
[000082] ------------ | | | /--* LCL_VAR long V02 tmp1
[000083] ------------ | | \--* SUB long
[000081] ------------ | | \--* LCL_VAR long V07 tmp6
[000091] -A-X-------- \--* ASG long
[000090] D------N---- \--* LCL_VAR long V09 tmp8
------------ BB08 [000..001), preds={} succs={BB09}
***** BB08, stmt 23
[000106] ------------ * STMT void (IL 0x000... ???)
[000102] ------------ | /--* CNS_INT int 1
[000103] ------------ | /--* ADD int
[000101] ------------ | | \--* HWIntrinsic int TrailingZeroCount
[000100] ------------ | | \--* LCL_VAR int V08 tmp7
[000105] -A---------- \--* ASG int
[000104] D------N---- \--* LCL_VAR int V10 tmp9
***** BB08, stmt 24
[000113] ------------ * STMT void (IL 0x000... ???)
[000109] ---------U-- | /--* CAST long <- ulong <- uint
[000108] ------------ | | \--* LCL_VAR int V10 tmp9
[000110] ------------ | /--* ADD long
[000107] ------------ | | \--* LCL_VAR long V09 tmp8
[000112] -A---------- \--* ASG long
[000111] D------N---- \--* LCL_VAR long V09 tmp8
***** BB08, stmt 25
[000119] ------------ * STMT void (IL 0x000... ???)
[000115] ------------ | /--* CNS_INT int 1
[000116] ------------ | /--* SUB int
[000114] ------------ | | \--* LCL_VAR int V05 tmp4
[000118] -A---------- \--* ASG int
[000117] D------N---- \--* LCL_VAR int V05 tmp4
***** BB08, stmt 26
[000127] ------------ * STMT void (IL 0x000... ???)
[000122] ------------ | /--* CNS_INT int 31
[000123] ------------ | /--* AND int
[000121] ------------ | | \--* LCL_VAR int V10 tmp9
[000124] ------------ | /--* RSZ int
[000120] ------------ | | \--* LCL_VAR int V08 tmp7
[000126] -A---------- \--* ASG int
[000125] D------N---- \--* LCL_VAR int V08 tmp7
------------ BB09 [000..001) -> BB08 (cond), preds={} succs={BB10,BB08}
***** BB09, stmt 27
[000098] ------------ * STMT void (IL 0x000... ???)
[000097] ------------ \--* JTRUE void
[000095] ------------ | /--* CNS_INT int 0
[000096] ------------ \--* GT int
[000094] ------------ \--* LCL_VAR int V05 tmp4
------------ BB10 [000..001), preds={} succs={BB11}
------------ BB11 [???..???) (return), preds={} succs={}
***** BB11, stmt 28
[000011] ------------ * STMT void (IL ???... ???)
[000010] --C--------- \--* RETURN int
[000131] ------------ | /--* CNS_INT int 1
[000132] ------------ \--* SUB int
[000130] ------------ \--* CAST int <- long
[000129] ------------ \--* LCL_VAR long V09 tmp8
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 06000005 Program:POPCNTButNoBMI2(int):int
[1 IL=0011 TR=000004 0600000A] [aggressive inline attribute] GetNthBitOffset:POPCNTButNoBMI2(long,int,int):int
Budget: initialTime=111, finalTime=317, initialBudget=1110, currentBudget=1316
Budget: increased by 206 because of force inlines
Budget: initialSize=518, finalSize=518
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 0.50 [000..001) i bwd
BB04 [0003] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB05 [0004] 1 0.50 [000..001)-> BB07 ( cond ) i
BB06 [0005] 1 0.50 [000..001) i
BB07 [0006] 2 0.50 [000..001)-> BB09 (always) i
BB08 [0007] 1 0.50 [000..001) i bwd
BB09 [0008] 2 0.50 [000..001)-> BB08 ( cond ) i bwd
BB10 [0009] 1 1 [000..001) i
BB11 [0010] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
; V02 tmp1 long
; V03 tmp2 long
; V04 tmp3 int
; V05 tmp4 int
; V06 tmp5 long
; V07 tmp6 long
; V08 tmp7 int
; V09 tmp8 long
; V10 tmp9 int
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
; V02 tmp1 long
; V03 tmp2 long
; V04 tmp3 int
; V05 tmp4 int
; V06 tmp5 long
; V07 tmp6 long
; V08 tmp7 int
; V09 tmp8 long
; V10 tmp9 int
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'Program:POPCNTButNoBMI2(int):int'
fgMorphTree BB01, stmt 1 (before)
[000001] ----G------- /--* FIELD long _bits
[000146] -A--G------- * ASG long
[000145] D------N---- \--* LCL_VAR long V02 tmp1
fgMorphTree BB01, stmt 1 (after)
[000001] x---G+------ /--* IND long
[000176] -----+------ | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits]
[000146] -A--G+------ * ASG long
[000145] D----+-N---- \--* LCL_VAR long V02 tmp1
fgMorphTree BB01, stmt 2 (before)
[000003] ------------ /--* LCL_VAR int V00 arg0
[000149] -A---------- * ASG int
[000148] D------N---- \--* LCL_VAR int V04 tmp3
GenTreeNode creates assertion:
[000149] -A---------- * ASG int
In BB01 New Local Copy Assertion: V04 == V00 index=#01, mask=0000000000000001
fgMorphTree BB01, stmt 3 (before)
[000151] ------------ /--* CNS_INT long 0
[000153] -A---------- * ASG long
[000152] D------N---- \--* LCL_VAR long V03 tmp2
GenTreeNode creates assertion:
[000153] -A---------- * ASG long
In BB01 New Local Constant Assertion: V03 == 0 index=#02, mask=0000000000000002
fgMorphTree BB01, stmt 4 (before)
[000155] ------------ /--* CNS_INT int 0
[000157] -A---------- * ASG int
[000156] D------N---- \--* LCL_VAR int V05 tmp4
GenTreeNode creates assertion:
[000157] -A---------- * ASG int
In BB01 New Local Constant Assertion: V05 == 0 index=#03, mask=0000000000000004
fgMorphTree BB01, stmt 5 (before)
[000159] ------------ /--* CNS_INT long 0
[000161] -A---------- * ASG long
[000160] D------N---- \--* LCL_VAR long V07 tmp6
GenTreeNode creates assertion:
[000161] -A---------- * ASG long
In BB01 New Local Constant Assertion: V07 == 0 index=#04, mask=0000000000000008
fgMorphTree BB01, stmt 6 (before)
[000163] ------------ /--* CNS_INT int 0
[000165] -A---------- * ASG int
[000164] D------N---- \--* LCL_VAR int V08 tmp7
GenTreeNode creates assertion:
[000165] -A---------- * ASG int
In BB01 New Local Constant Assertion: V08 == 0 index=#05, mask=0000000000000010
fgMorphTree BB01, stmt 7 (before)
[000167] ------------ /--* CNS_INT long 0
[000169] -A---------- * ASG long
[000168] D------N---- \--* LCL_VAR long V09 tmp8
GenTreeNode creates assertion:
[000169] -A---------- * ASG long
In BB01 New Local Constant Assertion: V09 == 0 index=#06, mask=0000000000000020
fgMorphTree BB01, stmt 8 (before)
[000171] ------------ /--* CNS_INT int 0
[000173] -A---------- * ASG int
[000172] D------N---- \--* LCL_VAR int V10 tmp9
GenTreeNode creates assertion:
[000173] -A---------- * ASG int
In BB01 New Local Constant Assertion: V10 == 0 index=#07, mask=0000000000000040
Morphing BB02 of 'Program:POPCNTButNoBMI2(int):int'
fgMorphTree BB02, stmt 9 (before)
[000013] ------------ /--* LCL_VAR long V02 tmp1
[000015] -A---------- * ASG long
[000014] D------N---- \--* LCL_VAR long V03 tmp2
GenTreeNode creates assertion:
[000015] -A---------- * ASG long
In BB02 New Local Copy Assertion: V03 == V02 index=#01, mask=0000000000000001
fgMorphTree BB02, stmt 10 (before)
[000017] ------------ /--* LCL_VAR int V04 tmp3
[000019] -A---------- * ASG int
[000018] D------N---- \--* LCL_VAR int V05 tmp4
GenTreeNode creates assertion:
[000019] -A---------- * ASG int
In BB02 New Local Copy Assertion: V05 == V04 index=#02, mask=0000000000000002
Morphing BB03 of 'Program:POPCNTButNoBMI2(int):int'
fgMorphTree BB03, stmt 11 (before)
[000028] ------------ /--* LCL_VAR int V04 tmp3
[000030] -A---------- * ASG int
[000029] D------N---- \--* LCL_VAR int V05 tmp4
GenTreeNode creates assertion:
[000030] -A---------- * ASG int
In BB03 New Local Copy Assertion: V05 == V04 index=#01, mask=0000000000000001
fgMorphTree BB03, stmt 12 (before)
[000033] ------------ /--* LCL_VAR long V03 tmp2
[000040] -A---------- * ASG long
[000039] D------N---- \--* LCL_VAR long V06 tmp5
GenTreeNode creates assertion:
[000040] -A---------- * ASG long
In BB03 New Local Copy Assertion: V06 == V03 index=#02, mask=0000000000000002
fgMorphTree BB03, stmt 13 (before)
[000036] ------------ /--* CAST long <- int
[000035] ------------ | \--* CNS_INT int 8
[000037] ------------ /--* ADD long
[000034] ------------ | \--* LCL_VAR long V03 tmp2
[000043] -A---------- * ASG long
[000038] D------N---- \--* LCL_VAR long V03 tmp2
Folding long operator with constant nodes into a constant:
[000036] ------------ * CAST long <- int
[000035] -----+------ \--* CNS_INT int 8
Bashed to long constant:
[000036] ------------ * CNS_INT long 8
The assignment [000043] using V06 removes: Copy Assertion: V06 == V03
fgMorphTree BB03, stmt 13 (after)
[000036] -----+------ /--* CNS_INT long 8
[000037] -----+------ /--* ADD long
[000034] -----+------ | \--* LCL_VAR long V03 tmp2
[000043] -A---+------ * ASG long
[000038] D----+-N---- \--* LCL_VAR long V03 tmp2
fgMorphTree BB03, stmt 14 (before)
[000047] ---XG------- /--* CAST int <- long
[000046] ---XG------- | \--* HWIntrinsic long PopCount
[000045] *--XG------- | \--* IND long
[000042] ------------ | \--* LCL_VAR long V06 tmp5
[000048] ---XG------- /--* SUB int
[000032] ------------ | \--* LCL_VAR int V04 tmp3
[000051] -A-XG------- * ASG int
[000050] D------N---- \--* LCL_VAR int V04 tmp3
The assignment [000051] using V05 removes: Copy Assertion: V05 == V04
Morphing BB04 of 'Program:POPCNTButNoBMI2(int):int'
fgMorphTree BB04, stmt 15 (before)
[000025] ------------ * JTRUE void
[000023] ------------ | /--* CNS_INT int 0
[000024] ------------ \--* GT int
[000022] ------------ \--* LCL_VAR int V04 tmp3
Morphing BB05 of 'Program:POPCNTButNoBMI2(int):int'
fgMorphTree BB05, stmt 16 (before)
[000056] ------------ /--* CAST long <- int
[000055] ------------ | \--* CNS_INT int 8
[000057] ------------ /--* SUB long
[000054] ------------ | \--* LCL_VAR long V03 tmp2
[000059] -A---------- * ASG long
[000058] D------N---- \--* LCL_VAR long V07 tmp6
Folding long operator with constant nodes into a constant:
[000056] ------------ * CAST long <- int
[000055] -----+------ \--* CNS_INT int 8
Bashed to long constant:
[000056] ------------ * CNS_INT long 8
fgMorphTree BB05, stmt 16 (after)
[000056] -----+------ /--* CNS_INT long -8
[000057] -----+------ /--* ADD long
[000054] -----+------ | \--* LCL_VAR long V03 tmp2
[000059] -A---+------ * ASG long
[000058] D----+-N---- \--* LCL_VAR long V07 tmp6
fgMorphTree BB05, stmt 17 (before)
[000064] ---XG------- /--* HWIntrinsic int PopCount
[000063] *--XG------- | \--* IND int
[000062] ------------ | \--* LCL_VAR long V07 tmp6
[000065] ---XG------- /--* SUB int
[000061] ------------ | \--* LCL_VAR int V05 tmp4
[000068] -A-XG------- * ASG int
[000067] D------N---- \--* LCL_VAR int V04 tmp3
fgMorphTree BB05, stmt 18 (before)
[000073] ------------ * JTRUE void
[000071] ------------ | /--* CNS_INT int 0
[000072] ------------ \--* LE int
[000070] ------------ \--* LCL_VAR int V04 tmp3
Morphing BB06 of 'Program:POPCNTButNoBMI2(int):int'
fgMorphTree BB06, stmt 19 (before)
[000134] ------------ /--* LCL_VAR int V04 tmp3
[000136] -A---------- * ASG int
[000135] D------N---- \--* LCL_VAR int V05 tmp4
GenTreeNode creates assertion:
[000136] -A---------- * ASG int
In BB06 New Local Copy Assertion: V05 == V04 index=#01, mask=0000000000000001
fgMorphTree BB06, stmt 20 (before)
[000140] ------------ /--* CAST long <- int
[000139] ------------ | \--* CNS_INT int 4
[000141] ------------ /--* ADD long
[000138] ------------ | \--* LCL_VAR long V07 tmp6
[000143] -A---------- * ASG long
[000142] D------N---- \--* LCL_VAR long V07 tmp6
Folding long operator with constant nodes into a constant:
[000140] ------------ * CAST long <- int
[000139] -----+------ \--* CNS_INT int 4
Bashed to long constant:
[000140] ------------ * CNS_INT long 4
fgMorphTree BB06, stmt 20 (after)
[000140] -----+------ /--* CNS_INT long 4
[000141] -----+------ /--* ADD long
[000138] -----+------ | \--* LCL_VAR long V07 tmp6
[000143] -A---+------ * ASG long
[000142] D----+-N---- \--* LCL_VAR long V07 tmp6
Morphing BB07 of 'Program:POPCNTButNoBMI2(int):int'
fgMorphTree BB07, stmt 21 (before)
[000077] *--XG------- /--* IND int
[000076] ------------ | \--* LCL_VAR long V07 tmp6
[000079] -A-XG------- * ASG int
[000078] D------N---- \--* LCL_VAR int V08 tmp7
GenTreeNode creates assertion:
[000079] -A-XG------- * ASG int
In BB07 New Local Subrange Assertion: V08 in [-2147483648..2147483647] index=#01, mask=0000000000000001
fgMorphTree BB07, stmt 22 (before)
[000088] ------------ /--* CAST long <- int
[000087] ------------ | \--* CNS_INT int 32
[000089] ---X-------- /--* MUL long
[000085] ------------ | | /--* CAST long <- int
[000084] ------------ | | | \--* CNS_INT int 4
[000086] ---X-------- | \--* DIV long
[000082] ------------ | | /--* LCL_VAR long V02 tmp1
[000083] ------------ | \--* SUB long
[000081] ------------ | \--* LCL_VAR long V07 tmp6
[000091] -A-X-------- * ASG long
[000090] D------N---- \--* LCL_VAR long V09 tmp8
Folding long operator with constant nodes into a constant:
[000085] ------------ * CAST long <- int
[000084] ------------ \--* CNS_INT int 4
Bashed to long constant:
[000085] ------------ * CNS_INT long 4
Folding long operator with constant nodes into a constant:
[000088] ------------ * CAST long <- int
[000087] -----+------ \--* CNS_INT int 32
Bashed to long constant:
[000088] ------------ * CNS_INT long 32
fgMorphTree BB07, stmt 22 (after)
[000088] -----+------ /--* CNS_INT long 5
[000089] -----+------ /--* LSH long
[000085] -----+------ | | /--* CNS_INT long 4
[000086] -----+------ | \--* DIV long
[000082] -----+------ | | /--* LCL_VAR long V02 tmp1
[000083] -----+------ | \--* SUB long
[000081] -----+------ | \--* LCL_VAR long V07 tmp6
[000091] -A---+------ * ASG long
[000090] D----+-N---- \--* LCL_VAR long V09 tmp8
Morphing BB08 of 'Program:POPCNTButNoBMI2(int):int'
fgMorphTree BB08, stmt 23 (before)
[000102] ------------ /--* CNS_INT int 1
[000103] ------------ /--* ADD int
[000101] ------------ | \--* HWIntrinsic int TrailingZeroCount
[000100] ------------ | \--* LCL_VAR int V08 tmp7
[000105] -A---------- * ASG int
[000104] D------N---- \--* LCL_VAR int V10 tmp9
fgMorphTree BB08, stmt 24 (before)
[000109] ---------U-- /--* CAST long <- ulong <- uint
[000108] ------------ | \--* LCL_VAR int V10 tmp9
[000110] ------------ /--* ADD long
[000107] ------------ | \--* LCL_VAR long V09 tmp8
[000112] -A---------- * ASG long
[000111] D------N---- \--* LCL_VAR long V09 tmp8
fgMorphTree BB08, stmt 25 (before)
[000115] ------------ /--* CNS_INT int 1
[000116] ------------ /--* SUB int
[000114] ------------ | \--* LCL_VAR int V05 tmp4
[000118] -A---------- * ASG int
[000117] D------N---- \--* LCL_VAR int V05 tmp4
fgMorphTree BB08, stmt 25 (after)
[000115] -----+------ /--* CNS_INT int -1
[000116] -----+------ /--* ADD int
[000114] -----+------ | \--* LCL_VAR int V05 tmp4
[000118] -A---+------ * ASG int
[000117] D----+-N---- \--* LCL_VAR int V05 tmp4
fgMorphTree BB08, stmt 26 (before)
[000122] ------------ /--* CNS_INT int 31
[000123] ------------ /--* AND int
[000121] ------------ | \--* LCL_VAR int V10 tmp9
[000124] ------------ /--* RSZ int
[000120] ------------ | \--* LCL_VAR int V08 tmp7
[000126] -A---------- * ASG int
[000125] D------N---- \--* LCL_VAR int V08 tmp7
Morphing BB09 of 'Program:POPCNTButNoBMI2(int):int'
fgMorphTree BB09, stmt 27 (before)
[000097] ------------ * JTRUE void
[000095] ------------ | /--* CNS_INT int 0
[000096] ------------ \--* GT int
[000094] ------------ \--* LCL_VAR int V05 tmp4
Morphing BB10 of 'Program:POPCNTButNoBMI2(int):int'
Morphing BB11 of 'Program:POPCNTButNoBMI2(int):int'
fgMorphTree BB11, stmt 28 (before)
[000010] --C--------- * RETURN int
[000131] ------------ | /--* CNS_INT int 1
[000132] ------------ \--* SUB int
[000130] ------------ \--* CAST int <- long
[000129] ------------ \--* LCL_VAR long V09 tmp8
fgMorphTree BB11, stmt 28 (after)
[000010] -----+------ * RETURN int
[000131] -----+------ | /--* CNS_INT int -1
[000132] -----+------ \--* ADD int
[000129] C----+------ \--* LCL_VAR int V09 tmp8
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 0.50 [000..001) i bwd
BB04 [0003] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB05 [0004] 1 0.50 [000..001)-> BB07 ( cond ) i
BB06 [0005] 1 0.50 [000..001) i
BB07 [0006] 2 0.50 [000..001)-> BB09 (always) i
BB08 [0007] 1 0.50 [000..001) i bwd
BB09 [0008] 2 0.50 [000..001)-> BB08 ( cond ) i bwd
BB10 [0009] 1 1 [000..001) i
BB11 [0010] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
New BlockSet epoch 2, # of blocks (including unused BB00): 12, bitset array size: 1 (short)
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i
BB02 [0001] 1 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 0.50 [000..001) i bwd
BB04 [0003] 2 0.50 [000..001)-> BB03 ( cond ) i bwd
BB05 [0004] 1 0.50 [000..001)-> BB07 ( cond ) i
BB06 [0005] 1 0.50 [000..001) i
BB07 [0006] 2 0.50 [000..001)-> BB09 (always) i
BB08 [0007] 1 0.50 [000..001) i bwd
BB09 [0008] 2 0.50 [000..001)-> BB08 ( cond ) i bwd
BB10 [0009] 1 1 [000..001) i
BB11 [0010] 1 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 BB04 0.50 [000..001) i label target bwd
BB04 [0003] 2 BB02,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 1 BB04 0.50 [000..001)-> BB07 ( cond ) i
BB06 [0005] 1 BB05 0.50 [000..001) i
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB09 (always) i label target
BB08 [0007] 1 BB09 0.50 [000..001) i label target bwd
BB09 [0008] 2 BB07,BB08 0.50 [000..001)-> BB08 ( cond ) i label target bwd
BB10 [0009] 1 BB09 1 [000..001) i
BB11 [0010] 1 BB10 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeEdgeWeights()
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 BB04 0.50 [000..001) i label target bwd
BB04 [0003] 2 BB02,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 1 BB04 0.50 [000..001)-> BB07 ( cond ) i
BB06 [0005] 1 BB05 0.50 [000..001) i
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB09 (always) i label target
BB08 [0007] 1 BB09 0.50 [000..001) i label target bwd
BB09 [0008] 2 BB07,BB08 0.50 [000..001)-> BB08 ( cond ) i label target bwd
BB10 [0009] 1 BB09 1 [000..001) i
BB11 [0010] 1 BB10 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights
*************** In fgCreateFunclets()
After fgCreateFunclets()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001)-> BB04 (always) i
BB03 [0002] 1 BB04 0.50 [000..001) i label target bwd
BB04 [0003] 2 BB02,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 1 BB04 0.50 [000..001)-> BB07 ( cond ) i
BB06 [0005] 1 BB05 0.50 [000..001) i
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB09 (always) i label target
BB08 [0007] 1 BB09 0.50 [000..001) i label target bwd
BB09 [0008] 2 BB07,BB08 0.50 [000..001)-> BB08 ( cond ) i label target bwd
BB10 [0009] 1 BB09 1 [000..001) i
BB11 [0010] 1 BB10 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
Duplication of loop condition [000024] is performed, because the cost of duplication (4) is less or equal than 32,
loopIterations = 8.000, countOfHelpers = 0, validProfileWeights = false
Duplicating loop condition in BB02 for loop (BB03 - BB04)
Estimated code size expansion is 4
[000181] ------------ * STMT void (IL 0x000... ???)
[000180] ------------ \--* JTRUE void
( 1, 1) [000179] ------------ | /--* CNS_INT int 0
( 5, 4) [000177] J------N---- \--* LE int
( 3, 2) [000178] ------------ \--* LCL_VAR int V04 tmp3
Duplication of loop condition [000096] is performed, because the cost of duplication (4) is less or equal than 32,
loopIterations = 8.000, countOfHelpers = 0, validProfileWeights = false
Duplicating loop condition in BB07 for loop (BB08 - BB09)
Estimated code size expansion is 4
[000186] ------------ * STMT void (IL 0x000... ???)
[000185] ------------ \--* JTRUE void
( 1, 1) [000184] ------------ | /--* CNS_INT int 0
( 5, 4) [000182] J------N---- \--* LE int
( 3, 2) [000183] ------------ \--* LCL_VAR int V05 tmp4
*************** In fgComputeEdgeWeights()
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001)-> BB05 ( cond ) i
BB03 [0002] 2 BB02,BB04 0.50 [000..001) i label target bwd
BB04 [0003] 1 BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB02,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0005] 1 BB05 0.50 [000..001) i
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB10 ( cond ) i label target
BB08 [0007] 2 BB07,BB09 0.50 [000..001) i label target bwd
BB09 [0008] 1 BB08 0.50 [000..001)-> BB08 ( cond ) i label target bwd
BB10 [0009] 2 BB07,BB09 1 [000..001) i label target
BB11 [0010] 1 BB10 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) i label target
BB02 [0001] 1 BB01 1 [000..001)-> BB05 ( cond ) i
BB03 [0002] 2 BB02,BB04 0.50 [000..001) i label target bwd
BB04 [0003] 1 BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB02,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0005] 1 BB05 0.50 [000..001) i
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB10 ( cond ) i label target
BB08 [0007] 2 BB07,BB09 0.50 [000..001) i label target bwd
BB09 [0008] 1 BB08 0.50 [000..001)-> BB08 ( cond ) i label target bwd
BB10 [0009] 2 BB07,BB09 1 [000..001) i label target
BB11 [0010] 1 BB10 1 [???..???) (return) internal
--------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB01 and BB02:
*************** In fgDebugCheckBBlist
Compacting blocks BB03 and BB04:
*************** In fgDebugCheckBBlist
Compacting blocks BB08 and BB09:
*************** In fgDebugCheckBBlist
Compacting blocks BB10 and BB11:
*************** In fgDebugCheckBBlist
After updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB05 ( cond ) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB01,BB03 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0005] 1 BB05 0.50 [000..001) i
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB10 ( cond ) i label target
BB08 [0007] 2 BB07,BB08 0.50 [000..001)-> BB08 ( cond ) i label target bwd
BB10 [0009] 2 BB07,BB08 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()
Initial BasicBlocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB05 ( cond ) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB01,BB03 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0005] 1 BB05 0.50 [000..001) i
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB10 ( cond ) i label target
BB08 [0007] 2 BB07,BB08 0.50 [000..001)-> BB08 ( cond ) i label target bwd
BB10 [0009] 2 BB07,BB08 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB05 ( cond ) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB01,BB03 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0005] 1 BB05 0.50 [000..001) i
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB10 ( cond ) i label target
BB08 [0007] 2 BB07,BB08 0.50 [000..001)-> BB08 ( cond ) i label target bwd
BB10 [0009] 2 BB07,BB08 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB05 ( cond ) i label target
BB03 [0002] 2 BB01,BB03 0.50 [000..001)-> BB03 ( cond ) i label target bwd
BB05 [0004] 2 BB01,BB03 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0005] 1 BB05 0.50 [000..001) i
BB07 [0006] 2 BB05,BB06 0.50 [000..001)-> BB10 ( cond ) i label target
BB08 [0007] 2 BB07,BB08 0.50 [000..001)-> BB08 ( cond ) i label target bwd
BB10 [0009] 2 BB07,BB08 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB05 to BB03
Renumber BB06 to BB04
Renumber BB07 to BB05
Renumber BB08 to BB06
Renumber BB10 to BB07
*************** After renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.50 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 3, # of blocks (including unused BB00): 8, bitset array size: 1 (short)
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB01 BB02
BB03 : BB01 BB02 BB03
BB04 : BB01 BB02 BB03 BB04
BB05 : BB01 BB02 BB03 BB04 BB05
BB06 : BB01 BB02 BB03 BB04 BB05 BB06
BB07 : BB01 BB02 BB03 BB04 BB05 BB06 BB07
After computing reachability:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.50 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i Loop label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
BB02: BB02 BB01
BB03: BB03 BB01
BB04: BB04 BB03 BB01
BB05: BB05 BB03 BB01
BB06: BB06 BB05 BB03 BB01
BB07: BB07 BB05 BB03 BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB03 BB02
BB03 : BB05 BB04
BB05 : BB07 BB06
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.50 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i Loop label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000147] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000176] -----+------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits]
[000146] -A--G+------ \--* ASG long
[000145] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000150] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000149] -A---+------ \--* ASG int
[000148] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000154] ------------ * STMT void (IL 0x000... ???)
[000151] -----+------ | /--* CNS_INT long 0
[000153] -A---+------ \--* ASG long
[000152] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000158] ------------ * STMT void (IL 0x000... ???)
[000155] -----+------ | /--* CNS_INT int 0
[000157] -A---+------ \--* ASG int
[000156] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000162] ------------ * STMT void (IL 0x000... ???)
[000159] -----+------ | /--* CNS_INT long 0
[000161] -A---+------ \--* ASG long
[000160] D----+-N---- \--* LCL_VAR long V07 tmp6
***** BB01, stmt 6
[000166] ------------ * STMT void (IL 0x000... ???)
[000163] -----+------ | /--* CNS_INT int 0
[000165] -A---+------ \--* ASG int
[000164] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB01, stmt 7
[000170] ------------ * STMT void (IL 0x000... ???)
[000167] -----+------ | /--* CNS_INT long 0
[000169] -A---+------ \--* ASG long
[000168] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB01, stmt 8
[000174] ------------ * STMT void (IL 0x000... ???)
[000171] -----+------ | /--* CNS_INT int 0
[000173] -A---+------ \--* ASG int
[000172] D----+-N---- \--* LCL_VAR int V10 tmp9
***** BB01, stmt 9
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 10
[000020] ------------ * STMT void (IL 0x000... ???)
[000017] -----+------ | /--* LCL_VAR int V04 tmp3
[000019] -A---+------ \--* ASG int
[000018] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 11
[000181] ------------ * STMT void (IL 0x000... ???)
[000180] ------------ \--* JTRUE void
( 1, 1) [000179] ------------ | /--* CNS_INT int 0
( 5, 4) [000177] J------N---- \--* LE int
( 3, 2) [000178] ------------ \--* LCL_VAR int V04 tmp3
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 12
[000031] ------------ * STMT void (IL 0x000... ???)
[000028] -----+------ | /--* LCL_VAR int V04 tmp3
[000030] -A---+------ \--* ASG int
[000029] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB02, stmt 13
[000041] ------------ * STMT void (IL 0x000... ???)
[000033] -----+------ | /--* LCL_VAR long V03 tmp2
[000040] -A---+------ \--* ASG long
[000039] D----+-N---- \--* LCL_VAR long V06 tmp5
***** BB02, stmt 14
[000044] ------------ * STMT void (IL 0x000... ???)
[000036] -----+------ | /--* CNS_INT long 8
[000037] -----+------ | /--* ADD long
[000034] -----+------ | | \--* LCL_VAR long V03 tmp2
[000043] -A---+------ \--* ASG long
[000038] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 15
[000052] ------------ * STMT void (IL 0x000... ???)
[000047] ---XG+------ | /--* CAST int <- long
[000046] ---XG+------ | | \--* HWIntrinsic long PopCount
[000045] *--XG+------ | | \--* IND long
[000042] -----+------ | | \--* LCL_VAR long V06 tmp5
[000048] ---XG+------ | /--* SUB int
[000032] -----+------ | | \--* LCL_VAR int V04 tmp3
[000051] -A-XG+------ \--* ASG int
[000050] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 16
[000026] ------------ * STMT void (IL 0x000... ???)
[000025] -----+------ \--* JTRUE void
( 1, 1) [000023] ------------ | /--* CNS_INT int 0
( 5, 4) [000024] J------N---- \--* GT int
( 3, 2) [000022] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 17
[000060] ------------ * STMT void (IL 0x000... ???)
[000056] -----+------ | /--* CNS_INT long -8
[000057] -----+------ | /--* ADD long
[000054] -----+------ | | \--* LCL_VAR long V03 tmp2
[000059] -A---+------ \--* ASG long
[000058] D----+-N---- \--* LCL_VAR long V07 tmp6
***** BB03, stmt 18
[000069] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG+------ | /--* HWIntrinsic int PopCount
[000063] *--XG+------ | | \--* IND int
[000062] -----+------ | | \--* LCL_VAR long V07 tmp6
[000065] ---XG+------ | /--* SUB int
[000061] -----+------ | | \--* LCL_VAR int V05 tmp4
[000068] -A-XG+------ \--* ASG int
[000067] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB03, stmt 19
[000074] ------------ * STMT void (IL 0x000... ???)
[000073] -----+------ \--* JTRUE void
[000071] -----+------ | /--* CNS_INT int 0
[000072] J----+-N---- \--* LE int
[000070] -----+------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 20
[000137] ------------ * STMT void (IL 0x000... ???)
[000134] -----+------ | /--* LCL_VAR int V04 tmp3
[000136] -A---+------ \--* ASG int
[000135] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB04, stmt 21
[000144] ------------ * STMT void (IL 0x000... ???)
[000140] -----+------ | /--* CNS_INT long 4
[000141] -----+------ | /--* ADD long
[000138] -----+------ | | \--* LCL_VAR long V07 tmp6
[000143] -A---+------ \--* ASG long
[000142] D----+-N---- \--* LCL_VAR long V07 tmp6
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 22
[000080] ------------ * STMT void (IL 0x000... ???)
[000077] *--XG+------ | /--* IND int
[000076] -----+------ | | \--* LCL_VAR long V07 tmp6
[000079] -A-XG+------ \--* ASG int
[000078] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB05, stmt 23
[000092] ------------ * STMT void (IL 0x000... ???)
[000088] -----+------ | /--* CNS_INT long 5
[000089] -----+------ | /--* LSH long
[000085] -----+------ | | | /--* CNS_INT long 4
[000086] -----+------ | | \--* DIV long
[000082] -----+------ | | | /--* LCL_VAR long V02 tmp1
[000083] -----+------ | | \--* SUB long
[000081] -----+------ | | \--* LCL_VAR long V07 tmp6
[000091] -A---+------ \--* ASG long
[000090] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB05, stmt 24
[000186] ------------ * STMT void (IL 0x000... ???)
[000185] ------------ \--* JTRUE void
( 1, 1) [000184] ------------ | /--* CNS_INT int 0
( 5, 4) [000182] J------N---- \--* LE int
( 3, 2) [000183] ------------ \--* LCL_VAR int V05 tmp4
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
[000106] ------------ * STMT void (IL 0x000... ???)
[000102] -----+------ | /--* CNS_INT int 1
[000103] -----+------ | /--* ADD int
[000101] -----+------ | | \--* HWIntrinsic int TrailingZeroCount
[000100] -----+------ | | \--* LCL_VAR int V08 tmp7
[000105] -A---+------ \--* ASG int
[000104] D----+-N---- \--* LCL_VAR int V10 tmp9
***** BB06, stmt 26
[000113] ------------ * STMT void (IL 0x000... ???)
[000109] -----+---U-- | /--* CAST long <- ulong <- uint
[000108] -----+------ | | \--* LCL_VAR int V10 tmp9
[000110] -----+------ | /--* ADD long
[000107] -----+------ | | \--* LCL_VAR long V09 tmp8
[000112] -A---+------ \--* ASG long
[000111] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB06, stmt 27
[000119] ------------ * STMT void (IL 0x000... ???)
[000115] -----+------ | /--* CNS_INT int -1
[000116] -----+------ | /--* ADD int
[000114] -----+------ | | \--* LCL_VAR int V05 tmp4
[000118] -A---+------ \--* ASG int
[000117] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB06, stmt 28
[000127] ------------ * STMT void (IL 0x000... ???)
[000122] -----+------ | /--* CNS_INT int 31
[000123] -----+------ | /--* AND int
[000121] -----+------ | | \--* LCL_VAR int V10 tmp9
[000124] -----+------ | /--* RSZ int
[000120] -----+------ | | \--* LCL_VAR int V08 tmp7
[000126] -A---+------ \--* ASG int
[000125] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB06, stmt 29
[000098] ------------ * STMT void (IL 0x000... ???)
[000097] -----+------ \--* JTRUE void
( 1, 1) [000095] ------------ | /--* CNS_INT int 0
( 5, 4) [000096] J------N---- \--* GT int
( 3, 2) [000094] ------------ \--* LCL_VAR int V05 tmp4
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 30
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000131] -----+------ | /--* CNS_INT int -1
[000132] -----+------ \--* ADD int
[000129] C----+------ \--* LCL_VAR int V09 tmp8
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 0.50 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.50 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 0.50 [000..001)-> BB06 ( cond ) i Loop label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000147] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000176] -----+------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits]
[000146] -A--G+------ \--* ASG long
[000145] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000150] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000149] -A---+------ \--* ASG int
[000148] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000154] ------------ * STMT void (IL 0x000... ???)
[000151] -----+------ | /--* CNS_INT long 0
[000153] -A---+------ \--* ASG long
[000152] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000158] ------------ * STMT void (IL 0x000... ???)
[000155] -----+------ | /--* CNS_INT int 0
[000157] -A---+------ \--* ASG int
[000156] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000162] ------------ * STMT void (IL 0x000... ???)
[000159] -----+------ | /--* CNS_INT long 0
[000161] -A---+------ \--* ASG long
[000160] D----+-N---- \--* LCL_VAR long V07 tmp6
***** BB01, stmt 6
[000166] ------------ * STMT void (IL 0x000... ???)
[000163] -----+------ | /--* CNS_INT int 0
[000165] -A---+------ \--* ASG int
[000164] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB01, stmt 7
[000170] ------------ * STMT void (IL 0x000... ???)
[000167] -----+------ | /--* CNS_INT long 0
[000169] -A---+------ \--* ASG long
[000168] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB01, stmt 8
[000174] ------------ * STMT void (IL 0x000... ???)
[000171] -----+------ | /--* CNS_INT int 0
[000173] -A---+------ \--* ASG int
[000172] D----+-N---- \--* LCL_VAR int V10 tmp9
***** BB01, stmt 9
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 10
[000020] ------------ * STMT void (IL 0x000... ???)
[000017] -----+------ | /--* LCL_VAR int V04 tmp3
[000019] -A---+------ \--* ASG int
[000018] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 11
[000181] ------------ * STMT void (IL 0x000... ???)
[000180] ------------ \--* JTRUE void
( 1, 1) [000179] ------------ | /--* CNS_INT int 0
( 5, 4) [000177] J------N---- \--* LE int
( 3, 2) [000178] ------------ \--* LCL_VAR int V04 tmp3
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 12
[000031] ------------ * STMT void (IL 0x000... ???)
[000028] -----+------ | /--* LCL_VAR int V04 tmp3
[000030] -A---+------ \--* ASG int
[000029] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB02, stmt 13
[000041] ------------ * STMT void (IL 0x000... ???)
[000033] -----+------ | /--* LCL_VAR long V03 tmp2
[000040] -A---+------ \--* ASG long
[000039] D----+-N---- \--* LCL_VAR long V06 tmp5
***** BB02, stmt 14
[000044] ------------ * STMT void (IL 0x000... ???)
[000036] -----+------ | /--* CNS_INT long 8
[000037] -----+------ | /--* ADD long
[000034] -----+------ | | \--* LCL_VAR long V03 tmp2
[000043] -A---+------ \--* ASG long
[000038] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 15
[000052] ------------ * STMT void (IL 0x000... ???)
[000047] ---XG+------ | /--* CAST int <- long
[000046] ---XG+------ | | \--* HWIntrinsic long PopCount
[000045] *--XG+------ | | \--* IND long
[000042] -----+------ | | \--* LCL_VAR long V06 tmp5
[000048] ---XG+------ | /--* SUB int
[000032] -----+------ | | \--* LCL_VAR int V04 tmp3
[000051] -A-XG+------ \--* ASG int
[000050] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 16
[000026] ------------ * STMT void (IL 0x000... ???)
[000025] -----+------ \--* JTRUE void
( 1, 1) [000023] ------------ | /--* CNS_INT int 0
( 5, 4) [000024] J------N---- \--* GT int
( 3, 2) [000022] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 17
[000060] ------------ * STMT void (IL 0x000... ???)
[000056] -----+------ | /--* CNS_INT long -8
[000057] -----+------ | /--* ADD long
[000054] -----+------ | | \--* LCL_VAR long V03 tmp2
[000059] -A---+------ \--* ASG long
[000058] D----+-N---- \--* LCL_VAR long V07 tmp6
***** BB03, stmt 18
[000069] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG+------ | /--* HWIntrinsic int PopCount
[000063] *--XG+------ | | \--* IND int
[000062] -----+------ | | \--* LCL_VAR long V07 tmp6
[000065] ---XG+------ | /--* SUB int
[000061] -----+------ | | \--* LCL_VAR int V05 tmp4
[000068] -A-XG+------ \--* ASG int
[000067] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB03, stmt 19
[000074] ------------ * STMT void (IL 0x000... ???)
[000073] -----+------ \--* JTRUE void
[000071] -----+------ | /--* CNS_INT int 0
[000072] J----+-N---- \--* LE int
[000070] -----+------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 20
[000137] ------------ * STMT void (IL 0x000... ???)
[000134] -----+------ | /--* LCL_VAR int V04 tmp3
[000136] -A---+------ \--* ASG int
[000135] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB04, stmt 21
[000144] ------------ * STMT void (IL 0x000... ???)
[000140] -----+------ | /--* CNS_INT long 4
[000141] -----+------ | /--* ADD long
[000138] -----+------ | | \--* LCL_VAR long V07 tmp6
[000143] -A---+------ \--* ASG long
[000142] D----+-N---- \--* LCL_VAR long V07 tmp6
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 22
[000080] ------------ * STMT void (IL 0x000... ???)
[000077] *--XG+------ | /--* IND int
[000076] -----+------ | | \--* LCL_VAR long V07 tmp6
[000079] -A-XG+------ \--* ASG int
[000078] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB05, stmt 23
[000092] ------------ * STMT void (IL 0x000... ???)
[000088] -----+------ | /--* CNS_INT long 5
[000089] -----+------ | /--* LSH long
[000085] -----+------ | | | /--* CNS_INT long 4
[000086] -----+------ | | \--* DIV long
[000082] -----+------ | | | /--* LCL_VAR long V02 tmp1
[000083] -----+------ | | \--* SUB long
[000081] -----+------ | | \--* LCL_VAR long V07 tmp6
[000091] -A---+------ \--* ASG long
[000090] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB05, stmt 24
[000186] ------------ * STMT void (IL 0x000... ???)
[000185] ------------ \--* JTRUE void
( 1, 1) [000184] ------------ | /--* CNS_INT int 0
( 5, 4) [000182] J------N---- \--* LE int
( 3, 2) [000183] ------------ \--* LCL_VAR int V05 tmp4
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
[000106] ------------ * STMT void (IL 0x000... ???)
[000102] -----+------ | /--* CNS_INT int 1
[000103] -----+------ | /--* ADD int
[000101] -----+------ | | \--* HWIntrinsic int TrailingZeroCount
[000100] -----+------ | | \--* LCL_VAR int V08 tmp7
[000105] -A---+------ \--* ASG int
[000104] D----+-N---- \--* LCL_VAR int V10 tmp9
***** BB06, stmt 26
[000113] ------------ * STMT void (IL 0x000... ???)
[000109] -----+---U-- | /--* CAST long <- ulong <- uint
[000108] -----+------ | | \--* LCL_VAR int V10 tmp9
[000110] -----+------ | /--* ADD long
[000107] -----+------ | | \--* LCL_VAR long V09 tmp8
[000112] -A---+------ \--* ASG long
[000111] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB06, stmt 27
[000119] ------------ * STMT void (IL 0x000... ???)
[000115] -----+------ | /--* CNS_INT int -1
[000116] -----+------ | /--* ADD int
[000114] -----+------ | | \--* LCL_VAR int V05 tmp4
[000118] -A---+------ \--* ASG int
[000117] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB06, stmt 28
[000127] ------------ * STMT void (IL 0x000... ???)
[000122] -----+------ | /--* CNS_INT int 31
[000123] -----+------ | /--* AND int
[000121] -----+------ | | \--* LCL_VAR int V10 tmp9
[000124] -----+------ | /--* RSZ int
[000120] -----+------ | | \--* LCL_VAR int V08 tmp7
[000126] -A---+------ \--* ASG int
[000125] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB06, stmt 29
[000098] ------------ * STMT void (IL 0x000... ???)
[000097] -----+------ \--* JTRUE void
( 1, 1) [000095] ------------ | /--* CNS_INT int 0
( 5, 4) [000096] J------N---- \--* GT int
( 3, 2) [000094] ------------ \--* LCL_VAR int V05 tmp4
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 30
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000131] -----+------ | /--* CNS_INT int -1
[000132] -----+------ \--* ADD int
[000129] C----+------ \--* LCL_VAR int V09 tmp8
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optOptimizeLoops()
After optSetBlockWeights:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 0.25 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 0.25 [000..001)-> BB06 ( cond ) i Loop label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optFindNaturalLoops()
Recorded loop L00, from BB02 to BB02 (Head=BB01, Entry=BB02, ExitCnt=1 at BB02)
Recorded loop L01, from BB06 to BB06 (Head=BB05, Entry=BB06, ExitCnt=1 at BB06)
Final natural loop table:
L00, from BB02 to BB02 (Head=BB01, Entry=BB02, ExitCnt=1 at BB02)
L01, from BB06 to BB06 (Head=BB05, Entry=BB06, ExitCnt=1 at BB06)
Marking loop L01
BB02(wt=2 )
Marking loop L02
BB06(wt=2 )
Found a total of 2 loops.
After loop weight marking:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** In optCloneLoops()
Blocks/Trees at start of phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000147] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000176] -----+------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits]
[000146] -A--G+------ \--* ASG long
[000145] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000150] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000149] -A---+------ \--* ASG int
[000148] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000154] ------------ * STMT void (IL 0x000... ???)
[000151] -----+------ | /--* CNS_INT long 0
[000153] -A---+------ \--* ASG long
[000152] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000158] ------------ * STMT void (IL 0x000... ???)
[000155] -----+------ | /--* CNS_INT int 0
[000157] -A---+------ \--* ASG int
[000156] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000162] ------------ * STMT void (IL 0x000... ???)
[000159] -----+------ | /--* CNS_INT long 0
[000161] -A---+------ \--* ASG long
[000160] D----+-N---- \--* LCL_VAR long V07 tmp6
***** BB01, stmt 6
[000166] ------------ * STMT void (IL 0x000... ???)
[000163] -----+------ | /--* CNS_INT int 0
[000165] -A---+------ \--* ASG int
[000164] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB01, stmt 7
[000170] ------------ * STMT void (IL 0x000... ???)
[000167] -----+------ | /--* CNS_INT long 0
[000169] -A---+------ \--* ASG long
[000168] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB01, stmt 8
[000174] ------------ * STMT void (IL 0x000... ???)
[000171] -----+------ | /--* CNS_INT int 0
[000173] -A---+------ \--* ASG int
[000172] D----+-N---- \--* LCL_VAR int V10 tmp9
***** BB01, stmt 9
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 10
[000020] ------------ * STMT void (IL 0x000... ???)
[000017] -----+------ | /--* LCL_VAR int V04 tmp3
[000019] -A---+------ \--* ASG int
[000018] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 11
[000181] ------------ * STMT void (IL 0x000... ???)
[000180] ------------ \--* JTRUE void
( 1, 1) [000179] ------------ | /--* CNS_INT int 0
( 5, 4) [000177] J------N---- \--* LE int
( 3, 2) [000178] ------------ \--* LCL_VAR int V04 tmp3
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 12
[000031] ------------ * STMT void (IL 0x000... ???)
[000028] -----+------ | /--* LCL_VAR int V04 tmp3
[000030] -A---+------ \--* ASG int
[000029] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB02, stmt 13
[000041] ------------ * STMT void (IL 0x000... ???)
[000033] -----+------ | /--* LCL_VAR long V03 tmp2
[000040] -A---+------ \--* ASG long
[000039] D----+-N---- \--* LCL_VAR long V06 tmp5
***** BB02, stmt 14
[000044] ------------ * STMT void (IL 0x000... ???)
[000036] -----+------ | /--* CNS_INT long 8
[000037] -----+------ | /--* ADD long
[000034] -----+------ | | \--* LCL_VAR long V03 tmp2
[000043] -A---+------ \--* ASG long
[000038] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 15
[000052] ------------ * STMT void (IL 0x000... ???)
[000047] ---XG+------ | /--* CAST int <- long
[000046] ---XG+------ | | \--* HWIntrinsic long PopCount
[000045] *--XG+------ | | \--* IND long
[000042] -----+------ | | \--* LCL_VAR long V06 tmp5
[000048] ---XG+------ | /--* SUB int
[000032] -----+------ | | \--* LCL_VAR int V04 tmp3
[000051] -A-XG+------ \--* ASG int
[000050] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 16
[000026] ------------ * STMT void (IL 0x000... ???)
[000025] -----+------ \--* JTRUE void
( 1, 1) [000023] ------------ | /--* CNS_INT int 0
( 5, 4) [000024] J------N---- \--* GT int
( 3, 2) [000022] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 17
[000060] ------------ * STMT void (IL 0x000... ???)
[000056] -----+------ | /--* CNS_INT long -8
[000057] -----+------ | /--* ADD long
[000054] -----+------ | | \--* LCL_VAR long V03 tmp2
[000059] -A---+------ \--* ASG long
[000058] D----+-N---- \--* LCL_VAR long V07 tmp6
***** BB03, stmt 18
[000069] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG+------ | /--* HWIntrinsic int PopCount
[000063] *--XG+------ | | \--* IND int
[000062] -----+------ | | \--* LCL_VAR long V07 tmp6
[000065] ---XG+------ | /--* SUB int
[000061] -----+------ | | \--* LCL_VAR int V05 tmp4
[000068] -A-XG+------ \--* ASG int
[000067] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB03, stmt 19
[000074] ------------ * STMT void (IL 0x000... ???)
[000073] -----+------ \--* JTRUE void
[000071] -----+------ | /--* CNS_INT int 0
[000072] J----+-N---- \--* LE int
[000070] -----+------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 20
[000137] ------------ * STMT void (IL 0x000... ???)
[000134] -----+------ | /--* LCL_VAR int V04 tmp3
[000136] -A---+------ \--* ASG int
[000135] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB04, stmt 21
[000144] ------------ * STMT void (IL 0x000... ???)
[000140] -----+------ | /--* CNS_INT long 4
[000141] -----+------ | /--* ADD long
[000138] -----+------ | | \--* LCL_VAR long V07 tmp6
[000143] -A---+------ \--* ASG long
[000142] D----+-N---- \--* LCL_VAR long V07 tmp6
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 22
[000080] ------------ * STMT void (IL 0x000... ???)
[000077] *--XG+------ | /--* IND int
[000076] -----+------ | | \--* LCL_VAR long V07 tmp6
[000079] -A-XG+------ \--* ASG int
[000078] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB05, stmt 23
[000092] ------------ * STMT void (IL 0x000... ???)
[000088] -----+------ | /--* CNS_INT long 5
[000089] -----+------ | /--* LSH long
[000085] -----+------ | | | /--* CNS_INT long 4
[000086] -----+------ | | \--* DIV long
[000082] -----+------ | | | /--* LCL_VAR long V02 tmp1
[000083] -----+------ | | \--* SUB long
[000081] -----+------ | | \--* LCL_VAR long V07 tmp6
[000091] -A---+------ \--* ASG long
[000090] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB05, stmt 24
[000186] ------------ * STMT void (IL 0x000... ???)
[000185] ------------ \--* JTRUE void
( 1, 1) [000184] ------------ | /--* CNS_INT int 0
( 5, 4) [000182] J------N---- \--* LE int
( 3, 2) [000183] ------------ \--* LCL_VAR int V05 tmp4
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
[000106] ------------ * STMT void (IL 0x000... ???)
[000102] -----+------ | /--* CNS_INT int 1
[000103] -----+------ | /--* ADD int
[000101] -----+------ | | \--* HWIntrinsic int TrailingZeroCount
[000100] -----+------ | | \--* LCL_VAR int V08 tmp7
[000105] -A---+------ \--* ASG int
[000104] D----+-N---- \--* LCL_VAR int V10 tmp9
***** BB06, stmt 26
[000113] ------------ * STMT void (IL 0x000... ???)
[000109] -----+---U-- | /--* CAST long <- ulong <- uint
[000108] -----+------ | | \--* LCL_VAR int V10 tmp9
[000110] -----+------ | /--* ADD long
[000107] -----+------ | | \--* LCL_VAR long V09 tmp8
[000112] -A---+------ \--* ASG long
[000111] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB06, stmt 27
[000119] ------------ * STMT void (IL 0x000... ???)
[000115] -----+------ | /--* CNS_INT int -1
[000116] -----+------ | /--* ADD int
[000114] -----+------ | | \--* LCL_VAR int V05 tmp4
[000118] -A---+------ \--* ASG int
[000117] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB06, stmt 28
[000127] ------------ * STMT void (IL 0x000... ???)
[000122] -----+------ | /--* CNS_INT int 31
[000123] -----+------ | /--* AND int
[000121] -----+------ | | \--* LCL_VAR int V10 tmp9
[000124] -----+------ | /--* RSZ int
[000120] -----+------ | | \--* LCL_VAR int V08 tmp7
[000126] -A---+------ \--* ASG int
[000125] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB06, stmt 29
[000098] ------------ * STMT void (IL 0x000... ???)
[000097] -----+------ \--* JTRUE void
( 1, 1) [000095] ------------ | /--* CNS_INT int 0
( 5, 4) [000096] J------N---- \--* GT int
( 3, 2) [000094] ------------ \--* LCL_VAR int V05 tmp4
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 30
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000131] -----+------ | /--* CNS_INT int -1
[000132] -----+------ \--* ADD int
[000129] C----+------ \--* LCL_VAR int V09 tmp8
-------------------------------------------------------------------------------------------------------------------
Considering loop 0 to clone for optimizations.
> No iter flag on loop 0.
------------------------------------------------------------
Considering loop 1 to clone for optimizations.
> No iter flag on loop 1.
------------------------------------------------------------
After loop cloning:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000147] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000176] -----+------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits]
[000146] -A--G+------ \--* ASG long
[000145] D----+-N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
[000150] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000149] -A---+------ \--* ASG int
[000148] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
[000154] ------------ * STMT void (IL 0x000... ???)
[000151] -----+------ | /--* CNS_INT long 0
[000153] -A---+------ \--* ASG long
[000152] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
[000158] ------------ * STMT void (IL 0x000... ???)
[000155] -----+------ | /--* CNS_INT int 0
[000157] -A---+------ \--* ASG int
[000156] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
[000162] ------------ * STMT void (IL 0x000... ???)
[000159] -----+------ | /--* CNS_INT long 0
[000161] -A---+------ \--* ASG long
[000160] D----+-N---- \--* LCL_VAR long V07 tmp6
***** BB01, stmt 6
[000166] ------------ * STMT void (IL 0x000... ???)
[000163] -----+------ | /--* CNS_INT int 0
[000165] -A---+------ \--* ASG int
[000164] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB01, stmt 7
[000170] ------------ * STMT void (IL 0x000... ???)
[000167] -----+------ | /--* CNS_INT long 0
[000169] -A---+------ \--* ASG long
[000168] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB01, stmt 8
[000174] ------------ * STMT void (IL 0x000... ???)
[000171] -----+------ | /--* CNS_INT int 0
[000173] -A---+------ \--* ASG int
[000172] D----+-N---- \--* LCL_VAR int V10 tmp9
***** BB01, stmt 9
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 10
[000020] ------------ * STMT void (IL 0x000... ???)
[000017] -----+------ | /--* LCL_VAR int V04 tmp3
[000019] -A---+------ \--* ASG int
[000018] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 11
[000181] ------------ * STMT void (IL 0x000... ???)
[000180] ------------ \--* JTRUE void
( 1, 1) [000179] ------------ | /--* CNS_INT int 0
( 5, 4) [000177] J------N---- \--* LE int
( 3, 2) [000178] ------------ \--* LCL_VAR int V04 tmp3
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 12
[000031] ------------ * STMT void (IL 0x000... ???)
[000028] -----+------ | /--* LCL_VAR int V04 tmp3
[000030] -A---+------ \--* ASG int
[000029] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB02, stmt 13
[000041] ------------ * STMT void (IL 0x000... ???)
[000033] -----+------ | /--* LCL_VAR long V03 tmp2
[000040] -A---+------ \--* ASG long
[000039] D----+-N---- \--* LCL_VAR long V06 tmp5
***** BB02, stmt 14
[000044] ------------ * STMT void (IL 0x000... ???)
[000036] -----+------ | /--* CNS_INT long 8
[000037] -----+------ | /--* ADD long
[000034] -----+------ | | \--* LCL_VAR long V03 tmp2
[000043] -A---+------ \--* ASG long
[000038] D----+-N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 15
[000052] ------------ * STMT void (IL 0x000... ???)
[000047] ---XG+------ | /--* CAST int <- long
[000046] ---XG+------ | | \--* HWIntrinsic long PopCount
[000045] *--XG+------ | | \--* IND long
[000042] -----+------ | | \--* LCL_VAR long V06 tmp5
[000048] ---XG+------ | /--* SUB int
[000032] -----+------ | | \--* LCL_VAR int V04 tmp3
[000051] -A-XG+------ \--* ASG int
[000050] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 16
[000026] ------------ * STMT void (IL 0x000... ???)
[000025] -----+------ \--* JTRUE void
( 1, 1) [000023] ------------ | /--* CNS_INT int 0
( 5, 4) [000024] J------N---- \--* GT int
( 3, 2) [000022] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 17
[000060] ------------ * STMT void (IL 0x000... ???)
[000056] -----+------ | /--* CNS_INT long -8
[000057] -----+------ | /--* ADD long
[000054] -----+------ | | \--* LCL_VAR long V03 tmp2
[000059] -A---+------ \--* ASG long
[000058] D----+-N---- \--* LCL_VAR long V07 tmp6
***** BB03, stmt 18
[000069] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG+------ | /--* HWIntrinsic int PopCount
[000063] *--XG+------ | | \--* IND int
[000062] -----+------ | | \--* LCL_VAR long V07 tmp6
[000065] ---XG+------ | /--* SUB int
[000061] -----+------ | | \--* LCL_VAR int V05 tmp4
[000068] -A-XG+------ \--* ASG int
[000067] D----+-N---- \--* LCL_VAR int V04 tmp3
***** BB03, stmt 19
[000074] ------------ * STMT void (IL 0x000... ???)
[000073] -----+------ \--* JTRUE void
[000071] -----+------ | /--* CNS_INT int 0
[000072] J----+-N---- \--* LE int
[000070] -----+------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 20
[000137] ------------ * STMT void (IL 0x000... ???)
[000134] -----+------ | /--* LCL_VAR int V04 tmp3
[000136] -A---+------ \--* ASG int
[000135] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB04, stmt 21
[000144] ------------ * STMT void (IL 0x000... ???)
[000140] -----+------ | /--* CNS_INT long 4
[000141] -----+------ | /--* ADD long
[000138] -----+------ | | \--* LCL_VAR long V07 tmp6
[000143] -A---+------ \--* ASG long
[000142] D----+-N---- \--* LCL_VAR long V07 tmp6
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 22
[000080] ------------ * STMT void (IL 0x000... ???)
[000077] *--XG+------ | /--* IND int
[000076] -----+------ | | \--* LCL_VAR long V07 tmp6
[000079] -A-XG+------ \--* ASG int
[000078] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB05, stmt 23
[000092] ------------ * STMT void (IL 0x000... ???)
[000088] -----+------ | /--* CNS_INT long 5
[000089] -----+------ | /--* LSH long
[000085] -----+------ | | | /--* CNS_INT long 4
[000086] -----+------ | | \--* DIV long
[000082] -----+------ | | | /--* LCL_VAR long V02 tmp1
[000083] -----+------ | | \--* SUB long
[000081] -----+------ | | \--* LCL_VAR long V07 tmp6
[000091] -A---+------ \--* ASG long
[000090] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB05, stmt 24
[000186] ------------ * STMT void (IL 0x000... ???)
[000185] ------------ \--* JTRUE void
( 1, 1) [000184] ------------ | /--* CNS_INT int 0
( 5, 4) [000182] J------N---- \--* LE int
( 3, 2) [000183] ------------ \--* LCL_VAR int V05 tmp4
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
[000106] ------------ * STMT void (IL 0x000... ???)
[000102] -----+------ | /--* CNS_INT int 1
[000103] -----+------ | /--* ADD int
[000101] -----+------ | | \--* HWIntrinsic int TrailingZeroCount
[000100] -----+------ | | \--* LCL_VAR int V08 tmp7
[000105] -A---+------ \--* ASG int
[000104] D----+-N---- \--* LCL_VAR int V10 tmp9
***** BB06, stmt 26
[000113] ------------ * STMT void (IL 0x000... ???)
[000109] -----+---U-- | /--* CAST long <- ulong <- uint
[000108] -----+------ | | \--* LCL_VAR int V10 tmp9
[000110] -----+------ | /--* ADD long
[000107] -----+------ | | \--* LCL_VAR long V09 tmp8
[000112] -A---+------ \--* ASG long
[000111] D----+-N---- \--* LCL_VAR long V09 tmp8
***** BB06, stmt 27
[000119] ------------ * STMT void (IL 0x000... ???)
[000115] -----+------ | /--* CNS_INT int -1
[000116] -----+------ | /--* ADD int
[000114] -----+------ | | \--* LCL_VAR int V05 tmp4
[000118] -A---+------ \--* ASG int
[000117] D----+-N---- \--* LCL_VAR int V05 tmp4
***** BB06, stmt 28
[000127] ------------ * STMT void (IL 0x000... ???)
[000122] -----+------ | /--* CNS_INT int 31
[000123] -----+------ | /--* AND int
[000121] -----+------ | | \--* LCL_VAR int V10 tmp9
[000124] -----+------ | /--* RSZ int
[000120] -----+------ | | \--* LCL_VAR int V08 tmp7
[000126] -A---+------ \--* ASG int
[000125] D----+-N---- \--* LCL_VAR int V08 tmp7
***** BB06, stmt 29
[000098] ------------ * STMT void (IL 0x000... ???)
[000097] -----+------ \--* JTRUE void
( 1, 1) [000095] ------------ | /--* CNS_INT int 0
( 5, 4) [000096] J------N---- \--* GT int
( 3, 2) [000094] ------------ \--* LCL_VAR int V05 tmp4
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 30
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000131] -----+------ | /--* CNS_INT int -1
[000132] -----+------ \--* ADD int
[000129] C----+------ \--* LCL_VAR int V09 tmp8
-------------------------------------------------------------------------------------------------------------------
*************** In optUnrollLoops()
*************** In fgDebugCheckBBlist
*************** In lvaMarkLocalVars()
*** marking local variables in block BB01 (weight=1 )
[000147] ------------ * STMT void (IL 0x000... ???)
[000001] x---G+------ | /--* IND long
[000176] -----+------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits]
[000146] -A--G+------ \--* ASG long
[000145] D----+-N---- \--* LCL_VAR long V02 tmp1
New refCnts for V02: refCnt = 1, refCntWtd = 2
[000150] ------------ * STMT void (IL 0x000... ???)
[000003] -----+------ | /--* LCL_VAR int V00 arg0
[000149] -A---+------ \--* ASG int
[000148] D----+-N---- \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 1, refCntWtd = 1
[000154] ------------ * STMT void (IL 0x000... ???)
[000151] -----+------ | /--* CNS_INT long 0
[000153] -A---+------ \--* ASG long
[000152] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 1, refCntWtd = 1
[000158] ------------ * STMT void (IL 0x000... ???)
[000155] -----+------ | /--* CNS_INT int 0
[000157] -A---+------ \--* ASG int
[000156] D----+-N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 1, refCntWtd = 1
[000162] ------------ * STMT void (IL 0x000... ???)
[000159] -----+------ | /--* CNS_INT long 0
[000161] -A---+------ \--* ASG long
[000160] D----+-N---- \--* LCL_VAR long V07 tmp6
New refCnts for V07: refCnt = 1, refCntWtd = 1
[000166] ------------ * STMT void (IL 0x000... ???)
[000163] -----+------ | /--* CNS_INT int 0
[000165] -A---+------ \--* ASG int
[000164] D----+-N---- \--* LCL_VAR int V08 tmp7
New refCnts for V08: refCnt = 1, refCntWtd = 1
[000170] ------------ * STMT void (IL 0x000... ???)
[000167] -----+------ | /--* CNS_INT long 0
[000169] -A---+------ \--* ASG long
[000168] D----+-N---- \--* LCL_VAR long V09 tmp8
New refCnts for V09: refCnt = 1, refCntWtd = 1
[000174] ------------ * STMT void (IL 0x000... ???)
[000171] -----+------ | /--* CNS_INT int 0
[000173] -A---+------ \--* ASG int
[000172] D----+-N---- \--* LCL_VAR int V10 tmp9
New refCnts for V10: refCnt = 1, refCntWtd = 1
[000016] ------------ * STMT void (IL 0x000... ???)
[000013] -----+------ | /--* LCL_VAR long V02 tmp1
[000015] -A---+------ \--* ASG long
[000014] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 2, refCntWtd = 4
[000020] ------------ * STMT void (IL 0x000... ???)
[000017] -----+------ | /--* LCL_VAR int V04 tmp3
[000019] -A---+------ \--* ASG int
[000018] D----+-N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V04: refCnt = 2, refCntWtd = 4
[000181] ------------ * STMT void (IL 0x000... ???)
[000180] ------------ \--* JTRUE void
( 1, 1) [000179] ------------ | /--* CNS_INT int 0
( 5, 4) [000177] J------N---- \--* LE int
( 3, 2) [000178] ------------ \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 3, refCntWtd = 6
*** marking local variables in block BB02 (weight=2 )
[000031] ------------ * STMT void (IL 0x000... ???)
[000028] -----+------ | /--* LCL_VAR int V04 tmp3
[000030] -A---+------ \--* ASG int
[000029] D----+-N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 3, refCntWtd = 4
New refCnts for V04: refCnt = 4, refCntWtd = 10
[000041] ------------ * STMT void (IL 0x000... ???)
[000033] -----+------ | /--* LCL_VAR long V03 tmp2
[000040] -A---+------ \--* ASG long
[000039] D----+-N---- \--* LCL_VAR long V06 tmp5
New refCnts for V06: refCnt = 1, refCntWtd = 4
New refCnts for V03: refCnt = 3, refCntWtd = 4
[000044] ------------ * STMT void (IL 0x000... ???)
[000036] -----+------ | /--* CNS_INT long 8
[000037] -----+------ | /--* ADD long
[000034] -----+------ | | \--* LCL_VAR long V03 tmp2
[000043] -A---+------ \--* ASG long
[000038] D----+-N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 4, refCntWtd = 6
New refCnts for V03: refCnt = 5, refCntWtd = 8
[000052] ------------ * STMT void (IL 0x000... ???)
[000047] ---XG+------ | /--* CAST int <- long
[000046] ---XG+------ | | \--* HWIntrinsic long PopCount
[000045] *--XG+------ | | \--* IND long
[000042] -----+------ | | \--* LCL_VAR long V06 tmp5
[000048] ---XG+------ | /--* SUB int
[000032] -----+------ | | \--* LCL_VAR int V04 tmp3
[000051] -A-XG+------ \--* ASG int
[000050] D----+-N---- \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 5, refCntWtd = 14
New refCnts for V04: refCnt = 6, refCntWtd = 18
New refCnts for V06: refCnt = 2, refCntWtd = 8
[000026] ------------ * STMT void (IL 0x000... ???)
[000025] -----+------ \--* JTRUE void
( 1, 1) [000023] ------------ | /--* CNS_INT int 0
( 5, 4) [000024] J------N---- \--* GT int
( 3, 2) [000022] ------------ \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 7, refCntWtd = 22
*** marking local variables in block BB03 (weight=0.50)
[000060] ------------ * STMT void (IL 0x000... ???)
[000056] -----+------ | /--* CNS_INT long -8
[000057] -----+------ | /--* ADD long
[000054] -----+------ | | \--* LCL_VAR long V03 tmp2
[000059] -A---+------ \--* ASG long
[000058] D----+-N---- \--* LCL_VAR long V07 tmp6
New refCnts for V07: refCnt = 2, refCntWtd = 1.50
New refCnts for V03: refCnt = 6, refCntWtd = 8.50
[000069] ------------ * STMT void (IL 0x000... ???)
[000064] ---XG+------ | /--* HWIntrinsic int PopCount
[000063] *--XG+------ | | \--* IND int
[000062] -----+------ | | \--* LCL_VAR long V07 tmp6
[000065] ---XG+------ | /--* SUB int
[000061] -----+------ | | \--* LCL_VAR int V05 tmp4
[000068] -A-XG+------ \--* ASG int
[000067] D----+-N---- \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 8, refCntWtd = 23
New refCnts for V05: refCnt = 4, refCntWtd = 4.50
New refCnts for V07: refCnt = 3, refCntWtd = 2
[000074] ------------ * STMT void (IL 0x000... ???)
[000073] -----+------ \--* JTRUE void
[000071] -----+------ | /--* CNS_INT int 0
[000072] J----+-N---- \--* LE int
[000070] -----+------ \--* LCL_VAR int V04 tmp3
New refCnts for V04: refCnt = 9, refCntWtd = 24
*** marking local variables in block BB04 (weight=0.25)
[000137] ------------ * STMT void (IL 0x000... ???)
[000134] -----+------ | /--* LCL_VAR int V04 tmp3
[000136] -A---+------ \--* ASG int
[000135] D----+-N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 5, refCntWtd = 4.75
New refCnts for V04: refCnt = 10, refCntWtd = 24.50
[000144] ------------ * STMT void (IL 0x000... ???)
[000140] -----+------ | /--* CNS_INT long 4
[000141] -----+------ | /--* ADD long
[000138] -----+------ | | \--* LCL_VAR long V07 tmp6
[000143] -A---+------ \--* ASG long
[000142] D----+-N---- \--* LCL_VAR long V07 tmp6
New refCnts for V07: refCnt = 4, refCntWtd = 2.25
New refCnts for V07: refCnt = 5, refCntWtd = 2.50
*** marking local variables in block BB05 (weight=0.50)
[000080] ------------ * STMT void (IL 0x000... ???)
[000077] *--XG+------ | /--* IND int
[000076] -----+------ | | \--* LCL_VAR long V07 tmp6
[000079] -A-XG+------ \--* ASG int
[000078] D----+-N---- \--* LCL_VAR int V08 tmp7
New refCnts for V08: refCnt = 2, refCntWtd = 1.50
New refCnts for V07: refCnt = 6, refCntWtd = 3
[000092] ------------ * STMT void (IL 0x000... ???)
[000088] -----+------ | /--* CNS_INT long 5
[000089] -----+------ | /--* LSH long
[000085] -----+------ | | | /--* CNS_INT long 4
[000086] -----+------ | | \--* DIV long
[000082] -----+------ | | | /--* LCL_VAR long V02 tmp1
[000083] -----+------ | | \--* SUB long
[000081] -----+------ | | \--* LCL_VAR long V07 tmp6
[000091] -A---+------ \--* ASG long
[000090] D----+-N---- \--* LCL_VAR long V09 tmp8
New refCnts for V09: refCnt = 2, refCntWtd = 1.50
New refCnts for V07: refCnt = 7, refCntWtd = 3.50
New refCnts for V02: refCnt = 3, refCntWtd = 5
[000186] ------------ * STMT void (IL 0x000... ???)
[000185] ------------ \--* JTRUE void
( 1, 1) [000184] ------------ | /--* CNS_INT int 0
( 5, 4) [000182] J------N---- \--* LE int
( 3, 2) [000183] ------------ \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 6, refCntWtd = 5.25
*** marking local variables in block BB06 (weight=2 )
[000106] ------------ * STMT void (IL 0x000... ???)
[000102] -----+------ | /--* CNS_INT int 1
[000103] -----+------ | /--* ADD int
[000101] -----+------ | | \--* HWIntrinsic int TrailingZeroCount
[000100] -----+------ | | \--* LCL_VAR int V08 tmp7
[000105] -A---+------ \--* ASG int
[000104] D----+-N---- \--* LCL_VAR int V10 tmp9
New refCnts for V10: refCnt = 2, refCntWtd = 3
New refCnts for V08: refCnt = 3, refCntWtd = 3.50
[000113] ------------ * STMT void (IL 0x000... ???)
[000109] -----+---U-- | /--* CAST long <- ulong <- uint
[000108] -----+------ | | \--* LCL_VAR int V10 tmp9
[000110] -----+------ | /--* ADD long
[000107] -----+------ | | \--* LCL_VAR long V09 tmp8
[000112] -A---+------ \--* ASG long
[000111] D----+-N---- \--* LCL_VAR long V09 tmp8
New refCnts for V09: refCnt = 3, refCntWtd = 3.50
New refCnts for V09: refCnt = 4, refCntWtd = 5.50
New refCnts for V10: refCnt = 3, refCntWtd = 5
[000119] ------------ * STMT void (IL 0x000... ???)
[000115] -----+------ | /--* CNS_INT int -1
[000116] -----+------ | /--* ADD int
[000114] -----+------ | | \--* LCL_VAR int V05 tmp4
[000118] -A---+------ \--* ASG int
[000117] D----+-N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 7, refCntWtd = 7.25
New refCnts for V05: refCnt = 8, refCntWtd = 9.25
[000127] ------------ * STMT void (IL 0x000... ???)
[000122] -----+------ | /--* CNS_INT int 31
[000123] -----+------ | /--* AND int
[000121] -----+------ | | \--* LCL_VAR int V10 tmp9
[000124] -----+------ | /--* RSZ int
[000120] -----+------ | | \--* LCL_VAR int V08 tmp7
[000126] -A---+------ \--* ASG int
[000125] D----+-N---- \--* LCL_VAR int V08 tmp7
New refCnts for V08: refCnt = 4, refCntWtd = 5.50
New refCnts for V08: refCnt = 5, refCntWtd = 7.50
New refCnts for V10: refCnt = 4, refCntWtd = 7
[000098] ------------ * STMT void (IL 0x000... ???)
[000097] -----+------ \--* JTRUE void
( 1, 1) [000095] ------------ | /--* CNS_INT int 0
( 5, 4) [000096] J------N---- \--* GT int
( 3, 2) [000094] ------------ \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 9, refCntWtd = 11.25
*** marking local variables in block BB07 (weight=1 )
[000011] ------------ * STMT void (IL ???... ???)
[000010] -----+------ \--* RETURN int
[000131] -----+------ | /--* CNS_INT int -1
[000132] -----+------ \--* ADD int
[000129] C----+------ \--* LCL_VAR int V09 tmp8
New refCnts for V09: refCnt = 5, refCntWtd = 6.50
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
*************** In optAddCopies()
refCnt table for 'POPCNTButNoBMI2':
V04 tmp3 [ int]: refCnt = 10, refCntWtd = 24.50
V05 tmp4 [ int]: refCnt = 9, refCntWtd = 11.25
V03 tmp2 [ long]: refCnt = 6, refCntWtd = 8.50
V06 tmp5 [ long]: refCnt = 2, refCntWtd = 8
V08 tmp7 [ int]: refCnt = 5, refCntWtd = 7.50
V10 tmp9 [ int]: refCnt = 4, refCntWtd = 7
V09 tmp8 [ long]: refCnt = 5, refCntWtd = 6.50
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3
V02 tmp1 [ long]: refCnt = 3, refCntWtd = 5
V07 tmp6 [ long]: refCnt = 7, refCntWtd = 3.50
V01 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
fgMarkLoopHead: Checking loop head block BB02: no guaranteed callsite exits, marking method as fully interruptible
fgMarkLoopHead: Checking loop head block BB06: method is already fully interruptible
The biggest BB has 9 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000147] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long
N001 ( 3, 10) [000176] ------------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits]
N004 ( 5, 12) [000146] -A--G---R--- \--* ASG long
N003 ( 1, 1) [000145] D------N---- \--* LCL_VAR long V02 tmp1
***** BB01, stmt 2
( 1, 3) [000150] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0
N003 ( 1, 3) [000149] -A------R--- \--* ASG int
N002 ( 1, 1) [000148] D------N---- \--* LCL_VAR int V04 tmp3
***** BB01, stmt 3
( 1, 3) [000154] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000151] ------------ | /--* CNS_INT long 0
N003 ( 1, 3) [000153] -A------R--- \--* ASG long
N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 4
( 1, 3) [000158] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000155] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000157] -A------R--- \--* ASG int
N002 ( 1, 1) [000156] D------N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 5
( 1, 3) [000162] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000159] ------------ | /--* CNS_INT long 0
N003 ( 1, 3) [000161] -A------R--- \--* ASG long
N002 ( 1, 1) [000160] D------N---- \--* LCL_VAR long V07 tmp6
***** BB01, stmt 6
( 1, 3) [000166] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000163] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000165] -A------R--- \--* ASG int
N002 ( 1, 1) [000164] D------N---- \--* LCL_VAR int V08 tmp7
***** BB01, stmt 7
( 1, 3) [000170] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000167] ------------ | /--* CNS_INT long 0
N003 ( 1, 3) [000169] -A------R--- \--* ASG long
N002 ( 1, 1) [000168] D------N---- \--* LCL_VAR long V09 tmp8
***** BB01, stmt 8
( 1, 3) [000174] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000171] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000173] -A------R--- \--* ASG int
N002 ( 1, 1) [000172] D------N---- \--* LCL_VAR int V10 tmp9
***** BB01, stmt 9
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1
N003 ( 1, 3) [000015] -A------R--- \--* ASG long
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2
***** BB01, stmt 10
( 1, 3) [000020] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000017] ------------ | /--* LCL_VAR int V04 tmp3
N003 ( 1, 3) [000019] -A------R--- \--* ASG int
N002 ( 1, 1) [000018] D------N---- \--* LCL_VAR int V05 tmp4
***** BB01, stmt 11
( 5, 5) [000181] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000180] ------------ \--* JTRUE void
N002 ( 1, 1) [000179] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000177] J------N---- \--* LE int
N001 ( 1, 1) [000178] ------------ \--* LCL_VAR int V04 tmp3
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 12
( 1, 3) [000031] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000028] ------------ | /--* LCL_VAR int V04 tmp3
N003 ( 1, 3) [000030] -A------R--- \--* ASG int
N002 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V05 tmp4
***** BB02, stmt 13
( 1, 3) [000041] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000033] ------------ | /--* LCL_VAR long V03 tmp2
N003 ( 1, 3) [000040] -A------R--- \--* ASG long
N002 ( 1, 1) [000039] D------N---- \--* LCL_VAR long V06 tmp5
***** BB02, stmt 14
( 3, 3) [000044] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000036] ------------ | /--* CNS_INT long 8
N003 ( 3, 3) [000037] ------------ | /--* ADD long
N001 ( 1, 1) [000034] ------------ | | \--* LCL_VAR long V03 tmp2
N005 ( 3, 3) [000043] -A------R--- \--* ASG long
N004 ( 1, 1) [000038] D------N---- \--* LCL_VAR long V03 tmp2
***** BB02, stmt 15
( 7, 7) [000052] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000047] ---XG------- | /--* CAST int <- long
N004 ( 4, 3) [000046] ---XG------- | | \--* HWIntrinsic long PopCount
N003 ( 3, 2) [000045] *--XG------- | | \--* IND long
N002 ( 1, 1) [000042] ------------ | | \--* LCL_VAR long V06 tmp5
N006 ( 7, 7) [000048] ---XG------- | /--* SUB int
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR int V04 tmp3
N008 ( 7, 7) [000051] -A-XG---R--- \--* ASG int
N007 ( 1, 1) [000050] D------N---- \--* LCL_VAR int V04 tmp3
***** BB02, stmt 16
( 5, 5) [000026] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000025] ------------ \--* JTRUE void
N002 ( 1, 1) [000023] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000024] J------N---- \--* GT int
N001 ( 1, 1) [000022] ------------ \--* LCL_VAR int V04 tmp3
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 17
( 3, 3) [000060] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000056] ------------ | /--* CNS_INT long -8
N003 ( 3, 3) [000057] ------------ | /--* ADD long
N001 ( 1, 1) [000054] ------------ | | \--* LCL_VAR long V03 tmp2
N005 ( 3, 3) [000059] -A------R--- \--* ASG long
N004 ( 1, 1) [000058] D------N---- \--* LCL_VAR long V07 tmp6
***** BB03, stmt 18
( 6, 5) [000069] ------------ * STMT void (IL 0x000... ???)
N004 ( 4, 3) [000064] ---XG------- | /--* HWIntrinsic int PopCount
N003 ( 3, 2) [000063] *--XG------- | | \--* IND int
N002 ( 1, 1) [000062] ------------ | | \--* LCL_VAR long V07 tmp6
N005 ( 6, 5) [000065] ---XG------- | /--* SUB int
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR int V05 tmp4
N007 ( 6, 5) [000068] -A-XG---R--- \--* ASG int
N006 ( 1, 1) [000067] D------N---- \--* LCL_VAR int V04 tmp3
***** BB03, stmt 19
( 5, 5) [000074] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000073] ------------ \--* JTRUE void
N002 ( 1, 1) [000071] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000072] J------N---- \--* LE int
N001 ( 1, 1) [000070] ------------ \--* LCL_VAR int V04 tmp3
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 20
( 1, 3) [000137] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000134] ------------ | /--* LCL_VAR int V04 tmp3
N003 ( 1, 3) [000136] -A------R--- \--* ASG int
N002 ( 1, 1) [000135] D------N---- \--* LCL_VAR int V05 tmp4
***** BB04, stmt 21
( 3, 3) [000144] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000140] ------------ | /--* CNS_INT long 4
N003 ( 3, 3) [000141] ------------ | /--* ADD long
N001 ( 1, 1) [000138] ------------ | | \--* LCL_VAR long V07 tmp6
N005 ( 3, 3) [000143] -A------R--- \--* ASG long
N004 ( 1, 1) [000142] D------N---- \--* LCL_VAR long V07 tmp6
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 22
( 3, 3) [000080] ------------ * STMT void (IL 0x000... ???)
N002 ( 3, 2) [000077] *--XG------- | /--* IND int
N001 ( 1, 1) [000076] ------------ | | \--* LCL_VAR long V07 tmp6
N004 ( 3, 3) [000079] -A-XG---R--- \--* ASG int
N003 ( 1, 1) [000078] D------N---- \--* LCL_VAR int V08 tmp7
***** BB05, stmt 23
( 26, 9) [000092] ------------ * STMT void (IL 0x000... ???)
N006 ( 1, 1) [000088] ------------ | /--* CNS_INT long 5
N007 ( 26, 9) [000089] ------------ | /--* LSH long
N004 ( 1, 1) [000085] ------------ | | | /--* CNS_INT long 4
N005 ( 24, 7) [000086] ------------ | | \--* DIV long
N002 ( 1, 1) [000082] ------------ | | | /--* LCL_VAR long V02 tmp1
N003 ( 3, 3) [000083] ------------ | | \--* SUB long
N001 ( 1, 1) [000081] ------------ | | \--* LCL_VAR long V07 tmp6
N009 ( 26, 9) [000091] -A------R--- \--* ASG long
N008 ( 1, 1) [000090] D------N---- \--* LCL_VAR long V09 tmp8
***** BB05, stmt 24
( 5, 5) [000186] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000185] ------------ \--* JTRUE void
N002 ( 1, 1) [000184] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000182] J------N---- \--* LE int
N001 ( 1, 1) [000183] ------------ \--* LCL_VAR int V05 tmp4
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
( 4, 4) [000106] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000102] ------------ | /--* CNS_INT int 1
N004 ( 4, 4) [000103] ------------ | /--* ADD int
N002 ( 2, 2) [000101] ------------ | | \--* HWIntrinsic int TrailingZeroCount
N001 ( 1, 1) [000100] ------------ | | \--* LCL_VAR int V08 tmp7
N006 ( 4, 4) [000105] -A------R--- \--* ASG int
N005 ( 1, 1) [000104] D------N---- \--* LCL_VAR int V10 tmp9
***** BB06, stmt 26
( 4, 5) [000113] ------------ * STMT void (IL 0x000... ???)
N003 ( 2, 3) [000109] ---------U-- | /--* CAST long <- ulong <- uint
N002 ( 1, 1) [000108] ------------ | | \--* LCL_VAR int V10 tmp9
N004 ( 4, 5) [000110] ------------ | /--* ADD long
N001 ( 1, 1) [000107] ------------ | | \--* LCL_VAR long V09 tmp8
N006 ( 4, 5) [000112] -A------R--- \--* ASG long
N005 ( 1, 1) [000111] D------N---- \--* LCL_VAR long V09 tmp8
***** BB06, stmt 27
( 3, 3) [000119] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000115] ------------ | /--* CNS_INT int -1
N003 ( 3, 3) [000116] ------------ | /--* ADD int
N001 ( 1, 1) [000114] ------------ | | \--* LCL_VAR int V05 tmp4
N005 ( 3, 3) [000118] -A------R--- \--* ASG int
N004 ( 1, 1) [000117] D------N---- \--* LCL_VAR int V05 tmp4
***** BB06, stmt 28
( 8, 5) [000127] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000122] ------------ | /--* CNS_INT int 31
N004 ( 3, 3) [000123] ------------ | /--* AND int
N002 ( 1, 1) [000121] ------------ | | \--* LCL_VAR int V10 tmp9
N005 ( 8, 5) [000124] ------------ | /--* RSZ int
N001 ( 1, 1) [000120] ------------ | | \--* LCL_VAR int V08 tmp7
N007 ( 8, 5) [000126] -A------R--- \--* ASG int
N006 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V08 tmp7
***** BB06, stmt 29
( 5, 5) [000098] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000097] ------------ \--* JTRUE void
N002 ( 1, 1) [000095] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000096] J------N---- \--* GT int
N001 ( 1, 1) [000094] ------------ \--* LCL_VAR int V05 tmp4
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 30
( 4, 4) [000011] ------------ * STMT void (IL ???... ???)
N004 ( 4, 4) [000010] ------------ \--* RETURN int
N002 ( 1, 1) [000131] ------------ | /--* CNS_INT int -1
N003 ( 3, 3) [000132] ------------ \--* ADD int
N001 ( 1, 1) [000129] C----------- \--* LCL_VAR int V09 tmp8
-------------------------------------------------------------------------------------------------------------------
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 8.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
*************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...)
*************** In SsaBuilder::InsertPhiFunctions()
*************** In fgLocalVarLiveness()
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={ V00 } + ByrefExposed + GcHeap
DEF(8)={V04 V05 V03 V08 V10 V09 V02 V07}
BB02 USE(2)={V04 V03 } + ByrefExposed + GcHeap
DEF(4)={V04 V05 V03 V06}
BB03 USE(2)={ V05 V03 } + ByrefExposed + GcHeap
DEF(2)={V04 V07}
BB04 USE(2)={V04 V07}
DEF(2)={ V05 V07}
BB05 USE(3)={V05 V02 V07} + ByrefExposed + GcHeap
DEF(2)={ V08 V09 }
BB06 USE(3)={V05 V08 V09}
DEF(4)={V05 V08 V10 V09}
BB07 USE(1)={V09}
DEF(0)={ }
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={ V00 } + ByrefExposed + GcHeap
OUT(4)={V04 V05 V03 V02} + ByrefExposed + GcHeap
BB02 IN (3)={V04 V03 V02} + ByrefExposed + GcHeap
OUT(4)={V04 V05 V03 V02} + ByrefExposed + GcHeap
BB03 IN (3)={ V05 V03 V02 } + ByrefExposed + GcHeap
OUT(4)={V04 V05 V02 V07} + ByrefExposed + GcHeap
BB04 IN (3)={V04 V02 V07} + ByrefExposed + GcHeap
OUT(3)={ V05 V02 V07} + ByrefExposed + GcHeap
BB05 IN (3)={V05 V02 V07} + ByrefExposed + GcHeap
OUT(3)={V05 V08 V09 }
BB06 IN (3)={V05 V08 V09}
OUT(3)={V05 V08 V09}
BB07 IN (1)={V09}
OUT(0)={ }
top level assign
removing stmt with no side effects
Removing statement [000174] in BB01 as useless:
( 1, 3) [000174] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000171] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000173] -A------R--- \--* ASG int
N002 ( 1, 1) [000172] D------N---- \--* LCL_VAR int V10 tmp9
New refCnts for V10: refCnt = 3, refCntWtd = 6
top level assign
removing stmt with no side effects
Removing statement [000170] in BB01 as useless:
( 1, 3) [000170] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000167] ------------ | /--* CNS_INT long 0
N003 ( 1, 3) [000169] -A------R--- \--* ASG long
N002 ( 1, 1) [000168] D------N---- \--* LCL_VAR long V09 tmp8
New refCnts for V09: refCnt = 4, refCntWtd = 5.50
top level assign
removing stmt with no side effects
Removing statement [000166] in BB01 as useless:
( 1, 3) [000166] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000163] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000165] -A------R--- \--* ASG int
N002 ( 1, 1) [000164] D------N---- \--* LCL_VAR int V08 tmp7
New refCnts for V08: refCnt = 4, refCntWtd = 6.50
top level assign
removing stmt with no side effects
Removing statement [000162] in BB01 as useless:
( 1, 3) [000162] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000159] ------------ | /--* CNS_INT long 0
N003 ( 1, 3) [000161] -A------R--- \--* ASG long
N002 ( 1, 1) [000160] D------N---- \--* LCL_VAR long V07 tmp6
New refCnts for V07: refCnt = 6, refCntWtd = 2.50
top level assign
removing stmt with no side effects
Removing statement [000158] in BB01 as useless:
( 1, 3) [000158] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000155] ------------ | /--* CNS_INT int 0
N003 ( 1, 3) [000157] -A------R--- \--* ASG int
N002 ( 1, 1) [000156] D------N---- \--* LCL_VAR int V05 tmp4
New refCnts for V05: refCnt = 8, refCntWtd = 10.25
top level assign
removing stmt with no side effects
Removing statement [000154] in BB01 as useless:
( 1, 3) [000154] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000151] ------------ | /--* CNS_INT long 0
N003 ( 1, 3) [000153] -A------R--- \--* ASG long
N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR long V03 tmp2
New refCnts for V03: refCnt = 5, refCntWtd = 7.50
In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal)
Inserting phi functions:
Inserting phi definition for V05 at start of BB06.
Inserting phi definition for V08 at start of BB06.
Inserting phi definition for V09 at start of BB07.
Inserting phi definition for V09 at start of BB06.
Inserting phi definition for V05 at start of BB05.
Inserting phi definition for V07 at start of BB05.
Inserting phi definition for V04 at start of BB02.
Inserting phi definition for V05 at start of BB03.
Inserting phi definition for V03 at start of BB03.
Inserting phi definition for V03 at start of BB02.
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000147] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long
N001 ( 3, 10) [000176] ------------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits]
N004 ( 5, 12) [000146] -A--G---R--- \--* ASG long
N003 ( 1, 1) [000145] D------N---- \--* LCL_VAR long V02 tmp1 d:2
***** BB01, stmt 2
( 1, 3) [000150] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use)
N003 ( 1, 3) [000149] -A------R--- \--* ASG int
N002 ( 1, 1) [000148] D------N---- \--* LCL_VAR int V04 tmp3 d:2
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2
N003 ( 1, 3) [000015] -A------R--- \--* ASG long
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2
***** BB01, stmt 4
( 1, 3) [000020] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000017] ------------ | /--* LCL_VAR int V04 tmp3 u:2
N003 ( 1, 3) [000019] -A------R--- \--* ASG int
N002 ( 1, 1) [000018] D------N---- \--* LCL_VAR int V05 tmp4 d:2
***** BB01, stmt 5
( 5, 5) [000181] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000180] ------------ \--* JTRUE void
N002 ( 1, 1) [000179] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000177] J------N---- \--* LE int
N001 ( 1, 1) [000178] ------------ \--* LCL_VAR int V04 tmp3 u:2
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 6
( 2, 3) [000226] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000224] ------------ | * PHI long
N001 ( 0, 0) [000239] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ | \--* PHI_ARG long V03 tmp2 u:2
N007 ( 2, 3) [000225] -A------R--- \--* ASG long
N006 ( 1, 1) [000223] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 7
( 2, 3) [000214] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000212] ------------ | * PHI int
N001 ( 0, 0) [000241] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ | \--* PHI_ARG int V04 tmp3 u:2
N007 ( 2, 3) [000213] -A------R--- \--* ASG int
N006 ( 1, 1) [000211] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 8
( 1, 3) [000031] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000028] ------------ | /--* LCL_VAR int V04 tmp3 u:3
N003 ( 1, 3) [000030] -A------R--- \--* ASG int
N002 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V05 tmp4 d:3
***** BB02, stmt 9
( 1, 3) [000041] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000033] ------------ | /--* LCL_VAR long V03 tmp2 u:3
N003 ( 1, 3) [000040] -A------R--- \--* ASG long
N002 ( 1, 1) [000039] D------N---- \--* LCL_VAR long V06 tmp5 d:2
***** BB02, stmt 10
( 3, 3) [000044] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000036] ------------ | /--* CNS_INT long 8
N003 ( 3, 3) [000037] ------------ | /--* ADD long
N001 ( 1, 1) [000034] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use)
N005 ( 3, 3) [000043] -A------R--- \--* ASG long
N004 ( 1, 1) [000038] D------N---- \--* LCL_VAR long V03 tmp2 d:4
***** BB02, stmt 11
( 7, 7) [000052] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000047] ---XG------- | /--* CAST int <- long
N004 ( 4, 3) [000046] ---XG------- | | \--* HWIntrinsic long PopCount
N003 ( 3, 2) [000045] *--XG------- | | \--* IND long
N002 ( 1, 1) [000042] ------------ | | \--* LCL_VAR long V06 tmp5 u:2 (last use)
N006 ( 7, 7) [000048] ---XG------- | /--* SUB int
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR int V04 tmp3 u:3 (last use)
N008 ( 7, 7) [000051] -A-XG---R--- \--* ASG int
N007 ( 1, 1) [000050] D------N---- \--* LCL_VAR int V04 tmp3 d:4
***** BB02, stmt 12
( 5, 5) [000026] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000025] ------------ \--* JTRUE void
N002 ( 1, 1) [000023] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000024] J------N---- \--* GT int
N001 ( 1, 1) [000022] ------------ \--* LCL_VAR int V04 tmp3 u:4
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 13
( 2, 3) [000222] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000220] ------------ | * PHI long
N001 ( 0, 0) [000235] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ | \--* PHI_ARG long V03 tmp2 u:2
N007 ( 2, 3) [000221] -A------R--- \--* ASG long
N006 ( 1, 1) [000219] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 14
( 2, 3) [000218] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000216] ------------ | * PHI int
N001 ( 0, 0) [000237] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ | \--* PHI_ARG int V05 tmp4 u:2
N007 ( 2, 3) [000217] -A------R--- \--* ASG int
N006 ( 1, 1) [000215] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB03, stmt 15
( 3, 3) [000060] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000056] ------------ | /--* CNS_INT long -8
N003 ( 3, 3) [000057] ------------ | /--* ADD long
N001 ( 1, 1) [000054] ------------ | | \--* LCL_VAR long V03 tmp2 u:5 (last use)
N005 ( 3, 3) [000059] -A------R--- \--* ASG long
N004 ( 1, 1) [000058] D------N---- \--* LCL_VAR long V07 tmp6 d:2
***** BB03, stmt 16
( 6, 5) [000069] ------------ * STMT void (IL 0x000... ???)
N004 ( 4, 3) [000064] ---XG------- | /--* HWIntrinsic int PopCount
N003 ( 3, 2) [000063] *--XG------- | | \--* IND int
N002 ( 1, 1) [000062] ------------ | | \--* LCL_VAR long V07 tmp6 u:2
N005 ( 6, 5) [000065] ---XG------- | /--* SUB int
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR int V05 tmp4 u:4
N007 ( 6, 5) [000068] -A-XG---R--- \--* ASG int
N006 ( 1, 1) [000067] D------N---- \--* LCL_VAR int V04 tmp3 d:5
***** BB03, stmt 17
( 5, 5) [000074] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000073] ------------ \--* JTRUE void
N002 ( 1, 1) [000071] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000072] J------N---- \--* LE int
N001 ( 1, 1) [000070] ------------ \--* LCL_VAR int V04 tmp3 u:5
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 18
( 1, 3) [000137] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000134] ------------ | /--* LCL_VAR int V04 tmp3 u:5 (last use)
N003 ( 1, 3) [000136] -A------R--- \--* ASG int
N002 ( 1, 1) [000135] D------N---- \--* LCL_VAR int V05 tmp4 d:5
***** BB04, stmt 19
( 3, 3) [000144] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000140] ------------ | /--* CNS_INT long 4
N003 ( 3, 3) [000141] ------------ | /--* ADD long
N001 ( 1, 1) [000138] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 (last use)
N005 ( 3, 3) [000143] -A------R--- \--* ASG long
N004 ( 1, 1) [000142] D------N---- \--* LCL_VAR long V07 tmp6 d:3
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 20
( 6, 5) [000210] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000208] ------------ | * PHI long
N001 ( 0, 0) [000247] ------------ | /--* PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ | \--* PHI_ARG long V07 tmp6 u:2
N007 ( 6, 5) [000209] -A------R--- \--* ASG long
N006 ( 3, 2) [000207] D------N---- \--* LCL_VAR long V07 tmp6 d:4
***** BB05, stmt 21
( 2, 3) [000206] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000204] ------------ | * PHI int
N001 ( 0, 0) [000249] ------------ | /--* PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ | \--* PHI_ARG int V05 tmp4 u:4
N007 ( 2, 3) [000205] -A------R--- \--* ASG int
N006 ( 1, 1) [000203] D------N---- \--* LCL_VAR int V05 tmp4 d:6
***** BB05, stmt 22
( 3, 3) [000080] ------------ * STMT void (IL 0x000... ???)
N002 ( 3, 2) [000077] *--XG------- | /--* IND int
N001 ( 1, 1) [000076] ------------ | | \--* LCL_VAR long V07 tmp6 u:4
N004 ( 3, 3) [000079] -A-XG---R--- \--* ASG int
N003 ( 1, 1) [000078] D------N---- \--* LCL_VAR int V08 tmp7 d:2
***** BB05, stmt 23
( 26, 9) [000092] ------------ * STMT void (IL 0x000... ???)
N006 ( 1, 1) [000088] ------------ | /--* CNS_INT long 5
N007 ( 26, 9) [000089] ------------ | /--* LSH long
N004 ( 1, 1) [000085] ------------ | | | /--* CNS_INT long 4
N005 ( 24, 7) [000086] ------------ | | \--* DIV long
N002 ( 1, 1) [000082] ------------ | | | /--* LCL_VAR long V02 tmp1 u:2 (last use)
N003 ( 3, 3) [000083] ------------ | | \--* SUB long
N001 ( 1, 1) [000081] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 (last use)
N009 ( 26, 9) [000091] -A------R--- \--* ASG long
N008 ( 1, 1) [000090] D------N---- \--* LCL_VAR long V09 tmp8 d:2
***** BB05, stmt 24
( 5, 5) [000186] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000185] ------------ \--* JTRUE void
N002 ( 1, 1) [000184] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000182] J------N---- \--* LE int
N001 ( 1, 1) [000183] ------------ \--* LCL_VAR int V05 tmp4 u:6
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
( 2, 3) [000202] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000200] ------------ | * PHI long
N001 ( 0, 0) [000261] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ | \--* PHI_ARG long V09 tmp8 u:2
N007 ( 2, 3) [000201] -A------R--- \--* ASG long
N006 ( 1, 1) [000199] D------N---- \--* LCL_VAR long V09 tmp8 d:3
***** BB06, stmt 26
( 2, 3) [000194] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000192] ------------ | * PHI int
N001 ( 0, 0) [000263] ------------ | /--* PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ | \--* PHI_ARG int V08 tmp7 u:2
N007 ( 2, 3) [000193] -A------R--- \--* ASG int
N006 ( 1, 1) [000191] D------N---- \--* LCL_VAR int V08 tmp7 d:3
***** BB06, stmt 27
( 2, 3) [000190] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000188] ------------ | * PHI int
N001 ( 0, 0) [000265] ------------ | /--* PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ | \--* PHI_ARG int V05 tmp4 u:6
N007 ( 2, 3) [000189] -A------R--- \--* ASG int
N006 ( 1, 1) [000187] D------N---- \--* LCL_VAR int V05 tmp4 d:7
***** BB06, stmt 28
( 4, 4) [000106] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000102] ------------ | /--* CNS_INT int 1
N004 ( 4, 4) [000103] ------------ | /--* ADD int
N002 ( 2, 2) [000101] ------------ | | \--* HWIntrinsic int TrailingZeroCount
N001 ( 1, 1) [000100] ------------ | | \--* LCL_VAR int V08 tmp7 u:3
N006 ( 4, 4) [000105] -A------R--- \--* ASG int
N005 ( 1, 1) [000104] D------N---- \--* LCL_VAR int V10 tmp9 d:2
***** BB06, stmt 29
( 4, 5) [000113] ------------ * STMT void (IL 0x000... ???)
N003 ( 2, 3) [000109] ---------U-- | /--* CAST long <- ulong <- uint
N002 ( 1, 1) [000108] ------------ | | \--* LCL_VAR int V10 tmp9 u:2
N004 ( 4, 5) [000110] ------------ | /--* ADD long
N001 ( 1, 1) [000107] ------------ | | \--* LCL_VAR long V09 tmp8 u:3 (last use)
N006 ( 4, 5) [000112] -A------R--- \--* ASG long
N005 ( 1, 1) [000111] D------N---- \--* LCL_VAR long V09 tmp8 d:4
***** BB06, stmt 30
( 3, 3) [000119] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000115] ------------ | /--* CNS_INT int -1
N003 ( 3, 3) [000116] ------------ | /--* ADD int
N001 ( 1, 1) [000114] ------------ | | \--* LCL_VAR int V05 tmp4 u:7 (last use)
N005 ( 3, 3) [000118] -A------R--- \--* ASG int
N004 ( 1, 1) [000117] D------N---- \--* LCL_VAR int V05 tmp4 d:8
***** BB06, stmt 31
( 8, 5) [000127] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000122] ------------ | /--* CNS_INT int 31
N004 ( 3, 3) [000123] ------------ | /--* AND int
N002 ( 1, 1) [000121] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 (last use)
N005 ( 8, 5) [000124] ------------ | /--* RSZ int
N001 ( 1, 1) [000120] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 (last use)
N007 ( 8, 5) [000126] -A------R--- \--* ASG int
N006 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V08 tmp7 d:4
***** BB06, stmt 32
( 5, 5) [000098] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000097] ------------ \--* JTRUE void
N002 ( 1, 1) [000095] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000096] J------N---- \--* GT int
N001 ( 1, 1) [000094] ------------ \--* LCL_VAR int V05 tmp4 u:8
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 33
( 2, 3) [000198] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000196] ------------ | * PHI long
N001 ( 0, 0) [000259] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ | \--* PHI_ARG long V09 tmp8 u:2
N007 ( 2, 3) [000197] -A------R--- \--* ASG long
N006 ( 1, 1) [000195] D------N---- \--* LCL_VAR long V09 tmp8 d:5
***** BB07, stmt 34
( 4, 4) [000011] ------------ * STMT void (IL ???... ???)
N004 ( 4, 4) [000010] ------------ \--* RETURN int
N002 ( 1, 1) [000131] ------------ | /--* CNS_INT int -1
N003 ( 3, 3) [000132] ------------ \--* ADD int
N001 ( 1, 1) [000129] C----------- \--* LCL_VAR int V09 tmp8 u:5 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In optEarlyProp()
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $c0
The SSA definition for ByrefExposed (#2) at start of BB01 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB01 is $c0 {InitVal($41)}
***** BB01, stmt 1 (before)
N002 ( 5, 12) [000001] x---G------- /--* IND long
N001 ( 3, 10) [000176] ------------ | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits]
N004 ( 5, 12) [000146] -A--G---R--- * ASG long
N003 ( 1, 1) [000145] D------N---- \--* LCL_VAR long V02 tmp1 d:2
N001 [000176] CNS_INT(h) 0x7fe9bcfc4498 static Fseq[_bits] => $100 {Hnd const: 0x00007FE9BCFC4498}
N002 [000001] IND => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N003 [000145] LCL_VAR V02 tmp1 d:2 => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N004 [000146] ASG => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
***** BB01, stmt 1 (after)
N002 ( 5, 12) [000001] x---G------- /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000176] ------------ | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
N004 ( 5, 12) [000146] -A--G---R--- * ASG long <l:$140, c:$180>
N003 ( 1, 1) [000145] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
---------
***** BB01, stmt 2 (before)
N001 ( 1, 1) [000003] ------------ /--* LCL_VAR int V00 arg0 u:2 (last use)
N003 ( 1, 3) [000149] -A------R--- * ASG int
N002 ( 1, 1) [000148] D------N---- \--* LCL_VAR int V04 tmp3 d:2
N001 [000003] LCL_VAR V00 arg0 u:2 (last use) => $80 {InitVal($40)}
N002 [000148] LCL_VAR V04 tmp3 d:2 => $80 {InitVal($40)}
N003 [000149] ASG => $80 {InitVal($40)}
***** BB01, stmt 2 (after)
N001 ( 1, 1) [000003] ------------ /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000149] -A------R--- * ASG int $80
N002 ( 1, 1) [000148] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
---------
***** BB01, stmt 3 (before)
N001 ( 1, 1) [000013] ------------ /--* LCL_VAR long V02 tmp1 u:2
N003 ( 1, 3) [000015] -A------R--- * ASG long
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2
N001 [000013] LCL_VAR V02 tmp1 u:2 => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N002 [000014] LCL_VAR V03 tmp2 d:2 => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N003 [000015] ASG => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
***** BB01, stmt 3 (after)
N001 ( 1, 1) [000013] ------------ /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- * ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
---------
***** BB01, stmt 4 (before)
N001 ( 1, 1) [000017] ------------ /--* LCL_VAR int V04 tmp3 u:2
N003 ( 1, 3) [000019] -A------R--- * ASG int
N002 ( 1, 1) [000018] D------N---- \--* LCL_VAR int V05 tmp4 d:2
N001 [000017] LCL_VAR V04 tmp3 u:2 => $80 {InitVal($40)}
N002 [000018] LCL_VAR V05 tmp4 d:2 => $80 {InitVal($40)}
N003 [000019] ASG => $80 {InitVal($40)}
***** BB01, stmt 4 (after)
N001 ( 1, 1) [000017] ------------ /--* LCL_VAR int V04 tmp3 u:2 $80
N003 ( 1, 3) [000019] -A------R--- * ASG int $80
N002 ( 1, 1) [000018] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $80
---------
***** BB01, stmt 5 (before)
N004 ( 5, 5) [000180] ------------ * JTRUE void
N002 ( 1, 1) [000179] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000177] J------N---- \--* LE int
N001 ( 1, 1) [000178] ------------ \--* LCL_VAR int V04 tmp3 u:2
N001 [000178] LCL_VAR V04 tmp3 u:2 => $80 {InitVal($40)}
N002 [000179] CNS_INT 0 => $40 {IntCns 0}
N003 [000177] LE => $200 {LE($80, $40)}
***** BB01, stmt 5 (after)
N004 ( 5, 5) [000180] ------------ * JTRUE void
N002 ( 1, 1) [000179] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000177] J------N---- \--* LE int $200
N001 ( 1, 1) [000178] ------------ \--* LCL_VAR int V04 tmp3 u:2 $80
finish(BB01).
Succ(BB02).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
Succ(BB03).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
SSA definition: set VN of local 3/3 to $141 {PhiDef($3, $3, $240)}.
SSA definition: set VN of local 4/3 to $280 {PhiDef($4, $3, $240)}.
The SSA definition for ByrefExposed (#2) at start of BB02 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB02 is $c0 {InitVal($41)}
***** BB02, stmt 6 (before)
N001 ( 1, 1) [000028] ------------ /--* LCL_VAR int V04 tmp3 u:3
N003 ( 1, 3) [000030] -A------R--- * ASG int
N002 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V05 tmp4 d:3
N001 [000028] LCL_VAR V04 tmp3 u:3 => $280 {PhiDef($4, $3, $240)}
N002 [000029] LCL_VAR V05 tmp4 d:3 => $280 {PhiDef($4, $3, $240)}
N003 [000030] ASG => $280 {PhiDef($4, $3, $240)}
***** BB02, stmt 6 (after)
N001 ( 1, 1) [000028] ------------ /--* LCL_VAR int V04 tmp3 u:3 $280
N003 ( 1, 3) [000030] -A------R--- * ASG int $280
N002 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $280
---------
***** BB02, stmt 7 (before)
N001 ( 1, 1) [000033] ------------ /--* LCL_VAR long V03 tmp2 u:3
N003 ( 1, 3) [000040] -A------R--- * ASG long
N002 ( 1, 1) [000039] D------N---- \--* LCL_VAR long V06 tmp5 d:2
N001 [000033] LCL_VAR V03 tmp2 u:3 => $141 {PhiDef($3, $3, $240)}
N002 [000039] LCL_VAR V06 tmp5 d:2 => $141 {PhiDef($3, $3, $240)}
N003 [000040] ASG => $141 {PhiDef($3, $3, $240)}
***** BB02, stmt 7 (after)
N001 ( 1, 1) [000033] ------------ /--* LCL_VAR long V03 tmp2 u:3 $141
N003 ( 1, 3) [000040] -A------R--- * ASG long $141
N002 ( 1, 1) [000039] D------N---- \--* LCL_VAR long V06 tmp5 d:2 $141
---------
***** BB02, stmt 8 (before)
N002 ( 1, 1) [000036] ------------ /--* CNS_INT long 8
N003 ( 3, 3) [000037] ------------ /--* ADD long
N001 ( 1, 1) [000034] ------------ | \--* LCL_VAR long V03 tmp2 u:3 (last use)
N005 ( 3, 3) [000043] -A------R--- * ASG long
N004 ( 1, 1) [000038] D------N---- \--* LCL_VAR long V03 tmp2 d:4
N001 [000034] LCL_VAR V03 tmp2 u:3 (last use) => $141 {PhiDef($3, $3, $240)}
N002 [000036] CNS_INT 8 => $340 {LngCns: 8}
N003 [000037] ADD => $241 {ADD($141, $340)}
N004 [000038] LCL_VAR V03 tmp2 d:4 => $241 {ADD($141, $340)}
N005 [000043] ASG => $241 {ADD($141, $340)}
***** BB02, stmt 8 (after)
N002 ( 1, 1) [000036] ------------ /--* CNS_INT long 8 $340
N003 ( 3, 3) [000037] ------------ /--* ADD long $241
N001 ( 1, 1) [000034] ------------ | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000043] -A------R--- * ASG long $241
N004 ( 1, 1) [000038] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $241
---------
***** BB02, stmt 9 (before)
N005 ( 5, 5) [000047] ---XG------- /--* CAST int <- long
N004 ( 4, 3) [000046] ---XG------- | \--* HWIntrinsic long PopCount
N003 ( 3, 2) [000045] *--XG------- | \--* IND long
N002 ( 1, 1) [000042] ------------ | \--* LCL_VAR long V06 tmp5 u:2 (last use)
N006 ( 7, 7) [000048] ---XG------- /--* SUB int
N001 ( 1, 1) [000032] ------------ | \--* LCL_VAR int V04 tmp3 u:3 (last use)
N008 ( 7, 7) [000051] -A-XG---R--- * ASG int
N007 ( 1, 1) [000050] D------N---- \--* LCL_VAR int V04 tmp3 d:4
N001 [000032] LCL_VAR V04 tmp3 u:3 (last use) => $280 {PhiDef($4, $3, $240)}
N002 [000042] LCL_VAR V06 tmp5 u:2 (last use) => $141 {PhiDef($3, $3, $240)}
N003 [000045] IND => <l:$142 {ByrefExposedLoad($42, $141, $c0)}, c:$302 {302}>
VNForCastOper(int) is $45
N005 [000047] CAST => $201 {Cast($380, $45)}
N006 [000048] SUB => $202 {SUB($280, $201)}
N007 [000050] LCL_VAR V04 tmp3 d:4 => $202 {SUB($280, $201)}
N008 [000051] ASG => $202 {SUB($280, $201)}
***** BB02, stmt 9 (after)
N005 ( 5, 5) [000047] ---XG------- /--* CAST int <- long $201
N004 ( 4, 3) [000046] ---XG------- | \--* HWIntrinsic long PopCount $380
N003 ( 3, 2) [000045] *--XG------- | \--* IND long <l:$142, c:$302>
N002 ( 1, 1) [000042] ------------ | \--* LCL_VAR long V06 tmp5 u:2 (last use) $141
N006 ( 7, 7) [000048] ---XG------- /--* SUB int $202
N001 ( 1, 1) [000032] ------------ | \--* LCL_VAR int V04 tmp3 u:3 (last use) $280
N008 ( 7, 7) [000051] -A-XG---R--- * ASG int $202
N007 ( 1, 1) [000050] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $202
---------
***** BB02, stmt 10 (before)
N004 ( 5, 5) [000025] ------------ * JTRUE void
N002 ( 1, 1) [000023] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000024] J------N---- \--* GT int
N001 ( 1, 1) [000022] ------------ \--* LCL_VAR int V04 tmp3 u:4
N001 [000022] LCL_VAR V04 tmp3 u:4 => $202 {SUB($280, $201)}
N002 [000023] CNS_INT 0 => $40 {IntCns 0}
N003 [000024] GT => $203 {GT($202, $40)}
***** BB02, stmt 10 (after)
N004 ( 5, 5) [000025] ------------ * JTRUE void
N002 ( 1, 1) [000023] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000024] J------N---- \--* GT int $203
N001 ( 1, 1) [000022] ------------ \--* LCL_VAR int V04 tmp3 u:4 $202
finish(BB02).
Succ(BB03).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB02).
SSA definition: set VN of local 3/5 to $143 {PhiDef($3, $5, $240)}.
SSA definition: set VN of local 5/4 to $281 {PhiDef($5, $4, $204)}.
The SSA definition for ByrefExposed (#2) at start of BB03 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB03 is $c0 {InitVal($41)}
***** BB03, stmt 13 (before)
N002 ( 1, 1) [000056] ------------ /--* CNS_INT long -8
N003 ( 3, 3) [000057] ------------ /--* ADD long
N001 ( 1, 1) [000054] ------------ | \--* LCL_VAR long V03 tmp2 u:5 (last use)
N005 ( 3, 3) [000059] -A------R--- * ASG long
N004 ( 1, 1) [000058] D------N---- \--* LCL_VAR long V07 tmp6 d:2
N001 [000054] LCL_VAR V03 tmp2 u:5 (last use) => $143 {PhiDef($3, $5, $240)}
N002 [000056] CNS_INT -8 => $342 {LngCns: -8}
N003 [000057] ADD => $242 {ADD($143, $342)}
N004 [000058] LCL_VAR V07 tmp6 d:2 => $242 {ADD($143, $342)}
N005 [000059] ASG => $242 {ADD($143, $342)}
***** BB03, stmt 13 (after)
N002 ( 1, 1) [000056] ------------ /--* CNS_INT long -8 $342
N003 ( 3, 3) [000057] ------------ /--* ADD long $242
N001 ( 1, 1) [000054] ------------ | \--* LCL_VAR long V03 tmp2 u:5 (last use) $143
N005 ( 3, 3) [000059] -A------R--- * ASG long $242
N004 ( 1, 1) [000058] D------N---- \--* LCL_VAR long V07 tmp6 d:2 $242
---------
***** BB03, stmt 14 (before)
N004 ( 4, 3) [000064] ---XG------- /--* HWIntrinsic int PopCount
N003 ( 3, 2) [000063] *--XG------- | \--* IND int
N002 ( 1, 1) [000062] ------------ | \--* LCL_VAR long V07 tmp6 u:2
N005 ( 6, 5) [000065] ---XG------- /--* SUB int
N001 ( 1, 1) [000061] ------------ | \--* LCL_VAR int V05 tmp4 u:4
N007 ( 6, 5) [000068] -A-XG---R--- * ASG int
N006 ( 1, 1) [000067] D------N---- \--* LCL_VAR int V04 tmp3 d:5
N001 [000061] LCL_VAR V05 tmp4 u:4 => $281 {PhiDef($5, $4, $204)}
N002 [000062] LCL_VAR V07 tmp6 u:2 => $242 {ADD($143, $342)}
N003 [000063] IND => <l:$282 {ByrefExposedLoad($47, $242, $c0)}, c:$1c2 {1c2}>
N005 [000065] SUB => $205 {SUB($281, $3c0)}
N006 [000067] LCL_VAR V04 tmp3 d:5 => $205 {SUB($281, $3c0)}
N007 [000068] ASG => $205 {SUB($281, $3c0)}
***** BB03, stmt 14 (after)
N004 ( 4, 3) [000064] ---XG------- /--* HWIntrinsic int PopCount $3c0
N003 ( 3, 2) [000063] *--XG------- | \--* IND int <l:$282, c:$1c2>
N002 ( 1, 1) [000062] ------------ | \--* LCL_VAR long V07 tmp6 u:2 $242
N005 ( 6, 5) [000065] ---XG------- /--* SUB int $205
N001 ( 1, 1) [000061] ------------ | \--* LCL_VAR int V05 tmp4 u:4 $281
N007 ( 6, 5) [000068] -A-XG---R--- * ASG int $205
N006 ( 1, 1) [000067] D------N---- \--* LCL_VAR int V04 tmp3 d:5 $205
---------
***** BB03, stmt 15 (before)
N004 ( 5, 5) [000073] ------------ * JTRUE void
N002 ( 1, 1) [000071] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000072] J------N---- \--* LE int
N001 ( 1, 1) [000070] ------------ \--* LCL_VAR int V04 tmp3 u:5
N001 [000070] LCL_VAR V04 tmp3 u:5 => $205 {SUB($281, $3c0)}
N002 [000071] CNS_INT 0 => $40 {IntCns 0}
N003 [000072] LE => $206 {LE($205, $40)}
***** BB03, stmt 15 (after)
N004 ( 5, 5) [000073] ------------ * JTRUE void
N002 ( 1, 1) [000071] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000072] J------N---- \--* LE int $206
N001 ( 1, 1) [000070] ------------ \--* LCL_VAR int V04 tmp3 u:5 $205
finish(BB03).
Succ(BB04).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB05).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
The SSA definition for ByrefExposed (#2) at start of BB04 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB04 is $c0 {InitVal($41)}
***** BB04, stmt 18 (before)
N001 ( 1, 1) [000134] ------------ /--* LCL_VAR int V04 tmp3 u:5 (last use)
N003 ( 1, 3) [000136] -A------R--- * ASG int
N002 ( 1, 1) [000135] D------N---- \--* LCL_VAR int V05 tmp4 d:5
N001 [000134] LCL_VAR V04 tmp3 u:5 (last use) => $205 {SUB($281, $3c0)}
N002 [000135] LCL_VAR V05 tmp4 d:5 => $205 {SUB($281, $3c0)}
N003 [000136] ASG => $205 {SUB($281, $3c0)}
***** BB04, stmt 18 (after)
N001 ( 1, 1) [000134] ------------ /--* LCL_VAR int V04 tmp3 u:5 (last use) $205
N003 ( 1, 3) [000136] -A------R--- * ASG int $205
N002 ( 1, 1) [000135] D------N---- \--* LCL_VAR int V05 tmp4 d:5 $205
---------
***** BB04, stmt 19 (before)
N002 ( 1, 1) [000140] ------------ /--* CNS_INT long 4
N003 ( 3, 3) [000141] ------------ /--* ADD long
N001 ( 1, 1) [000138] ------------ | \--* LCL_VAR long V07 tmp6 u:2 (last use)
N005 ( 3, 3) [000143] -A------R--- * ASG long
N004 ( 1, 1) [000142] D------N---- \--* LCL_VAR long V07 tmp6 d:3
N001 [000138] LCL_VAR V07 tmp6 u:2 (last use) => $242 {ADD($143, $342)}
N002 [000140] CNS_INT 4 => $343 {LngCns: 4}
N003 [000141] ADD => $243 {ADD($242, $343)}
N004 [000142] LCL_VAR V07 tmp6 d:3 => $243 {ADD($242, $343)}
N005 [000143] ASG => $243 {ADD($242, $343)}
***** BB04, stmt 19 (after)
N002 ( 1, 1) [000140] ------------ /--* CNS_INT long 4 $343
N003 ( 3, 3) [000141] ------------ /--* ADD long $243
N001 ( 1, 1) [000138] ------------ | \--* LCL_VAR long V07 tmp6 u:2 (last use) $242
N005 ( 3, 3) [000143] -A------R--- * ASG long $243
N004 ( 1, 1) [000142] D------N---- \--* LCL_VAR long V07 tmp6 d:3 $243
finish(BB04).
Succ(BB05).
Not yet completed.
All preds complete, adding to allDone.
SSA definition: set VN of local 7/4 to $144 {PhiDef($7, $4, $204)}.
SSA definition: set VN of local 5/6 to $283 {PhiDef($5, $6, $207)}.
The SSA definition for ByrefExposed (#2) at start of BB05 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB05 is $c0 {InitVal($41)}
***** BB05, stmt 20 (before)
N002 ( 3, 2) [000077] *--XG------- /--* IND int
N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR long V07 tmp6 u:4
N004 ( 3, 3) [000079] -A-XG---R--- * ASG int
N003 ( 1, 1) [000078] D------N---- \--* LCL_VAR int V08 tmp7 d:2
N001 [000076] LCL_VAR V07 tmp6 u:4 => $144 {PhiDef($7, $4, $204)}
N002 [000077] IND => <l:$284 {ByrefExposedLoad($47, $144, $c0)}, c:$1c5 {1c5}>
N003 [000078] LCL_VAR V08 tmp7 d:2 => <l:$284 {ByrefExposedLoad($47, $144, $c0)}, c:$1c5 {1c5}>
N004 [000079] ASG => <l:$284 {ByrefExposedLoad($47, $144, $c0)}, c:$1c5 {1c5}>
***** BB05, stmt 20 (after)
N002 ( 3, 2) [000077] *--XG------- /--* IND int <l:$284, c:$1c5>
N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR long V07 tmp6 u:4 $144
N004 ( 3, 3) [000079] -A-XG---R--- * ASG int <l:$284, c:$1c5>
N003 ( 1, 1) [000078] D------N---- \--* LCL_VAR int V08 tmp7 d:2 <l:$284, c:$1c5>
---------
***** BB05, stmt 21 (before)
N006 ( 1, 1) [000088] ------------ /--* CNS_INT long 5
N007 ( 26, 9) [000089] ------------ /--* LSH long
N004 ( 1, 1) [000085] ------------ | | /--* CNS_INT long 4
N005 ( 24, 7) [000086] ------------ | \--* DIV long
N002 ( 1, 1) [000082] ------------ | | /--* LCL_VAR long V02 tmp1 u:2 (last use)
N003 ( 3, 3) [000083] ------------ | \--* SUB long
N001 ( 1, 1) [000081] ------------ | \--* LCL_VAR long V07 tmp6 u:4 (last use)
N009 ( 26, 9) [000091] -A------R--- * ASG long
N008 ( 1, 1) [000090] D------N---- \--* LCL_VAR long V09 tmp8 d:2
N001 [000081] LCL_VAR V07 tmp6 u:4 (last use) => $144 {PhiDef($7, $4, $204)}
N002 [000082] LCL_VAR V02 tmp1 u:2 (last use) => <l:$140 {ByrefExposedLoad($42, $100, $c0)}, c:$180 {180}>
N003 [000083] SUB => <l:$244 {SUB($144, $140)}, c:$245 {SUB($144, $180)}>
N004 [000085] CNS_INT 4 => $343 {LngCns: 4}
N005 [000086] DIV => <l:$246 {DIV($244, $343)}, c:$247 {DIV($245, $343)}>
N006 [000088] CNS_INT 5 => $345 {LngCns: 5}
N007 [000089] LSH => <l:$248 {LSH($246, $345)}, c:$249 {LSH($247, $345)}>
N008 [000090] LCL_VAR V09 tmp8 d:2 => <l:$248 {LSH($246, $345)}, c:$249 {LSH($247, $345)}>
N009 [000091] ASG => <l:$248 {LSH($246, $345)}, c:$249 {LSH($247, $345)}>
***** BB05, stmt 21 (after)
N006 ( 1, 1) [000088] ------------ /--* CNS_INT long 5 $345
N007 ( 26, 9) [000089] ------------ /--* LSH long <l:$248, c:$249>
N004 ( 1, 1) [000085] ------------ | | /--* CNS_INT long 4 $343
N005 ( 24, 7) [000086] ------------ | \--* DIV long <l:$246, c:$247>
N002 ( 1, 1) [000082] ------------ | | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000083] ------------ | \--* SUB long <l:$244, c:$245>
N001 ( 1, 1) [000081] ------------ | \--* LCL_VAR long V07 tmp6 u:4 (last use) $144
N009 ( 26, 9) [000091] -A------R--- * ASG long <l:$248, c:$249>
N008 ( 1, 1) [000090] D------N---- \--* LCL_VAR long V09 tmp8 d:2 <l:$248, c:$249>
---------
***** BB05, stmt 22 (before)
N004 ( 5, 5) [000185] ------------ * JTRUE void
N002 ( 1, 1) [000184] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000182] J------N---- \--* LE int
N001 ( 1, 1) [000183] ------------ \--* LCL_VAR int V05 tmp4 u:6
N001 [000183] LCL_VAR V05 tmp4 u:6 => $283 {PhiDef($5, $6, $207)}
N002 [000184] CNS_INT 0 => $40 {IntCns 0}
N003 [000182] LE => $208 {LE($283, $40)}
***** BB05, stmt 22 (after)
N004 ( 5, 5) [000185] ------------ * JTRUE void
N002 ( 1, 1) [000184] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000182] J------N---- \--* LE int $208
N001 ( 1, 1) [000183] ------------ \--* LCL_VAR int V05 tmp4 u:6 $283
finish(BB05).
Succ(BB06).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
Succ(BB07).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
SSA definition: set VN of local 9/3 to $145 {PhiDef($9, $3, $240)}.
SSA definition: set VN of local 8/3 to $285 {PhiDef($8, $3, $240)}.
SSA definition: set VN of local 5/7 to $286 {PhiDef($5, $7, $209)}.
The SSA definition for ByrefExposed (#2) at start of BB06 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB06 is $c0 {InitVal($41)}
***** BB06, stmt 25 (before)
N003 ( 1, 1) [000102] ------------ /--* CNS_INT int 1
N004 ( 4, 4) [000103] ------------ /--* ADD int
N002 ( 2, 2) [000101] ------------ | \--* HWIntrinsic int TrailingZeroCount
N001 ( 1, 1) [000100] ------------ | \--* LCL_VAR int V08 tmp7 u:3
N006 ( 4, 4) [000105] -A------R--- * ASG int
N005 ( 1, 1) [000104] D------N---- \--* LCL_VAR int V10 tmp9 d:2
N001 [000100] LCL_VAR V08 tmp7 u:3 => $285 {PhiDef($8, $3, $240)}
N003 [000102] CNS_INT 1 => $4b {IntCns 1}
N004 [000103] ADD => $20a {ADD($4b, $400)}
N005 [000104] LCL_VAR V10 tmp9 d:2 => $20a {ADD($4b, $400)}
N006 [000105] ASG => $20a {ADD($4b, $400)}
***** BB06, stmt 25 (after)
N003 ( 1, 1) [000102] ------------ /--* CNS_INT int 1 $4b
N004 ( 4, 4) [000103] ------------ /--* ADD int $20a
N002 ( 2, 2) [000101] ------------ | \--* HWIntrinsic int TrailingZeroCount $400
N001 ( 1, 1) [000100] ------------ | \--* LCL_VAR int V08 tmp7 u:3 $285
N006 ( 4, 4) [000105] -A------R--- * ASG int $20a
N005 ( 1, 1) [000104] D------N---- \--* LCL_VAR int V10 tmp9 d:2 $20a
---------
***** BB06, stmt 26 (before)
N003 ( 2, 3) [000109] ---------U-- /--* CAST long <- ulong <- uint
N002 ( 1, 1) [000108] ------------ | \--* LCL_VAR int V10 tmp9 u:2
N004 ( 4, 5) [000110] ------------ /--* ADD long
N001 ( 1, 1) [000107] ------------ | \--* LCL_VAR long V09 tmp8 u:3 (last use)
N006 ( 4, 5) [000112] -A------R--- * ASG long
N005 ( 1, 1) [000111] D------N---- \--* LCL_VAR long V09 tmp8 d:4
N001 [000107] LCL_VAR V09 tmp8 u:3 (last use) => $145 {PhiDef($9, $3, $240)}
N002 [000108] LCL_VAR V10 tmp9 u:2 => $20a {ADD($4b, $400)}
VNForCastOper(ulong, unsignedSrc) is $4c
N003 [000109] CAST => $24a {Cast($20a, $4c)}
N004 [000110] ADD => $24b {ADD($145, $24a)}
N005 [000111] LCL_VAR V09 tmp8 d:4 => $24b {ADD($145, $24a)}
N006 [000112] ASG => $24b {ADD($145, $24a)}
***** BB06, stmt 26 (after)
N003 ( 2, 3) [000109] ---------U-- /--* CAST long <- ulong <- uint $24a
N002 ( 1, 1) [000108] ------------ | \--* LCL_VAR int V10 tmp9 u:2 $20a
N004 ( 4, 5) [000110] ------------ /--* ADD long $24b
N001 ( 1, 1) [000107] ------------ | \--* LCL_VAR long V09 tmp8 u:3 (last use) $145
N006 ( 4, 5) [000112] -A------R--- * ASG long $24b
N005 ( 1, 1) [000111] D------N---- \--* LCL_VAR long V09 tmp8 d:4 $24b
---------
***** BB06, stmt 27 (before)
N002 ( 1, 1) [000115] ------------ /--* CNS_INT int -1
N003 ( 3, 3) [000116] ------------ /--* ADD int
N001 ( 1, 1) [000114] ------------ | \--* LCL_VAR int V05 tmp4 u:7 (last use)
N005 ( 3, 3) [000118] -A------R--- * ASG int
N004 ( 1, 1) [000117] D------N---- \--* LCL_VAR int V05 tmp4 d:8
N001 [000114] LCL_VAR V05 tmp4 u:7 (last use) => $286 {PhiDef($5, $7, $209)}
N002 [000115] CNS_INT -1 => $41 {IntCns -1}
N003 [000116] ADD => $20b {ADD($41, $286)}
N004 [000117] LCL_VAR V05 tmp4 d:8 => $20b {ADD($41, $286)}
N005 [000118] ASG => $20b {ADD($41, $286)}
***** BB06, stmt 27 (after)
N002 ( 1, 1) [000115] ------------ /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ /--* ADD int $20b
N001 ( 1, 1) [000114] ------------ | \--* LCL_VAR int V05 tmp4 u:7 (last use) $286
N005 ( 3, 3) [000118] -A------R--- * ASG int $20b
N004 ( 1, 1) [000117] D------N---- \--* LCL_VAR int V05 tmp4 d:8 $20b
---------
***** BB06, stmt 28 (before)
N003 ( 1, 1) [000122] ------------ /--* CNS_INT int 31
N004 ( 3, 3) [000123] ------------ /--* AND int
N002 ( 1, 1) [000121] ------------ | \--* LCL_VAR int V10 tmp9 u:2 (last use)
N005 ( 8, 5) [000124] ------------ /--* RSZ int
N001 ( 1, 1) [000120] ------------ | \--* LCL_VAR int V08 tmp7 u:3 (last use)
N007 ( 8, 5) [000126] -A------R--- * ASG int
N006 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V08 tmp7 d:4
N001 [000120] LCL_VAR V08 tmp7 u:3 (last use) => $285 {PhiDef($8, $3, $240)}
N002 [000121] LCL_VAR V10 tmp9 u:2 (last use) => $20a {ADD($4b, $400)}
N003 [000122] CNS_INT 31 => $4d {IntCns 31}
N004 [000123] AND => $20c {AND($4d, $20a)}
N005 [000124] RSZ => $20d {RSZ($285, $20c)}
N006 [000125] LCL_VAR V08 tmp7 d:4 => $20d {RSZ($285, $20c)}
N007 [000126] ASG => $20d {RSZ($285, $20c)}
***** BB06, stmt 28 (after)
N003 ( 1, 1) [000122] ------------ /--* CNS_INT int 31 $4d
N004 ( 3, 3) [000123] ------------ /--* AND int $20c
N002 ( 1, 1) [000121] ------------ | \--* LCL_VAR int V10 tmp9 u:2 (last use) $20a
N005 ( 8, 5) [000124] ------------ /--* RSZ int $20d
N001 ( 1, 1) [000120] ------------ | \--* LCL_VAR int V08 tmp7 u:3 (last use) $285
N007 ( 8, 5) [000126] -A------R--- * ASG int $20d
N006 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V08 tmp7 d:4 $20d
---------
***** BB06, stmt 29 (before)
N004 ( 5, 5) [000097] ------------ * JTRUE void
N002 ( 1, 1) [000095] ------------ | /--* CNS_INT int 0
N003 ( 3, 3) [000096] J------N---- \--* GT int
N001 ( 1, 1) [000094] ------------ \--* LCL_VAR int V05 tmp4 u:8
N001 [000094] LCL_VAR V05 tmp4 u:8 => $20b {ADD($41, $286)}
N002 [000095] CNS_INT 0 => $40 {IntCns 0}
N003 [000096] GT => $20e {GT($20b, $40)}
***** BB06, stmt 29 (after)
N004 ( 5, 5) [000097] ------------ * JTRUE void
N002 ( 1, 1) [000095] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000096] J------N---- \--* GT int $20e
N001 ( 1, 1) [000094] ------------ \--* LCL_VAR int V05 tmp4 u:8 $20b
finish(BB06).
Succ(BB07).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB06).
SSA definition: set VN of local 9/5 to $146 {PhiDef($9, $5, $240)}.
The SSA definition for ByrefExposed (#2) at start of BB07 is $c0 {InitVal($41)}
The SSA definition for GcHeap (#2) at start of BB07 is $c0 {InitVal($41)}
***** BB07, stmt 33 (before)
N004 ( 4, 4) [000010] ------------ * RETURN int
N002 ( 1, 1) [000131] ------------ | /--* CNS_INT int -1
N003 ( 3, 3) [000132] ------------ \--* ADD int
N001 ( 1, 1) [000129] C----------- \--* LCL_VAR int V09 tmp8 u:5 (last use)
VNForCastOper(int) is $45
N001 [000129] LCL_VAR V09 tmp8 u:5 (last use) => $20f {Cast($146, $45)}
N002 [000131] CNS_INT -1 => $41 {IntCns -1}
N003 [000132] ADD => $210 {ADD($41, $20f)}
N004 [000010] RETURN => $1c7 {1c7}
***** BB07, stmt 33 (after)
N004 ( 4, 4) [000010] ------------ * RETURN int $1c7
N002 ( 1, 1) [000131] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000132] ------------ \--* ADD int $210
N001 ( 1, 1) [000129] C----------- \--* LCL_VAR int V09 tmp8 u:5 (last use) $20f
finish(BB07).
*************** In optHoistLoopCode()
Blocks/Trees before phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000147] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000176] ------------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
N004 ( 5, 12) [000146] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000145] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000150] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000149] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000148] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
***** BB01, stmt 4
( 1, 3) [000020] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000017] ------------ | /--* LCL_VAR int V04 tmp3 u:2 $80
N003 ( 1, 3) [000019] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000018] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $80
***** BB01, stmt 5
( 5, 5) [000181] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000180] ------------ \--* JTRUE void
N002 ( 1, 1) [000179] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000177] J------N---- \--* LE int $200
N001 ( 1, 1) [000178] ------------ \--* LCL_VAR int V04 tmp3 u:2 $80
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 6
( 2, 3) [000226] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000224] ------------ | * PHI long
N001 ( 0, 0) [000239] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000225] -A------R--- \--* ASG long
N006 ( 1, 1) [000223] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 7
( 2, 3) [000214] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000212] ------------ | * PHI int
N001 ( 0, 0) [000241] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000213] -A------R--- \--* ASG int
N006 ( 1, 1) [000211] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 8
( 1, 3) [000031] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000028] ------------ | /--* LCL_VAR int V04 tmp3 u:3 $280
N003 ( 1, 3) [000030] -A------R--- \--* ASG int $280
N002 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $280
***** BB02, stmt 9
( 1, 3) [000041] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000033] ------------ | /--* LCL_VAR long V03 tmp2 u:3 $141
N003 ( 1, 3) [000040] -A------R--- \--* ASG long $141
N002 ( 1, 1) [000039] D------N---- \--* LCL_VAR long V06 tmp5 d:2 $141
***** BB02, stmt 10
( 3, 3) [000044] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000036] ------------ | /--* CNS_INT long 8 $340
N003 ( 3, 3) [000037] ------------ | /--* ADD long $241
N001 ( 1, 1) [000034] ------------ | | \--* LCL_VAR long V03 tmp2 u:3 (last use) $141
N005 ( 3, 3) [000043] -A------R--- \--* ASG long $241
N004 ( 1, 1) [000038] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $241
***** BB02, stmt 11
( 7, 7) [000052] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000047] ---XG------- | /--* CAST int <- long $201
N004 ( 4, 3) [000046] ---XG------- | | \--* HWIntrinsic long PopCount $380
N003 ( 3, 2) [000045] *--XG------- | | \--* IND long <l:$142, c:$302>
N002 ( 1, 1) [000042] ------------ | | \--* LCL_VAR long V06 tmp5 u:2 (last use) $141
N006 ( 7, 7) [000048] ---XG------- | /--* SUB int $202
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR int V04 tmp3 u:3 (last use) $280
N008 ( 7, 7) [000051] -A-XG---R--- \--* ASG int $202
N007 ( 1, 1) [000050] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $202
***** BB02, stmt 12
( 5, 5) [000026] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000025] ------------ \--* JTRUE void
N002 ( 1, 1) [000023] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000024] J------N---- \--* GT int $203
N001 ( 1, 1) [000022] ------------ \--* LCL_VAR int V04 tmp3 u:4 $202
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 13
( 2, 3) [000222] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000220] ------------ | * PHI long
N001 ( 0, 0) [000235] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000221] -A------R--- \--* ASG long
N006 ( 1, 1) [000219] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 14
( 2, 3) [000218] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000216] ------------ | * PHI int
N001 ( 0, 0) [000237] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ | \--* PHI_ARG int V05 tmp4 u:2 $80
N007 ( 2, 3) [000217] -A------R--- \--* ASG int
N006 ( 1, 1) [000215] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB03, stmt 15
( 3, 3) [000060] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000056] ------------ | /--* CNS_INT long -8 $342
N003 ( 3, 3) [000057] ------------ | /--* ADD long $242
N001 ( 1, 1) [000054] ------------ | | \--* LCL_VAR long V03 tmp2 u:5 (last use) $143
N005 ( 3, 3) [000059] -A------R--- \--* ASG long $242
N004 ( 1, 1) [000058] D------N---- \--* LCL_VAR long V07 tmp6 d:2 $242
***** BB03, stmt 16
( 6, 5) [000069] ------------ * STMT void (IL 0x000... ???)
N004 ( 4, 3) [000064] ---XG------- | /--* HWIntrinsic int PopCount $3c0
N003 ( 3, 2) [000063] *--XG------- | | \--* IND int <l:$282, c:$1c2>
N002 ( 1, 1) [000062] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 $242
N005 ( 6, 5) [000065] ---XG------- | /--* SUB int $205
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR int V05 tmp4 u:4 $281
N007 ( 6, 5) [000068] -A-XG---R--- \--* ASG int $205
N006 ( 1, 1) [000067] D------N---- \--* LCL_VAR int V04 tmp3 d:5 $205
***** BB03, stmt 17
( 5, 5) [000074] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000073] ------------ \--* JTRUE void
N002 ( 1, 1) [000071] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000072] J------N---- \--* LE int $206
N001 ( 1, 1) [000070] ------------ \--* LCL_VAR int V04 tmp3 u:5 $205
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 18
( 1, 3) [000137] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000134] ------------ | /--* LCL_VAR int V04 tmp3 u:5 (last use) $205
N003 ( 1, 3) [000136] -A------R--- \--* ASG int $205
N002 ( 1, 1) [000135] D------N---- \--* LCL_VAR int V05 tmp4 d:5 $205
***** BB04, stmt 19
( 3, 3) [000144] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000140] ------------ | /--* CNS_INT long 4 $343
N003 ( 3, 3) [000141] ------------ | /--* ADD long $243
N001 ( 1, 1) [000138] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 (last use) $242
N005 ( 3, 3) [000143] -A------R--- \--* ASG long $243
N004 ( 1, 1) [000142] D------N---- \--* LCL_VAR long V07 tmp6 d:3 $243
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 20
( 6, 5) [000210] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000208] ------------ | * PHI long
N001 ( 0, 0) [000247] ------------ | /--* PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ | \--* PHI_ARG long V07 tmp6 u:2 $242
N007 ( 6, 5) [000209] -A------R--- \--* ASG long
N006 ( 3, 2) [000207] D------N---- \--* LCL_VAR long V07 tmp6 d:4
***** BB05, stmt 21
( 2, 3) [000206] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000204] ------------ | * PHI int
N001 ( 0, 0) [000249] ------------ | /--* PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ | \--* PHI_ARG int V05 tmp4 u:4 $281
N007 ( 2, 3) [000205] -A------R--- \--* ASG int
N006 ( 1, 1) [000203] D------N---- \--* LCL_VAR int V05 tmp4 d:6
***** BB05, stmt 22
( 3, 3) [000080] ------------ * STMT void (IL 0x000... ???)
N002 ( 3, 2) [000077] *--XG------- | /--* IND int <l:$284, c:$1c5>
N001 ( 1, 1) [000076] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 $144
N004 ( 3, 3) [000079] -A-XG---R--- \--* ASG int <l:$284, c:$1c5>
N003 ( 1, 1) [000078] D------N---- \--* LCL_VAR int V08 tmp7 d:2 <l:$284, c:$1c5>
***** BB05, stmt 23
( 26, 9) [000092] ------------ * STMT void (IL 0x000... ???)
N006 ( 1, 1) [000088] ------------ | /--* CNS_INT long 5 $345
N007 ( 26, 9) [000089] ------------ | /--* LSH long <l:$248, c:$249>
N004 ( 1, 1) [000085] ------------ | | | /--* CNS_INT long 4 $343
N005 ( 24, 7) [000086] ------------ | | \--* DIV long <l:$246, c:$247>
N002 ( 1, 1) [000082] ------------ | | | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000083] ------------ | | \--* SUB long <l:$244, c:$245>
N001 ( 1, 1) [000081] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 (last use) $144
N009 ( 26, 9) [000091] -A------R--- \--* ASG long <l:$248, c:$249>
N008 ( 1, 1) [000090] D------N---- \--* LCL_VAR long V09 tmp8 d:2 <l:$248, c:$249>
***** BB05, stmt 24
( 5, 5) [000186] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000185] ------------ \--* JTRUE void
N002 ( 1, 1) [000184] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000182] J------N---- \--* LE int $208
N001 ( 1, 1) [000183] ------------ \--* LCL_VAR int V05 tmp4 u:6 $283
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
( 2, 3) [000202] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000200] ------------ | * PHI long
N001 ( 0, 0) [000261] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ | \--* PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
N007 ( 2, 3) [000201] -A------R--- \--* ASG long
N006 ( 1, 1) [000199] D------N---- \--* LCL_VAR long V09 tmp8 d:3
***** BB06, stmt 26
( 2, 3) [000194] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000192] ------------ | * PHI int
N001 ( 0, 0) [000263] ------------ | /--* PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ | \--* PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
N007 ( 2, 3) [000193] -A------R--- \--* ASG int
N006 ( 1, 1) [000191] D------N---- \--* LCL_VAR int V08 tmp7 d:3
***** BB06, stmt 27
( 2, 3) [000190] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000188] ------------ | * PHI int
N001 ( 0, 0) [000265] ------------ | /--* PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ | \--* PHI_ARG int V05 tmp4 u:6 $283
N007 ( 2, 3) [000189] -A------R--- \--* ASG int
N006 ( 1, 1) [000187] D------N---- \--* LCL_VAR int V05 tmp4 d:7
***** BB06, stmt 28
( 4, 4) [000106] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000102] ------------ | /--* CNS_INT int 1 $4b
N004 ( 4, 4) [000103] ------------ | /--* ADD int $20a
N002 ( 2, 2) [000101] ------------ | | \--* HWIntrinsic int TrailingZeroCount $400
N001 ( 1, 1) [000100] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 $285
N006 ( 4, 4) [000105] -A------R--- \--* ASG int $20a
N005 ( 1, 1) [000104] D------N---- \--* LCL_VAR int V10 tmp9 d:2 $20a
***** BB06, stmt 29
( 4, 5) [000113] ------------ * STMT void (IL 0x000... ???)
N003 ( 2, 3) [000109] ---------U-- | /--* CAST long <- ulong <- uint $24a
N002 ( 1, 1) [000108] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 $20a
N004 ( 4, 5) [000110] ------------ | /--* ADD long $24b
N001 ( 1, 1) [000107] ------------ | | \--* LCL_VAR long V09 tmp8 u:3 (last use) $145
N006 ( 4, 5) [000112] -A------R--- \--* ASG long $24b
N005 ( 1, 1) [000111] D------N---- \--* LCL_VAR long V09 tmp8 d:4 $24b
***** BB06, stmt 30
( 3, 3) [000119] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000115] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | /--* ADD int $20b
N001 ( 1, 1) [000114] ------------ | | \--* LCL_VAR int V05 tmp4 u:7 (last use) $286
N005 ( 3, 3) [000118] -A------R--- \--* ASG int $20b
N004 ( 1, 1) [000117] D------N---- \--* LCL_VAR int V05 tmp4 d:8 $20b
***** BB06, stmt 31
( 8, 5) [000127] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000122] ------------ | /--* CNS_INT int 31 $4d
N004 ( 3, 3) [000123] ------------ | /--* AND int $20c
N002 ( 1, 1) [000121] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 (last use) $20a
N005 ( 8, 5) [000124] ------------ | /--* RSZ int $20d
N001 ( 1, 1) [000120] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 (last use) $285
N007 ( 8, 5) [000126] -A------R--- \--* ASG int $20d
N006 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V08 tmp7 d:4 $20d
***** BB06, stmt 32
( 5, 5) [000098] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000097] ------------ \--* JTRUE void
N002 ( 1, 1) [000095] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000096] J------N---- \--* GT int $20e
N001 ( 1, 1) [000094] ------------ \--* LCL_VAR int V05 tmp4 u:8 $20b
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 33
( 2, 3) [000198] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000196] ------------ | * PHI long
N001 ( 0, 0) [000259] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ | \--* PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
N007 ( 2, 3) [000197] -A------R--- \--* ASG long
N006 ( 1, 1) [000195] D------N---- \--* LCL_VAR long V09 tmp8 d:5
***** BB07, stmt 34
( 4, 4) [000011] ------------ * STMT void (IL ???... ???)
N004 ( 4, 4) [000010] ------------ \--* RETURN int $1c7
N002 ( 1, 1) [000131] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000132] ------------ \--* ADD int $210
N001 ( 1, 1) [000129] C----------- \--* LCL_VAR int V09 tmp8 u:5 (last use) $20f
-------------------------------------------------------------------------------------------------------------------
optHoistLoopCode for loop L00 <BB02..BB02>:
Loop body does not contain a call
USEDEF (4)={V04 V05 V03 V06}
INOUT (4)={V04 V05 V03 V02}
LOOPVARS(3)={V04 V05 V03}
optHoistLoopExprsForBlock BB02 (weight= 2 ) of loop L00 <BB02..BB02>, firstBlock is true
optHoistLoopCode for loop L01 <BB06..BB06>:
Loop body does not contain a call
USEDEF (4)={V05 V08 V10 V09}
INOUT (3)={V05 V08 V09}
LOOPVARS(3)={V05 V08 V09}
optHoistLoopExprsForBlock BB06 (weight= 2 ) of loop L01 <BB06..BB06>, firstBlock is true
*************** In optVnCopyProp()
*************** In SsaBuilder::ComputeDominators(Compiler*, ...)
Copy Assertion for BB01
curSsaName stack: { }
Live vars: {V00} => {V00 V02}
Live vars: {V00 V02} => {V02}
Live vars: {V02} => {V02 V04}
Live vars: {V02 V04} => {V02 V03 V04}
Live vars: {V02 V03 V04} => {V02 V03 V04 V05}
VN based copy assertion for [000178] V04 @00000080 by [000018] V05 @00000080.
N001 ( 1, 1) [000178] ------------ * LCL_VAR int V04 tmp3 u:2 $80
New refCnts for V04: refCnt = 9, refCntWtd = 22.50
New refCnts for V05: refCnt = 9, refCntWtd = 11.25
copy propagated to:
N001 ( 1, 1) [000178] ------------ * LCL_VAR int V05 tmp4 u:2 $80
Copy Assertion for BB03
curSsaName stack: { 0-[000003]:V00 2-[000145]:V02 3-[000014]:V03 4-[000148]:V04 5-[000018]:V05 }
Live vars: {V02 V03 V05} => {V02 V05}
Live vars: {V02 V05} => {V02 V05 V07}
Live vars: {V02 V05 V07} => {V02 V04 V05 V07}
Copy Assertion for BB05
curSsaName stack: { 0-[000003]:V00 2-[000145]:V02 3-[000219]:V03 4-[000067]:V04 5-[000215]:V05 7-[000058]:V07 }
Live vars: {V02 V05 V07} => {V02 V05 V07 V08}
Live vars: {V02 V05 V07 V08} => {V02 V05 V08}
Live vars: {V02 V05 V08} => {V05 V08}
Live vars: {V05 V08} => {V05 V08 V09}
Copy Assertion for BB07
curSsaName stack: { 0-[000003]:V00 2-[000145]:V02 3-[000219]:V03 4-[000067]:V04 5-[000203]:V05 7-[000207]:V07 8-[000078]:V08 9-[000090]:V09 }
Live vars: {V09} => {}
Copy Assertion for BB06
curSsaName stack: { 0-[000003]:V00 2-[000145]:V02 3-[000219]:V03 4-[000067]:V04 5-[000203]:V05 7-[000207]:V07 8-[000078]:V08 9-[000090]:V09 }
Live vars: {V05 V08 V09} => {V05 V08 V09 V10}
Live vars: {V05 V08 V09 V10} => {V05 V08 V10}
Live vars: {V05 V08 V10} => {V05 V08 V09 V10}
Live vars: {V05 V08 V09 V10} => {V08 V09 V10}
Live vars: {V08 V09 V10} => {V05 V08 V09 V10}
Live vars: {V05 V08 V09 V10} => {V05 V09 V10}
Live vars: {V05 V09 V10} => {V05 V09}
Live vars: {V05 V09} => {V05 V08 V09}
Copy Assertion for BB04
curSsaName stack: { 0-[000003]:V00 2-[000145]:V02 3-[000219]:V03 4-[000067]:V04 5-[000215]:V05 7-[000058]:V07 }
Live vars: {V02 V04 V07} => {V02 V07}
Live vars: {V02 V07} => {V02 V05 V07}
Live vars: {V02 V05 V07} => {V02 V05}
Live vars: {V02 V05} => {V02 V05 V07}
Copy Assertion for BB02
curSsaName stack: { 0-[000003]:V00 2-[000145]:V02 3-[000014]:V03 4-[000148]:V04 5-[000018]:V05 }
Live vars: {V02 V03 V04} => {V02 V03 V04 V05}
Live vars: {V02 V03 V04 V05} => {V02 V03 V04 V05 V06}
Live vars: {V02 V03 V04 V05 V06} => {V02 V04 V05 V06}
VN based copy assertion for [000034] V03 @00000141 by [000039] V06 @00000141.
N001 ( 1, 1) [000034] ------------ * LCL_VAR long V03 tmp2 u:3 (last use) $141
New refCnts for V03: refCnt = 4, refCntWtd = 5.50
New refCnts for V06: refCnt = 3, refCntWtd = 12
copy propagated to:
N001 ( 1, 1) [000034] ------------ * LCL_VAR long V06 tmp5 u:2 (last use) $141
Live vars: {V02 V04 V05 V06} => {V02 V03 V04 V05 V06}
Live vars: {V02 V03 V04 V05 V06} => {V02 V03 V05 V06}
VN based copy assertion for [000032] V04 @00000280 by [000029] V05 @00000280.
N001 ( 1, 1) [000032] ------------ * LCL_VAR int V04 tmp3 u:3 (last use) $280
New refCnts for V04: refCnt = 8, refCntWtd = 18.50
New refCnts for V05: refCnt = 10, refCntWtd = 13.25
copy propagated to:
N001 ( 1, 1) [000032] ------------ * LCL_VAR int V05 tmp4 u:3 (last use) $280
Live vars: {V02 V03 V05 V06} => {V02 V03 V05}
Live vars: {V02 V03 V05} => {V02 V03 V04 V05}
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000147] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000176] ------------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
N004 ( 5, 12) [000146] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000145] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000150] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000149] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000148] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
***** BB01, stmt 4
( 1, 3) [000020] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000017] ------------ | /--* LCL_VAR int V04 tmp3 u:2 $80
N003 ( 1, 3) [000019] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000018] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $80
***** BB01, stmt 5
( 5, 5) [000181] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000180] ------------ \--* JTRUE void
N002 ( 1, 1) [000179] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000177] J------N---- \--* LE int $200
N001 ( 1, 1) [000178] ------------ \--* LCL_VAR int V05 tmp4 u:2 $80
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 6
( 2, 3) [000226] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000224] ------------ | * PHI long
N001 ( 0, 0) [000239] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000225] -A------R--- \--* ASG long
N006 ( 1, 1) [000223] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 7
( 2, 3) [000214] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000212] ------------ | * PHI int
N001 ( 0, 0) [000241] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000213] -A------R--- \--* ASG int
N006 ( 1, 1) [000211] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 8
( 1, 3) [000031] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000028] ------------ | /--* LCL_VAR int V04 tmp3 u:3 $280
N003 ( 1, 3) [000030] -A------R--- \--* ASG int $280
N002 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $280
***** BB02, stmt 9
( 1, 3) [000041] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000033] ------------ | /--* LCL_VAR long V03 tmp2 u:3 $141
N003 ( 1, 3) [000040] -A------R--- \--* ASG long $141
N002 ( 1, 1) [000039] D------N---- \--* LCL_VAR long V06 tmp5 d:2 $141
***** BB02, stmt 10
( 3, 3) [000044] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000036] ------------ | /--* CNS_INT long 8 $340
N003 ( 3, 3) [000037] ------------ | /--* ADD long $241
N001 ( 1, 1) [000034] ------------ | | \--* LCL_VAR long V06 tmp5 u:2 (last use) $141
N005 ( 3, 3) [000043] -A------R--- \--* ASG long $241
N004 ( 1, 1) [000038] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $241
***** BB02, stmt 11
( 7, 7) [000052] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000047] ---XG------- | /--* CAST int <- long $201
N004 ( 4, 3) [000046] ---XG------- | | \--* HWIntrinsic long PopCount $380
N003 ( 3, 2) [000045] *--XG------- | | \--* IND long <l:$142, c:$302>
N002 ( 1, 1) [000042] ------------ | | \--* LCL_VAR long V06 tmp5 u:2 (last use) $141
N006 ( 7, 7) [000048] ---XG------- | /--* SUB int $202
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR int V05 tmp4 u:3 (last use) $280
N008 ( 7, 7) [000051] -A-XG---R--- \--* ASG int $202
N007 ( 1, 1) [000050] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $202
***** BB02, stmt 12
( 5, 5) [000026] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000025] ------------ \--* JTRUE void
N002 ( 1, 1) [000023] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000024] J------N---- \--* GT int $203
N001 ( 1, 1) [000022] ------------ \--* LCL_VAR int V04 tmp3 u:4 $202
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 13
( 2, 3) [000222] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000220] ------------ | * PHI long
N001 ( 0, 0) [000235] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000221] -A------R--- \--* ASG long
N006 ( 1, 1) [000219] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 14
( 2, 3) [000218] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000216] ------------ | * PHI int
N001 ( 0, 0) [000237] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ | \--* PHI_ARG int V05 tmp4 u:2 $80
N007 ( 2, 3) [000217] -A------R--- \--* ASG int
N006 ( 1, 1) [000215] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB03, stmt 15
( 3, 3) [000060] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000056] ------------ | /--* CNS_INT long -8 $342
N003 ( 3, 3) [000057] ------------ | /--* ADD long $242
N001 ( 1, 1) [000054] ------------ | | \--* LCL_VAR long V03 tmp2 u:5 (last use) $143
N005 ( 3, 3) [000059] -A------R--- \--* ASG long $242
N004 ( 1, 1) [000058] D------N---- \--* LCL_VAR long V07 tmp6 d:2 $242
***** BB03, stmt 16
( 6, 5) [000069] ------------ * STMT void (IL 0x000... ???)
N004 ( 4, 3) [000064] ---XG------- | /--* HWIntrinsic int PopCount $3c0
N003 ( 3, 2) [000063] *--XG------- | | \--* IND int <l:$282, c:$1c2>
N002 ( 1, 1) [000062] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 $242
N005 ( 6, 5) [000065] ---XG------- | /--* SUB int $205
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR int V05 tmp4 u:4 $281
N007 ( 6, 5) [000068] -A-XG---R--- \--* ASG int $205
N006 ( 1, 1) [000067] D------N---- \--* LCL_VAR int V04 tmp3 d:5 $205
***** BB03, stmt 17
( 5, 5) [000074] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000073] ------------ \--* JTRUE void
N002 ( 1, 1) [000071] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000072] J------N---- \--* LE int $206
N001 ( 1, 1) [000070] ------------ \--* LCL_VAR int V04 tmp3 u:5 $205
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 18
( 1, 3) [000137] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000134] ------------ | /--* LCL_VAR int V04 tmp3 u:5 (last use) $205
N003 ( 1, 3) [000136] -A------R--- \--* ASG int $205
N002 ( 1, 1) [000135] D------N---- \--* LCL_VAR int V05 tmp4 d:5 $205
***** BB04, stmt 19
( 3, 3) [000144] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000140] ------------ | /--* CNS_INT long 4 $343
N003 ( 3, 3) [000141] ------------ | /--* ADD long $243
N001 ( 1, 1) [000138] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 (last use) $242
N005 ( 3, 3) [000143] -A------R--- \--* ASG long $243
N004 ( 1, 1) [000142] D------N---- \--* LCL_VAR long V07 tmp6 d:3 $243
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 20
( 6, 5) [000210] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000208] ------------ | * PHI long
N001 ( 0, 0) [000247] ------------ | /--* PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ | \--* PHI_ARG long V07 tmp6 u:2 $242
N007 ( 6, 5) [000209] -A------R--- \--* ASG long
N006 ( 3, 2) [000207] D------N---- \--* LCL_VAR long V07 tmp6 d:4
***** BB05, stmt 21
( 2, 3) [000206] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000204] ------------ | * PHI int
N001 ( 0, 0) [000249] ------------ | /--* PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ | \--* PHI_ARG int V05 tmp4 u:4 $281
N007 ( 2, 3) [000205] -A------R--- \--* ASG int
N006 ( 1, 1) [000203] D------N---- \--* LCL_VAR int V05 tmp4 d:6
***** BB05, stmt 22
( 3, 3) [000080] ------------ * STMT void (IL 0x000... ???)
N002 ( 3, 2) [000077] *--XG------- | /--* IND int <l:$284, c:$1c5>
N001 ( 1, 1) [000076] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 $144
N004 ( 3, 3) [000079] -A-XG---R--- \--* ASG int <l:$284, c:$1c5>
N003 ( 1, 1) [000078] D------N---- \--* LCL_VAR int V08 tmp7 d:2 <l:$284, c:$1c5>
***** BB05, stmt 23
( 26, 9) [000092] ------------ * STMT void (IL 0x000... ???)
N006 ( 1, 1) [000088] ------------ | /--* CNS_INT long 5 $345
N007 ( 26, 9) [000089] ------------ | /--* LSH long <l:$248, c:$249>
N004 ( 1, 1) [000085] ------------ | | | /--* CNS_INT long 4 $343
N005 ( 24, 7) [000086] ------------ | | \--* DIV long <l:$246, c:$247>
N002 ( 1, 1) [000082] ------------ | | | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000083] ------------ | | \--* SUB long <l:$244, c:$245>
N001 ( 1, 1) [000081] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 (last use) $144
N009 ( 26, 9) [000091] -A------R--- \--* ASG long <l:$248, c:$249>
N008 ( 1, 1) [000090] D------N---- \--* LCL_VAR long V09 tmp8 d:2 <l:$248, c:$249>
***** BB05, stmt 24
( 5, 5) [000186] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000185] ------------ \--* JTRUE void
N002 ( 1, 1) [000184] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000182] J------N---- \--* LE int $208
N001 ( 1, 1) [000183] ------------ \--* LCL_VAR int V05 tmp4 u:6 $283
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
( 2, 3) [000202] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000200] ------------ | * PHI long
N001 ( 0, 0) [000261] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ | \--* PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
N007 ( 2, 3) [000201] -A------R--- \--* ASG long
N006 ( 1, 1) [000199] D------N---- \--* LCL_VAR long V09 tmp8 d:3
***** BB06, stmt 26
( 2, 3) [000194] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000192] ------------ | * PHI int
N001 ( 0, 0) [000263] ------------ | /--* PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ | \--* PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
N007 ( 2, 3) [000193] -A------R--- \--* ASG int
N006 ( 1, 1) [000191] D------N---- \--* LCL_VAR int V08 tmp7 d:3
***** BB06, stmt 27
( 2, 3) [000190] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000188] ------------ | * PHI int
N001 ( 0, 0) [000265] ------------ | /--* PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ | \--* PHI_ARG int V05 tmp4 u:6 $283
N007 ( 2, 3) [000189] -A------R--- \--* ASG int
N006 ( 1, 1) [000187] D------N---- \--* LCL_VAR int V05 tmp4 d:7
***** BB06, stmt 28
( 4, 4) [000106] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000102] ------------ | /--* CNS_INT int 1 $4b
N004 ( 4, 4) [000103] ------------ | /--* ADD int $20a
N002 ( 2, 2) [000101] ------------ | | \--* HWIntrinsic int TrailingZeroCount $400
N001 ( 1, 1) [000100] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 $285
N006 ( 4, 4) [000105] -A------R--- \--* ASG int $20a
N005 ( 1, 1) [000104] D------N---- \--* LCL_VAR int V10 tmp9 d:2 $20a
***** BB06, stmt 29
( 4, 5) [000113] ------------ * STMT void (IL 0x000... ???)
N003 ( 2, 3) [000109] ---------U-- | /--* CAST long <- ulong <- uint $24a
N002 ( 1, 1) [000108] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 $20a
N004 ( 4, 5) [000110] ------------ | /--* ADD long $24b
N001 ( 1, 1) [000107] ------------ | | \--* LCL_VAR long V09 tmp8 u:3 (last use) $145
N006 ( 4, 5) [000112] -A------R--- \--* ASG long $24b
N005 ( 1, 1) [000111] D------N---- \--* LCL_VAR long V09 tmp8 d:4 $24b
***** BB06, stmt 30
( 3, 3) [000119] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000115] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | /--* ADD int $20b
N001 ( 1, 1) [000114] ------------ | | \--* LCL_VAR int V05 tmp4 u:7 (last use) $286
N005 ( 3, 3) [000118] -A------R--- \--* ASG int $20b
N004 ( 1, 1) [000117] D------N---- \--* LCL_VAR int V05 tmp4 d:8 $20b
***** BB06, stmt 31
( 8, 5) [000127] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000122] ------------ | /--* CNS_INT int 31 $4d
N004 ( 3, 3) [000123] ------------ | /--* AND int $20c
N002 ( 1, 1) [000121] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 (last use) $20a
N005 ( 8, 5) [000124] ------------ | /--* RSZ int $20d
N001 ( 1, 1) [000120] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 (last use) $285
N007 ( 8, 5) [000126] -A------R--- \--* ASG int $20d
N006 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V08 tmp7 d:4 $20d
***** BB06, stmt 32
( 5, 5) [000098] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000097] ------------ \--* JTRUE void
N002 ( 1, 1) [000095] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000096] J------N---- \--* GT int $20e
N001 ( 1, 1) [000094] ------------ \--* LCL_VAR int V05 tmp4 u:8 $20b
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 33
( 2, 3) [000198] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000196] ------------ | * PHI long
N001 ( 0, 0) [000259] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ | \--* PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
N007 ( 2, 3) [000197] -A------R--- \--* ASG long
N006 ( 1, 1) [000195] D------N---- \--* LCL_VAR long V09 tmp8 d:5
***** BB07, stmt 34
( 4, 4) [000011] ------------ * STMT void (IL ???... ???)
N004 ( 4, 4) [000010] ------------ \--* RETURN int $1c7
N002 ( 1, 1) [000131] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000132] ------------ \--* ADD int $210
N001 ( 1, 1) [000129] C----------- \--* LCL_VAR int V09 tmp8 u:5 (last use) $20f
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000147] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000176] ------------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
N004 ( 5, 12) [000146] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000145] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000150] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000149] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000148] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
***** BB01, stmt 4
( 1, 3) [000020] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000017] ------------ | /--* LCL_VAR int V04 tmp3 u:2 $80
N003 ( 1, 3) [000019] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000018] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $80
***** BB01, stmt 5
( 5, 5) [000181] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000180] ------------ \--* JTRUE void
N002 ( 1, 1) [000179] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000177] J------N---- \--* LE int $200
N001 ( 1, 1) [000178] ------------ \--* LCL_VAR int V05 tmp4 u:2 $80
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 6
( 2, 3) [000226] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000224] ------------ | * PHI long
N001 ( 0, 0) [000239] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000225] -A------R--- \--* ASG long
N006 ( 1, 1) [000223] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 7
( 2, 3) [000214] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000212] ------------ | * PHI int
N001 ( 0, 0) [000241] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000213] -A------R--- \--* ASG int
N006 ( 1, 1) [000211] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 8
( 1, 3) [000031] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000028] ------------ | /--* LCL_VAR int V04 tmp3 u:3 $280
N003 ( 1, 3) [000030] -A------R--- \--* ASG int $280
N002 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $280
***** BB02, stmt 9
( 1, 3) [000041] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000033] ------------ | /--* LCL_VAR long V03 tmp2 u:3 $141
N003 ( 1, 3) [000040] -A------R--- \--* ASG long $141
N002 ( 1, 1) [000039] D------N---- \--* LCL_VAR long V06 tmp5 d:2 $141
***** BB02, stmt 10
( 3, 3) [000044] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000036] ------------ | /--* CNS_INT long 8 $340
N003 ( 3, 3) [000037] ------------ | /--* ADD long $241
N001 ( 1, 1) [000034] ------------ | | \--* LCL_VAR long V06 tmp5 u:2 (last use) $141
N005 ( 3, 3) [000043] -A------R--- \--* ASG long $241
N004 ( 1, 1) [000038] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $241
***** BB02, stmt 11
( 7, 7) [000052] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000047] ---XG------- | /--* CAST int <- long $201
N004 ( 4, 3) [000046] ---XG------- | | \--* HWIntrinsic long PopCount $380
N003 ( 3, 2) [000045] *--XG------- | | \--* IND long <l:$142, c:$302>
N002 ( 1, 1) [000042] ------------ | | \--* LCL_VAR long V06 tmp5 u:2 (last use) $141
N006 ( 7, 7) [000048] ---XG------- | /--* SUB int $202
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR int V05 tmp4 u:3 (last use) $280
N008 ( 7, 7) [000051] -A-XG---R--- \--* ASG int $202
N007 ( 1, 1) [000050] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $202
***** BB02, stmt 12
( 5, 5) [000026] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000025] ------------ \--* JTRUE void
N002 ( 1, 1) [000023] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000024] J------N---- \--* GT int $203
N001 ( 1, 1) [000022] ------------ \--* LCL_VAR int V04 tmp3 u:4 $202
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 13
( 2, 3) [000222] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000220] ------------ | * PHI long
N001 ( 0, 0) [000235] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000221] -A------R--- \--* ASG long
N006 ( 1, 1) [000219] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 14
( 2, 3) [000218] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000216] ------------ | * PHI int
N001 ( 0, 0) [000237] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ | \--* PHI_ARG int V05 tmp4 u:2 $80
N007 ( 2, 3) [000217] -A------R--- \--* ASG int
N006 ( 1, 1) [000215] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB03, stmt 15
( 3, 3) [000060] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000056] ------------ | /--* CNS_INT long -8 $342
N003 ( 3, 3) [000057] ------------ | /--* ADD long $242
N001 ( 1, 1) [000054] ------------ | | \--* LCL_VAR long V03 tmp2 u:5 (last use) $143
N005 ( 3, 3) [000059] -A------R--- \--* ASG long $242
N004 ( 1, 1) [000058] D------N---- \--* LCL_VAR long V07 tmp6 d:2 $242
***** BB03, stmt 16
( 6, 5) [000069] ------------ * STMT void (IL 0x000... ???)
N004 ( 4, 3) [000064] ---XG------- | /--* HWIntrinsic int PopCount $3c0
N003 ( 3, 2) [000063] *--XG------- | | \--* IND int <l:$282, c:$1c2>
N002 ( 1, 1) [000062] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 $242
N005 ( 6, 5) [000065] ---XG------- | /--* SUB int $205
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR int V05 tmp4 u:4 $281
N007 ( 6, 5) [000068] -A-XG---R--- \--* ASG int $205
N006 ( 1, 1) [000067] D------N---- \--* LCL_VAR int V04 tmp3 d:5 $205
***** BB03, stmt 17
( 5, 5) [000074] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000073] ------------ \--* JTRUE void
N002 ( 1, 1) [000071] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000072] J------N---- \--* LE int $206
N001 ( 1, 1) [000070] ------------ \--* LCL_VAR int V04 tmp3 u:5 $205
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 18
( 1, 3) [000137] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000134] ------------ | /--* LCL_VAR int V04 tmp3 u:5 (last use) $205
N003 ( 1, 3) [000136] -A------R--- \--* ASG int $205
N002 ( 1, 1) [000135] D------N---- \--* LCL_VAR int V05 tmp4 d:5 $205
***** BB04, stmt 19
( 3, 3) [000144] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000140] ------------ | /--* CNS_INT long 4 $343
N003 ( 3, 3) [000141] ------------ | /--* ADD long $243
N001 ( 1, 1) [000138] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 (last use) $242
N005 ( 3, 3) [000143] -A------R--- \--* ASG long $243
N004 ( 1, 1) [000142] D------N---- \--* LCL_VAR long V07 tmp6 d:3 $243
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 20
( 6, 5) [000210] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000208] ------------ | * PHI long
N001 ( 0, 0) [000247] ------------ | /--* PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ | \--* PHI_ARG long V07 tmp6 u:2 $242
N007 ( 6, 5) [000209] -A------R--- \--* ASG long
N006 ( 3, 2) [000207] D------N---- \--* LCL_VAR long V07 tmp6 d:4
***** BB05, stmt 21
( 2, 3) [000206] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000204] ------------ | * PHI int
N001 ( 0, 0) [000249] ------------ | /--* PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ | \--* PHI_ARG int V05 tmp4 u:4 $281
N007 ( 2, 3) [000205] -A------R--- \--* ASG int
N006 ( 1, 1) [000203] D------N---- \--* LCL_VAR int V05 tmp4 d:6
***** BB05, stmt 22
( 3, 3) [000080] ------------ * STMT void (IL 0x000... ???)
N002 ( 3, 2) [000077] *--XG------- | /--* IND int <l:$284, c:$1c5>
N001 ( 1, 1) [000076] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 $144
N004 ( 3, 3) [000079] -A-XG---R--- \--* ASG int <l:$284, c:$1c5>
N003 ( 1, 1) [000078] D------N---- \--* LCL_VAR int V08 tmp7 d:2 <l:$284, c:$1c5>
***** BB05, stmt 23
( 26, 9) [000092] ------------ * STMT void (IL 0x000... ???)
N006 ( 1, 1) [000088] ------------ | /--* CNS_INT long 5 $345
N007 ( 26, 9) [000089] ------------ | /--* LSH long <l:$248, c:$249>
N004 ( 1, 1) [000085] ------------ | | | /--* CNS_INT long 4 $343
N005 ( 24, 7) [000086] ------------ | | \--* DIV long <l:$246, c:$247>
N002 ( 1, 1) [000082] ------------ | | | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000083] ------------ | | \--* SUB long <l:$244, c:$245>
N001 ( 1, 1) [000081] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 (last use) $144
N009 ( 26, 9) [000091] -A------R--- \--* ASG long <l:$248, c:$249>
N008 ( 1, 1) [000090] D------N---- \--* LCL_VAR long V09 tmp8 d:2 <l:$248, c:$249>
***** BB05, stmt 24
( 5, 5) [000186] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000185] ------------ \--* JTRUE void
N002 ( 1, 1) [000184] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000182] J------N---- \--* LE int $208
N001 ( 1, 1) [000183] ------------ \--* LCL_VAR int V05 tmp4 u:6 $283
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
( 2, 3) [000202] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000200] ------------ | * PHI long
N001 ( 0, 0) [000261] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ | \--* PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
N007 ( 2, 3) [000201] -A------R--- \--* ASG long
N006 ( 1, 1) [000199] D------N---- \--* LCL_VAR long V09 tmp8 d:3
***** BB06, stmt 26
( 2, 3) [000194] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000192] ------------ | * PHI int
N001 ( 0, 0) [000263] ------------ | /--* PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ | \--* PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
N007 ( 2, 3) [000193] -A------R--- \--* ASG int
N006 ( 1, 1) [000191] D------N---- \--* LCL_VAR int V08 tmp7 d:3
***** BB06, stmt 27
( 2, 3) [000190] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000188] ------------ | * PHI int
N001 ( 0, 0) [000265] ------------ | /--* PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ | \--* PHI_ARG int V05 tmp4 u:6 $283
N007 ( 2, 3) [000189] -A------R--- \--* ASG int
N006 ( 1, 1) [000187] D------N---- \--* LCL_VAR int V05 tmp4 d:7
***** BB06, stmt 28
( 4, 4) [000106] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000102] ------------ | /--* CNS_INT int 1 $4b
N004 ( 4, 4) [000103] ------------ | /--* ADD int $20a
N002 ( 2, 2) [000101] ------------ | | \--* HWIntrinsic int TrailingZeroCount $400
N001 ( 1, 1) [000100] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 $285
N006 ( 4, 4) [000105] -A------R--- \--* ASG int $20a
N005 ( 1, 1) [000104] D------N---- \--* LCL_VAR int V10 tmp9 d:2 $20a
***** BB06, stmt 29
( 4, 5) [000113] ------------ * STMT void (IL 0x000... ???)
N003 ( 2, 3) [000109] ---------U-- | /--* CAST long <- ulong <- uint $24a
N002 ( 1, 1) [000108] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 $20a
N004 ( 4, 5) [000110] ------------ | /--* ADD long $24b
N001 ( 1, 1) [000107] ------------ | | \--* LCL_VAR long V09 tmp8 u:3 (last use) $145
N006 ( 4, 5) [000112] -A------R--- \--* ASG long $24b
N005 ( 1, 1) [000111] D------N---- \--* LCL_VAR long V09 tmp8 d:4 $24b
***** BB06, stmt 30
( 3, 3) [000119] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000115] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | /--* ADD int $20b
N001 ( 1, 1) [000114] ------------ | | \--* LCL_VAR int V05 tmp4 u:7 (last use) $286
N005 ( 3, 3) [000118] -A------R--- \--* ASG int $20b
N004 ( 1, 1) [000117] D------N---- \--* LCL_VAR int V05 tmp4 d:8 $20b
***** BB06, stmt 31
( 8, 5) [000127] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000122] ------------ | /--* CNS_INT int 31 $4d
N004 ( 3, 3) [000123] ------------ | /--* AND int $20c
N002 ( 1, 1) [000121] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 (last use) $20a
N005 ( 8, 5) [000124] ------------ | /--* RSZ int $20d
N001 ( 1, 1) [000120] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 (last use) $285
N007 ( 8, 5) [000126] -A------R--- \--* ASG int $20d
N006 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V08 tmp7 d:4 $20d
***** BB06, stmt 32
( 5, 5) [000098] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000097] ------------ \--* JTRUE void
N002 ( 1, 1) [000095] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000096] J------N---- \--* GT int $20e
N001 ( 1, 1) [000094] ------------ \--* LCL_VAR int V05 tmp4 u:8 $20b
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 33
( 2, 3) [000198] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000196] ------------ | * PHI long
N001 ( 0, 0) [000259] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ | \--* PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
N007 ( 2, 3) [000197] -A------R--- \--* ASG long
N006 ( 1, 1) [000195] D------N---- \--* LCL_VAR long V09 tmp8 d:5
***** BB07, stmt 34
( 4, 4) [000011] ------------ * STMT void (IL ???... ???)
N004 ( 4, 4) [000010] ------------ \--* RETURN int $1c7
N002 ( 1, 1) [000131] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000132] ------------ \--* ADD int $210
N001 ( 1, 1) [000129] C----------- \--* LCL_VAR int V09 tmp8 u:5 (last use) $20f
-------------------------------------------------------------------------------------------------------------------
GenTreeNode creates assertion:
N004 ( 5, 5) [000180] ------------ * JTRUE void
In BB01 New Global Constant Assertion: (512, 64) ($200,$40) Loop_Bnd {LE($80, $40)} is not {IntCns 0} index=#01, mask=0000000000000001
GenTreeNode creates assertion:
N004 ( 5, 5) [000180] ------------ * JTRUE void
In BB01 New Global Constant Assertion: (512, 64) ($200,$40) Loop_Bnd {LE($80, $40)} is {IntCns 0} index=#02, mask=0000000000000002
GenTreeNode creates assertion:
N004 ( 5, 5) [000025] ------------ * JTRUE void
In BB02 New Global Constant Assertion: (515, 64) ($203,$40) Loop_Bnd {GT($202, $40)} is not {IntCns 0} index=#03, mask=0000000000000004
GenTreeNode creates assertion:
N004 ( 5, 5) [000025] ------------ * JTRUE void
In BB02 New Global Constant Assertion: (515, 64) ($203,$40) Loop_Bnd {GT($202, $40)} is {IntCns 0} index=#04, mask=0000000000000008
GenTreeNode creates assertion:
N004 ( 5, 5) [000073] ------------ * JTRUE void
In BB03 New Global Constant Assertion: (518, 64) ($206,$40) Loop_Bnd {LE($205, $40)} is not {IntCns 0} index=#05, mask=0000000000000010
GenTreeNode creates assertion:
N004 ( 5, 5) [000073] ------------ * JTRUE void
In BB03 New Global Constant Assertion: (518, 64) ($206,$40) Loop_Bnd {LE($205, $40)} is {IntCns 0} index=#06, mask=0000000000000020
GenTreeNode creates assertion:
N004 ( 5, 5) [000185] ------------ * JTRUE void
In BB05 New Global Constant Assertion: (520, 64) ($208,$40) Loop_Bnd {LE($283, $40)} is not {IntCns 0} index=#07, mask=0000000000000040
GenTreeNode creates assertion:
N004 ( 5, 5) [000185] ------------ * JTRUE void
In BB05 New Global Constant Assertion: (520, 64) ($208,$40) Loop_Bnd {LE($283, $40)} is {IntCns 0} index=#08, mask=0000000000000080
GenTreeNode creates assertion:
N004 ( 5, 5) [000097] ------------ * JTRUE void
In BB06 New Global Constant Assertion: (526, 64) ($20e,$40) Loop_Bnd {GT($20b, $40)} is not {IntCns 0} index=#09, mask=0000000000000100
GenTreeNode creates assertion:
N004 ( 5, 5) [000097] ------------ * JTRUE void
In BB06 New Global Constant Assertion: (526, 64) ($20e,$40) Loop_Bnd {GT($20b, $40)} is {IntCns 0} index=#10, mask=0000000000000200
BB01 valueGen = 0000000000000002 => BB03 valueGen = 0000000000000001,
BB02 valueGen = 0000000000000008 => BB02 valueGen = 0000000000000004,
BB03 valueGen = 0000000000000020 => BB05 valueGen = 0000000000000010,
BB04 valueGen = 0000000000000000
BB05 valueGen = 0000000000000080 => BB07 valueGen = 0000000000000040,
BB06 valueGen = 0000000000000200 => BB06 valueGen = 0000000000000100,
BB07 valueGen = 0000000000000000AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000
AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000
AssertionPropCallback::Changed : BB01 before out -> 00000000000003FF; after out -> 0000000000000002;
jumpDest before out -> 00000000000003FF; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB02 in -> 00000000000003FF
AssertionPropCallback::Merge : BB02 in -> 00000000000003FF, predBlock BB01 out -> 0000000000000002
AssertionPropCallback::Merge : BB02 in -> 0000000000000002, predBlock BB02 out -> 00000000000003FF
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000002
AssertionPropCallback::Changed : BB02 before out -> 00000000000003FF; after out -> 000000000000000A;
jumpDest before out -> 00000000000003FF; jumpDest after out -> 0000000000000006;
AssertionPropCallback::StartMerge: BB03 in -> 00000000000003FF
AssertionPropCallback::Merge : BB03 in -> 00000000000003FF, predBlock BB01 out -> 0000000000000002
AssertionPropCallback::Merge : BB03 in -> 0000000000000001, predBlock BB02 out -> 000000000000000A
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000
AssertionPropCallback::Changed : BB03 before out -> 00000000000003FF; after out -> 0000000000000020;
jumpDest before out -> 00000000000003FF; jumpDest after out -> 0000000000000010;
AssertionPropCallback::StartMerge: BB03 in -> 0000000000000000
AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB01 out -> 0000000000000002
AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB02 out -> 000000000000000A
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000
AssertionPropCallback::Unchanged : BB03 out -> 0000000000000020; jumpDest out -> 0000000000000010
AssertionPropCallback::StartMerge: BB02 in -> 0000000000000002
AssertionPropCallback::Merge : BB02 in -> 0000000000000002, predBlock BB01 out -> 0000000000000002
AssertionPropCallback::Merge : BB02 in -> 0000000000000002, predBlock BB02 out -> 000000000000000A
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000002
AssertionPropCallback::Unchanged : BB02 out -> 000000000000000A; jumpDest out -> 0000000000000006
AssertionPropCallback::StartMerge: BB04 in -> 00000000000003FF
AssertionPropCallback::Merge : BB04 in -> 00000000000003FF, predBlock BB03 out -> 0000000000000020
AssertionPropCallback::EndMerge : BB04 in -> 0000000000000020
AssertionPropCallback::Changed : BB04 before out -> 00000000000003FF; after out -> 0000000000000020;
jumpDest before out -> 00000000000003FF; jumpDest after out -> 0000000000000020;
AssertionPropCallback::StartMerge: BB05 in -> 00000000000003FF
AssertionPropCallback::Merge : BB05 in -> 00000000000003FF, predBlock BB03 out -> 0000000000000020
AssertionPropCallback::Merge : BB05 in -> 0000000000000010, predBlock BB04 out -> 0000000000000020
AssertionPropCallback::EndMerge : BB05 in -> 0000000000000000
AssertionPropCallback::Changed : BB05 before out -> 00000000000003FF; after out -> 0000000000000080;
jumpDest before out -> 00000000000003FF; jumpDest after out -> 0000000000000040;
AssertionPropCallback::StartMerge: BB05 in -> 0000000000000000
AssertionPropCallback::Merge : BB05 in -> 0000000000000000, predBlock BB03 out -> 0000000000000020
AssertionPropCallback::Merge : BB05 in -> 0000000000000000, predBlock BB04 out -> 0000000000000020
AssertionPropCallback::EndMerge : BB05 in -> 0000000000000000
AssertionPropCallback::Unchanged : BB05 out -> 0000000000000080; jumpDest out -> 0000000000000040
AssertionPropCallback::StartMerge: BB06 in -> 00000000000003FF
AssertionPropCallback::Merge : BB06 in -> 00000000000003FF, predBlock BB05 out -> 0000000000000080
AssertionPropCallback::Merge : BB06 in -> 0000000000000080, predBlock BB06 out -> 00000000000003FF
AssertionPropCallback::EndMerge : BB06 in -> 0000000000000080
AssertionPropCallback::Changed : BB06 before out -> 00000000000003FF; after out -> 0000000000000280;
jumpDest before out -> 00000000000003FF; jumpDest after out -> 0000000000000180;
AssertionPropCallback::StartMerge: BB07 in -> 00000000000003FF
AssertionPropCallback::Merge : BB07 in -> 00000000000003FF, predBlock BB05 out -> 0000000000000080
AssertionPropCallback::Merge : BB07 in -> 0000000000000040, predBlock BB06 out -> 0000000000000280
AssertionPropCallback::EndMerge : BB07 in -> 0000000000000000
AssertionPropCallback::Changed : BB07 before out -> 00000000000003FF; after out -> 0000000000000000;
jumpDest before out -> 00000000000003FF; jumpDest after out -> 0000000000000000;
AssertionPropCallback::StartMerge: BB07 in -> 0000000000000000
AssertionPropCallback::Merge : BB07 in -> 0000000000000000, predBlock BB05 out -> 0000000000000080
AssertionPropCallback::Merge : BB07 in -> 0000000000000000, predBlock BB06 out -> 0000000000000280
AssertionPropCallback::EndMerge : BB07 in -> 0000000000000000
AssertionPropCallback::Unchanged : BB07 out -> 0000000000000000; jumpDest out -> 0000000000000000
AssertionPropCallback::StartMerge: BB06 in -> 0000000000000080
AssertionPropCallback::Merge : BB06 in -> 0000000000000080, predBlock BB05 out -> 0000000000000080
AssertionPropCallback::Merge : BB06 in -> 0000000000000080, predBlock BB06 out -> 0000000000000280
AssertionPropCallback::EndMerge : BB06 in -> 0000000000000080
AssertionPropCallback::Unchanged : BB06 out -> 0000000000000280; jumpDest out -> 0000000000000180
BB01 valueIn = 0000000000000000 valueOut = 0000000000000002 => BB03 valueOut= 0000000000000001
BB02 valueIn = 0000000000000002 valueOut = 000000000000000A => BB02 valueOut= 0000000000000006
BB03 valueIn = 0000000000000000 valueOut = 0000000000000020 => BB05 valueOut= 0000000000000010
BB04 valueIn = 0000000000000020 valueOut = 0000000000000020
BB05 valueIn = 0000000000000000 valueOut = 0000000000000080 => BB07 valueOut= 0000000000000040
BB06 valueIn = 0000000000000080 valueOut = 0000000000000280 => BB06 valueOut= 0000000000000180
BB07 valueIn = 0000000000000000 valueOut = 0000000000000000
Propagating 0000000000000000 assertions for BB01, stmt [000147], tree [000176], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000147], tree [000001], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000147], tree [000145], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000147], tree [000146], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000150], tree [000003], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000150], tree [000148], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000150], tree [000149], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000016], tree [000013], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000016], tree [000014], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000016], tree [000015], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000020], tree [000017], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000020], tree [000018], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000020], tree [000019], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000181], tree [000178], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000181], tree [000179], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt [000181], tree [000177], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000031], tree [000028], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000031], tree [000029], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000031], tree [000030], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000041], tree [000033], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000041], tree [000039], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000041], tree [000040], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000044], tree [000034], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000044], tree [000036], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000044], tree [000037], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000044], tree [000038], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000044], tree [000043], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000052], tree [000032], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000052], tree [000042], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000052], tree [000045], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000052], tree [000046], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000052], tree [000047], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000052], tree [000048], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000052], tree [000050], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000052], tree [000051], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000026], tree [000022], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000026], tree [000023], tree -> 0
Propagating 0000000000000002 assertions for BB02, stmt [000026], tree [000024], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000060], tree [000054], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000060], tree [000056], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000060], tree [000057], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000060], tree [000058], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000060], tree [000059], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000069], tree [000061], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000069], tree [000062], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000069], tree [000063], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000069], tree [000064], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000069], tree [000065], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000069], tree [000067], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000069], tree [000068], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000074], tree [000070], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000074], tree [000071], tree -> 0
Propagating 0000000000000000 assertions for BB03, stmt [000074], tree [000072], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000137], tree [000134], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000137], tree [000135], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000137], tree [000136], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000144], tree [000138], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000144], tree [000140], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000144], tree [000141], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000144], tree [000142], tree -> 0
Propagating 0000000000000020 assertions for BB04, stmt [000144], tree [000143], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000080], tree [000076], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000080], tree [000077], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000080], tree [000078], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000080], tree [000079], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000092], tree [000081], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000092], tree [000082], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000092], tree [000083], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000092], tree [000085], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000092], tree [000086], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000092], tree [000088], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000092], tree [000089], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000092], tree [000090], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000092], tree [000091], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000186], tree [000183], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000186], tree [000184], tree -> 0
Propagating 0000000000000000 assertions for BB05, stmt [000186], tree [000182], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000106], tree [000100], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000106], tree [000101], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000106], tree [000102], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000106], tree [000103], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000106], tree [000104], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000106], tree [000105], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000113], tree [000107], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000113], tree [000108], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000113], tree [000109], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000113], tree [000110], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000113], tree [000111], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000113], tree [000112], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000119], tree [000114], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000119], tree [000115], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000119], tree [000116], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000119], tree [000117], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000119], tree [000118], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000127], tree [000120], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000127], tree [000121], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000127], tree [000122], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000127], tree [000123], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000127], tree [000124], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000127], tree [000125], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000127], tree [000126], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000098], tree [000094], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000098], tree [000095], tree -> 0
Propagating 0000000000000080 assertions for BB06, stmt [000098], tree [000096], tree -> 0
Propagating 0000000000000000 assertions for BB07, stmt [000011], tree [000129], tree -> 0
Propagating 0000000000000000 assertions for BB07, stmt [000011], tree [000131], tree -> 0
Propagating 0000000000000000 assertions for BB07, stmt [000011], tree [000132], tree -> 0
Propagating 0000000000000000 assertions for BB07, stmt [000011], tree [000010], tree -> 0
*************** In fgDebugCheckBBlist
*************** In OptimizeRangeChecks()
Blocks/trees before phase
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000147] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000176] ------------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
N004 ( 5, 12) [000146] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000145] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000150] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000149] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000148] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
***** BB01, stmt 4
( 1, 3) [000020] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000017] ------------ | /--* LCL_VAR int V04 tmp3 u:2 $80
N003 ( 1, 3) [000019] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000018] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $80
***** BB01, stmt 5
( 5, 5) [000181] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000180] ------------ \--* JTRUE void
N002 ( 1, 1) [000179] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000177] J------N---- \--* LE int $200
N001 ( 1, 1) [000178] ------------ \--* LCL_VAR int V05 tmp4 u:2 $80
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 6
( 2, 3) [000226] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000224] ------------ | * PHI long
N001 ( 0, 0) [000239] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000225] -A------R--- \--* ASG long
N006 ( 1, 1) [000223] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 7
( 2, 3) [000214] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000212] ------------ | * PHI int
N001 ( 0, 0) [000241] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000213] -A------R--- \--* ASG int
N006 ( 1, 1) [000211] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 8
( 1, 3) [000031] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000028] ------------ | /--* LCL_VAR int V04 tmp3 u:3 $280
N003 ( 1, 3) [000030] -A------R--- \--* ASG int $280
N002 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $280
***** BB02, stmt 9
( 1, 3) [000041] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000033] ------------ | /--* LCL_VAR long V03 tmp2 u:3 $141
N003 ( 1, 3) [000040] -A------R--- \--* ASG long $141
N002 ( 1, 1) [000039] D------N---- \--* LCL_VAR long V06 tmp5 d:2 $141
***** BB02, stmt 10
( 3, 3) [000044] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000036] ------------ | /--* CNS_INT long 8 $340
N003 ( 3, 3) [000037] ------------ | /--* ADD long $241
N001 ( 1, 1) [000034] ------------ | | \--* LCL_VAR long V06 tmp5 u:2 (last use) $141
N005 ( 3, 3) [000043] -A------R--- \--* ASG long $241
N004 ( 1, 1) [000038] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $241
***** BB02, stmt 11
( 7, 7) [000052] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000047] ---XG------- | /--* CAST int <- long $201
N004 ( 4, 3) [000046] ---XG------- | | \--* HWIntrinsic long PopCount $380
N003 ( 3, 2) [000045] *--XG------- | | \--* IND long <l:$142, c:$302>
N002 ( 1, 1) [000042] ------------ | | \--* LCL_VAR long V06 tmp5 u:2 (last use) $141
N006 ( 7, 7) [000048] ---XG------- | /--* SUB int $202
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR int V05 tmp4 u:3 (last use) $280
N008 ( 7, 7) [000051] -A-XG---R--- \--* ASG int $202
N007 ( 1, 1) [000050] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $202
***** BB02, stmt 12
( 5, 5) [000026] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000025] ------------ \--* JTRUE void
N002 ( 1, 1) [000023] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000024] J------N---- \--* GT int $203
N001 ( 1, 1) [000022] ------------ \--* LCL_VAR int V04 tmp3 u:4 $202
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 13
( 2, 3) [000222] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000220] ------------ | * PHI long
N001 ( 0, 0) [000235] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000221] -A------R--- \--* ASG long
N006 ( 1, 1) [000219] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 14
( 2, 3) [000218] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000216] ------------ | * PHI int
N001 ( 0, 0) [000237] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ | \--* PHI_ARG int V05 tmp4 u:2 $80
N007 ( 2, 3) [000217] -A------R--- \--* ASG int
N006 ( 1, 1) [000215] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB03, stmt 15
( 3, 3) [000060] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000056] ------------ | /--* CNS_INT long -8 $342
N003 ( 3, 3) [000057] ------------ | /--* ADD long $242
N001 ( 1, 1) [000054] ------------ | | \--* LCL_VAR long V03 tmp2 u:5 (last use) $143
N005 ( 3, 3) [000059] -A------R--- \--* ASG long $242
N004 ( 1, 1) [000058] D------N---- \--* LCL_VAR long V07 tmp6 d:2 $242
***** BB03, stmt 16
( 6, 5) [000069] ------------ * STMT void (IL 0x000... ???)
N004 ( 4, 3) [000064] ---XG------- | /--* HWIntrinsic int PopCount $3c0
N003 ( 3, 2) [000063] *--XG------- | | \--* IND int <l:$282, c:$1c2>
N002 ( 1, 1) [000062] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 $242
N005 ( 6, 5) [000065] ---XG------- | /--* SUB int $205
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR int V05 tmp4 u:4 $281
N007 ( 6, 5) [000068] -A-XG---R--- \--* ASG int $205
N006 ( 1, 1) [000067] D------N---- \--* LCL_VAR int V04 tmp3 d:5 $205
***** BB03, stmt 17
( 5, 5) [000074] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000073] ------------ \--* JTRUE void
N002 ( 1, 1) [000071] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000072] J------N---- \--* LE int $206
N001 ( 1, 1) [000070] ------------ \--* LCL_VAR int V04 tmp3 u:5 $205
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 18
( 1, 3) [000137] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000134] ------------ | /--* LCL_VAR int V04 tmp3 u:5 (last use) $205
N003 ( 1, 3) [000136] -A------R--- \--* ASG int $205
N002 ( 1, 1) [000135] D------N---- \--* LCL_VAR int V05 tmp4 d:5 $205
***** BB04, stmt 19
( 3, 3) [000144] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000140] ------------ | /--* CNS_INT long 4 $343
N003 ( 3, 3) [000141] ------------ | /--* ADD long $243
N001 ( 1, 1) [000138] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 (last use) $242
N005 ( 3, 3) [000143] -A------R--- \--* ASG long $243
N004 ( 1, 1) [000142] D------N---- \--* LCL_VAR long V07 tmp6 d:3 $243
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 20
( 6, 5) [000210] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000208] ------------ | * PHI long
N001 ( 0, 0) [000247] ------------ | /--* PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ | \--* PHI_ARG long V07 tmp6 u:2 $242
N007 ( 6, 5) [000209] -A------R--- \--* ASG long
N006 ( 3, 2) [000207] D------N---- \--* LCL_VAR long V07 tmp6 d:4
***** BB05, stmt 21
( 2, 3) [000206] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000204] ------------ | * PHI int
N001 ( 0, 0) [000249] ------------ | /--* PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ | \--* PHI_ARG int V05 tmp4 u:4 $281
N007 ( 2, 3) [000205] -A------R--- \--* ASG int
N006 ( 1, 1) [000203] D------N---- \--* LCL_VAR int V05 tmp4 d:6
***** BB05, stmt 22
( 3, 3) [000080] ------------ * STMT void (IL 0x000... ???)
N002 ( 3, 2) [000077] *--XG------- | /--* IND int <l:$284, c:$1c5>
N001 ( 1, 1) [000076] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 $144
N004 ( 3, 3) [000079] -A-XG---R--- \--* ASG int <l:$284, c:$1c5>
N003 ( 1, 1) [000078] D------N---- \--* LCL_VAR int V08 tmp7 d:2 <l:$284, c:$1c5>
***** BB05, stmt 23
( 26, 9) [000092] ------------ * STMT void (IL 0x000... ???)
N006 ( 1, 1) [000088] ------------ | /--* CNS_INT long 5 $345
N007 ( 26, 9) [000089] ------------ | /--* LSH long <l:$248, c:$249>
N004 ( 1, 1) [000085] ------------ | | | /--* CNS_INT long 4 $343
N005 ( 24, 7) [000086] ------------ | | \--* DIV long <l:$246, c:$247>
N002 ( 1, 1) [000082] ------------ | | | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000083] ------------ | | \--* SUB long <l:$244, c:$245>
N001 ( 1, 1) [000081] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 (last use) $144
N009 ( 26, 9) [000091] -A------R--- \--* ASG long <l:$248, c:$249>
N008 ( 1, 1) [000090] D------N---- \--* LCL_VAR long V09 tmp8 d:2 <l:$248, c:$249>
***** BB05, stmt 24
( 5, 5) [000186] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000185] ------------ \--* JTRUE void
N002 ( 1, 1) [000184] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000182] J------N---- \--* LE int $208
N001 ( 1, 1) [000183] ------------ \--* LCL_VAR int V05 tmp4 u:6 $283
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
( 2, 3) [000202] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000200] ------------ | * PHI long
N001 ( 0, 0) [000261] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ | \--* PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
N007 ( 2, 3) [000201] -A------R--- \--* ASG long
N006 ( 1, 1) [000199] D------N---- \--* LCL_VAR long V09 tmp8 d:3
***** BB06, stmt 26
( 2, 3) [000194] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000192] ------------ | * PHI int
N001 ( 0, 0) [000263] ------------ | /--* PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ | \--* PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
N007 ( 2, 3) [000193] -A------R--- \--* ASG int
N006 ( 1, 1) [000191] D------N---- \--* LCL_VAR int V08 tmp7 d:3
***** BB06, stmt 27
( 2, 3) [000190] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000188] ------------ | * PHI int
N001 ( 0, 0) [000265] ------------ | /--* PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ | \--* PHI_ARG int V05 tmp4 u:6 $283
N007 ( 2, 3) [000189] -A------R--- \--* ASG int
N006 ( 1, 1) [000187] D------N---- \--* LCL_VAR int V05 tmp4 d:7
***** BB06, stmt 28
( 4, 4) [000106] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000102] ------------ | /--* CNS_INT int 1 $4b
N004 ( 4, 4) [000103] ------------ | /--* ADD int $20a
N002 ( 2, 2) [000101] ------------ | | \--* HWIntrinsic int TrailingZeroCount $400
N001 ( 1, 1) [000100] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 $285
N006 ( 4, 4) [000105] -A------R--- \--* ASG int $20a
N005 ( 1, 1) [000104] D------N---- \--* LCL_VAR int V10 tmp9 d:2 $20a
***** BB06, stmt 29
( 4, 5) [000113] ------------ * STMT void (IL 0x000... ???)
N003 ( 2, 3) [000109] ---------U-- | /--* CAST long <- ulong <- uint $24a
N002 ( 1, 1) [000108] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 $20a
N004 ( 4, 5) [000110] ------------ | /--* ADD long $24b
N001 ( 1, 1) [000107] ------------ | | \--* LCL_VAR long V09 tmp8 u:3 (last use) $145
N006 ( 4, 5) [000112] -A------R--- \--* ASG long $24b
N005 ( 1, 1) [000111] D------N---- \--* LCL_VAR long V09 tmp8 d:4 $24b
***** BB06, stmt 30
( 3, 3) [000119] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000115] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | /--* ADD int $20b
N001 ( 1, 1) [000114] ------------ | | \--* LCL_VAR int V05 tmp4 u:7 (last use) $286
N005 ( 3, 3) [000118] -A------R--- \--* ASG int $20b
N004 ( 1, 1) [000117] D------N---- \--* LCL_VAR int V05 tmp4 d:8 $20b
***** BB06, stmt 31
( 8, 5) [000127] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000122] ------------ | /--* CNS_INT int 31 $4d
N004 ( 3, 3) [000123] ------------ | /--* AND int $20c
N002 ( 1, 1) [000121] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 (last use) $20a
N005 ( 8, 5) [000124] ------------ | /--* RSZ int $20d
N001 ( 1, 1) [000120] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 (last use) $285
N007 ( 8, 5) [000126] -A------R--- \--* ASG int $20d
N006 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V08 tmp7 d:4 $20d
***** BB06, stmt 32
( 5, 5) [000098] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000097] ------------ \--* JTRUE void
N002 ( 1, 1) [000095] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000096] J------N---- \--* GT int $20e
N001 ( 1, 1) [000094] ------------ \--* LCL_VAR int V05 tmp4 u:8 $20b
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 33
( 2, 3) [000198] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000196] ------------ | * PHI long
N001 ( 0, 0) [000259] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ | \--* PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
N007 ( 2, 3) [000197] -A------R--- \--* ASG long
N006 ( 1, 1) [000195] D------N---- \--* LCL_VAR long V09 tmp8 d:5
***** BB07, stmt 34
( 4, 4) [000011] ------------ * STMT void (IL ???... ???)
N004 ( 4, 4) [000010] ------------ \--* RETURN int $1c7
N002 ( 1, 1) [000131] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000132] ------------ \--* ADD int $210
N001 ( 1, 1) [000129] C----------- \--* LCL_VAR int V09 tmp8 u:5 (last use) $20f
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target
BB04 [0005] 1 BB03 0.25 [000..001) i
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 12) [000147] ------------ * STMT void (IL 0x000... ???)
N002 ( 5, 12) [000001] x---G------- | /--* IND long <l:$140, c:$180>
N001 ( 3, 10) [000176] ------------ | | \--* CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
N004 ( 5, 12) [000146] -A--G---R--- \--* ASG long <l:$140, c:$180>
N003 ( 1, 1) [000145] D------N---- \--* LCL_VAR long V02 tmp1 d:2 <l:$140, c:$180>
***** BB01, stmt 2
( 1, 3) [000150] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000003] ------------ | /--* LCL_VAR int V00 arg0 u:2 (last use) $80
N003 ( 1, 3) [000149] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000148] D------N---- \--* LCL_VAR int V04 tmp3 d:2 $80
***** BB01, stmt 3
( 1, 3) [000016] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000013] ------------ | /--* LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
N003 ( 1, 3) [000015] -A------R--- \--* ASG long <l:$140, c:$180>
N002 ( 1, 1) [000014] D------N---- \--* LCL_VAR long V03 tmp2 d:2 <l:$140, c:$180>
***** BB01, stmt 4
( 1, 3) [000020] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000017] ------------ | /--* LCL_VAR int V04 tmp3 u:2 $80
N003 ( 1, 3) [000019] -A------R--- \--* ASG int $80
N002 ( 1, 1) [000018] D------N---- \--* LCL_VAR int V05 tmp4 d:2 $80
***** BB01, stmt 5
( 5, 5) [000181] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000180] ------------ \--* JTRUE void
N002 ( 1, 1) [000179] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000177] J------N---- \--* LE int $200
N001 ( 1, 1) [000178] ------------ \--* LCL_VAR int V05 tmp4 u:2 $80
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
***** BB02, stmt 6
( 2, 3) [000226] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000224] ------------ | * PHI long
N001 ( 0, 0) [000239] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000225] -A------R--- \--* ASG long
N006 ( 1, 1) [000223] D------N---- \--* LCL_VAR long V03 tmp2 d:3
***** BB02, stmt 7
( 2, 3) [000214] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000212] ------------ | * PHI int
N001 ( 0, 0) [000241] ------------ | /--* PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ | \--* PHI_ARG int V04 tmp3 u:2 $80
N007 ( 2, 3) [000213] -A------R--- \--* ASG int
N006 ( 1, 1) [000211] D------N---- \--* LCL_VAR int V04 tmp3 d:3
***** BB02, stmt 8
( 1, 3) [000031] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000028] ------------ | /--* LCL_VAR int V04 tmp3 u:3 $280
N003 ( 1, 3) [000030] -A------R--- \--* ASG int $280
N002 ( 1, 1) [000029] D------N---- \--* LCL_VAR int V05 tmp4 d:3 $280
***** BB02, stmt 9
( 1, 3) [000041] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000033] ------------ | /--* LCL_VAR long V03 tmp2 u:3 $141
N003 ( 1, 3) [000040] -A------R--- \--* ASG long $141
N002 ( 1, 1) [000039] D------N---- \--* LCL_VAR long V06 tmp5 d:2 $141
***** BB02, stmt 10
( 3, 3) [000044] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000036] ------------ | /--* CNS_INT long 8 $340
N003 ( 3, 3) [000037] ------------ | /--* ADD long $241
N001 ( 1, 1) [000034] ------------ | | \--* LCL_VAR long V06 tmp5 u:2 (last use) $141
N005 ( 3, 3) [000043] -A------R--- \--* ASG long $241
N004 ( 1, 1) [000038] D------N---- \--* LCL_VAR long V03 tmp2 d:4 $241
***** BB02, stmt 11
( 7, 7) [000052] ------------ * STMT void (IL 0x000... ???)
N005 ( 5, 5) [000047] ---XG------- | /--* CAST int <- long $201
N004 ( 4, 3) [000046] ---XG------- | | \--* HWIntrinsic long PopCount $380
N003 ( 3, 2) [000045] *--XG------- | | \--* IND long <l:$142, c:$302>
N002 ( 1, 1) [000042] ------------ | | \--* LCL_VAR long V06 tmp5 u:2 (last use) $141
N006 ( 7, 7) [000048] ---XG------- | /--* SUB int $202
N001 ( 1, 1) [000032] ------------ | | \--* LCL_VAR int V05 tmp4 u:3 (last use) $280
N008 ( 7, 7) [000051] -A-XG---R--- \--* ASG int $202
N007 ( 1, 1) [000050] D------N---- \--* LCL_VAR int V04 tmp3 d:4 $202
***** BB02, stmt 12
( 5, 5) [000026] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000025] ------------ \--* JTRUE void
N002 ( 1, 1) [000023] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000024] J------N---- \--* GT int $203
N001 ( 1, 1) [000022] ------------ \--* LCL_VAR int V04 tmp3 u:4 $202
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
***** BB03, stmt 13
( 2, 3) [000222] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000220] ------------ | * PHI long
N001 ( 0, 0) [000235] ------------ | /--* PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ | \--* PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
N007 ( 2, 3) [000221] -A------R--- \--* ASG long
N006 ( 1, 1) [000219] D------N---- \--* LCL_VAR long V03 tmp2 d:5
***** BB03, stmt 14
( 2, 3) [000218] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000216] ------------ | * PHI int
N001 ( 0, 0) [000237] ------------ | /--* PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ | \--* PHI_ARG int V05 tmp4 u:2 $80
N007 ( 2, 3) [000217] -A------R--- \--* ASG int
N006 ( 1, 1) [000215] D------N---- \--* LCL_VAR int V05 tmp4 d:4
***** BB03, stmt 15
( 3, 3) [000060] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000056] ------------ | /--* CNS_INT long -8 $342
N003 ( 3, 3) [000057] ------------ | /--* ADD long $242
N001 ( 1, 1) [000054] ------------ | | \--* LCL_VAR long V03 tmp2 u:5 (last use) $143
N005 ( 3, 3) [000059] -A------R--- \--* ASG long $242
N004 ( 1, 1) [000058] D------N---- \--* LCL_VAR long V07 tmp6 d:2 $242
***** BB03, stmt 16
( 6, 5) [000069] ------------ * STMT void (IL 0x000... ???)
N004 ( 4, 3) [000064] ---XG------- | /--* HWIntrinsic int PopCount $3c0
N003 ( 3, 2) [000063] *--XG------- | | \--* IND int <l:$282, c:$1c2>
N002 ( 1, 1) [000062] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 $242
N005 ( 6, 5) [000065] ---XG------- | /--* SUB int $205
N001 ( 1, 1) [000061] ------------ | | \--* LCL_VAR int V05 tmp4 u:4 $281
N007 ( 6, 5) [000068] -A-XG---R--- \--* ASG int $205
N006 ( 1, 1) [000067] D------N---- \--* LCL_VAR int V04 tmp3 d:5 $205
***** BB03, stmt 17
( 5, 5) [000074] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000073] ------------ \--* JTRUE void
N002 ( 1, 1) [000071] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000072] J------N---- \--* LE int $206
N001 ( 1, 1) [000070] ------------ \--* LCL_VAR int V04 tmp3 u:5 $205
------------ BB04 [000..001), preds={BB03} succs={BB05}
***** BB04, stmt 18
( 1, 3) [000137] ------------ * STMT void (IL 0x000... ???)
N001 ( 1, 1) [000134] ------------ | /--* LCL_VAR int V04 tmp3 u:5 (last use) $205
N003 ( 1, 3) [000136] -A------R--- \--* ASG int $205
N002 ( 1, 1) [000135] D------N---- \--* LCL_VAR int V05 tmp4 d:5 $205
***** BB04, stmt 19
( 3, 3) [000144] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000140] ------------ | /--* CNS_INT long 4 $343
N003 ( 3, 3) [000141] ------------ | /--* ADD long $243
N001 ( 1, 1) [000138] ------------ | | \--* LCL_VAR long V07 tmp6 u:2 (last use) $242
N005 ( 3, 3) [000143] -A------R--- \--* ASG long $243
N004 ( 1, 1) [000142] D------N---- \--* LCL_VAR long V07 tmp6 d:3 $243
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
***** BB05, stmt 20
( 6, 5) [000210] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000208] ------------ | * PHI long
N001 ( 0, 0) [000247] ------------ | /--* PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ | \--* PHI_ARG long V07 tmp6 u:2 $242
N007 ( 6, 5) [000209] -A------R--- \--* ASG long
N006 ( 3, 2) [000207] D------N---- \--* LCL_VAR long V07 tmp6 d:4
***** BB05, stmt 21
( 2, 3) [000206] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000204] ------------ | * PHI int
N001 ( 0, 0) [000249] ------------ | /--* PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ | \--* PHI_ARG int V05 tmp4 u:4 $281
N007 ( 2, 3) [000205] -A------R--- \--* ASG int
N006 ( 1, 1) [000203] D------N---- \--* LCL_VAR int V05 tmp4 d:6
***** BB05, stmt 22
( 3, 3) [000080] ------------ * STMT void (IL 0x000... ???)
N002 ( 3, 2) [000077] *--XG------- | /--* IND int <l:$284, c:$1c5>
N001 ( 1, 1) [000076] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 $144
N004 ( 3, 3) [000079] -A-XG---R--- \--* ASG int <l:$284, c:$1c5>
N003 ( 1, 1) [000078] D------N---- \--* LCL_VAR int V08 tmp7 d:2 <l:$284, c:$1c5>
***** BB05, stmt 23
( 26, 9) [000092] ------------ * STMT void (IL 0x000... ???)
N006 ( 1, 1) [000088] ------------ | /--* CNS_INT long 5 $345
N007 ( 26, 9) [000089] ------------ | /--* LSH long <l:$248, c:$249>
N004 ( 1, 1) [000085] ------------ | | | /--* CNS_INT long 4 $343
N005 ( 24, 7) [000086] ------------ | | \--* DIV long <l:$246, c:$247>
N002 ( 1, 1) [000082] ------------ | | | /--* LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
N003 ( 3, 3) [000083] ------------ | | \--* SUB long <l:$244, c:$245>
N001 ( 1, 1) [000081] ------------ | | \--* LCL_VAR long V07 tmp6 u:4 (last use) $144
N009 ( 26, 9) [000091] -A------R--- \--* ASG long <l:$248, c:$249>
N008 ( 1, 1) [000090] D------N---- \--* LCL_VAR long V09 tmp8 d:2 <l:$248, c:$249>
***** BB05, stmt 24
( 5, 5) [000186] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000185] ------------ \--* JTRUE void
N002 ( 1, 1) [000184] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000182] J------N---- \--* LE int $208
N001 ( 1, 1) [000183] ------------ \--* LCL_VAR int V05 tmp4 u:6 $283
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
***** BB06, stmt 25
( 2, 3) [000202] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000200] ------------ | * PHI long
N001 ( 0, 0) [000261] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ | \--* PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
N007 ( 2, 3) [000201] -A------R--- \--* ASG long
N006 ( 1, 1) [000199] D------N---- \--* LCL_VAR long V09 tmp8 d:3
***** BB06, stmt 26
( 2, 3) [000194] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000192] ------------ | * PHI int
N001 ( 0, 0) [000263] ------------ | /--* PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ | \--* PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
N007 ( 2, 3) [000193] -A------R--- \--* ASG int
N006 ( 1, 1) [000191] D------N---- \--* LCL_VAR int V08 tmp7 d:3
***** BB06, stmt 27
( 2, 3) [000190] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000188] ------------ | * PHI int
N001 ( 0, 0) [000265] ------------ | /--* PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ | \--* PHI_ARG int V05 tmp4 u:6 $283
N007 ( 2, 3) [000189] -A------R--- \--* ASG int
N006 ( 1, 1) [000187] D------N---- \--* LCL_VAR int V05 tmp4 d:7
***** BB06, stmt 28
( 4, 4) [000106] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000102] ------------ | /--* CNS_INT int 1 $4b
N004 ( 4, 4) [000103] ------------ | /--* ADD int $20a
N002 ( 2, 2) [000101] ------------ | | \--* HWIntrinsic int TrailingZeroCount $400
N001 ( 1, 1) [000100] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 $285
N006 ( 4, 4) [000105] -A------R--- \--* ASG int $20a
N005 ( 1, 1) [000104] D------N---- \--* LCL_VAR int V10 tmp9 d:2 $20a
***** BB06, stmt 29
( 4, 5) [000113] ------------ * STMT void (IL 0x000... ???)
N003 ( 2, 3) [000109] ---------U-- | /--* CAST long <- ulong <- uint $24a
N002 ( 1, 1) [000108] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 $20a
N004 ( 4, 5) [000110] ------------ | /--* ADD long $24b
N001 ( 1, 1) [000107] ------------ | | \--* LCL_VAR long V09 tmp8 u:3 (last use) $145
N006 ( 4, 5) [000112] -A------R--- \--* ASG long $24b
N005 ( 1, 1) [000111] D------N---- \--* LCL_VAR long V09 tmp8 d:4 $24b
***** BB06, stmt 30
( 3, 3) [000119] ------------ * STMT void (IL 0x000... ???)
N002 ( 1, 1) [000115] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000116] ------------ | /--* ADD int $20b
N001 ( 1, 1) [000114] ------------ | | \--* LCL_VAR int V05 tmp4 u:7 (last use) $286
N005 ( 3, 3) [000118] -A------R--- \--* ASG int $20b
N004 ( 1, 1) [000117] D------N---- \--* LCL_VAR int V05 tmp4 d:8 $20b
***** BB06, stmt 31
( 8, 5) [000127] ------------ * STMT void (IL 0x000... ???)
N003 ( 1, 1) [000122] ------------ | /--* CNS_INT int 31 $4d
N004 ( 3, 3) [000123] ------------ | /--* AND int $20c
N002 ( 1, 1) [000121] ------------ | | \--* LCL_VAR int V10 tmp9 u:2 (last use) $20a
N005 ( 8, 5) [000124] ------------ | /--* RSZ int $20d
N001 ( 1, 1) [000120] ------------ | | \--* LCL_VAR int V08 tmp7 u:3 (last use) $285
N007 ( 8, 5) [000126] -A------R--- \--* ASG int $20d
N006 ( 1, 1) [000125] D------N---- \--* LCL_VAR int V08 tmp7 d:4 $20d
***** BB06, stmt 32
( 5, 5) [000098] ------------ * STMT void (IL 0x000... ???)
N004 ( 5, 5) [000097] ------------ \--* JTRUE void
N002 ( 1, 1) [000095] ------------ | /--* CNS_INT int 0 $40
N003 ( 3, 3) [000096] J------N---- \--* GT int $20e
N001 ( 1, 1) [000094] ------------ \--* LCL_VAR int V05 tmp4 u:8 $20b
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
***** BB07, stmt 33
( 2, 3) [000198] ------------ * STMT void (IL ???... ???)
N005 ( 2, 2) [000196] ------------ | * PHI long
N001 ( 0, 0) [000259] ------------ | /--* PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ | \--* PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
N007 ( 2, 3) [000197] -A------R--- \--* ASG long
N006 ( 1, 1) [000195] D------N---- \--* LCL_VAR long V09 tmp8 d:5
***** BB07, stmt 34
( 4, 4) [000011] ------------ * STMT void (IL ???... ???)
N004 ( 4, 4) [000010] ------------ \--* RETURN int $1c7
N002 ( 1, 1) [000131] ------------ | /--* CNS_INT int -1 $41
N003 ( 3, 3) [000132] ------------ \--* ADD int $210
N001 ( 1, 1) [000129] C----------- \--* LCL_VAR int V09 tmp8 u:5 (last use) $20f
-------------------------------------------------------------------------------------------------------------------
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000225] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000213] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N008 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000221] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000217] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 6, 5) [000209] DA---------- * STORE_LCL_VAR long V07 tmp6 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000205] DA---------- * STORE_LCL_VAR int V05 tmp4 d:6
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N009 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000201] DA---------- * STORE_LCL_VAR long V09 tmp8 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000193] DA---------- * STORE_LCL_VAR int V08 tmp7 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000189] DA---------- * STORE_LCL_VAR int V05 tmp4 d:7
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 2, 3) [000197] DA---------- * STORE_LCL_VAR long V09 tmp8 d:5
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 1 BB03 0.25 [000..001) i LIR
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target LIR
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000147] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
/--* t176 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000150] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 1, 3) [000020] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V04 tmp3 u:2 $80
/--* t17 int
N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000181] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000178] ------------ t178 = LCL_VAR int V05 tmp4 u:2 $80
N002 ( 1, 1) [000179] ------------ t179 = CNS_INT int 0 $40
/--* t178 int
+--* t179 int
N003 ( 3, 3) [000177] J------N---- t177 = * LE int $200
/--* t177 int
N004 ( 5, 5) [000180] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000239] ------------ t239 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ t227 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t239 long
+--* t227 long
N005 ( 2, 2) [000224] ------------ t224 = * PHI long
/--* t224 long
N007 ( 2, 3) [000225] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000241] ------------ t241 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ t229 = PHI_ARG int V04 tmp3 u:2 $80
/--* t241 int
+--* t229 int
N005 ( 2, 2) [000212] ------------ t212 = * PHI int
/--* t212 int
N007 ( 2, 3) [000213] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 1, 3) [000031] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000028] ------------ t28 = LCL_VAR int V04 tmp3 u:3 $280
/--* t28 int
N003 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 1, 3) [000041] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR long V03 tmp2 u:3 $141
/--* t33 long
N003 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2
( 3, 3) [000044] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR long V06 tmp5 u:2 (last use) $141
N002 ( 1, 1) [000036] ------------ t36 = CNS_INT long 8 $340
/--* t34 long
+--* t36 long
N003 ( 3, 3) [000037] ------------ t37 = * ADD long $241
/--* t37 long
N005 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 7, 7) [000052] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V05 tmp4 u:3 (last use) $280
N002 ( 1, 1) [000042] ------------ t42 = LCL_VAR long V06 tmp5 u:2 (last use) $141
/--* t42 long
N003 ( 3, 2) [000045] *--XG------- t45 = * IND long <l:$142, c:$302>
/--* t45 long
N004 ( 4, 3) [000046] ---XG------- t46 = * HWIntrinsic long PopCount $380
/--* t46 long
N005 ( 5, 5) [000047] ---XG------- t47 = * CAST int <- long $201
/--* t32 int
+--* t47 int
N006 ( 7, 7) [000048] ---XG------- t48 = * SUB int $202
/--* t48 int
N008 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 5, 5) [000026] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V04 tmp3 u:4 $202
N002 ( 1, 1) [000023] ------------ t23 = CNS_INT int 0 $40
/--* t22 int
+--* t23 int
N003 ( 3, 3) [000024] J------N---- t24 = * GT int $203
/--* t24 int
N004 ( 5, 5) [000025] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000235] ------------ t235 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ t231 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t235 long
+--* t231 long
N005 ( 2, 2) [000220] ------------ t220 = * PHI long
/--* t220 long
N007 ( 2, 3) [000221] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000237] ------------ t237 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ t233 = PHI_ARG int V05 tmp4 u:2 $80
/--* t237 int
+--* t233 int
N005 ( 2, 2) [000216] ------------ t216 = * PHI int
/--* t216 int
N007 ( 2, 3) [000217] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
( 3, 3) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000054] ------------ t54 = LCL_VAR long V03 tmp2 u:5 (last use) $143
N002 ( 1, 1) [000056] ------------ t56 = CNS_INT long -8 $342
/--* t54 long
+--* t56 long
N003 ( 3, 3) [000057] ------------ t57 = * ADD long $242
/--* t57 long
N005 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2
( 6, 5) [000069] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V05 tmp4 u:4 $281
N002 ( 1, 1) [000062] ------------ t62 = LCL_VAR long V07 tmp6 u:2 $242
/--* t62 long
N003 ( 3, 2) [000063] *--XG------- t63 = * IND int <l:$282, c:$1c2>
/--* t63 int
N004 ( 4, 3) [000064] ---XG------- t64 = * HWIntrinsic int PopCount $3c0
/--* t61 int
+--* t64 int
N005 ( 6, 5) [000065] ---XG------- t65 = * SUB int $205
/--* t65 int
N007 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5
( 5, 5) [000074] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000070] ------------ t70 = LCL_VAR int V04 tmp3 u:5 $205
N002 ( 1, 1) [000071] ------------ t71 = CNS_INT int 0 $40
/--* t70 int
+--* t71 int
N003 ( 3, 3) [000072] J------N---- t72 = * LE int $206
/--* t72 int
N004 ( 5, 5) [000073] ------------ * JTRUE void
------------ BB04 [000..001), preds={BB03} succs={BB05}
( 1, 3) [000137] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000134] ------------ t134 = LCL_VAR int V04 tmp3 u:5 (last use) $205
/--* t134 int
N003 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5
( 3, 3) [000144] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000138] ------------ t138 = LCL_VAR long V07 tmp6 u:2 (last use) $242
N002 ( 1, 1) [000140] ------------ t140 = CNS_INT long 4 $343
/--* t138 long
+--* t140 long
N003 ( 3, 3) [000141] ------------ t141 = * ADD long $243
/--* t141 long
N005 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
N001 ( 0, 0) [000247] ------------ t247 = PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ t243 = PHI_ARG long V07 tmp6 u:2 $242
/--* t247 long
+--* t243 long
N005 ( 2, 2) [000208] ------------ t208 = * PHI long
/--* t208 long
N007 ( 6, 5) [000209] DA---------- * STORE_LCL_VAR long V07 tmp6 d:4
N001 ( 0, 0) [000249] ------------ t249 = PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ t245 = PHI_ARG int V05 tmp4 u:4 $281
/--* t249 int
+--* t245 int
N005 ( 2, 2) [000204] ------------ t204 = * PHI int
/--* t204 int
N007 ( 2, 3) [000205] DA---------- * STORE_LCL_VAR int V05 tmp4 d:6
( 3, 3) [000080] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR long V07 tmp6 u:4 $144
/--* t76 long
N002 ( 3, 2) [000077] *--XG------- t77 = * IND int <l:$284, c:$1c5>
/--* t77 int
N004 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2
( 26, 9) [000092] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000081] ------------ t81 = LCL_VAR long V07 tmp6 u:4 (last use) $144
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t81 long
+--* t82 long
N003 ( 3, 3) [000083] ------------ t83 = * SUB long <l:$244, c:$245>
N004 ( 1, 1) [000085] ------------ t85 = CNS_INT long 4 $343
/--* t83 long
+--* t85 long
N005 ( 24, 7) [000086] ------------ t86 = * DIV long <l:$246, c:$247>
N006 ( 1, 1) [000088] ------------ t88 = CNS_INT long 5 $345
/--* t86 long
+--* t88 long
N007 ( 26, 9) [000089] ------------ t89 = * LSH long <l:$248, c:$249>
/--* t89 long
N009 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2
( 5, 5) [000186] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000183] ------------ t183 = LCL_VAR int V05 tmp4 u:6 $283
N002 ( 1, 1) [000184] ------------ t184 = CNS_INT int 0 $40
/--* t183 int
+--* t184 int
N003 ( 3, 3) [000182] J------N---- t182 = * LE int $208
/--* t182 int
N004 ( 5, 5) [000185] ------------ * JTRUE void
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
N001 ( 0, 0) [000261] ------------ t261 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ t251 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t261 long
+--* t251 long
N005 ( 2, 2) [000200] ------------ t200 = * PHI long
/--* t200 long
N007 ( 2, 3) [000201] DA---------- * STORE_LCL_VAR long V09 tmp8 d:3
N001 ( 0, 0) [000263] ------------ t263 = PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ t253 = PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
/--* t263 int
+--* t253 int
N005 ( 2, 2) [000192] ------------ t192 = * PHI int
/--* t192 int
N007 ( 2, 3) [000193] DA---------- * STORE_LCL_VAR int V08 tmp7 d:3
N001 ( 0, 0) [000265] ------------ t265 = PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ t255 = PHI_ARG int V05 tmp4 u:6 $283
/--* t265 int
+--* t255 int
N005 ( 2, 2) [000188] ------------ t188 = * PHI int
/--* t188 int
N007 ( 2, 3) [000189] DA---------- * STORE_LCL_VAR int V05 tmp4 d:7
( 4, 4) [000106] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000100] ------------ t100 = LCL_VAR int V08 tmp7 u:3 $285
/--* t100 int
N002 ( 2, 2) [000101] ------------ t101 = * HWIntrinsic int TrailingZeroCount $400
N003 ( 1, 1) [000102] ------------ t102 = CNS_INT int 1 $4b
/--* t101 int
+--* t102 int
N004 ( 4, 4) [000103] ------------ t103 = * ADD int $20a
/--* t103 int
N006 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2
( 4, 5) [000113] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000107] ------------ t107 = LCL_VAR long V09 tmp8 u:3 (last use) $145
N002 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V10 tmp9 u:2 $20a
/--* t108 int
N003 ( 2, 3) [000109] ---------U-- t109 = * CAST long <- ulong <- uint $24a
/--* t107 long
+--* t109 long
N004 ( 4, 5) [000110] ------------ t110 = * ADD long $24b
/--* t110 long
N006 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4
( 3, 3) [000119] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:7 (last use) $286
N002 ( 1, 1) [000115] ------------ t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20b
/--* t116 int
N005 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8
( 8, 5) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000120] ------------ t120 = LCL_VAR int V08 tmp7 u:3 (last use) $285
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V10 tmp9 u:2 (last use) $20a
N003 ( 1, 1) [000122] ------------ t122 = CNS_INT int 31 $4d
/--* t121 int
+--* t122 int
N004 ( 3, 3) [000123] ------------ t123 = * AND int $20c
/--* t120 int
+--* t123 int
N005 ( 8, 5) [000124] ------------ t124 = * RSZ int $20d
/--* t124 int
N007 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4
( 5, 5) [000098] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V05 tmp4 u:8 $20b
N002 ( 1, 1) [000095] ------------ t95 = CNS_INT int 0 $40
/--* t94 int
+--* t95 int
N003 ( 3, 3) [000096] J------N---- t96 = * GT int $20e
/--* t96 int
N004 ( 5, 5) [000097] ------------ * JTRUE void
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
N001 ( 0, 0) [000259] ------------ t259 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ t257 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t259 long
+--* t257 long
N005 ( 2, 2) [000196] ------------ t196 = * PHI long
/--* t196 long
N007 ( 2, 3) [000197] DA---------- * STORE_LCL_VAR long V09 tmp8 d:5
N001 ( 1, 1) [000129] C----------- t129 = LCL_VAR int V09 tmp8 u:5 (last use) $20f
N002 ( 1, 1) [000131] ------------ t131 = CNS_INT int -1 $41
/--* t129 int
+--* t131 int
N003 ( 3, 3) [000132] ------------ t132 = * ADD int $210
/--* t132 int
N004 ( 4, 4) [000010] ------------ * RETURN int $1c7
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 1 BB03 0.25 [000..001) i LIR
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target LIR
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000147] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
/--* t176 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000150] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 1, 3) [000020] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V04 tmp3 u:2 $80
/--* t17 int
N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000181] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000178] ------------ t178 = LCL_VAR int V05 tmp4 u:2 $80
N002 ( 1, 1) [000179] ------------ t179 = CNS_INT int 0 $40
/--* t178 int
+--* t179 int
N003 ( 3, 3) [000177] J------N---- t177 = * LE int $200
/--* t177 int
N004 ( 5, 5) [000180] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000239] ------------ t239 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ t227 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t239 long
+--* t227 long
N005 ( 2, 2) [000224] ------------ t224 = * PHI long
/--* t224 long
N007 ( 2, 3) [000225] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000241] ------------ t241 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ t229 = PHI_ARG int V04 tmp3 u:2 $80
/--* t241 int
+--* t229 int
N005 ( 2, 2) [000212] ------------ t212 = * PHI int
/--* t212 int
N007 ( 2, 3) [000213] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 1, 3) [000031] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000028] ------------ t28 = LCL_VAR int V04 tmp3 u:3 $280
/--* t28 int
N003 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 1, 3) [000041] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR long V03 tmp2 u:3 $141
/--* t33 long
N003 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2
( 3, 3) [000044] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR long V06 tmp5 u:2 (last use) $141
N002 ( 1, 1) [000036] ------------ t36 = CNS_INT long 8 $340
/--* t34 long
+--* t36 long
N003 ( 3, 3) [000037] ------------ t37 = * ADD long $241
/--* t37 long
N005 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 7, 7) [000052] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V05 tmp4 u:3 (last use) $280
N002 ( 1, 1) [000042] ------------ t42 = LCL_VAR long V06 tmp5 u:2 (last use) $141
/--* t42 long
N003 ( 3, 2) [000045] *--XG------- t45 = * IND long <l:$142, c:$302>
/--* t45 long
N004 ( 4, 3) [000046] ---XG------- t46 = * HWIntrinsic long PopCount $380
/--* t46 long
N005 ( 5, 5) [000047] ---XG------- t47 = * CAST int <- long $201
/--* t32 int
+--* t47 int
N006 ( 7, 7) [000048] ---XG------- t48 = * SUB int $202
/--* t48 int
N008 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 5, 5) [000026] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V04 tmp3 u:4 $202
N002 ( 1, 1) [000023] ------------ t23 = CNS_INT int 0 $40
/--* t22 int
+--* t23 int
N003 ( 3, 3) [000024] J------N---- t24 = * GT int $203
/--* t24 int
N004 ( 5, 5) [000025] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000235] ------------ t235 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ t231 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t235 long
+--* t231 long
N005 ( 2, 2) [000220] ------------ t220 = * PHI long
/--* t220 long
N007 ( 2, 3) [000221] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000237] ------------ t237 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ t233 = PHI_ARG int V05 tmp4 u:2 $80
/--* t237 int
+--* t233 int
N005 ( 2, 2) [000216] ------------ t216 = * PHI int
/--* t216 int
N007 ( 2, 3) [000217] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
( 3, 3) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000054] ------------ t54 = LCL_VAR long V03 tmp2 u:5 (last use) $143
N002 ( 1, 1) [000056] ------------ t56 = CNS_INT long -8 $342
/--* t54 long
+--* t56 long
N003 ( 3, 3) [000057] ------------ t57 = * ADD long $242
/--* t57 long
N005 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2
( 6, 5) [000069] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V05 tmp4 u:4 $281
N002 ( 1, 1) [000062] ------------ t62 = LCL_VAR long V07 tmp6 u:2 $242
/--* t62 long
N003 ( 3, 2) [000063] *--XG------- t63 = * IND int <l:$282, c:$1c2>
/--* t63 int
N004 ( 4, 3) [000064] ---XG------- t64 = * HWIntrinsic int PopCount $3c0
/--* t61 int
+--* t64 int
N005 ( 6, 5) [000065] ---XG------- t65 = * SUB int $205
/--* t65 int
N007 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5
( 5, 5) [000074] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000070] ------------ t70 = LCL_VAR int V04 tmp3 u:5 $205
N002 ( 1, 1) [000071] ------------ t71 = CNS_INT int 0 $40
/--* t70 int
+--* t71 int
N003 ( 3, 3) [000072] J------N---- t72 = * LE int $206
/--* t72 int
N004 ( 5, 5) [000073] ------------ * JTRUE void
------------ BB04 [000..001), preds={BB03} succs={BB05}
( 1, 3) [000137] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000134] ------------ t134 = LCL_VAR int V04 tmp3 u:5 (last use) $205
/--* t134 int
N003 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5
( 3, 3) [000144] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000138] ------------ t138 = LCL_VAR long V07 tmp6 u:2 (last use) $242
N002 ( 1, 1) [000140] ------------ t140 = CNS_INT long 4 $343
/--* t138 long
+--* t140 long
N003 ( 3, 3) [000141] ------------ t141 = * ADD long $243
/--* t141 long
N005 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
N001 ( 0, 0) [000247] ------------ t247 = PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ t243 = PHI_ARG long V07 tmp6 u:2 $242
/--* t247 long
+--* t243 long
N005 ( 2, 2) [000208] ------------ t208 = * PHI long
/--* t208 long
N007 ( 6, 5) [000209] DA---------- * STORE_LCL_VAR long V07 tmp6 d:4
N001 ( 0, 0) [000249] ------------ t249 = PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ t245 = PHI_ARG int V05 tmp4 u:4 $281
/--* t249 int
+--* t245 int
N005 ( 2, 2) [000204] ------------ t204 = * PHI int
/--* t204 int
N007 ( 2, 3) [000205] DA---------- * STORE_LCL_VAR int V05 tmp4 d:6
( 3, 3) [000080] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR long V07 tmp6 u:4 $144
/--* t76 long
N002 ( 3, 2) [000077] *--XG------- t77 = * IND int <l:$284, c:$1c5>
/--* t77 int
N004 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2
( 26, 9) [000092] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000081] ------------ t81 = LCL_VAR long V07 tmp6 u:4 (last use) $144
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t81 long
+--* t82 long
N003 ( 3, 3) [000083] ------------ t83 = * SUB long <l:$244, c:$245>
N004 ( 1, 1) [000085] ------------ t85 = CNS_INT long 4 $343
/--* t83 long
+--* t85 long
N005 ( 24, 7) [000086] ------------ t86 = * DIV long <l:$246, c:$247>
N006 ( 1, 1) [000088] ------------ t88 = CNS_INT long 5 $345
/--* t86 long
+--* t88 long
N007 ( 26, 9) [000089] ------------ t89 = * LSH long <l:$248, c:$249>
/--* t89 long
N009 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2
( 5, 5) [000186] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000183] ------------ t183 = LCL_VAR int V05 tmp4 u:6 $283
N002 ( 1, 1) [000184] ------------ t184 = CNS_INT int 0 $40
/--* t183 int
+--* t184 int
N003 ( 3, 3) [000182] J------N---- t182 = * LE int $208
/--* t182 int
N004 ( 5, 5) [000185] ------------ * JTRUE void
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
N001 ( 0, 0) [000261] ------------ t261 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ t251 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t261 long
+--* t251 long
N005 ( 2, 2) [000200] ------------ t200 = * PHI long
/--* t200 long
N007 ( 2, 3) [000201] DA---------- * STORE_LCL_VAR long V09 tmp8 d:3
N001 ( 0, 0) [000263] ------------ t263 = PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ t253 = PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
/--* t263 int
+--* t253 int
N005 ( 2, 2) [000192] ------------ t192 = * PHI int
/--* t192 int
N007 ( 2, 3) [000193] DA---------- * STORE_LCL_VAR int V08 tmp7 d:3
N001 ( 0, 0) [000265] ------------ t265 = PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ t255 = PHI_ARG int V05 tmp4 u:6 $283
/--* t265 int
+--* t255 int
N005 ( 2, 2) [000188] ------------ t188 = * PHI int
/--* t188 int
N007 ( 2, 3) [000189] DA---------- * STORE_LCL_VAR int V05 tmp4 d:7
( 4, 4) [000106] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000100] ------------ t100 = LCL_VAR int V08 tmp7 u:3 $285
/--* t100 int
N002 ( 2, 2) [000101] ------------ t101 = * HWIntrinsic int TrailingZeroCount $400
N003 ( 1, 1) [000102] ------------ t102 = CNS_INT int 1 $4b
/--* t101 int
+--* t102 int
N004 ( 4, 4) [000103] ------------ t103 = * ADD int $20a
/--* t103 int
N006 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2
( 4, 5) [000113] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000107] ------------ t107 = LCL_VAR long V09 tmp8 u:3 (last use) $145
N002 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V10 tmp9 u:2 $20a
/--* t108 int
N003 ( 2, 3) [000109] ---------U-- t109 = * CAST long <- ulong <- uint $24a
/--* t107 long
+--* t109 long
N004 ( 4, 5) [000110] ------------ t110 = * ADD long $24b
/--* t110 long
N006 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4
( 3, 3) [000119] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:7 (last use) $286
N002 ( 1, 1) [000115] ------------ t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20b
/--* t116 int
N005 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8
( 8, 5) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000120] ------------ t120 = LCL_VAR int V08 tmp7 u:3 (last use) $285
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V10 tmp9 u:2 (last use) $20a
N003 ( 1, 1) [000122] ------------ t122 = CNS_INT int 31 $4d
/--* t121 int
+--* t122 int
N004 ( 3, 3) [000123] ------------ t123 = * AND int $20c
/--* t120 int
+--* t123 int
N005 ( 8, 5) [000124] ------------ t124 = * RSZ int $20d
/--* t124 int
N007 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4
( 5, 5) [000098] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V05 tmp4 u:8 $20b
N002 ( 1, 1) [000095] ------------ t95 = CNS_INT int 0 $40
/--* t94 int
+--* t95 int
N003 ( 3, 3) [000096] J------N---- t96 = * GT int $20e
/--* t96 int
N004 ( 5, 5) [000097] ------------ * JTRUE void
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
N001 ( 0, 0) [000259] ------------ t259 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ t257 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t259 long
+--* t257 long
N005 ( 2, 2) [000196] ------------ t196 = * PHI long
/--* t196 long
N007 ( 2, 3) [000197] DA---------- * STORE_LCL_VAR long V09 tmp8 d:5
N001 ( 1, 1) [000129] C----------- t129 = LCL_VAR int V09 tmp8 u:5 (last use) $20f
N002 ( 1, 1) [000131] ------------ t131 = CNS_INT int -1 $41
/--* t129 int
+--* t131 int
N003 ( 3, 3) [000132] ------------ t132 = * ADD int $210
/--* t132 int
N004 ( 4, 4) [000010] ------------ * RETURN int $1c7
-------------------------------------------------------------------------------------------------------------------
No addressing mode:
N001 ( 3, 10) [000176] ------------ * CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
No addressing mode:
N002 ( 1, 1) [000042] ------------ * LCL_VAR long V06 tmp5 u:2 (last use) $141
No addressing mode:
N002 ( 1, 1) [000062] ------------ * LCL_VAR long V07 tmp6 u:2 $242
No addressing mode:
N001 ( 1, 1) [000076] ------------ * LCL_VAR long V07 tmp6 u:4 $144
lvaGrabTemp returning 11 (V11 rat0) called for ReplaceWithLclVar is creating a new local variable.
New refCnts for V11: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 2, refCntWtd = 2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
[000268] DA---------- * STORE_LCL_VAR long V11 rat0
ReplaceWithLclVar created store :
[000268] DA---------- * STORE_LCL_VAR long V11 rat0
New refCnts for V11: refCnt = 3, refCntWtd = 3
lowering GT_RETURN
N004 ( 4, 4) [000010] ------------ * RETURN int $1c7
============Lower has completed modifying nodes.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 1 BB03 0.25 [000..001) i LIR
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target LIR
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000147] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
/--* t176 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000150] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 1, 3) [000020] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V04 tmp3 u:2 $80
/--* t17 int
N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000181] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000178] ------------ t178 = LCL_VAR int V05 tmp4 u:2 $80
N002 ( 1, 1) [000179] -c---------- t179 = CNS_INT int 0 $40
/--* t178 int
+--* t179 int
N003 ( 3, 3) [000177] J------N---- * LE void $200
N004 ( 5, 5) [000180] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000239] ------------ t239 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ t227 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t239 long
+--* t227 long
N005 ( 2, 2) [000224] ------------ t224 = * PHI long
/--* t224 long
N007 ( 2, 3) [000225] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000241] ------------ t241 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ t229 = PHI_ARG int V04 tmp3 u:2 $80
/--* t241 int
+--* t229 int
N005 ( 2, 2) [000212] ------------ t212 = * PHI int
/--* t212 int
N007 ( 2, 3) [000213] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 1, 3) [000031] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000028] ------------ t28 = LCL_VAR int V04 tmp3 u:3 $280
/--* t28 int
N003 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 1, 3) [000041] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR long V03 tmp2 u:3 $141
/--* t33 long
N003 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2
( 3, 3) [000044] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR long V06 tmp5 u:2 (last use) $141
N002 ( 1, 1) [000036] -c---------- t36 = CNS_INT long 8 $340
/--* t34 long
+--* t36 long
N003 ( 3, 3) [000037] ------------ t37 = * ADD long $241
/--* t37 long
N005 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 7, 7) [000052] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V05 tmp4 u:3 (last use) $280
N002 ( 1, 1) [000042] ------------ t42 = LCL_VAR long V06 tmp5 u:2 (last use) $141
/--* t42 long
N003 ( 3, 2) [000045] *c-XG------- t45 = * IND long <l:$142, c:$302>
/--* t45 long
N004 ( 4, 3) [000046] ---XG------- t46 = * HWIntrinsic long PopCount $380
/--* t46 long
N005 ( 5, 5) [000047] ---XG------- t47 = * CAST int <- long $201
/--* t32 int
+--* t47 int
N006 ( 7, 7) [000048] ---XG------- t48 = * SUB int $202
/--* t48 int
N008 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 5, 5) [000026] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V04 tmp3 u:4 $202
N002 ( 1, 1) [000023] -c---------- t23 = CNS_INT int 0 $40
/--* t22 int
+--* t23 int
N003 ( 3, 3) [000024] J------N---- * GT void $203
N004 ( 5, 5) [000025] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000235] ------------ t235 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ t231 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t235 long
+--* t231 long
N005 ( 2, 2) [000220] ------------ t220 = * PHI long
/--* t220 long
N007 ( 2, 3) [000221] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000237] ------------ t237 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ t233 = PHI_ARG int V05 tmp4 u:2 $80
/--* t237 int
+--* t233 int
N005 ( 2, 2) [000216] ------------ t216 = * PHI int
/--* t216 int
N007 ( 2, 3) [000217] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
( 3, 3) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000054] ------------ t54 = LCL_VAR long V03 tmp2 u:5 (last use) $143
N002 ( 1, 1) [000056] -c---------- t56 = CNS_INT long -8 $342
/--* t54 long
+--* t56 long
N003 ( 3, 3) [000057] ------------ t57 = * ADD long $242
/--* t57 long
N005 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2
( 6, 5) [000069] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V05 tmp4 u:4 $281
N002 ( 1, 1) [000062] ------------ t62 = LCL_VAR long V07 tmp6 u:2 $242
/--* t62 long
N003 ( 3, 2) [000063] *c-XG------- t63 = * IND int <l:$282, c:$1c2>
/--* t63 int
N004 ( 4, 3) [000064] ---XG------- t64 = * HWIntrinsic int PopCount $3c0
/--* t61 int
+--* t64 int
N005 ( 6, 5) [000065] ---XG------- t65 = * SUB int $205
/--* t65 int
N007 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5
( 5, 5) [000074] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000070] ------------ t70 = LCL_VAR int V04 tmp3 u:5 $205
N002 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 0 $40
/--* t70 int
+--* t71 int
N003 ( 3, 3) [000072] J------N---- * LE void $206
N004 ( 5, 5) [000073] ------------ * JTRUE void
------------ BB04 [000..001), preds={BB03} succs={BB05}
( 1, 3) [000137] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000134] ------------ t134 = LCL_VAR int V04 tmp3 u:5 (last use) $205
/--* t134 int
N003 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5
( 3, 3) [000144] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000138] ------------ t138 = LCL_VAR long V07 tmp6 u:2 (last use) $242
N002 ( 1, 1) [000140] -c---------- t140 = CNS_INT long 4 $343
/--* t138 long
+--* t140 long
N003 ( 3, 3) [000141] ------------ t141 = * ADD long $243
/--* t141 long
N005 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
N001 ( 0, 0) [000247] ------------ t247 = PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ t243 = PHI_ARG long V07 tmp6 u:2 $242
/--* t247 long
+--* t243 long
N005 ( 2, 2) [000208] ------------ t208 = * PHI long
/--* t208 long
N007 ( 6, 5) [000209] DA---------- * STORE_LCL_VAR long V07 tmp6 d:4
N001 ( 0, 0) [000249] ------------ t249 = PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ t245 = PHI_ARG int V05 tmp4 u:4 $281
/--* t249 int
+--* t245 int
N005 ( 2, 2) [000204] ------------ t204 = * PHI int
/--* t204 int
N007 ( 2, 3) [000205] DA---------- * STORE_LCL_VAR int V05 tmp4 d:6
( 3, 3) [000080] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR long V07 tmp6 u:4 $144
/--* t76 long
N002 ( 3, 2) [000077] *--XG------- t77 = * IND int <l:$284, c:$1c5>
/--* t77 int
N004 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2
( 26, 9) [000092] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000081] ------------ t81 = LCL_VAR long V07 tmp6 u:4 (last use) $144
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t81 long
+--* t82 long
N003 ( 3, 3) [000083] ------------ t83 = * SUB long <l:$244, c:$245>
/--* t83 long
[000268] DA---------- * STORE_LCL_VAR long V11 rat0
N001 ( 1, 1) [000269] ------------ t269 = LCL_VAR long V11 rat0
N002 ( 1, 1) [000270] -c---------- t270 = CNS_INT int 63
/--* t269 long
+--* t270 int
N003 ( 3, 3) [000271] ------------ t271 = * RSH long
N004 ( 1, 1) [000272] -c---------- t272 = CNS_INT long 3
/--* t271 long
+--* t272 long
N005 ( 5, 5) [000273] ------------ t273 = * AND long
N006 ( 1, 1) [000274] ------------ t274 = LCL_VAR long V11 rat0
/--* t273 long
+--* t274 long
N007 ( 7, 7) [000275] ------------ t275 = * ADD long
N008 ( 1, 1) [000085] -c---------- t85 = CNS_INT long 2 $343
/--* t275 long
+--* t85 long
N009 ( 9, 9) [000276] ------------ t276 = * RSH long
N006 ( 1, 1) [000088] -c---------- t88 = CNS_INT long 5 $345
/--* t276 long
+--* t88 long
N007 ( 26, 9) [000089] ------------ t89 = * LSH long <l:$248, c:$249>
/--* t89 long
N009 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2
( 5, 5) [000186] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000183] ------------ t183 = LCL_VAR int V05 tmp4 u:6 $283
N002 ( 1, 1) [000184] -c---------- t184 = CNS_INT int 0 $40
/--* t183 int
+--* t184 int
N003 ( 3, 3) [000182] J------N---- * LE void $208
N004 ( 5, 5) [000185] ------------ * JTRUE void
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
N001 ( 0, 0) [000261] ------------ t261 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ t251 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t261 long
+--* t251 long
N005 ( 2, 2) [000200] ------------ t200 = * PHI long
/--* t200 long
N007 ( 2, 3) [000201] DA---------- * STORE_LCL_VAR long V09 tmp8 d:3
N001 ( 0, 0) [000263] ------------ t263 = PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ t253 = PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
/--* t263 int
+--* t253 int
N005 ( 2, 2) [000192] ------------ t192 = * PHI int
/--* t192 int
N007 ( 2, 3) [000193] DA---------- * STORE_LCL_VAR int V08 tmp7 d:3
N001 ( 0, 0) [000265] ------------ t265 = PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ t255 = PHI_ARG int V05 tmp4 u:6 $283
/--* t265 int
+--* t255 int
N005 ( 2, 2) [000188] ------------ t188 = * PHI int
/--* t188 int
N007 ( 2, 3) [000189] DA---------- * STORE_LCL_VAR int V05 tmp4 d:7
( 4, 4) [000106] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000100] ------------ t100 = LCL_VAR int V08 tmp7 u:3 $285
/--* t100 int
N002 ( 2, 2) [000101] ------------ t101 = * HWIntrinsic int TrailingZeroCount $400
N003 ( 1, 1) [000102] -c---------- t102 = CNS_INT int 1 $4b
/--* t101 int
+--* t102 int
N004 ( 4, 4) [000103] ------------ t103 = * ADD int $20a
/--* t103 int
N006 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2
( 4, 5) [000113] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000107] ------------ t107 = LCL_VAR long V09 tmp8 u:3 (last use) $145
N002 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V10 tmp9 u:2 $20a
/--* t108 int
N003 ( 2, 3) [000109] ---------U-- t109 = * CAST long <- ulong <- uint $24a
/--* t107 long
+--* t109 long
N004 ( 4, 5) [000110] ------------ t110 = * ADD long $24b
/--* t110 long
N006 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4
( 3, 3) [000119] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:7 (last use) $286
N002 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20b
/--* t116 int
N005 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8
( 8, 5) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000120] ------------ t120 = LCL_VAR int V08 tmp7 u:3 (last use) $285
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V10 tmp9 u:2 (last use) $20a
/--* t120 int
+--* t121 int
N005 ( 8, 5) [000124] ------------ t124 = * RSZ int $20d
/--* t124 int
N007 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4
( 5, 5) [000098] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V05 tmp4 u:8 $20b
N002 ( 1, 1) [000095] -c---------- t95 = CNS_INT int 0 $40
/--* t94 int
+--* t95 int
N003 ( 3, 3) [000096] J------N---- * GT void $20e
N004 ( 5, 5) [000097] ------------ * JTRUE void
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
N001 ( 0, 0) [000259] ------------ t259 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ t257 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t259 long
+--* t257 long
N005 ( 2, 2) [000196] ------------ t196 = * PHI long
/--* t196 long
N007 ( 2, 3) [000197] DA---------- * STORE_LCL_VAR long V09 tmp8 d:5
N001 ( 1, 1) [000129] C----------- t129 = LCL_VAR int V09 tmp8 u:5 (last use) $20f
N002 ( 1, 1) [000131] -c---------- t131 = CNS_INT int -1 $41
/--* t129 int
+--* t131 int
N003 ( 3, 3) [000132] ------------ t132 = * ADD int $210
/--* t132 int
N004 ( 4, 4) [000010] ------------ * RETURN int $1c7
-------------------------------------------------------------------------------------------------------------------
New refCnts for V02: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 1, refCntWtd = 2
New refCnts for V02: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V04: refCnt = 2, refCntWtd = 4
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V04: refCnt = 3, refCntWtd = 8
New refCnts for V05: refCnt = 3, refCntWtd = 4
New refCnts for V03: refCnt = 2, refCntWtd = 3
New refCnts for V06: refCnt = 1, refCntWtd = 4
New refCnts for V06: refCnt = 2, refCntWtd = 8
New refCnts for V03: refCnt = 3, refCntWtd = 5
New refCnts for V05: refCnt = 4, refCntWtd = 6
New refCnts for V06: refCnt = 3, refCntWtd = 12
New refCnts for V04: refCnt = 4, refCntWtd = 12
New refCnts for V04: refCnt = 5, refCntWtd = 16
New refCnts for V03: refCnt = 4, refCntWtd = 5.50
New refCnts for V07: refCnt = 1, refCntWtd = 0.50
New refCnts for V05: refCnt = 5, refCntWtd = 6.50
New refCnts for V07: refCnt = 2, refCntWtd = 1
New refCnts for V04: refCnt = 6, refCntWtd = 17
New refCnts for V04: refCnt = 7, refCntWtd = 18
New refCnts for V04: refCnt = 8, refCntWtd = 18.50
New refCnts for V05: refCnt = 6, refCntWtd = 6.75
New refCnts for V07: refCnt = 3, refCntWtd = 1.25
New refCnts for V07: refCnt = 4, refCntWtd = 1.50
New refCnts for V07: refCnt = 5, refCntWtd = 2
New refCnts for V08: refCnt = 1, refCntWtd = 0.50
New refCnts for V07: refCnt = 6, refCntWtd = 2.50
New refCnts for V02: refCnt = 3, refCntWtd = 5
New refCnts for V11: refCnt = 1, refCntWtd = 1
New refCnts for V11: refCnt = 2, refCntWtd = 2
New refCnts for V11: refCnt = 3, refCntWtd = 3
New refCnts for V09: refCnt = 1, refCntWtd = 0.50
New refCnts for V05: refCnt = 7, refCntWtd = 7.25
New refCnts for V08: refCnt = 2, refCntWtd = 2.50
New refCnts for V10: refCnt = 1, refCntWtd = 2
New refCnts for V09: refCnt = 2, refCntWtd = 2.50
New refCnts for V10: refCnt = 2, refCntWtd = 4
New refCnts for V09: refCnt = 3, refCntWtd = 4.50
New refCnts for V05: refCnt = 8, refCntWtd = 9.25
New refCnts for V05: refCnt = 9, refCntWtd = 11.25
New refCnts for V08: refCnt = 3, refCntWtd = 4.50
New refCnts for V10: refCnt = 3, refCntWtd = 6
New refCnts for V08: refCnt = 4, refCntWtd = 6.50
New refCnts for V05: refCnt = 10, refCntWtd = 13.25
New refCnts for V09: refCnt = 4, refCntWtd = 5.50
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk ( 0)
; V02 tmp1 long
; V03 tmp2 long
; V04 tmp3 int
; V05 tmp4 int
; V06 tmp5 long
; V07 tmp6 long
; V08 tmp7 int
; V09 tmp8 long
; V10 tmp9 int
; V11 rat0 long
In fgLocalVarLivenessInit, sorting locals
refCnt table for 'POPCNTButNoBMI2':
V04 tmp3 [ int]: refCnt = 8, refCntWtd = 18.50
V05 tmp4 [ int]: refCnt = 10, refCntWtd = 13.25
V06 tmp5 [ long]: refCnt = 3, refCntWtd = 12
V08 tmp7 [ int]: refCnt = 4, refCntWtd = 6.50
V10 tmp9 [ int]: refCnt = 3, refCntWtd = 6
V03 tmp2 [ long]: refCnt = 4, refCntWtd = 5.50
V09 tmp8 [ long]: refCnt = 4, refCntWtd = 5.50
V00 arg0 [ int]: refCnt = 3, refCntWtd = 3
V02 tmp1 [ long]: refCnt = 3, refCntWtd = 5
V11 rat0 [ long]: refCnt = 3, refCntWtd = 3
V07 tmp6 [ long]: refCnt = 6, refCntWtd = 2.50
V01 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={ V00 } + ByrefExposed + GcHeap
DEF(4)={V04 V05 V03 V02}
BB02 USE(2)={V04 V03} + ByrefExposed + GcHeap
DEF(4)={V04 V05 V06 V03}
BB03 USE(2)={ V05 V03 } + ByrefExposed + GcHeap
DEF(2)={V04 V07}
BB04 USE(2)={V04 V07}
DEF(2)={ V05 V07}
BB05 USE(3)={V05 V02 V07} + ByrefExposed + GcHeap
DEF(3)={ V08 V09 V11 }
BB06 USE(3)={V05 V08 V09}
DEF(4)={V05 V08 V10 V09}
BB07 USE(1)={V09}
DEF(0)={ }
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={ V00 } + ByrefExposed + GcHeap
OUT(4)={V04 V05 V03 V02} + ByrefExposed + GcHeap
BB02 IN (3)={V04 V03 V02} + ByrefExposed + GcHeap
OUT(4)={V04 V05 V03 V02} + ByrefExposed + GcHeap
BB03 IN (3)={ V05 V03 V02 } + ByrefExposed + GcHeap
OUT(4)={V04 V05 V02 V07} + ByrefExposed + GcHeap
BB04 IN (3)={V04 V02 V07} + ByrefExposed + GcHeap
OUT(3)={ V05 V02 V07} + ByrefExposed + GcHeap
BB05 IN (3)={V05 V02 V07} + ByrefExposed + GcHeap
OUT(3)={V05 V08 V09 }
BB06 IN (3)={V05 V08 V09}
OUT(3)={V05 V08 V09}
BB07 IN (1)={V09}
OUT(0)={ }
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 1 BB03 0.25 [000..001) i LIR
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target LIR
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Liveness pass finished after lowering, IR:
lvasortagain = 0
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 1 BB03 0.25 [000..001) i LIR
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target LIR
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000147] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
/--* t176 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000150] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 1, 3) [000020] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V04 tmp3 u:2 $80
/--* t17 int
N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000181] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000178] ------------ t178 = LCL_VAR int V05 tmp4 u:2 $80
N002 ( 1, 1) [000179] -c---------- t179 = CNS_INT int 0 $40
/--* t178 int
+--* t179 int
N003 ( 3, 3) [000177] J------N---- * LE void $200
N004 ( 5, 5) [000180] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000239] ------------ t239 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ t227 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t239 long
+--* t227 long
N005 ( 2, 2) [000224] ------------ t224 = * PHI long
/--* t224 long
N007 ( 2, 3) [000225] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000241] ------------ t241 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ t229 = PHI_ARG int V04 tmp3 u:2 $80
/--* t241 int
+--* t229 int
N005 ( 2, 2) [000212] ------------ t212 = * PHI int
/--* t212 int
N007 ( 2, 3) [000213] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 1, 3) [000031] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000028] ------------ t28 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t28 int
N003 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 1, 3) [000041] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR long V03 tmp2 u:3 (last use) $141
/--* t33 long
N003 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2
( 3, 3) [000044] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR long V06 tmp5 u:2 $141
N002 ( 1, 1) [000036] -c---------- t36 = CNS_INT long 8 $340
/--* t34 long
+--* t36 long
N003 ( 3, 3) [000037] ------------ t37 = * ADD long $241
/--* t37 long
N005 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 7, 7) [000052] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V05 tmp4 u:3 $280
N002 ( 1, 1) [000042] ------------ t42 = LCL_VAR long V06 tmp5 u:2 (last use) $141
/--* t42 long
N003 ( 3, 2) [000045] *c-XG------- t45 = * IND long <l:$142, c:$302>
/--* t45 long
N004 ( 4, 3) [000046] ---XG------- t46 = * HWIntrinsic long PopCount $380
/--* t46 long
N005 ( 5, 5) [000047] ---XG------- t47 = * CAST int <- long $201
/--* t32 int
+--* t47 int
N006 ( 7, 7) [000048] ---XG------- t48 = * SUB int $202
/--* t48 int
N008 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 5, 5) [000026] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V04 tmp3 u:4 $202
N002 ( 1, 1) [000023] -c---------- t23 = CNS_INT int 0 $40
/--* t22 int
+--* t23 int
N003 ( 3, 3) [000024] J------N---- * GT void $203
N004 ( 5, 5) [000025] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000235] ------------ t235 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ t231 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t235 long
+--* t231 long
N005 ( 2, 2) [000220] ------------ t220 = * PHI long
/--* t220 long
N007 ( 2, 3) [000221] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000237] ------------ t237 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ t233 = PHI_ARG int V05 tmp4 u:2 $80
/--* t237 int
+--* t233 int
N005 ( 2, 2) [000216] ------------ t216 = * PHI int
/--* t216 int
N007 ( 2, 3) [000217] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
( 3, 3) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000054] ------------ t54 = LCL_VAR long V03 tmp2 u:5 (last use) $143
N002 ( 1, 1) [000056] -c---------- t56 = CNS_INT long -8 $342
/--* t54 long
+--* t56 long
N003 ( 3, 3) [000057] ------------ t57 = * ADD long $242
/--* t57 long
N005 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2
( 6, 5) [000069] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V05 tmp4 u:4 $281
N002 ( 1, 1) [000062] ------------ t62 = LCL_VAR long V07 tmp6 u:2 $242
/--* t62 long
N003 ( 3, 2) [000063] *c-XG------- t63 = * IND int <l:$282, c:$1c2>
/--* t63 int
N004 ( 4, 3) [000064] ---XG------- t64 = * HWIntrinsic int PopCount $3c0
/--* t61 int
+--* t64 int
N005 ( 6, 5) [000065] ---XG------- t65 = * SUB int $205
/--* t65 int
N007 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5
( 5, 5) [000074] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000070] ------------ t70 = LCL_VAR int V04 tmp3 u:5 $205
N002 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 0 $40
/--* t70 int
+--* t71 int
N003 ( 3, 3) [000072] J------N---- * LE void $206
N004 ( 5, 5) [000073] ------------ * JTRUE void
------------ BB04 [000..001), preds={BB03} succs={BB05}
( 1, 3) [000137] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000134] ------------ t134 = LCL_VAR int V04 tmp3 u:5 (last use) $205
/--* t134 int
N003 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5
( 3, 3) [000144] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000138] ------------ t138 = LCL_VAR long V07 tmp6 u:2 (last use) $242
N002 ( 1, 1) [000140] -c---------- t140 = CNS_INT long 4 $343
/--* t138 long
+--* t140 long
N003 ( 3, 3) [000141] ------------ t141 = * ADD long $243
/--* t141 long
N005 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
N001 ( 0, 0) [000247] ------------ t247 = PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ t243 = PHI_ARG long V07 tmp6 u:2 $242
/--* t247 long
+--* t243 long
N005 ( 2, 2) [000208] ------------ t208 = * PHI long
/--* t208 long
N007 ( 6, 5) [000209] DA---------- * STORE_LCL_VAR long V07 tmp6 d:4
N001 ( 0, 0) [000249] ------------ t249 = PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ t245 = PHI_ARG int V05 tmp4 u:4 $281
/--* t249 int
+--* t245 int
N005 ( 2, 2) [000204] ------------ t204 = * PHI int
/--* t204 int
N007 ( 2, 3) [000205] DA---------- * STORE_LCL_VAR int V05 tmp4 d:6
( 3, 3) [000080] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR long V07 tmp6 u:4 $144
/--* t76 long
N002 ( 3, 2) [000077] *--XG------- t77 = * IND int <l:$284, c:$1c5>
/--* t77 int
N004 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2
( 26, 9) [000092] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000081] ------------ t81 = LCL_VAR long V07 tmp6 u:4 (last use) $144
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t81 long
+--* t82 long
N003 ( 3, 3) [000083] ------------ t83 = * SUB long <l:$244, c:$245>
/--* t83 long
[000268] DA---------- * STORE_LCL_VAR long V11 rat0
N001 ( 1, 1) [000269] ------------ t269 = LCL_VAR long V11 rat0
N002 ( 1, 1) [000270] -c---------- t270 = CNS_INT int 63
/--* t269 long
+--* t270 int
N003 ( 3, 3) [000271] ------------ t271 = * RSH long
N004 ( 1, 1) [000272] -c---------- t272 = CNS_INT long 3
/--* t271 long
+--* t272 long
N005 ( 5, 5) [000273] ------------ t273 = * AND long
N006 ( 1, 1) [000274] ------------ t274 = LCL_VAR long V11 rat0 (last use)
/--* t273 long
+--* t274 long
N007 ( 7, 7) [000275] ------------ t275 = * ADD long
N008 ( 1, 1) [000085] -c---------- t85 = CNS_INT long 2 $343
/--* t275 long
+--* t85 long
N009 ( 9, 9) [000276] ------------ t276 = * RSH long
N006 ( 1, 1) [000088] -c---------- t88 = CNS_INT long 5 $345
/--* t276 long
+--* t88 long
N007 ( 26, 9) [000089] ------------ t89 = * LSH long <l:$248, c:$249>
/--* t89 long
N009 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2
( 5, 5) [000186] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000183] ------------ t183 = LCL_VAR int V05 tmp4 u:6 $283
N002 ( 1, 1) [000184] -c---------- t184 = CNS_INT int 0 $40
/--* t183 int
+--* t184 int
N003 ( 3, 3) [000182] J------N---- * LE void $208
N004 ( 5, 5) [000185] ------------ * JTRUE void
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
N001 ( 0, 0) [000261] ------------ t261 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ t251 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t261 long
+--* t251 long
N005 ( 2, 2) [000200] ------------ t200 = * PHI long
/--* t200 long
N007 ( 2, 3) [000201] DA---------- * STORE_LCL_VAR long V09 tmp8 d:3
N001 ( 0, 0) [000263] ------------ t263 = PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ t253 = PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
/--* t263 int
+--* t253 int
N005 ( 2, 2) [000192] ------------ t192 = * PHI int
/--* t192 int
N007 ( 2, 3) [000193] DA---------- * STORE_LCL_VAR int V08 tmp7 d:3
N001 ( 0, 0) [000265] ------------ t265 = PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ t255 = PHI_ARG int V05 tmp4 u:6 $283
/--* t265 int
+--* t255 int
N005 ( 2, 2) [000188] ------------ t188 = * PHI int
/--* t188 int
N007 ( 2, 3) [000189] DA---------- * STORE_LCL_VAR int V05 tmp4 d:7
( 4, 4) [000106] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000100] ------------ t100 = LCL_VAR int V08 tmp7 u:3 $285
/--* t100 int
N002 ( 2, 2) [000101] ------------ t101 = * HWIntrinsic int TrailingZeroCount $400
N003 ( 1, 1) [000102] -c---------- t102 = CNS_INT int 1 $4b
/--* t101 int
+--* t102 int
N004 ( 4, 4) [000103] ------------ t103 = * ADD int $20a
/--* t103 int
N006 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2
( 4, 5) [000113] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000107] ------------ t107 = LCL_VAR long V09 tmp8 u:3 (last use) $145
N002 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V10 tmp9 u:2 $20a
/--* t108 int
N003 ( 2, 3) [000109] ---------U-- t109 = * CAST long <- ulong <- uint $24a
/--* t107 long
+--* t109 long
N004 ( 4, 5) [000110] ------------ t110 = * ADD long $24b
/--* t110 long
N006 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4
( 3, 3) [000119] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:7 (last use) $286
N002 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20b
/--* t116 int
N005 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8
( 8, 5) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000120] ------------ t120 = LCL_VAR int V08 tmp7 u:3 (last use) $285
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V10 tmp9 u:2 (last use) $20a
/--* t120 int
+--* t121 int
N005 ( 8, 5) [000124] ------------ t124 = * RSZ int $20d
/--* t124 int
N007 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4
( 5, 5) [000098] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V05 tmp4 u:8 $20b
N002 ( 1, 1) [000095] -c---------- t95 = CNS_INT int 0 $40
/--* t94 int
+--* t95 int
N003 ( 3, 3) [000096] J------N---- * GT void $20e
N004 ( 5, 5) [000097] ------------ * JTRUE void
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
N001 ( 0, 0) [000259] ------------ t259 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ t257 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t259 long
+--* t257 long
N005 ( 2, 2) [000196] ------------ t196 = * PHI long
/--* t196 long
N007 ( 2, 3) [000197] DA---------- * STORE_LCL_VAR long V09 tmp8 d:5
N001 ( 1, 1) [000129] C----------- t129 = LCL_VAR int V09 tmp8 u:5 (last use) $20f
N002 ( 1, 1) [000131] -c---------- t131 = CNS_INT int -1 $41
/--* t129 int
+--* t131 int
N003 ( 3, 3) [000132] ------------ t132 = * ADD int $210
/--* t132 int
N004 ( 4, 4) [000010] ------------ * RETURN int $1c7
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 1 BB03 0.25 [000..001) i LIR
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target LIR
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000147] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
/--* t176 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000150] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 1, 3) [000020] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V04 tmp3 u:2 $80
/--* t17 int
N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000181] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000178] ------------ t178 = LCL_VAR int V05 tmp4 u:2 $80
N002 ( 1, 1) [000179] -c---------- t179 = CNS_INT int 0 $40
/--* t178 int
+--* t179 int
N003 ( 3, 3) [000177] J------N---- * LE void $200
N004 ( 5, 5) [000180] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000239] ------------ t239 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ t227 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t239 long
+--* t227 long
N005 ( 2, 2) [000224] ------------ t224 = * PHI long
/--* t224 long
N007 ( 2, 3) [000225] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000241] ------------ t241 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ t229 = PHI_ARG int V04 tmp3 u:2 $80
/--* t241 int
+--* t229 int
N005 ( 2, 2) [000212] ------------ t212 = * PHI int
/--* t212 int
N007 ( 2, 3) [000213] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 1, 3) [000031] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000028] ------------ t28 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t28 int
N003 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 1, 3) [000041] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR long V03 tmp2 u:3 (last use) $141
/--* t33 long
N003 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2
( 3, 3) [000044] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR long V06 tmp5 u:2 $141
N002 ( 1, 1) [000036] -c---------- t36 = CNS_INT long 8 $340
/--* t34 long
+--* t36 long
N003 ( 3, 3) [000037] ------------ t37 = * ADD long $241
/--* t37 long
N005 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 7, 7) [000052] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V05 tmp4 u:3 $280
N002 ( 1, 1) [000042] ------------ t42 = LCL_VAR long V06 tmp5 u:2 (last use) $141
/--* t42 long
N003 ( 3, 2) [000045] *c-XG------- t45 = * IND long <l:$142, c:$302>
/--* t45 long
N004 ( 4, 3) [000046] ---XG------- t46 = * HWIntrinsic long PopCount $380
/--* t46 long
N005 ( 5, 5) [000047] ---XG------- t47 = * CAST int <- long $201
/--* t32 int
+--* t47 int
N006 ( 7, 7) [000048] ---XG------- t48 = * SUB int $202
/--* t48 int
N008 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 5, 5) [000026] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V04 tmp3 u:4 $202
N002 ( 1, 1) [000023] -c---------- t23 = CNS_INT int 0 $40
/--* t22 int
+--* t23 int
N003 ( 3, 3) [000024] J------N---- * GT void $203
N004 ( 5, 5) [000025] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000235] ------------ t235 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ t231 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t235 long
+--* t231 long
N005 ( 2, 2) [000220] ------------ t220 = * PHI long
/--* t220 long
N007 ( 2, 3) [000221] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000237] ------------ t237 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ t233 = PHI_ARG int V05 tmp4 u:2 $80
/--* t237 int
+--* t233 int
N005 ( 2, 2) [000216] ------------ t216 = * PHI int
/--* t216 int
N007 ( 2, 3) [000217] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
( 3, 3) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000054] ------------ t54 = LCL_VAR long V03 tmp2 u:5 (last use) $143
N002 ( 1, 1) [000056] -c---------- t56 = CNS_INT long -8 $342
/--* t54 long
+--* t56 long
N003 ( 3, 3) [000057] ------------ t57 = * ADD long $242
/--* t57 long
N005 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2
( 6, 5) [000069] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V05 tmp4 u:4 $281
N002 ( 1, 1) [000062] ------------ t62 = LCL_VAR long V07 tmp6 u:2 $242
/--* t62 long
N003 ( 3, 2) [000063] *c-XG------- t63 = * IND int <l:$282, c:$1c2>
/--* t63 int
N004 ( 4, 3) [000064] ---XG------- t64 = * HWIntrinsic int PopCount $3c0
/--* t61 int
+--* t64 int
N005 ( 6, 5) [000065] ---XG------- t65 = * SUB int $205
/--* t65 int
N007 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5
( 5, 5) [000074] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000070] ------------ t70 = LCL_VAR int V04 tmp3 u:5 $205
N002 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 0 $40
/--* t70 int
+--* t71 int
N003 ( 3, 3) [000072] J------N---- * LE void $206
N004 ( 5, 5) [000073] ------------ * JTRUE void
------------ BB04 [000..001), preds={BB03} succs={BB05}
( 1, 3) [000137] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000134] ------------ t134 = LCL_VAR int V04 tmp3 u:5 (last use) $205
/--* t134 int
N003 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5
( 3, 3) [000144] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000138] ------------ t138 = LCL_VAR long V07 tmp6 u:2 (last use) $242
N002 ( 1, 1) [000140] -c---------- t140 = CNS_INT long 4 $343
/--* t138 long
+--* t140 long
N003 ( 3, 3) [000141] ------------ t141 = * ADD long $243
/--* t141 long
N005 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
N001 ( 0, 0) [000247] ------------ t247 = PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ t243 = PHI_ARG long V07 tmp6 u:2 $242
/--* t247 long
+--* t243 long
N005 ( 2, 2) [000208] ------------ t208 = * PHI long
/--* t208 long
N007 ( 6, 5) [000209] DA---------- * STORE_LCL_VAR long V07 tmp6 d:4
N001 ( 0, 0) [000249] ------------ t249 = PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ t245 = PHI_ARG int V05 tmp4 u:4 $281
/--* t249 int
+--* t245 int
N005 ( 2, 2) [000204] ------------ t204 = * PHI int
/--* t204 int
N007 ( 2, 3) [000205] DA---------- * STORE_LCL_VAR int V05 tmp4 d:6
( 3, 3) [000080] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR long V07 tmp6 u:4 $144
/--* t76 long
N002 ( 3, 2) [000077] *--XG------- t77 = * IND int <l:$284, c:$1c5>
/--* t77 int
N004 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2
( 26, 9) [000092] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000081] ------------ t81 = LCL_VAR long V07 tmp6 u:4 (last use) $144
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t81 long
+--* t82 long
N003 ( 3, 3) [000083] ------------ t83 = * SUB long <l:$244, c:$245>
/--* t83 long
[000268] DA---------- * STORE_LCL_VAR long V11 rat0
N001 ( 1, 1) [000269] ------------ t269 = LCL_VAR long V11 rat0
N002 ( 1, 1) [000270] -c---------- t270 = CNS_INT int 63
/--* t269 long
+--* t270 int
N003 ( 3, 3) [000271] ------------ t271 = * RSH long
N004 ( 1, 1) [000272] -c---------- t272 = CNS_INT long 3
/--* t271 long
+--* t272 long
N005 ( 5, 5) [000273] ------------ t273 = * AND long
N006 ( 1, 1) [000274] ------------ t274 = LCL_VAR long V11 rat0 (last use)
/--* t273 long
+--* t274 long
N007 ( 7, 7) [000275] ------------ t275 = * ADD long
N008 ( 1, 1) [000085] -c---------- t85 = CNS_INT long 2 $343
/--* t275 long
+--* t85 long
N009 ( 9, 9) [000276] ------------ t276 = * RSH long
N006 ( 1, 1) [000088] -c---------- t88 = CNS_INT long 5 $345
/--* t276 long
+--* t88 long
N007 ( 26, 9) [000089] ------------ t89 = * LSH long <l:$248, c:$249>
/--* t89 long
N009 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2
( 5, 5) [000186] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000183] ------------ t183 = LCL_VAR int V05 tmp4 u:6 $283
N002 ( 1, 1) [000184] -c---------- t184 = CNS_INT int 0 $40
/--* t183 int
+--* t184 int
N003 ( 3, 3) [000182] J------N---- * LE void $208
N004 ( 5, 5) [000185] ------------ * JTRUE void
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
N001 ( 0, 0) [000261] ------------ t261 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ t251 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t261 long
+--* t251 long
N005 ( 2, 2) [000200] ------------ t200 = * PHI long
/--* t200 long
N007 ( 2, 3) [000201] DA---------- * STORE_LCL_VAR long V09 tmp8 d:3
N001 ( 0, 0) [000263] ------------ t263 = PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ t253 = PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
/--* t263 int
+--* t253 int
N005 ( 2, 2) [000192] ------------ t192 = * PHI int
/--* t192 int
N007 ( 2, 3) [000193] DA---------- * STORE_LCL_VAR int V08 tmp7 d:3
N001 ( 0, 0) [000265] ------------ t265 = PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ t255 = PHI_ARG int V05 tmp4 u:6 $283
/--* t265 int
+--* t255 int
N005 ( 2, 2) [000188] ------------ t188 = * PHI int
/--* t188 int
N007 ( 2, 3) [000189] DA---------- * STORE_LCL_VAR int V05 tmp4 d:7
( 4, 4) [000106] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000100] ------------ t100 = LCL_VAR int V08 tmp7 u:3 $285
/--* t100 int
N002 ( 2, 2) [000101] ------------ t101 = * HWIntrinsic int TrailingZeroCount $400
N003 ( 1, 1) [000102] -c---------- t102 = CNS_INT int 1 $4b
/--* t101 int
+--* t102 int
N004 ( 4, 4) [000103] ------------ t103 = * ADD int $20a
/--* t103 int
N006 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2
( 4, 5) [000113] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000107] ------------ t107 = LCL_VAR long V09 tmp8 u:3 (last use) $145
N002 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V10 tmp9 u:2 $20a
/--* t108 int
N003 ( 2, 3) [000109] ---------U-- t109 = * CAST long <- ulong <- uint $24a
/--* t107 long
+--* t109 long
N004 ( 4, 5) [000110] ------------ t110 = * ADD long $24b
/--* t110 long
N006 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4
( 3, 3) [000119] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:7 (last use) $286
N002 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20b
/--* t116 int
N005 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8
( 8, 5) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000120] ------------ t120 = LCL_VAR int V08 tmp7 u:3 (last use) $285
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V10 tmp9 u:2 (last use) $20a
/--* t120 int
+--* t121 int
N005 ( 8, 5) [000124] ------------ t124 = * RSZ int $20d
/--* t124 int
N007 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4
( 5, 5) [000098] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V05 tmp4 u:8 $20b
N002 ( 1, 1) [000095] -c---------- t95 = CNS_INT int 0 $40
/--* t94 int
+--* t95 int
N003 ( 3, 3) [000096] J------N---- * GT void $20e
N004 ( 5, 5) [000097] ------------ * JTRUE void
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
N001 ( 0, 0) [000259] ------------ t259 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ t257 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t259 long
+--* t257 long
N005 ( 2, 2) [000196] ------------ t196 = * PHI long
/--* t196 long
N007 ( 2, 3) [000197] DA---------- * STORE_LCL_VAR long V09 tmp8 d:5
N001 ( 1, 1) [000129] C----------- t129 = LCL_VAR int V09 tmp8 u:5 (last use) $20f
N002 ( 1, 1) [000131] -c---------- t131 = CNS_INT int -1 $41
/--* t129 int
+--* t131 int
N003 ( 3, 3) [000132] ------------ t132 = * ADD int $210
/--* t132 int
N004 ( 4, 4) [000010] ------------ * RETURN int $1c7
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 1 BB03 0.25 [000..001) i LIR
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target LIR
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000147] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
/--* t176 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000150] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 1, 3) [000020] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V04 tmp3 u:2 $80
/--* t17 int
N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000181] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000178] ------------ t178 = LCL_VAR int V05 tmp4 u:2 $80
N002 ( 1, 1) [000179] -c---------- t179 = CNS_INT int 0 $40
/--* t178 int
+--* t179 int
N003 ( 3, 3) [000177] J------N---- * LE void $200
N004 ( 5, 5) [000180] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000239] ------------ t239 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ t227 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t239 long
+--* t227 long
N005 ( 2, 2) [000224] ------------ t224 = * PHI long
/--* t224 long
N007 ( 2, 3) [000225] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000241] ------------ t241 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ t229 = PHI_ARG int V04 tmp3 u:2 $80
/--* t241 int
+--* t229 int
N005 ( 2, 2) [000212] ------------ t212 = * PHI int
/--* t212 int
N007 ( 2, 3) [000213] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 1, 3) [000031] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000028] ------------ t28 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t28 int
N003 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 1, 3) [000041] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR long V03 tmp2 u:3 (last use) $141
/--* t33 long
N003 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2
( 3, 3) [000044] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR long V06 tmp5 u:2 $141
N002 ( 1, 1) [000036] -c---------- t36 = CNS_INT long 8 $340
/--* t34 long
+--* t36 long
N003 ( 3, 3) [000037] ------------ t37 = * ADD long $241
/--* t37 long
N005 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 7, 7) [000052] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V05 tmp4 u:3 $280
N002 ( 1, 1) [000042] ------------ t42 = LCL_VAR long V06 tmp5 u:2 (last use) $141
/--* t42 long
N003 ( 3, 2) [000045] *c-XG------- t45 = * IND long <l:$142, c:$302>
/--* t45 long
N004 ( 4, 3) [000046] ---XG------- t46 = * HWIntrinsic long PopCount $380
/--* t46 long
N005 ( 5, 5) [000047] ---XG------- t47 = * CAST int <- long $201
/--* t32 int
+--* t47 int
N006 ( 7, 7) [000048] ---XG------- t48 = * SUB int $202
/--* t48 int
N008 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 5, 5) [000026] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V04 tmp3 u:4 $202
N002 ( 1, 1) [000023] -c---------- t23 = CNS_INT int 0 $40
/--* t22 int
+--* t23 int
N003 ( 3, 3) [000024] J------N---- * GT void $203
N004 ( 5, 5) [000025] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000235] ------------ t235 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ t231 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t235 long
+--* t231 long
N005 ( 2, 2) [000220] ------------ t220 = * PHI long
/--* t220 long
N007 ( 2, 3) [000221] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000237] ------------ t237 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ t233 = PHI_ARG int V05 tmp4 u:2 $80
/--* t237 int
+--* t233 int
N005 ( 2, 2) [000216] ------------ t216 = * PHI int
/--* t216 int
N007 ( 2, 3) [000217] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
( 3, 3) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000054] ------------ t54 = LCL_VAR long V03 tmp2 u:5 (last use) $143
N002 ( 1, 1) [000056] -c---------- t56 = CNS_INT long -8 $342
/--* t54 long
+--* t56 long
N003 ( 3, 3) [000057] ------------ t57 = * ADD long $242
/--* t57 long
N005 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2
( 6, 5) [000069] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V05 tmp4 u:4 $281
N002 ( 1, 1) [000062] ------------ t62 = LCL_VAR long V07 tmp6 u:2 $242
/--* t62 long
N003 ( 3, 2) [000063] *c-XG------- t63 = * IND int <l:$282, c:$1c2>
/--* t63 int
N004 ( 4, 3) [000064] ---XG------- t64 = * HWIntrinsic int PopCount $3c0
/--* t61 int
+--* t64 int
N005 ( 6, 5) [000065] ---XG------- t65 = * SUB int $205
/--* t65 int
N007 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5
( 5, 5) [000074] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000070] ------------ t70 = LCL_VAR int V04 tmp3 u:5 $205
N002 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 0 $40
/--* t70 int
+--* t71 int
N003 ( 3, 3) [000072] J------N---- * LE void $206
N004 ( 5, 5) [000073] ------------ * JTRUE void
------------ BB04 [000..001), preds={BB03} succs={BB05}
( 1, 3) [000137] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000134] ------------ t134 = LCL_VAR int V04 tmp3 u:5 (last use) $205
/--* t134 int
N003 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5
( 3, 3) [000144] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000138] ------------ t138 = LCL_VAR long V07 tmp6 u:2 (last use) $242
N002 ( 1, 1) [000140] -c---------- t140 = CNS_INT long 4 $343
/--* t138 long
+--* t140 long
N003 ( 3, 3) [000141] ------------ t141 = * ADD long $243
/--* t141 long
N005 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
N001 ( 0, 0) [000247] ------------ t247 = PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ t243 = PHI_ARG long V07 tmp6 u:2 $242
/--* t247 long
+--* t243 long
N005 ( 2, 2) [000208] ------------ t208 = * PHI long
/--* t208 long
N007 ( 6, 5) [000209] DA---------- * STORE_LCL_VAR long V07 tmp6 d:4
N001 ( 0, 0) [000249] ------------ t249 = PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ t245 = PHI_ARG int V05 tmp4 u:4 $281
/--* t249 int
+--* t245 int
N005 ( 2, 2) [000204] ------------ t204 = * PHI int
/--* t204 int
N007 ( 2, 3) [000205] DA---------- * STORE_LCL_VAR int V05 tmp4 d:6
( 3, 3) [000080] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR long V07 tmp6 u:4 $144
/--* t76 long
N002 ( 3, 2) [000077] *--XG------- t77 = * IND int <l:$284, c:$1c5>
/--* t77 int
N004 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2
( 26, 9) [000092] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000081] ------------ t81 = LCL_VAR long V07 tmp6 u:4 (last use) $144
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t81 long
+--* t82 long
N003 ( 3, 3) [000083] ------------ t83 = * SUB long <l:$244, c:$245>
/--* t83 long
[000268] DA---------- * STORE_LCL_VAR long V11 rat0
N001 ( 1, 1) [000269] ------------ t269 = LCL_VAR long V11 rat0
N002 ( 1, 1) [000270] -c---------- t270 = CNS_INT int 63
/--* t269 long
+--* t270 int
N003 ( 3, 3) [000271] ------------ t271 = * RSH long
N004 ( 1, 1) [000272] -c---------- t272 = CNS_INT long 3
/--* t271 long
+--* t272 long
N005 ( 5, 5) [000273] ------------ t273 = * AND long
N006 ( 1, 1) [000274] ------------ t274 = LCL_VAR long V11 rat0 (last use)
/--* t273 long
+--* t274 long
N007 ( 7, 7) [000275] ------------ t275 = * ADD long
N008 ( 1, 1) [000085] -c---------- t85 = CNS_INT long 2 $343
/--* t275 long
+--* t85 long
N009 ( 9, 9) [000276] ------------ t276 = * RSH long
N006 ( 1, 1) [000088] -c---------- t88 = CNS_INT long 5 $345
/--* t276 long
+--* t88 long
N007 ( 26, 9) [000089] ------------ t89 = * LSH long <l:$248, c:$249>
/--* t89 long
N009 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2
( 5, 5) [000186] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000183] ------------ t183 = LCL_VAR int V05 tmp4 u:6 $283
N002 ( 1, 1) [000184] -c---------- t184 = CNS_INT int 0 $40
/--* t183 int
+--* t184 int
N003 ( 3, 3) [000182] J------N---- * LE void $208
N004 ( 5, 5) [000185] ------------ * JTRUE void
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
N001 ( 0, 0) [000261] ------------ t261 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ t251 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t261 long
+--* t251 long
N005 ( 2, 2) [000200] ------------ t200 = * PHI long
/--* t200 long
N007 ( 2, 3) [000201] DA---------- * STORE_LCL_VAR long V09 tmp8 d:3
N001 ( 0, 0) [000263] ------------ t263 = PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ t253 = PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
/--* t263 int
+--* t253 int
N005 ( 2, 2) [000192] ------------ t192 = * PHI int
/--* t192 int
N007 ( 2, 3) [000193] DA---------- * STORE_LCL_VAR int V08 tmp7 d:3
N001 ( 0, 0) [000265] ------------ t265 = PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ t255 = PHI_ARG int V05 tmp4 u:6 $283
/--* t265 int
+--* t255 int
N005 ( 2, 2) [000188] ------------ t188 = * PHI int
/--* t188 int
N007 ( 2, 3) [000189] DA---------- * STORE_LCL_VAR int V05 tmp4 d:7
( 4, 4) [000106] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000100] ------------ t100 = LCL_VAR int V08 tmp7 u:3 $285
/--* t100 int
N002 ( 2, 2) [000101] ------------ t101 = * HWIntrinsic int TrailingZeroCount $400
N003 ( 1, 1) [000102] -c---------- t102 = CNS_INT int 1 $4b
/--* t101 int
+--* t102 int
N004 ( 4, 4) [000103] ------------ t103 = * ADD int $20a
/--* t103 int
N006 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2
( 4, 5) [000113] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000107] ------------ t107 = LCL_VAR long V09 tmp8 u:3 (last use) $145
N002 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V10 tmp9 u:2 $20a
/--* t108 int
N003 ( 2, 3) [000109] ---------U-- t109 = * CAST long <- ulong <- uint $24a
/--* t107 long
+--* t109 long
N004 ( 4, 5) [000110] ------------ t110 = * ADD long $24b
/--* t110 long
N006 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4
( 3, 3) [000119] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:7 (last use) $286
N002 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20b
/--* t116 int
N005 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8
( 8, 5) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000120] ------------ t120 = LCL_VAR int V08 tmp7 u:3 (last use) $285
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V10 tmp9 u:2 (last use) $20a
/--* t120 int
+--* t121 int
N005 ( 8, 5) [000124] ------------ t124 = * RSZ int $20d
/--* t124 int
N007 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4
( 5, 5) [000098] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V05 tmp4 u:8 $20b
N002 ( 1, 1) [000095] -c---------- t95 = CNS_INT int 0 $40
/--* t94 int
+--* t95 int
N003 ( 3, 3) [000096] J------N---- * GT void $20e
N004 ( 5, 5) [000097] ------------ * JTRUE void
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
N001 ( 0, 0) [000259] ------------ t259 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ t257 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t259 long
+--* t257 long
N005 ( 2, 2) [000196] ------------ t196 = * PHI long
/--* t196 long
N007 ( 2, 3) [000197] DA---------- * STORE_LCL_VAR long V09 tmp8 d:5
N001 ( 1, 1) [000129] C----------- t129 = LCL_VAR int V09 tmp8 u:5 (last use) $20f
N002 ( 1, 1) [000131] -c---------- t131 = CNS_INT int -1 $41
/--* t129 int
+--* t131 int
N003 ( 3, 3) [000132] ------------ t132 = * ADD int $210
/--* t132 int
N004 ( 4, 4) [000010] ------------ * RETURN int $1c7
-------------------------------------------------------------------------------------------------------------------
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB03 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB02 2 [000..001)-> BB02 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB01,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 1 BB03 0.25 [000..001) i LIR
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target LIR
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 12) [000147] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] $100
/--* t176 long
N002 ( 5, 12) [000001] x---G------- t1 = * IND long <l:$140, c:$180>
/--* t1 long
N004 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2
( 1, 3) [000150] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 (last use) $80
/--* t3 int
N003 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2
( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 <l:$140, c:$180>
/--* t13 long
N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2
( 1, 3) [000020] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V04 tmp3 u:2 $80
/--* t17 int
N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2
( 5, 5) [000181] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000178] ------------ t178 = LCL_VAR int V05 tmp4 u:2 $80
N002 ( 1, 1) [000179] -c---------- t179 = CNS_INT int 0 $40
/--* t178 int
+--* t179 int
N003 ( 3, 3) [000177] J------N---- * LE void $200
N004 ( 5, 5) [000180] ------------ * JTRUE void
------------ BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
N001 ( 0, 0) [000239] ------------ t239 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ t227 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t239 long
+--* t227 long
N005 ( 2, 2) [000224] ------------ t224 = * PHI long
/--* t224 long
N007 ( 2, 3) [000225] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000241] ------------ t241 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ t229 = PHI_ARG int V04 tmp3 u:2 $80
/--* t241 int
+--* t229 int
N005 ( 2, 2) [000212] ------------ t212 = * PHI int
/--* t212 int
N007 ( 2, 3) [000213] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
( 1, 3) [000031] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000028] ------------ t28 = LCL_VAR int V04 tmp3 u:3 (last use) $280
/--* t28 int
N003 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3
( 1, 3) [000041] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR long V03 tmp2 u:3 (last use) $141
/--* t33 long
N003 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2
( 3, 3) [000044] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR long V06 tmp5 u:2 $141
N002 ( 1, 1) [000036] -c---------- t36 = CNS_INT long 8 $340
/--* t34 long
+--* t36 long
N003 ( 3, 3) [000037] ------------ t37 = * ADD long $241
/--* t37 long
N005 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4
( 7, 7) [000052] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V05 tmp4 u:3 $280
N002 ( 1, 1) [000042] ------------ t42 = LCL_VAR long V06 tmp5 u:2 (last use) $141
/--* t42 long
N003 ( 3, 2) [000045] *c-XG------- t45 = * IND long <l:$142, c:$302>
/--* t45 long
N004 ( 4, 3) [000046] ---XG------- t46 = * HWIntrinsic long PopCount $380
/--* t46 long
N005 ( 5, 5) [000047] ---XG------- t47 = * CAST int <- long $201
/--* t32 int
+--* t47 int
N006 ( 7, 7) [000048] ---XG------- t48 = * SUB int $202
/--* t48 int
N008 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4
( 5, 5) [000026] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V04 tmp3 u:4 $202
N002 ( 1, 1) [000023] -c---------- t23 = CNS_INT int 0 $40
/--* t22 int
+--* t23 int
N003 ( 3, 3) [000024] J------N---- * GT void $203
N004 ( 5, 5) [000025] ------------ * JTRUE void
------------ BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000235] ------------ t235 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ t231 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t235 long
+--* t231 long
N005 ( 2, 2) [000220] ------------ t220 = * PHI long
/--* t220 long
N007 ( 2, 3) [000221] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000237] ------------ t237 = PHI_ARG int V05 tmp4 u:3
N002 ( 0, 0) [000233] ------------ t233 = PHI_ARG int V05 tmp4 u:2 $80
/--* t237 int
+--* t233 int
N005 ( 2, 2) [000216] ------------ t216 = * PHI int
/--* t216 int
N007 ( 2, 3) [000217] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4
( 3, 3) [000060] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000054] ------------ t54 = LCL_VAR long V03 tmp2 u:5 (last use) $143
N002 ( 1, 1) [000056] -c---------- t56 = CNS_INT long -8 $342
/--* t54 long
+--* t56 long
N003 ( 3, 3) [000057] ------------ t57 = * ADD long $242
/--* t57 long
N005 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2
( 6, 5) [000069] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V05 tmp4 u:4 $281
N002 ( 1, 1) [000062] ------------ t62 = LCL_VAR long V07 tmp6 u:2 $242
/--* t62 long
N003 ( 3, 2) [000063] *c-XG------- t63 = * IND int <l:$282, c:$1c2>
/--* t63 int
N004 ( 4, 3) [000064] ---XG------- t64 = * HWIntrinsic int PopCount $3c0
/--* t61 int
+--* t64 int
N005 ( 6, 5) [000065] ---XG------- t65 = * SUB int $205
/--* t65 int
N007 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5
( 5, 5) [000074] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000070] ------------ t70 = LCL_VAR int V04 tmp3 u:5 $205
N002 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 0 $40
/--* t70 int
+--* t71 int
N003 ( 3, 3) [000072] J------N---- * LE void $206
N004 ( 5, 5) [000073] ------------ * JTRUE void
------------ BB04 [000..001), preds={BB03} succs={BB05}
( 1, 3) [000137] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000134] ------------ t134 = LCL_VAR int V04 tmp3 u:5 (last use) $205
/--* t134 int
N003 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5
( 3, 3) [000144] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000138] ------------ t138 = LCL_VAR long V07 tmp6 u:2 (last use) $242
N002 ( 1, 1) [000140] -c---------- t140 = CNS_INT long 4 $343
/--* t138 long
+--* t140 long
N003 ( 3, 3) [000141] ------------ t141 = * ADD long $243
/--* t141 long
N005 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
N001 ( 0, 0) [000247] ------------ t247 = PHI_ARG long V07 tmp6 u:3
N002 ( 0, 0) [000243] ------------ t243 = PHI_ARG long V07 tmp6 u:2 $242
/--* t247 long
+--* t243 long
N005 ( 2, 2) [000208] ------------ t208 = * PHI long
/--* t208 long
N007 ( 6, 5) [000209] DA---------- * STORE_LCL_VAR long V07 tmp6 d:4
N001 ( 0, 0) [000249] ------------ t249 = PHI_ARG int V05 tmp4 u:5
N002 ( 0, 0) [000245] ------------ t245 = PHI_ARG int V05 tmp4 u:4 $281
/--* t249 int
+--* t245 int
N005 ( 2, 2) [000204] ------------ t204 = * PHI int
/--* t204 int
N007 ( 2, 3) [000205] DA---------- * STORE_LCL_VAR int V05 tmp4 d:6
( 3, 3) [000080] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR long V07 tmp6 u:4 $144
/--* t76 long
N002 ( 3, 2) [000077] *--XG------- t77 = * IND int <l:$284, c:$1c5>
/--* t77 int
N004 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2
( 26, 9) [000092] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000081] ------------ t81 = LCL_VAR long V07 tmp6 u:4 (last use) $144
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR long V02 tmp1 u:2 (last use) <l:$140, c:$180>
/--* t81 long
+--* t82 long
N003 ( 3, 3) [000083] ------------ t83 = * SUB long <l:$244, c:$245>
/--* t83 long
[000268] DA---------- * STORE_LCL_VAR long V11 rat0
N001 ( 1, 1) [000269] ------------ t269 = LCL_VAR long V11 rat0
N002 ( 1, 1) [000270] -c---------- t270 = CNS_INT int 63
/--* t269 long
+--* t270 int
N003 ( 3, 3) [000271] ------------ t271 = * RSH long
N004 ( 1, 1) [000272] -c---------- t272 = CNS_INT long 3
/--* t271 long
+--* t272 long
N005 ( 5, 5) [000273] ------------ t273 = * AND long
N006 ( 1, 1) [000274] ------------ t274 = LCL_VAR long V11 rat0 (last use)
/--* t273 long
+--* t274 long
N007 ( 7, 7) [000275] ------------ t275 = * ADD long
N008 ( 1, 1) [000085] -c---------- t85 = CNS_INT long 2 $343
/--* t275 long
+--* t85 long
N009 ( 9, 9) [000276] ------------ t276 = * RSH long
N006 ( 1, 1) [000088] -c---------- t88 = CNS_INT long 5 $345
/--* t276 long
+--* t88 long
N007 ( 26, 9) [000089] ------------ t89 = * LSH long <l:$248, c:$249>
/--* t89 long
N009 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2
( 5, 5) [000186] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000183] ------------ t183 = LCL_VAR int V05 tmp4 u:6 $283
N002 ( 1, 1) [000184] -c---------- t184 = CNS_INT int 0 $40
/--* t183 int
+--* t184 int
N003 ( 3, 3) [000182] J------N---- * LE void $208
N004 ( 5, 5) [000185] ------------ * JTRUE void
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
N001 ( 0, 0) [000261] ------------ t261 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000251] ------------ t251 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t261 long
+--* t251 long
N005 ( 2, 2) [000200] ------------ t200 = * PHI long
/--* t200 long
N007 ( 2, 3) [000201] DA---------- * STORE_LCL_VAR long V09 tmp8 d:3
N001 ( 0, 0) [000263] ------------ t263 = PHI_ARG int V08 tmp7 u:4
N002 ( 0, 0) [000253] ------------ t253 = PHI_ARG int V08 tmp7 u:2 <l:$284, c:$1c5>
/--* t263 int
+--* t253 int
N005 ( 2, 2) [000192] ------------ t192 = * PHI int
/--* t192 int
N007 ( 2, 3) [000193] DA---------- * STORE_LCL_VAR int V08 tmp7 d:3
N001 ( 0, 0) [000265] ------------ t265 = PHI_ARG int V05 tmp4 u:8
N002 ( 0, 0) [000255] ------------ t255 = PHI_ARG int V05 tmp4 u:6 $283
/--* t265 int
+--* t255 int
N005 ( 2, 2) [000188] ------------ t188 = * PHI int
/--* t188 int
N007 ( 2, 3) [000189] DA---------- * STORE_LCL_VAR int V05 tmp4 d:7
( 4, 4) [000106] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000100] ------------ t100 = LCL_VAR int V08 tmp7 u:3 $285
/--* t100 int
N002 ( 2, 2) [000101] ------------ t101 = * HWIntrinsic int TrailingZeroCount $400
N003 ( 1, 1) [000102] -c---------- t102 = CNS_INT int 1 $4b
/--* t101 int
+--* t102 int
N004 ( 4, 4) [000103] ------------ t103 = * ADD int $20a
/--* t103 int
N006 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2
( 4, 5) [000113] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000107] ------------ t107 = LCL_VAR long V09 tmp8 u:3 (last use) $145
N002 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V10 tmp9 u:2 $20a
/--* t108 int
N003 ( 2, 3) [000109] ---------U-- t109 = * CAST long <- ulong <- uint $24a
/--* t107 long
+--* t109 long
N004 ( 4, 5) [000110] ------------ t110 = * ADD long $24b
/--* t110 long
N006 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4
( 3, 3) [000119] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:7 (last use) $286
N002 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 $41
/--* t114 int
+--* t115 int
N003 ( 3, 3) [000116] ------------ t116 = * ADD int $20b
/--* t116 int
N005 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8
( 8, 5) [000127] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000120] ------------ t120 = LCL_VAR int V08 tmp7 u:3 (last use) $285
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V10 tmp9 u:2 (last use) $20a
/--* t120 int
+--* t121 int
N005 ( 8, 5) [000124] ------------ t124 = * RSZ int $20d
/--* t124 int
N007 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4
( 5, 5) [000098] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V05 tmp4 u:8 $20b
N002 ( 1, 1) [000095] -c---------- t95 = CNS_INT int 0 $40
/--* t94 int
+--* t95 int
N003 ( 3, 3) [000096] J------N---- * GT void $20e
N004 ( 5, 5) [000097] ------------ * JTRUE void
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
N001 ( 0, 0) [000259] ------------ t259 = PHI_ARG long V09 tmp8 u:4
N002 ( 0, 0) [000257] ------------ t257 = PHI_ARG long V09 tmp8 u:2 <l:$248, c:$249>
/--* t259 long
+--* t257 long
N005 ( 2, 2) [000196] ------------ t196 = * PHI long
/--* t196 long
N007 ( 2, 3) [000197] DA---------- * STORE_LCL_VAR long V09 tmp8 d:5
N001 ( 1, 1) [000129] C----------- t129 = LCL_VAR int V09 tmp8 u:5 (last use) $20f
N002 ( 1, 1) [000131] -c---------- t131 = CNS_INT int -1 $41
/--* t129 int
+--* t131 int
N003 ( 3, 3) [000132] ------------ t132 = * ADD int $210
/--* t132 int
N004 ( 4, 4) [000010] ------------ * RETURN int $1c7
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{V00}
{V02 V03 V04 V05}
{V00}
{V02 V03 V04 V05}
BB02 use def in out
{V03 V04}
{V03 V04 V05 V06}
{V02 V03 V04}
{V02 V03 V04 V05}
BB03 use def in out
{V03 V05}
{V04 V07}
{V02 V03 V05}
{V02 V04 V05 V07}
BB04 use def in out
{V04 V07}
{V05 V07}
{V02 V04 V07}
{V02 V05 V07}
BB05 use def in out
{V02 V05 V07}
{V08 V09 V11}
{V02 V05 V07}
{V05 V08 V09}
BB06 use def in out
{V05 V08 V09}
{V05 V08 V09 V10}
{V05 V08 V09}
{V05 V08 V09}
BB07 use def in out
{V09}
{}
{V09}
{}
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
Interval 7: RefPositions {} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {} physReg:NA Preferences=[allInt]
Interval 9: RefPositions {} physReg:NA Preferences=[allInt]
Interval 10: RefPositions {} physReg:NA Preferences=[allInt]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 1, singleExit = 1
; Decided to create an EBP based frame for ETW stackwalking (BasicBlock Count)
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 ) BB02( 2 ) BB03( 0.50) BB04( 0.25) BB05( 0.50) BB06( 2 ) BB07( 1 )
BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N000. IL_OFFSET IL offset: 0x0
N001. t176* = CNS_INT(h) 0x7fe9bcfc4498 static Fseq[_bits]
N002. t1 = IND ; t176*
N004. V02(t146); t1
N000. IL_OFFSET IL offset: 0x0
N001. V00(t3*)
N003. V04(t149); t3*
N000. IL_OFFSET IL offset: 0x0
N001. V02(t13)
N003. V03(t15); t13
N000. IL_OFFSET IL offset: 0x0
N001. V04(t17)
N003. V05(t19); t17
N000. IL_OFFSET IL offset: 0x0
N001. V05(t178)
N002. CNS_INT 0
N003. LE ; t178
N004. JTRUE
BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V04(t28*)
N003. V05(t30); t28*
N000. IL_OFFSET IL offset: 0x0
N001. V03(t33*)
N003. V06(t40); t33*
N000. IL_OFFSET IL offset: 0x0
N001. V06(t34)
N002. CNS_INT 8
N003. t37 = ADD ; t34
N005. V03(t43); t37
N000. IL_OFFSET IL offset: 0x0
N001. V05(t32)
N002. V06(t42*)
N003. t45 = IND ; t42*
N004. t46 = HWIntrinsic; t45
N005. t47 = CAST ; t46
N006. t48 = SUB ; t32,t47
N008. V04(t51); t48
N000. IL_OFFSET IL offset: 0x0
N001. V04(t22)
N002. CNS_INT 0
N003. GT ; t22
N004. JTRUE
BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V03(t54*)
N002. CNS_INT -8
N003. t57 = ADD ; t54*
N005. V07(t59); t57
N000. IL_OFFSET IL offset: 0x0
N001. V05(t61)
N002. V07(t62)
N003. t63 = IND ; t62
N004. t64 = HWIntrinsic; t63
N005. t65 = SUB ; t61,t64
N007. V04(t68); t65
N000. IL_OFFSET IL offset: 0x0
N001. V04(t70)
N002. CNS_INT 0
N003. LE ; t70
N004. JTRUE
BB04 [000..001), preds={BB03} succs={BB05}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V04(t134*)
N003. V05(t136); t134*
N000. IL_OFFSET IL offset: 0x0
N001. V07(t138*)
N002. CNS_INT 4
N003. t141 = ADD ; t138*
N005. V07(t143); t141
BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V07(t76)
N002. t77 = IND ; t76
N004. V08(t79); t77
N000. IL_OFFSET IL offset: 0x0
N001. V07(t81*)
N002. V02(t82*)
N003. t83 = SUB ; t81*,t82*
N000. V11(t268); t83
N001. V11(t269)
N002. CNS_INT 63
N003. t271 = RSH ; t269
N004. CNS_INT 3
N005. t273 = AND ; t271
N006. V11(t274*)
N007. t275 = ADD ; t273,t274*
N008. CNS_INT 2
N009. t276 = RSH ; t275
N006. CNS_INT 5
N007. t89 = LSH ; t276
N009. V09(t91); t89
N000. IL_OFFSET IL offset: 0x0
N001. V05(t183)
N002. CNS_INT 0
N003. LE ; t183
N004. JTRUE
BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V08(t100)
N002. t101 = HWIntrinsic; t100
N003. CNS_INT 1
N004. t103 = ADD ; t101
N006. V10(t105); t103
N000. IL_OFFSET IL offset: 0x0
N001. V09(t107*)
N002. V10(t108)
N003. t109 = CAST ; t108
N004. t110 = ADD ; t107*,t109
N006. V09(t112); t110
N000. IL_OFFSET IL offset: 0x0
N001. V05(t114*)
N002. CNS_INT -1
N003. t116 = ADD ; t114*
N005. V05(t118); t116
N000. IL_OFFSET IL offset: 0x0
N001. V08(t120*)
N002. V10(t121*)
N005. t124 = RSZ ; t120*,t121*
N007. V08(t126); t124
N000. IL_OFFSET IL offset: 0x0
N001. V05(t94)
N002. CNS_INT 0
N003. GT ; t94
N004. JTRUE
BB07 [000..001) (return), preds={BB05,BB06} succs={}
=====
N001. V09(t129*)
N002. CNS_INT -1
N003. t132 = ADD ; t129*
N004. RETURN ; t132
buildIntervals second part ========
Int arg V00 in reg rdi
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
NEW BLOCK BB01
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N003 ( 5, 12) [000147] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N005 ( 3, 10) [000176] ------------ * CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] REG NA $100
Interval 11: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #2 @6 RefTypeDef <Ivl:11> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N005.t176. CNS_INT }
N007 ( 5, 12) [000001] x---G------- * IND long REG NA <l:$140, c:$180>
<RefPosition #3 @7 RefTypeUse <Ivl:11> BB01 regmask=[allInt] minReg=1 last>
Interval 12: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #4 @8 RefTypeDef <Ivl:12> IND BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N007.t1. IND }
N009 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2 NA REG NA
<RefPosition #5 @9 RefTypeUse <Ivl:12> BB01 regmask=[allInt] minReg=1 last>
Assigning related <L1> to <I12>
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N011 ( 1, 3) [000150] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N013 ( 1, 1) [000003] ------------ * LCL_VAR int V00 arg0 u:2 NA (last use) REG NA $80
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N015 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2 NA REG NA
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Assigning related <L3> to <L0>
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N017 ( 1, 3) [000016] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N019 ( 1, 1) [000013] ------------ * LCL_VAR long V02 tmp1 u:2 NA REG NA <l:$140, c:$180>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N021 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2 NA REG NA
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N023 ( 1, 3) [000020] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N025 ( 1, 1) [000017] ------------ * LCL_VAR int V04 tmp3 u:2 NA REG NA $80
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N027 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2 NA REG NA
<RefPosition #11 @27 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #12 @28 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N029 ( 5, 5) [000181] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N031 ( 1, 1) [000178] ------------ * LCL_VAR int V05 tmp4 u:2 NA REG NA $80
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N033 ( 1, 1) [000179] -c---------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N035 ( 3, 3) [000177] J------N---- * LE void REG NA $200
<RefPosition #13 @35 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N037 ( 5, 5) [000180] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 1, liveout={V02 V03 V04 V05}
==============================
use: {V00}
def: {V02 V03 V04 V05}
NEW BLOCK BB02
Setting BB02 as the predecessor for determining incoming variable registers of BB01
<RefPosition #14 @39 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N041 ( 1, 3) [000031] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N043 ( 1, 1) [000028] ------------ * LCL_VAR int V04 tmp3 u:3 NA (last use) REG NA $280
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N045 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3 NA REG NA
<RefPosition #15 @45 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Assigning related <L4> to <L3>
<RefPosition #16 @46 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N047 ( 1, 3) [000041] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N049 ( 1, 1) [000033] ------------ * LCL_VAR long V03 tmp2 u:3 NA (last use) REG NA $141
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N051 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2 NA REG NA
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Assigning related <L5> to <L2>
<RefPosition #18 @52 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N053 ( 3, 3) [000044] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N055 ( 1, 1) [000034] ------------ * LCL_VAR long V06 tmp5 u:2 NA REG NA $141
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N057 ( 1, 1) [000036] -c---------- * CNS_INT long 8 REG NA $340
Contained
DefList: { }
N059 ( 3, 3) [000037] ------------ * ADD long REG NA $241
<RefPosition #19 @59 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 13: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #20 @60 RefTypeDef <Ivl:13> ADD BB02 regmask=[allInt] minReg=1>
Assigning related <L5> to <I13>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N059.t37. ADD }
N061 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4 NA REG NA
<RefPosition #21 @61 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L2> to <I13>
<RefPosition #22 @62 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N063 ( 7, 7) [000052] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N065 ( 1, 1) [000032] ------------ * LCL_VAR int V05 tmp4 u:3 NA REG NA $280
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N067 ( 1, 1) [000042] ------------ * LCL_VAR long V06 tmp5 u:2 NA (last use) REG NA $141
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N069 ( 3, 2) [000045] *c-XG------- * IND long REG NA <l:$142, c:$302>
Contained
DefList: { }
N071 ( 4, 3) [000046] ---XG------- * HWIntrinsic long PopCount REG NA $380
<RefPosition #23 @71 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 14: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #24 @72 RefTypeDef <Ivl:14> HWIntrinsic BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N071.t46. HWIntrinsic }
N073 ( 5, 5) [000047] ---XG------- * CAST int <- long REG NA $201
<RefPosition #25 @73 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last>
Interval 15: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #26 @74 RefTypeDef <Ivl:15> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N073.t47. CAST }
N075 ( 7, 7) [000048] ---XG------- * SUB int REG NA $202
<RefPosition #27 @75 RefTypeUse <Ivl:4 V05> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #28 @75 RefTypeUse <Ivl:15> BB02 regmask=[allInt] minReg=1 last>
Interval 16: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #29 @76 RefTypeDef <Ivl:16> SUB BB02 regmask=[allInt] minReg=1>
Assigning related <L4> to <I16>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N075.t48. SUB }
N077 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4 NA REG NA
<RefPosition #30 @77 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last>
Assigning related <L3> to <I16>
<RefPosition #31 @78 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N079 ( 5, 5) [000026] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N081 ( 1, 1) [000022] ------------ * LCL_VAR int V04 tmp3 u:4 NA REG NA $202
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N083 ( 1, 1) [000023] -c---------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N085 ( 3, 3) [000024] J------N---- * GT void REG NA $203
<RefPosition #32 @85 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N087 ( 5, 5) [000025] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
Exposed uses:<RefPosition #33 @89 RefTypeExpUse <Ivl:3 V04> BB02 regmask=[allInt] minReg=1>
V04
CHECKING LAST USES for block 2, liveout={V02 V03 V04 V05}
==============================
use: {V03 V04}
def: {V03 V04 V05 V06}
NEW BLOCK BB03
Setting BB03 as the predecessor for determining incoming variable registers of BB02
<RefPosition #34 @89 RefTypeBB BB03 regmask=[] minReg=1>
DefList: { }
N091 ( 3, 3) [000060] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N093 ( 1, 1) [000054] ------------ * LCL_VAR long V03 tmp2 u:5 NA (last use) REG NA $143
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N095 ( 1, 1) [000056] -c---------- * CNS_INT long -8 REG NA $342
Contained
DefList: { }
N097 ( 3, 3) [000057] ------------ * ADD long REG NA $242
<RefPosition #35 @97 RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
Interval 17: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #36 @98 RefTypeDef <Ivl:17> ADD BB03 regmask=[allInt] minReg=1>
Assigning related <L2> to <I17>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N097.t57. ADD }
N099 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2 NA REG NA
<RefPosition #37 @99 RefTypeUse <Ivl:17> BB03 regmask=[allInt] minReg=1 last>
Assigning related <L6> to <I17>
<RefPosition #38 @100 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N101 ( 6, 5) [000069] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N103 ( 1, 1) [000061] ------------ * LCL_VAR int V05 tmp4 u:4 NA REG NA $281
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N105 ( 1, 1) [000062] ------------ * LCL_VAR long V07 tmp6 u:2 NA REG NA $242
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N107 ( 3, 2) [000063] *c-XG------- * IND int REG NA <l:$282, c:$1c2>
Contained
DefList: { }
N109 ( 4, 3) [000064] ---XG------- * HWIntrinsic int PopCount REG NA $3c0
<RefPosition #39 @109 RefTypeUse <Ivl:6 V07> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
Interval 18: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #40 @110 RefTypeDef <Ivl:18> HWIntrinsic BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N109.t64. HWIntrinsic }
N111 ( 6, 5) [000065] ---XG------- * SUB int REG NA $205
<RefPosition #41 @111 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
<RefPosition #42 @111 RefTypeUse <Ivl:18> BB03 regmask=[allInt] minReg=1 last>
Interval 19: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #43 @112 RefTypeDef <Ivl:19> SUB BB03 regmask=[allInt] minReg=1>
Assigning related <L4> to <I19>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N111.t65. SUB }
N113 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5 NA REG NA
<RefPosition #44 @113 RefTypeUse <Ivl:19> BB03 regmask=[allInt] minReg=1 last>
Assigning related <L3> to <I19>
<RefPosition #45 @114 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N115 ( 5, 5) [000074] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N117 ( 1, 1) [000070] ------------ * LCL_VAR int V04 tmp3 u:5 NA REG NA $205
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N119 ( 1, 1) [000071] -c---------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N121 ( 3, 3) [000072] J------N---- * LE void REG NA $206
<RefPosition #46 @121 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N123 ( 5, 5) [000073] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 3, liveout={V02 V04 V05 V07}
==============================
use: {V03 V05}
def: {V04 V07}
NEW BLOCK BB04
Setting BB04 as the predecessor for determining incoming variable registers of BB03
<RefPosition #47 @125 RefTypeBB BB04 regmask=[] minReg=1>
DefList: { }
N127 ( 1, 3) [000137] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N129 ( 1, 1) [000134] ------------ * LCL_VAR int V04 tmp3 u:5 NA (last use) REG NA $205
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N131 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5 NA REG NA
<RefPosition #48 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #49 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N133 ( 3, 3) [000144] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N135 ( 1, 1) [000138] ------------ * LCL_VAR long V07 tmp6 u:2 NA (last use) REG NA $242
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N137 ( 1, 1) [000140] -c---------- * CNS_INT long 4 REG NA $343
Contained
DefList: { }
N139 ( 3, 3) [000141] ------------ * ADD long REG NA $243
<RefPosition #50 @139 RefTypeUse <Ivl:6 V07> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
Interval 20: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #51 @140 RefTypeDef <Ivl:20> ADD BB04 regmask=[allInt] minReg=1>
Assigning related <L6> to <I20>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N139.t141. ADD }
N141 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3 NA REG NA
<RefPosition #52 @141 RefTypeUse <Ivl:20> BB04 regmask=[allInt] minReg=1 last>
Assigning related <L6> to <I20>
<RefPosition #53 @142 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
CHECKING LAST USES for block 4, liveout={V02 V05 V07}
==============================
use: {V04 V07}
def: {V05 V07}
NEW BLOCK BB05
Setting BB05 as the predecessor for determining incoming variable registers of BB03
<RefPosition #54 @143 RefTypeBB BB05 regmask=[] minReg=1>
DefList: { }
N145 ( 3, 3) [000080] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N147 ( 1, 1) [000076] ------------ * LCL_VAR long V07 tmp6 u:4 NA REG NA $144
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N149 ( 3, 2) [000077] *--XG------- * IND int REG NA <l:$284, c:$1c5>
<RefPosition #55 @149 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 21: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #56 @150 RefTypeDef <Ivl:21> IND BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N149.t77. IND }
N151 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2 NA REG NA
<RefPosition #57 @151 RefTypeUse <Ivl:21> BB05 regmask=[allInt] minReg=1 last>
Assigning related <L7> to <I21>
<RefPosition #58 @152 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N153 ( 26, 9) [000092] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N155 ( 1, 1) [000081] ------------ * LCL_VAR long V07 tmp6 u:4 NA (last use) REG NA $144
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N157 ( 1, 1) [000082] ------------ * LCL_VAR long V02 tmp1 u:2 NA (last use) REG NA <l:$140, c:$180>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N159 ( 3, 3) [000083] ------------ * SUB long REG NA <l:$244, c:$245>
<RefPosition #59 @159 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #60 @159 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 22: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #61 @160 RefTypeDef <Ivl:22> SUB BB05 regmask=[allInt] minReg=1>
Assigning related <L6> to <I22>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N159.t83. SUB }
N161 (???,???) [000268] DA---------- * STORE_LCL_VAR long V11 rat0 NA REG NA
<RefPosition #62 @161 RefTypeUse <Ivl:22> BB05 regmask=[allInt] minReg=1 last>
Assigning related <L10> to <I22>
<RefPosition #63 @162 RefTypeDef <Ivl:10 V11> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N163 ( 1, 1) [000269] ------------ * LCL_VAR long V11 rat0 NA REG NA
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N165 ( 1, 1) [000270] -c---------- * CNS_INT int 63 REG NA
Contained
DefList: { }
N167 ( 3, 3) [000271] ------------ * RSH long REG NA
<RefPosition #64 @167 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 23: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #65 @168 RefTypeDef <Ivl:23> RSH BB05 regmask=[allInt] minReg=1>
Assigning related <L10> to <I23>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N167.t271. RSH }
N169 ( 1, 1) [000272] -c---------- * CNS_INT long 3 REG NA
Contained
DefList: { N167.t271. RSH }
N171 ( 5, 5) [000273] ------------ * AND long REG NA
<RefPosition #66 @171 RefTypeUse <Ivl:23> BB05 regmask=[allInt] minReg=1 last>
Interval 24: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #67 @172 RefTypeDef <Ivl:24> AND BB05 regmask=[allInt] minReg=1>
Assigning related <I23> to <I24>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N171.t273. AND }
N173 ( 1, 1) [000274] ------------ * LCL_VAR long V11 rat0 NA (last use) REG NA
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { N171.t273. AND }
N175 ( 7, 7) [000275] ------------ * ADD long REG NA
<RefPosition #68 @175 RefTypeUse <Ivl:24> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #69 @175 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
Interval 25: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #70 @176 RefTypeDef <Ivl:25> ADD BB05 regmask=[allInt] minReg=1>
Assigning related <I24> to <I25>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N175.t275. ADD }
N177 ( 1, 1) [000085] -c---------- * CNS_INT long 2 REG NA $343
Contained
DefList: { N175.t275. ADD }
N179 ( 9, 9) [000276] ------------ * RSH long REG NA
<RefPosition #71 @179 RefTypeUse <Ivl:25> BB05 regmask=[allInt] minReg=1 last>
Interval 26: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #72 @180 RefTypeDef <Ivl:26> RSH BB05 regmask=[allInt] minReg=1>
Assigning related <I25> to <I26>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N179.t276. RSH }
N181 ( 1, 1) [000088] -c---------- * CNS_INT long 5 REG NA $345
Contained
DefList: { N179.t276. RSH }
N183 ( 26, 9) [000089] ------------ * LSH long REG NA <l:$248, c:$249>
<RefPosition #73 @183 RefTypeUse <Ivl:26> BB05 regmask=[allInt] minReg=1 last>
Interval 27: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #74 @184 RefTypeDef <Ivl:27> LSH BB05 regmask=[allInt] minReg=1>
Assigning related <I26> to <I27>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N183.t89. LSH }
N185 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2 NA REG NA
<RefPosition #75 @185 RefTypeUse <Ivl:27> BB05 regmask=[allInt] minReg=1 last>
Assigning related <L8> to <I27>
<RefPosition #76 @186 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N187 ( 5, 5) [000186] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N189 ( 1, 1) [000183] ------------ * LCL_VAR int V05 tmp4 u:6 NA REG NA $283
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N191 ( 1, 1) [000184] -c---------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N193 ( 3, 3) [000182] J------N---- * LE void REG NA $208
<RefPosition #77 @193 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N195 ( 5, 5) [000185] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
CHECKING LAST USES for block 5, liveout={V05 V08 V09}
==============================
use: {V02 V05 V07}
def: {V08 V09 V11}
NEW BLOCK BB06
Setting BB06 as the predecessor for determining incoming variable registers of BB05
<RefPosition #78 @197 RefTypeBB BB06 regmask=[] minReg=1>
DefList: { }
N199 ( 4, 4) [000106] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N201 ( 1, 1) [000100] ------------ * LCL_VAR int V08 tmp7 u:3 NA REG NA $285
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N203 ( 2, 2) [000101] ------------ * HWIntrinsic int TrailingZeroCount REG NA $400
<RefPosition #79 @203 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
Interval 28: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #80 @204 RefTypeDef <Ivl:28> HWIntrinsic BB06 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N203.t101. HWIntrinsic }
N205 ( 1, 1) [000102] -c---------- * CNS_INT int 1 REG NA $4b
Contained
DefList: { N203.t101. HWIntrinsic }
N207 ( 4, 4) [000103] ------------ * ADD int REG NA $20a
<RefPosition #81 @207 RefTypeUse <Ivl:28> BB06 regmask=[allInt] minReg=1 last>
Interval 29: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #82 @208 RefTypeDef <Ivl:29> ADD BB06 regmask=[allInt] minReg=1>
Assigning related <I28> to <I29>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N207.t103. ADD }
N209 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2 NA REG NA
<RefPosition #83 @209 RefTypeUse <Ivl:29> BB06 regmask=[allInt] minReg=1 last>
Assigning related <L9> to <I29>
<RefPosition #84 @210 RefTypeDef <Ivl:9 V10> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N211 ( 4, 5) [000113] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N213 ( 1, 1) [000107] ------------ * LCL_VAR long V09 tmp8 u:3 NA (last use) REG NA $145
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N215 ( 1, 1) [000108] ------------ * LCL_VAR int V10 tmp9 u:2 NA REG NA $20a
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N217 ( 2, 3) [000109] ---------U-- * CAST long <- ulong <- uint REG NA $24a
<RefPosition #85 @217 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
Interval 30: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #86 @218 RefTypeDef <Ivl:30> CAST BB06 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N217.t109. CAST }
N219 ( 4, 5) [000110] ------------ * ADD long REG NA $24b
<RefPosition #87 @219 RefTypeUse <Ivl:8 V09> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
<RefPosition #88 @219 RefTypeUse <Ivl:30> BB06 regmask=[allInt] minReg=1 last>
Interval 31: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #89 @220 RefTypeDef <Ivl:31> ADD BB06 regmask=[allInt] minReg=1>
Assigning related <L8> to <I31>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N219.t110. ADD }
N221 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4 NA REG NA
<RefPosition #90 @221 RefTypeUse <Ivl:31> BB06 regmask=[allInt] minReg=1 last>
Assigning related <L8> to <I31>
<RefPosition #91 @222 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N223 ( 3, 3) [000119] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N225 ( 1, 1) [000114] ------------ * LCL_VAR int V05 tmp4 u:7 NA (last use) REG NA $286
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N227 ( 1, 1) [000115] -c---------- * CNS_INT int -1 REG NA $41
Contained
DefList: { }
N229 ( 3, 3) [000116] ------------ * ADD int REG NA $20b
<RefPosition #92 @229 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
Interval 32: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #93 @230 RefTypeDef <Ivl:32> ADD BB06 regmask=[allInt] minReg=1>
Assigning related <L4> to <I32>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N229.t116. ADD }
N231 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8 NA REG NA
<RefPosition #94 @231 RefTypeUse <Ivl:32> BB06 regmask=[allInt] minReg=1 last>
Assigning related <L4> to <I32>
<RefPosition #95 @232 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N233 ( 8, 5) [000127] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N235 ( 1, 1) [000120] ------------ * LCL_VAR int V08 tmp7 u:3 NA (last use) REG NA $285
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N237 ( 1, 1) [000121] ------------ * LCL_VAR int V10 tmp9 u:2 NA (last use) REG NA $20a
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N239 ( 8, 5) [000124] ------------ * RSZ int REG NA $20d
<RefPosition #96 @239 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #97 @239 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #98 @239 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #99 @240 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1>
Interval 33: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #100 @240 RefTypeDef <Ivl:33> RSZ BB06 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
Assigning related <L7> to <I33>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N239.t124. RSZ }
N241 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4 NA REG NA
<RefPosition #101 @241 RefTypeUse <Ivl:33> BB06 regmask=[allInt] minReg=1 last>
Assigning related <L7> to <I33>
<RefPosition #102 @242 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N243 ( 5, 5) [000098] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N245 ( 1, 1) [000094] ------------ * LCL_VAR int V05 tmp4 u:8 NA REG NA $20b
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { }
N247 ( 1, 1) [000095] -c---------- * CNS_INT int 0 REG NA $40
Contained
DefList: { }
N249 ( 3, 3) [000096] J------N---- * GT void REG NA $20e
<RefPosition #103 @249 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N251 ( 5, 5) [000097] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
Exposed uses:<RefPosition #104 @253 RefTypeExpUse <Ivl:4 V05> BB06 regmask=[allInt] minReg=1>
V05<RefPosition #105 @253 RefTypeExpUse <Ivl:7 V08> BB06 regmask=[allInt] minReg=1>
V08
CHECKING LAST USES for block 6, liveout={V05 V08 V09}
==============================
use: {V05 V08 V09}
def: {V05 V08 V09 V10}
NEW BLOCK BB07
Setting BB07 as the predecessor for determining incoming variable registers of BB06
<RefPosition #106 @253 RefTypeBB BB07 regmask=[] minReg=1>
DefList: { }
N255 ( 1, 1) [000129] C----------- * LCL_VAR int V09 tmp8 u:5 NA (last use) REG NA $20f
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { }
N257 ( 1, 1) [000131] -c---------- * CNS_INT int -1 REG NA $41
Contained
DefList: { }
N259 ( 3, 3) [000132] ------------ * ADD int REG NA $210
<RefPosition #107 @259 RefTypeUse <Ivl:8 V09> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
Interval 34: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #108 @260 RefTypeDef <Ivl:34> ADD BB07 regmask=[allInt] minReg=1>
Assigning related <L8> to <I34>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N259.t132. ADD }
N261 ( 4, 4) [000010] ------------ * RETURN int REG NA $1c7
<RefPosition #109 @261 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #110 @261 RefTypeUse <Ivl:34> BB07 regmask=[rax] minReg=1 last fixed>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
CHECKING LAST USES for block 7, liveout={}
==============================
use: {V09}
def: {}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) RefPositions {#0@0 #7@15} physReg:rdi Preferences=[rdi] RelatedInterval <L3>[0000000002327E78]
Interval 1: (V02) RefPositions {#6@10 #9@21 #60@159} physReg:NA Preferences=[allInt]
Interval 2: (V03) RefPositions {#10@22 #17@51 #22@62 #35@97} physReg:NA Preferences=[allInt] RelatedInterval <L5>[0000000002327F18]
Interval 3: (V04) RefPositions {#8@16 #11@27 #15@45 #31@78 #32@85 #33@89 #45@114 #46@121 #48@131} physReg:NA Preferences=[allInt] RelatedInterval <L4>[0000000002327EC8]
Interval 4: (V05) RefPositions {#12@28 #13@35 #16@46 #27@75 #41@111 #49@132 #77@193 #92@229 #95@232 #103@249 #104@253} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 5: (V06) RefPositions {#18@52 #19@59 #23@71} physReg:NA Preferences=[allInt]
Interval 6: (V07) RefPositions {#38@100 #39@109 #50@139 #53@142 #55@149 #59@159} physReg:NA Preferences=[allInt]
Interval 7: (V08) RefPositions {#58@152 #79@203 #96@239 #102@242 #105@253} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 8: (V09) RefPositions {#76@186 #87@219 #91@222 #107@259} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 9: (V10) RefPositions {#84@210 #85@217 #98@239} physReg:NA Preferences=[rcx]
Interval 10: (V11) RefPositions {#63@162 #64@167 #69@175} physReg:NA Preferences=[allInt]
Interval 11: (constant) RefPositions {#2@6 #3@7} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#4@8 #5@9} physReg:NA Preferences=[allInt] RelatedInterval <L1>[0000000002327DD8]
Interval 13: RefPositions {#20@60 #21@61} physReg:NA Preferences=[allInt] RelatedInterval <L2>[0000000002327E28]
Interval 14: RefPositions {#24@72 #25@73} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#26@74 #28@75} physReg:NA Preferences=[allInt]
Interval 16: (interfering uses) RefPositions {#29@76 #30@77} physReg:NA Preferences=[allInt] RelatedInterval <L3>[0000000002327E78]
Interval 17: RefPositions {#36@98 #37@99} physReg:NA Preferences=[allInt] RelatedInterval <L6>[0000000002327F68]
Interval 18: RefPositions {#40@110 #42@111} physReg:NA Preferences=[allInt]
Interval 19: (interfering uses) RefPositions {#43@112 #44@113} physReg:NA Preferences=[allInt] RelatedInterval <L3>[0000000002327E78]
Interval 20: RefPositions {#51@140 #52@141} physReg:NA Preferences=[allInt] RelatedInterval <L6>[0000000002327F68]
Interval 21: RefPositions {#56@150 #57@151} physReg:NA Preferences=[allInt] RelatedInterval <L7>[0000000002327FB8]
Interval 22: (interfering uses) RefPositions {#61@160 #62@161} physReg:NA Preferences=[allInt] RelatedInterval <L10>[00000000023280A8]
Interval 23: RefPositions {#65@168 #66@171} physReg:NA Preferences=[allInt] RelatedInterval <L10>[00000000023280A8]
Interval 24: RefPositions {#67@172 #68@175} physReg:NA Preferences=[allInt] RelatedInterval <I23>[000000000232AA30]
Interval 25: RefPositions {#70@176 #71@179} physReg:NA Preferences=[allInt] RelatedInterval <I24>[000000000232AB80]
Interval 26: RefPositions {#72@180 #73@183} physReg:NA Preferences=[allInt] RelatedInterval <I25>[000000000232AD10]
Interval 27: RefPositions {#74@184 #75@185} physReg:NA Preferences=[allInt] RelatedInterval <L8>[0000000002328008]
Interval 28: RefPositions {#80@204 #81@207} physReg:NA Preferences=[allInt]
Interval 29: RefPositions {#82@208 #83@209} physReg:NA Preferences=[allInt] RelatedInterval <L9>[0000000002328058]
Interval 30: RefPositions {#86@218 #88@219} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#89@220 #90@221} physReg:NA Preferences=[allInt] RelatedInterval <L8>[0000000002328008]
Interval 32: RefPositions {#93@230 #94@231} physReg:NA Preferences=[allInt] RelatedInterval <L4>[0000000002327EC8]
Interval 33: (interfering uses) RefPositions {#100@240 #101@241} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15] RelatedInterval <L7>[0000000002327FB8]
Interval 34: RefPositions {#108@260 #110@261} physReg:NA Preferences=[rax] RelatedInterval <L8>[0000000002328008]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @6 RefTypeDef <Ivl:11> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #3 @7 RefTypeUse <Ivl:11> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #4 @8 RefTypeDef <Ivl:12> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #5 @9 RefTypeUse <Ivl:12> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @27 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #12 @28 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @35 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional>
<RefPosition #14 @39 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #15 @45 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #16 @46 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #18 @52 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #19 @59 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @60 RefTypeDef <Ivl:13> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #21 @61 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #22 @62 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #23 @71 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #24 @72 RefTypeDef <Ivl:14> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #25 @73 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #26 @74 RefTypeDef <Ivl:15> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @75 RefTypeUse <Ivl:4 V05> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #28 @75 RefTypeUse <Ivl:15> BB02 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #29 @76 RefTypeDef <Ivl:16> SUB BB02 regmask=[allInt] minReg=1>
<RefPosition #30 @77 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #31 @78 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @85 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #33 @89 RefTypeExpUse <Ivl:3 V04> BB02 regmask=[allInt] minReg=1>
<RefPosition #34 @89 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #35 @97 RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
<RefPosition #36 @98 RefTypeDef <Ivl:17> ADD BB03 regmask=[allInt] minReg=1>
<RefPosition #37 @99 RefTypeUse <Ivl:17> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #38 @100 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #39 @109 RefTypeUse <Ivl:6 V07> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #40 @110 RefTypeDef <Ivl:18> HWIntrinsic BB03 regmask=[allInt] minReg=1>
<RefPosition #41 @111 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #42 @111 RefTypeUse <Ivl:18> BB03 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #43 @112 RefTypeDef <Ivl:19> SUB BB03 regmask=[allInt] minReg=1>
<RefPosition #44 @113 RefTypeUse <Ivl:19> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #45 @114 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #46 @121 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[allInt] minReg=1 regOptional>
<RefPosition #47 @125 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #48 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #49 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #50 @139 RefTypeUse <Ivl:6 V07> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #51 @140 RefTypeDef <Ivl:20> ADD BB04 regmask=[allInt] minReg=1>
<RefPosition #52 @141 RefTypeUse <Ivl:20> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #53 @142 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #54 @143 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #55 @149 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #56 @150 RefTypeDef <Ivl:21> IND BB05 regmask=[allInt] minReg=1>
<RefPosition #57 @151 RefTypeUse <Ivl:21> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #58 @152 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #59 @159 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #60 @159 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #61 @160 RefTypeDef <Ivl:22> SUB BB05 regmask=[allInt] minReg=1>
<RefPosition #62 @161 RefTypeUse <Ivl:22> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #63 @162 RefTypeDef <Ivl:10 V11> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #64 @167 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #65 @168 RefTypeDef <Ivl:23> RSH BB05 regmask=[allInt] minReg=1>
<RefPosition #66 @171 RefTypeUse <Ivl:23> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #67 @172 RefTypeDef <Ivl:24> AND BB05 regmask=[allInt] minReg=1>
<RefPosition #68 @175 RefTypeUse <Ivl:24> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #69 @175 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #70 @176 RefTypeDef <Ivl:25> ADD BB05 regmask=[allInt] minReg=1>
<RefPosition #71 @179 RefTypeUse <Ivl:25> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #72 @180 RefTypeDef <Ivl:26> RSH BB05 regmask=[allInt] minReg=1>
<RefPosition #73 @183 RefTypeUse <Ivl:26> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #74 @184 RefTypeDef <Ivl:27> LSH BB05 regmask=[allInt] minReg=1>
<RefPosition #75 @185 RefTypeUse <Ivl:27> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #76 @186 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #77 @193 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 regOptional>
<RefPosition #78 @197 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #79 @203 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #80 @204 RefTypeDef <Ivl:28> HWIntrinsic BB06 regmask=[allInt] minReg=1>
<RefPosition #81 @207 RefTypeUse <Ivl:28> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #82 @208 RefTypeDef <Ivl:29> ADD BB06 regmask=[allInt] minReg=1>
<RefPosition #83 @209 RefTypeUse <Ivl:29> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #84 @210 RefTypeDef <Ivl:9 V10> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #85 @217 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #86 @218 RefTypeDef <Ivl:30> CAST BB06 regmask=[allInt] minReg=1>
<RefPosition #87 @219 RefTypeUse <Ivl:8 V09> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #88 @219 RefTypeUse <Ivl:30> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #89 @220 RefTypeDef <Ivl:31> ADD BB06 regmask=[allInt] minReg=1>
<RefPosition #90 @221 RefTypeUse <Ivl:31> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #91 @222 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #92 @229 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
<RefPosition #93 @230 RefTypeDef <Ivl:32> ADD BB06 regmask=[allInt] minReg=1>
<RefPosition #94 @231 RefTypeUse <Ivl:32> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #95 @232 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #96 @239 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #97 @239 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #98 @239 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[rcx] minReg=1 last fixed delay>
<RefPosition #99 @240 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #100 @240 RefTypeDef <Ivl:33> RSZ BB06 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #101 @241 RefTypeUse <Ivl:33> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #102 @242 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #103 @249 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #104 @253 RefTypeExpUse <Ivl:4 V05> BB06 regmask=[allInt] minReg=1>
<RefPosition #105 @253 RefTypeExpUse <Ivl:7 V08> BB06 regmask=[allInt] minReg=1>
<RefPosition #106 @253 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #107 @259 RefTypeUse <Ivl:8 V09> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
<RefPosition #108 @260 RefTypeDef <Ivl:34> ADD BB07 regmask=[rax] minReg=1>
<RefPosition #109 @261 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #110 @261 RefTypeUse <Ivl:34> BB07 regmask=[rax] minReg=1 last fixed>
-----------------
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @27 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #15 @45 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #31 @78 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @85 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #33 @89 RefTypeExpUse <Ivl:3 V04> BB02 regmask=[allInt] minReg=1>
<RefPosition #45 @114 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #46 @121 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[allInt] minReg=1 regOptional>
<RefPosition #48 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #12 @28 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @35 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional>
<RefPosition #16 @46 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @75 RefTypeUse <Ivl:4 V05> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #41 @111 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #49 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #77 @193 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 regOptional>
<RefPosition #92 @229 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
<RefPosition #95 @232 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #103 @249 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #104 @253 RefTypeExpUse <Ivl:4 V05> BB06 regmask=[allInt] minReg=1>
-----------------
<RefPosition #18 @52 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #19 @59 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #23 @71 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #58 @152 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #79 @203 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #96 @239 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #102 @242 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #105 @253 RefTypeExpUse <Ivl:7 V08> BB06 regmask=[allInt] minReg=1>
-----------------
<RefPosition #84 @210 RefTypeDef <Ivl:9 V10> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #85 @217 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #98 @239 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[rcx] minReg=1 last fixed delay>
-----------------
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #22 @62 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #35 @97 RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #76 @186 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #87 @219 RefTypeUse <Ivl:8 V09> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #91 @222 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #107 @259 RefTypeUse <Ivl:8 V09> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #60 @159 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[allInt] minReg=1 last delay regOptional>
-----------------
<RefPosition #63 @162 RefTypeDef <Ivl:10 V11> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #64 @167 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #69 @175 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
-----------------
<RefPosition #38 @100 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #39 @109 RefTypeUse <Ivl:6 V07> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #50 @139 RefTypeUse <Ivl:6 V07> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #53 @142 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #55 @149 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #59 @159 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00
BB01 [000..011) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N003. IL_OFFSET IL offset: 0x0 REG NA
N005. CNS_INT(h) 0x7fe9bcfc4498 static Fseq[_bits] REG NA
Def:<I11>(#2)
N007. IND
Use:<I11>(#3) *
Def:<I12>(#4) Pref:<L1>
N009. V02(L1)
Use:<I12>(#5) *
Def:<L1>(#6)
N011. IL_OFFSET IL offset: 0x0 REG NA
N013. V00(L0)
N015. V04(L3)
Use:<L0>(#7) *
Def:<L3>(#8) Pref:<L4>
N017. IL_OFFSET IL offset: 0x0 REG NA
N019. V02(L1)
N021. V03(L2)
Use:<L1>(#9)
Def:<L2>(#10) Pref:<L5>
N023. IL_OFFSET IL offset: 0x0 REG NA
N025. V04(L3)
N027. V05(L4)
Use:<L3>(#11)
Def:<L4>(#12)
N029. IL_OFFSET IL offset: 0x0 REG NA
N031. V05(L4)
N033. CNS_INT 0 REG NA
N035. LE
Use:<L4>(#13)
N037. JTRUE
BB02 [000..001) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02}
=====
N041. IL_OFFSET IL offset: 0x0 REG NA
N043. V04(L3)
N045. V05(L4)
Use:<L3>(#15) *
Def:<L4>(#16)
N047. IL_OFFSET IL offset: 0x0 REG NA
N049. V03(L2)
N051. V06(L5)
Use:<L2>(#17) *
Def:<L5>(#18)
N053. IL_OFFSET IL offset: 0x0 REG NA
N055. V06(L5)
N057. CNS_INT 8 REG NA
N059. ADD
Use:<L5>(#19)
Def:<I13>(#20) Pref:<L2>
N061. V03(L2)
Use:<I13>(#21) *
Def:<L2>(#22) Pref:<L5>
N063. IL_OFFSET IL offset: 0x0 REG NA
N065. V05(L4)
N067. V06(L5)
N069. IND
N071. HWIntrinsic
Use:<L5>(#23) *
Def:<I14>(#24)
N073. CAST
Use:<I14>(#25) *
Def:<I15>(#26)
N075. SUB
Use:<L4>(#27)
Use:<I15>(#28) *
Def:<I16>(#29) Pref:<L3>
N077. V04(L3)
Use:<I16>(#30) *
Def:<L3>(#31) Pref:<L4>
N079. IL_OFFSET IL offset: 0x0 REG NA
N081. V04(L3)
N083. CNS_INT 0 REG NA
N085. GT
Use:<L3>(#32)
N087. JTRUE
Exposed use of V04 at #33
BB03 [000..001) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05}
=====
N091. IL_OFFSET IL offset: 0x0 REG NA
N093. V03(L2)
N095. CNS_INT -8 REG NA
N097. ADD
Use:<L2>(#35) *
Def:<I17>(#36) Pref:<L6>
N099. V07(L6)
Use:<I17>(#37) *
Def:<L6>(#38)
N101. IL_OFFSET IL offset: 0x0 REG NA
N103. V05(L4)
N105. V07(L6)
N107. IND
N109. HWIntrinsic
Use:<L6>(#39)
Def:<I18>(#40)
N111. SUB
Use:<L4>(#41)
Use:<I18>(#42) *
Def:<I19>(#43) Pref:<L3>
N113. V04(L3)
Use:<I19>(#44) *
Def:<L3>(#45) Pref:<L4>
N115. IL_OFFSET IL offset: 0x0 REG NA
N117. V04(L3)
N119. CNS_INT 0 REG NA
N121. LE
Use:<L3>(#46)
N123. JTRUE
BB04 [000..001), preds={BB03} succs={BB05}
=====
N127. IL_OFFSET IL offset: 0x0 REG NA
N129. V04(L3)
N131. V05(L4)
Use:<L3>(#48) *
Def:<L4>(#49)
N133. IL_OFFSET IL offset: 0x0 REG NA
N135. V07(L6)
N137. CNS_INT 4 REG NA
N139. ADD
Use:<L6>(#50) *
Def:<I20>(#51) Pref:<L6>
N141. V07(L6)
Use:<I20>(#52) *
Def:<L6>(#53)
BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
=====
N145. IL_OFFSET IL offset: 0x0 REG NA
N147. V07(L6)
N149. IND
Use:<L6>(#55)
Def:<I21>(#56) Pref:<L7>
N151. V08(L7)
Use:<I21>(#57) *
Def:<L7>(#58)
N153. IL_OFFSET IL offset: 0x0 REG NA
N155. V07(L6)
N157. V02(L1)
N159. SUB
Use:<L6>(#59) *
Use:<L1>(#60) *
Def:<I22>(#61) Pref:<L10>
N161. V11(L10)
Use:<I22>(#62) *
Def:<L10>(#63)
N163. V11(L10)
N165. CNS_INT 63 REG NA
N167. RSH
Use:<L10>(#64)
Def:<I23>(#65) Pref:<L10>
N169. CNS_INT 3 REG NA
N171. AND
Use:<I23>(#66) *
Def:<I24>(#67) Pref:<I23>
N173. V11(L10)
N175. ADD
Use:<I24>(#68) *
Use:<L10>(#69) *
Def:<I25>(#70) Pref:<I24>
N177. CNS_INT 2 REG NA
N179. RSH
Use:<I25>(#71) *
Def:<I26>(#72) Pref:<I25>
N181. CNS_INT 5 REG NA
N183. LSH
Use:<I26>(#73) *
Def:<I27>(#74) Pref:<L8>
N185. V09(L8)
Use:<I27>(#75) *
Def:<L8>(#76)
N187. IL_OFFSET IL offset: 0x0 REG NA
N189. V05(L4)
N191. CNS_INT 0 REG NA
N193. LE
Use:<L4>(#77)
N195. JTRUE
BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
=====
N199. IL_OFFSET IL offset: 0x0 REG NA
N201. V08(L7)
N203. HWIntrinsic
Use:<L7>(#79)
Def:<I28>(#80)
N205. CNS_INT 1 REG NA
N207. ADD
Use:<I28>(#81) *
Def:<I29>(#82) Pref:<L9>
N209. V10(L9)
Use:<I29>(#83) *
Def:<L9>(#84)
N211. IL_OFFSET IL offset: 0x0 REG NA
N213. V09(L8)
N215. V10(L9)
N217. CAST
Use:<L9>(#85)
Def:<I30>(#86)
N219. ADD
Use:<L8>(#87) *
Use:<I30>(#88) *
Def:<I31>(#89) Pref:<L8>
N221. V09(L8)
Use:<I31>(#90) *
Def:<L8>(#91)
N223. IL_OFFSET IL offset: 0x0 REG NA
N225. V05(L4)
N227. CNS_INT -1 REG NA
N229. ADD
Use:<L4>(#92) *
Def:<I32>(#93) Pref:<L4>
N231. V05(L4)
Use:<I32>(#94) *
Def:<L4>(#95)
N233. IL_OFFSET IL offset: 0x0 REG NA
N235. V08(L7)
N237. V10(L9)
N239. RSZ
Use:<L7>(#96) *
Use:<L9>(#98) Fixed:rcx(#97) *
Kill: rcx
Def:<I33>(#100) Pref:<L7>
N241. V08(L7)
Use:<I33>(#101) *
Def:<L7>(#102)
N243. IL_OFFSET IL offset: 0x0 REG NA
N245. V05(L4)
N247. CNS_INT 0 REG NA
N249. GT
Use:<L4>(#103)
N251. JTRUE
Exposed use of V05 at #104
Exposed use of V08 at #105
BB07 [000..001) (return), preds={BB05,BB06} succs={}
=====
N255. V09(L8)
N257. CNS_INT -1 REG NA
N259. ADD
Use:<L8>(#107) *
Def:<I34>(#108) Pref:<L8>
N261. RETURN
Use:<I34>(#110) Fixed:rax(#109) *
Linear scan intervals after buildIntervals:
Interval 0: (V00) RefPositions {#0@0 #7@15} physReg:rdi Preferences=[rdi] RelatedInterval <L3>[0000000002327E78]
Interval 1: (V02) RefPositions {#6@10 #9@21 #60@159} physReg:NA Preferences=[allInt]
Interval 2: (V03) RefPositions {#10@22 #17@51 #22@62 #35@97} physReg:NA Preferences=[allInt] RelatedInterval <L5>[0000000002327F18]
Interval 3: (V04) RefPositions {#8@16 #11@27 #15@45 #31@78 #32@85 #33@89 #45@114 #46@121 #48@131} physReg:NA Preferences=[allInt] RelatedInterval <L4>[0000000002327EC8]
Interval 4: (V05) RefPositions {#12@28 #13@35 #16@46 #27@75 #41@111 #49@132 #77@193 #92@229 #95@232 #103@249 #104@253} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 5: (V06) RefPositions {#18@52 #19@59 #23@71} physReg:NA Preferences=[allInt]
Interval 6: (V07) RefPositions {#38@100 #39@109 #50@139 #53@142 #55@149 #59@159} physReg:NA Preferences=[allInt]
Interval 7: (V08) RefPositions {#58@152 #79@203 #96@239 #102@242 #105@253} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 8: (V09) RefPositions {#76@186 #87@219 #91@222 #107@259} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 9: (V10) RefPositions {#84@210 #85@217 #98@239} physReg:NA Preferences=[rcx]
Interval 10: (V11) RefPositions {#63@162 #64@167 #69@175} physReg:NA Preferences=[allInt]
Interval 11: (constant) RefPositions {#2@6 #3@7} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#4@8 #5@9} physReg:NA Preferences=[allInt] RelatedInterval <L1>[0000000002327DD8]
Interval 13: RefPositions {#20@60 #21@61} physReg:NA Preferences=[allInt] RelatedInterval <L2>[0000000002327E28]
Interval 14: RefPositions {#24@72 #25@73} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#26@74 #28@75} physReg:NA Preferences=[allInt]
Interval 16: (interfering uses) RefPositions {#29@76 #30@77} physReg:NA Preferences=[allInt] RelatedInterval <L3>[0000000002327E78]
Interval 17: RefPositions {#36@98 #37@99} physReg:NA Preferences=[allInt] RelatedInterval <L6>[0000000002327F68]
Interval 18: RefPositions {#40@110 #42@111} physReg:NA Preferences=[allInt]
Interval 19: (interfering uses) RefPositions {#43@112 #44@113} physReg:NA Preferences=[allInt] RelatedInterval <L3>[0000000002327E78]
Interval 20: RefPositions {#51@140 #52@141} physReg:NA Preferences=[allInt] RelatedInterval <L6>[0000000002327F68]
Interval 21: RefPositions {#56@150 #57@151} physReg:NA Preferences=[allInt] RelatedInterval <L7>[0000000002327FB8]
Interval 22: (interfering uses) RefPositions {#61@160 #62@161} physReg:NA Preferences=[allInt] RelatedInterval <L10>[00000000023280A8]
Interval 23: RefPositions {#65@168 #66@171} physReg:NA Preferences=[allInt] RelatedInterval <L10>[00000000023280A8]
Interval 24: RefPositions {#67@172 #68@175} physReg:NA Preferences=[allInt] RelatedInterval <I23>[000000000232AA30]
Interval 25: RefPositions {#70@176 #71@179} physReg:NA Preferences=[allInt] RelatedInterval <I24>[000000000232AB80]
Interval 26: RefPositions {#72@180 #73@183} physReg:NA Preferences=[allInt] RelatedInterval <I25>[000000000232AD10]
Interval 27: RefPositions {#74@184 #75@185} physReg:NA Preferences=[allInt] RelatedInterval <L8>[0000000002328008]
Interval 28: RefPositions {#80@204 #81@207} physReg:NA Preferences=[allInt]
Interval 29: RefPositions {#82@208 #83@209} physReg:NA Preferences=[allInt] RelatedInterval <L9>[0000000002328058]
Interval 30: RefPositions {#86@218 #88@219} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#89@220 #90@221} physReg:NA Preferences=[allInt] RelatedInterval <L8>[0000000002328008]
Interval 32: RefPositions {#93@230 #94@231} physReg:NA Preferences=[allInt] RelatedInterval <L4>[0000000002327EC8]
Interval 33: (interfering uses) RefPositions {#100@240 #101@241} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15] RelatedInterval <L7>[0000000002327FB8]
Interval 34: RefPositions {#108@260 #110@261} physReg:NA Preferences=[rax] RelatedInterval <L8>[0000000002328008]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) RefPositions {#0@0 #7@15} physReg:rdi Preferences=[rdi] RelatedInterval <L3>[0000000002327E78]
Interval 1: (V02) RefPositions {#6@10 #9@21 #60@159} physReg:NA Preferences=[allInt]
Interval 2: (V03) RefPositions {#10@22 #17@51 #22@62 #35@97} physReg:NA Preferences=[allInt] RelatedInterval <L5>[0000000002327F18]
Interval 3: (V04) RefPositions {#8@16 #11@27 #15@45 #31@78 #32@85 #33@89 #45@114 #46@121 #48@131} physReg:NA Preferences=[allInt] RelatedInterval <L4>[0000000002327EC8]
Interval 4: (V05) RefPositions {#12@28 #13@35 #16@46 #27@75 #41@111 #49@132 #77@193 #92@229 #95@232 #103@249 #104@253} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 5: (V06) RefPositions {#18@52 #19@59 #23@71} physReg:NA Preferences=[allInt]
Interval 6: (V07) RefPositions {#38@100 #39@109 #50@139 #53@142 #55@149 #59@159} physReg:NA Preferences=[allInt]
Interval 7: (V08) RefPositions {#58@152 #79@203 #96@239 #102@242 #105@253} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 8: (V09) RefPositions {#76@186 #87@219 #91@222 #107@259} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 9: (V10) RefPositions {#84@210 #85@217 #98@239} physReg:NA Preferences=[rcx]
Interval 10: (V11) RefPositions {#63@162 #64@167 #69@175} physReg:NA Preferences=[allInt]
Interval 11: (constant) RefPositions {#2@6 #3@7} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#4@8 #5@9} physReg:NA Preferences=[allInt] RelatedInterval <L1>[0000000002327DD8]
Interval 13: RefPositions {#20@60 #21@61} physReg:NA Preferences=[allInt] RelatedInterval <L2>[0000000002327E28]
Interval 14: RefPositions {#24@72 #25@73} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#26@74 #28@75} physReg:NA Preferences=[allInt]
Interval 16: (interfering uses) RefPositions {#29@76 #30@77} physReg:NA Preferences=[allInt] RelatedInterval <L3>[0000000002327E78]
Interval 17: RefPositions {#36@98 #37@99} physReg:NA Preferences=[allInt] RelatedInterval <L6>[0000000002327F68]
Interval 18: RefPositions {#40@110 #42@111} physReg:NA Preferences=[allInt]
Interval 19: (interfering uses) RefPositions {#43@112 #44@113} physReg:NA Preferences=[allInt] RelatedInterval <L3>[0000000002327E78]
Interval 20: RefPositions {#51@140 #52@141} physReg:NA Preferences=[allInt] RelatedInterval <L6>[0000000002327F68]
Interval 21: RefPositions {#56@150 #57@151} physReg:NA Preferences=[allInt] RelatedInterval <L7>[0000000002327FB8]
Interval 22: (interfering uses) RefPositions {#61@160 #62@161} physReg:NA Preferences=[allInt] RelatedInterval <L10>[00000000023280A8]
Interval 23: RefPositions {#65@168 #66@171} physReg:NA Preferences=[allInt] RelatedInterval <L10>[00000000023280A8]
Interval 24: RefPositions {#67@172 #68@175} physReg:NA Preferences=[allInt] RelatedInterval <I23>[000000000232AA30]
Interval 25: RefPositions {#70@176 #71@179} physReg:NA Preferences=[allInt] RelatedInterval <I24>[000000000232AB80]
Interval 26: RefPositions {#72@180 #73@183} physReg:NA Preferences=[allInt] RelatedInterval <I25>[000000000232AD10]
Interval 27: RefPositions {#74@184 #75@185} physReg:NA Preferences=[allInt] RelatedInterval <L8>[0000000002328008]
Interval 28: RefPositions {#80@204 #81@207} physReg:NA Preferences=[allInt]
Interval 29: RefPositions {#82@208 #83@209} physReg:NA Preferences=[allInt] RelatedInterval <L9>[0000000002328058]
Interval 30: RefPositions {#86@218 #88@219} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#89@220 #90@221} physReg:NA Preferences=[allInt] RelatedInterval <L8>[0000000002328008]
Interval 32: RefPositions {#93@230 #94@231} physReg:NA Preferences=[allInt] RelatedInterval <L4>[0000000002327EC8]
Interval 33: (interfering uses) RefPositions {#100@240 #101@241} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15] RelatedInterval <L7>[0000000002327FB8]
Interval 34: RefPositions {#108@260 #110@261} physReg:NA Preferences=[rax] RelatedInterval <L8>[0000000002328008]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @6 RefTypeDef <Ivl:11> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #3 @7 RefTypeUse <Ivl:11> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #4 @8 RefTypeDef <Ivl:12> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #5 @9 RefTypeUse <Ivl:12> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @27 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #12 @28 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @35 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional>
<RefPosition #14 @39 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #15 @45 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #16 @46 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #18 @52 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #19 @59 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @60 RefTypeDef <Ivl:13> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #21 @61 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #22 @62 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #23 @71 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #24 @72 RefTypeDef <Ivl:14> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #25 @73 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #26 @74 RefTypeDef <Ivl:15> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @75 RefTypeUse <Ivl:4 V05> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #28 @75 RefTypeUse <Ivl:15> BB02 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #29 @76 RefTypeDef <Ivl:16> SUB BB02 regmask=[allInt] minReg=1>
<RefPosition #30 @77 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #31 @78 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @85 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #33 @89 RefTypeExpUse <Ivl:3 V04> BB02 regmask=[allInt] minReg=1>
<RefPosition #34 @89 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #35 @97 RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
<RefPosition #36 @98 RefTypeDef <Ivl:17> ADD BB03 regmask=[allInt] minReg=1>
<RefPosition #37 @99 RefTypeUse <Ivl:17> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #38 @100 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #39 @109 RefTypeUse <Ivl:6 V07> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #40 @110 RefTypeDef <Ivl:18> HWIntrinsic BB03 regmask=[allInt] minReg=1>
<RefPosition #41 @111 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #42 @111 RefTypeUse <Ivl:18> BB03 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #43 @112 RefTypeDef <Ivl:19> SUB BB03 regmask=[allInt] minReg=1>
<RefPosition #44 @113 RefTypeUse <Ivl:19> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #45 @114 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #46 @121 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[allInt] minReg=1 regOptional>
<RefPosition #47 @125 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #48 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #49 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #50 @139 RefTypeUse <Ivl:6 V07> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #51 @140 RefTypeDef <Ivl:20> ADD BB04 regmask=[allInt] minReg=1>
<RefPosition #52 @141 RefTypeUse <Ivl:20> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #53 @142 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #54 @143 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #55 @149 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #56 @150 RefTypeDef <Ivl:21> IND BB05 regmask=[allInt] minReg=1>
<RefPosition #57 @151 RefTypeUse <Ivl:21> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #58 @152 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #59 @159 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
<RefPosition #60 @159 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #61 @160 RefTypeDef <Ivl:22> SUB BB05 regmask=[allInt] minReg=1>
<RefPosition #62 @161 RefTypeUse <Ivl:22> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #63 @162 RefTypeDef <Ivl:10 V11> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #64 @167 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #65 @168 RefTypeDef <Ivl:23> RSH BB05 regmask=[allInt] minReg=1>
<RefPosition #66 @171 RefTypeUse <Ivl:23> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #67 @172 RefTypeDef <Ivl:24> AND BB05 regmask=[allInt] minReg=1>
<RefPosition #68 @175 RefTypeUse <Ivl:24> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #69 @175 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #70 @176 RefTypeDef <Ivl:25> ADD BB05 regmask=[allInt] minReg=1>
<RefPosition #71 @179 RefTypeUse <Ivl:25> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #72 @180 RefTypeDef <Ivl:26> RSH BB05 regmask=[allInt] minReg=1>
<RefPosition #73 @183 RefTypeUse <Ivl:26> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #74 @184 RefTypeDef <Ivl:27> LSH BB05 regmask=[allInt] minReg=1>
<RefPosition #75 @185 RefTypeUse <Ivl:27> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #76 @186 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #77 @193 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 regOptional>
<RefPosition #78 @197 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #79 @203 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #80 @204 RefTypeDef <Ivl:28> HWIntrinsic BB06 regmask=[allInt] minReg=1>
<RefPosition #81 @207 RefTypeUse <Ivl:28> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #82 @208 RefTypeDef <Ivl:29> ADD BB06 regmask=[allInt] minReg=1>
<RefPosition #83 @209 RefTypeUse <Ivl:29> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #84 @210 RefTypeDef <Ivl:9 V10> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #85 @217 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #86 @218 RefTypeDef <Ivl:30> CAST BB06 regmask=[allInt] minReg=1>
<RefPosition #87 @219 RefTypeUse <Ivl:8 V09> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #88 @219 RefTypeUse <Ivl:30> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #89 @220 RefTypeDef <Ivl:31> ADD BB06 regmask=[allInt] minReg=1>
<RefPosition #90 @221 RefTypeUse <Ivl:31> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #91 @222 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #92 @229 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
<RefPosition #93 @230 RefTypeDef <Ivl:32> ADD BB06 regmask=[allInt] minReg=1>
<RefPosition #94 @231 RefTypeUse <Ivl:32> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #95 @232 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #96 @239 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #97 @239 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #98 @239 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[rcx] minReg=1 last fixed delay>
<RefPosition #99 @240 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #100 @240 RefTypeDef <Ivl:33> RSZ BB06 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #101 @241 RefTypeUse <Ivl:33> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #102 @242 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #103 @249 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #104 @253 RefTypeExpUse <Ivl:4 V05> BB06 regmask=[allInt] minReg=1>
<RefPosition #105 @253 RefTypeExpUse <Ivl:7 V08> BB06 regmask=[allInt] minReg=1>
<RefPosition #106 @253 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #107 @259 RefTypeUse <Ivl:8 V09> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
<RefPosition #108 @260 RefTypeDef <Ivl:34> ADD BB07 regmask=[rax] minReg=1>
<RefPosition #109 @261 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #110 @261 RefTypeUse <Ivl:34> BB07 regmask=[rax] minReg=1 last fixed>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
--- V01
--- V02
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #60 @159 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[allInt] minReg=1 last delay regOptional>
--- V03
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #22 @62 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #35 @97 RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
--- V04
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @27 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #15 @45 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #31 @78 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @85 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #33 @89 RefTypeExpUse <Ivl:3 V04> BB02 regmask=[allInt] minReg=1>
<RefPosition #45 @114 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #46 @121 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[allInt] minReg=1 regOptional>
<RefPosition #48 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
--- V05
<RefPosition #12 @28 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @35 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional>
<RefPosition #16 @46 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @75 RefTypeUse <Ivl:4 V05> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #41 @111 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #49 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #77 @193 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[allInt] minReg=1 regOptional>
<RefPosition #92 @229 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
<RefPosition #95 @232 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #103 @249 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #104 @253 RefTypeExpUse <Ivl:4 V05> BB06 regmask=[allInt] minReg=1>
--- V06
<RefPosition #18 @52 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #19 @59 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #23 @71 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
--- V07
<RefPosition #38 @100 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #39 @109 RefTypeUse <Ivl:6 V07> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #50 @139 RefTypeUse <Ivl:6 V07> LCL_VAR BB04 regmask=[allInt] minReg=1 last>
<RefPosition #53 @142 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #55 @149 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #59 @159 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[allInt] minReg=1 last>
--- V08
<RefPosition #58 @152 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #79 @203 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #96 @239 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #102 @242 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #105 @253 RefTypeExpUse <Ivl:7 V08> BB06 regmask=[allInt] minReg=1>
--- V09
<RefPosition #76 @186 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #87 @219 RefTypeUse <Ivl:8 V09> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #91 @222 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #107 @259 RefTypeUse <Ivl:8 V09> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
--- V10
<RefPosition #84 @210 RefTypeDef <Ivl:9 V10> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #85 @217 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #98 @239 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[rcx] minReg=1 last fixed delay>
--- V11
<RefPosition #63 @162 RefTypeDef <Ivl:10 V11> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #64 @167 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #69 @175 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[allInt] minReg=1 last regOptional>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
--------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |r12 |r13 |
--------------------------------+----+----+----+----+----+
| | | | | |
--------------------------------+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+
0.#0 V0 Parm Keep rdi | | | |V0 a| | |
1.#1 BB1 PredBB0 | | | |V0 a| | |
6.#2 C11 Def Alloc rcx | |C11a| |V0 a| | |
7.#3 C11 Use * Keep rcx | |C11a| |V0 a| | |
8.#4 I12 Def Alloc rcx | |I12a| |V0 a| | |
9.#5 I12 Use * Keep rcx | |I12a| |V0 a| | |
10.#6 V2 Def Alloc rcx | |V2 a| |V0 a| | |
15.#7 V0 Use * Keep rdi | |V2 a| |V0 a| | |
16.#8 V4 Def Alloc rax |V4 a|V2 a| | | | |
21.#9 V2 Use Keep rcx |V4 a|V2 a| | | | |
22.#10 V3 Def Alloc rdi |V4 a|V2 a| |V3 a| | |
27.#11 V4 Use Keep rax |V4 a|V2 a| |V3 a| | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
28.#12 V5 Def Alloc rsi |V4 a|V2 a| |V5 a|V3 a| | |
35.#13 V5 Use Keep rsi |V4 a|V2 a| |V5 a|V3 a| | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
39.#14 BB2 PredBB1 |V4 a|V2 a| |V5 i|V3 a| | |
45.#15 V4 Use * Keep rax |V4 i|V2 a| |V5 i|V3 a| | |
46.#16 V5 Def Keep rsi |V4 i|V2 a| |V5 a|V3 a| | |
51.#17 V3 Use * Keep rdi |V4 i|V2 a| |V5 a|V3 i| | |
52.#18 V6 Def Alloc rdi |V4 i|V2 a| |V5 a|V6 a| | |
59.#19 V6 Use Keep rdi |V4 i|V2 a| |V5 a|V6 a| | |
60.#20 I13 Def Alloc rax |I13a|V2 a| |V5 a|V6 a| | |
61.#21 I13 Use * Keep rax |I13a|V2 a| |V5 a|V6 a| | |
Restr rax |V4 i|V2 a| |V5 a|V6 a| | |
62.#22 V3 Def Alloc rax |V3 a|V2 a| |V5 a|V6 a| | |
71.#23 V6 Use * Keep rdi |V3 a|V2 a| |V5 a|V6 a| | |
72.#24 I14 Def Alloc rdi |V3 a|V2 a| |V5 a|I14a| | |
73.#25 I14 Use * Keep rdi |V3 a|V2 a| |V5 a|I14a| | |
74.#26 I15 Def Alloc rdi |V3 a|V2 a| |V5 a|I15a| | |
75.#27 V5 Use Keep rsi |V3 a|V2 a| |V5 a|I15a| | |
75.#28 I15 Use *D Keep rdi |V3 a|V2 a| |V5 a|I15a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
76.#29 I16 Def Alloc rdx |V3 a|V2 a|I16a| |V5 a|I15a| | |
77.#30 I16 Use * Keep rdx |V3 a|V2 a|I16a| |V5 a| | | |
78.#31 V4 Def Alloc rdx |V3 a|V2 a|V4 a| |V5 a| | | |
85.#32 V4 Use Keep rdx |V3 a|V2 a|V4 a| |V5 a| | | |
89.#33 V4 ExpU Keep NA |V3 a|V2 a|V4 a| |V5 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
89.#34 BB3 PredBB2 |V3 a|V2 a|V4 i| |V5 a| | | |
97.#35 V3 Use * Keep rax |V3 a|V2 a|V4 i| |V5 a| | | |
98.#36 I17 Def Alloc rax |I17a|V2 a|V4 i| |V5 a| | | |
99.#37 I17 Use * Keep rax |I17a|V2 a|V4 i| |V5 a| | | |
100.#38 V7 Def Alloc rax |V7 a|V2 a|V4 i| |V5 a| | | |
109.#39 V7 Use Keep rax |V7 a|V2 a|V4 i| |V5 a| | | |
110.#40 I18 Def Alloc rdx |V7 a|V2 a|I18a| |V5 a| | | |
111.#41 V5 Use Keep rsi |V7 a|V2 a|I18a| |V5 a| | | |
111.#42 I18 Use *D Keep rdx |V7 a|V2 a|I18a| |V5 a| | | |
112.#43 I19 Def Alloc rdi |V7 a|V2 a|I18a| |V5 a|I19a| | |
Restr rdx |V7 a|V2 a|V4 i| |V5 a|I19a| | |
113.#44 I19 Use * Keep rdi |V7 a|V2 a|V4 i| |V5 a|I19a| | |
114.#45 V4 Def Alloc rdx |V7 a|V2 a|V4 a| |V5 a| | | |
121.#46 V4 Use Keep rdx |V7 a|V2 a|V4 a| |V5 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
125.#47 BB4 PredBB3 |V7 a|V2 a|V4 a| |V5 i| | | |
131.#48 V4 Use * Keep rdx |V7 a|V2 a|V4 a| |V5 i| | | |
132.#49 V5 Def Keep rsi |V7 a|V2 a| | |V5 a| | | |
139.#50 V7 Use * Keep rax |V7 i|V2 a| | |V5 a| | | |
140.#51 I20 Def Alloc rax |I20a|V2 a| | |V5 a| | | |
141.#52 I20 Use * Keep rax |I20a|V2 a| | |V5 a| | | |
Restr rax |V7 i|V2 a| | |V5 a| | | |
142.#53 V7 Def Alloc rax |V7 a|V2 a| | |V5 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
143.#54 BB5 PredBB3 |V7 a|V2 a| | |V5 a| | | |
149.#55 V7 Use Keep rax |V7 a|V2 a| | |V5 a| | | |
150.#56 I21 Def Alloc rdi |V7 a|V2 a| | |V5 a|I21a| | |
151.#57 I21 Use * Keep rdi |V7 a|V2 a| | |V5 a|I21a| | |
152.#58 V8 Def Alloc rdi |V7 a|V2 a| | |V5 a|V8 a| | |
159.#59 V7 Use * Keep rax |V7 a|V2 a| | |V5 a|V8 a| | |
159.#60 V2 Use *D Keep rcx |V7 a|V2 a| | |V5 a|V8 a| | |
160.#61 I22 Def Alloc rax |I22a|V2 a| | |V5 a|V8 a| | |
161.#62 I22 Use * Keep rax |I22a| | | |V5 a|V8 a| | |
162.#63 V11 Def Alloc rax |V11a| | | |V5 a|V8 a| | |
167.#64 V11 Use Keep rax |V11a| | | |V5 a|V8 a| | |
168.#65 I23 Def Alloc rcx |V11a|I23a| | |V5 a|V8 a| | |
171.#66 I23 Use * Keep rcx |V11a|I23a| | |V5 a|V8 a| | |
172.#67 I24 Def Alloc rcx |V11a|I24a| | |V5 a|V8 a| | |
175.#68 I24 Use * Keep rcx |V11a|I24a| | |V5 a|V8 a| | |
175.#69 V11 Use * Keep rax |V11a|I24a| | |V5 a|V8 a| | |
176.#70 I25 Def Alloc rcx | |I25a| | |V5 a|V8 a| | |
179.#71 I25 Use * Keep rcx | |I25a| | |V5 a|V8 a| | |
180.#72 I26 Def Alloc rcx | |I26a| | |V5 a|V8 a| | |
183.#73 I26 Use * Keep rcx | |I26a| | |V5 a|V8 a| | |
184.#74 I27 Def Alloc rax |I27a| | | |V5 a|V8 a| | |
185.#75 I27 Use * Keep rax |I27a| | | |V5 a|V8 a| | |
186.#76 V9 Def Alloc rax |V9 a| | | |V5 a|V8 a| | |
193.#77 V5 Use Keep rsi |V9 a| | | |V5 a|V8 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
197.#78 BB6 PredBB5 |V9 a| | | |V5 a|V8 a| | |
203.#79 V8 Use Keep rdi |V9 a| | | |V5 a|V8 a| | |
204.#80 I28 Def Alloc rcx |V9 a|I28a| | |V5 a|V8 a| | |
207.#81 I28 Use * Keep rcx |V9 a|I28a| | |V5 a|V8 a| | |
208.#82 I29 Def Alloc rcx |V9 a|I29a| | |V5 a|V8 a| | |
209.#83 I29 Use * Keep rcx |V9 a|I29a| | |V5 a|V8 a| | |
210.#84 V10 Def Alloc rcx |V9 a|V10a| | |V5 a|V8 a| | |
217.#85 V10 Use Keep rcx |V9 a|V10a| | |V5 a|V8 a| | |
218.#86 I30 Def Alloc rdx |V9 a|V10a|I30a| |V5 a|V8 a| | |
219.#87 V9 Use * Keep rax |V9 i|V10a|I30a| |V5 a|V8 a| | |
219.#88 I30 Use * Keep rdx |V9 i|V10a|I30a| |V5 a|V8 a| | |
220.#89 I31 Def Alloc rax |I31a|V10a| | |V5 a|V8 a| | |
221.#90 I31 Use * Keep rax |I31a|V10a| | |V5 a|V8 a| | |
Restr rax |V9 i|V10a| | |V5 a|V8 a| | |
222.#91 V9 Def Alloc rax |V9 a|V10a| | |V5 a|V8 a| | |
229.#92 V5 Use * Keep rsi |V9 a|V10a| | |V5 i|V8 a| | |
230.#93 I32 Def Alloc rsi |V9 a|V10a| | |I32a|V8 a| | |
231.#94 I32 Use * Keep rsi |V9 a|V10a| | |I32a|V8 a| | |
Restr rsi |V9 a|V10a| | |V5 i|V8 a| | |
232.#95 V5 Def Alloc rsi |V9 a|V10a| | |V5 a|V8 a| | |
239.#96 V8 Use * Keep rdi |V9 a|V10a| | |V5 a|V8 i| | |
239.#97 rcx Fixd Keep rcx |V9 a|V10a| | |V5 a|V8 i| | |
239.#98 V10 Use *D Keep rcx |V9 a|V10a| | |V5 a|V8 i| | |
240.#99 rcx Kill Keep rcx |V9 a| | | |V5 a|V8 i| | |
240.#100 I33 Def Alloc rdi |V9 a| | | |V5 a|I33a| | |
241.#101 I33 Use * Keep rdi |V9 a| | | |V5 a|I33a| | |
Restr rdi |V9 a| | | |V5 a|V8 i| | |
242.#102 V8 Def Alloc rdi |V9 a| | | |V5 a|V8 a| | |
249.#103 V5 Use Keep rsi |V9 a| | | |V5 a|V8 a| | |
253.#104 V5 ExpU Keep NA |V9 a| | | |V5 a|V8 a| | |
253.#105 V8 ExpU Keep NA |V9 a| | | |V5 a|V8 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
253.#106 BB7 PredBB6 |V9 a| | | | | | | |
259.#107 V9 Use * Keep rax |V9 a| | | | | | | |
260.#108 I34 Def Alloc rax |I34a| | | | | | | |
261.#109 rax Fixd Keep rax |I34a| | | | | | | |
261.#110 I34 Use * Keep rax | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @6 RefTypeDef <Ivl:11> CNS_INT BB01 regmask=[rcx] minReg=1>
<RefPosition #3 @7 RefTypeUse <Ivl:11> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #4 @8 RefTypeDef <Ivl:12> IND BB01 regmask=[rcx] minReg=1>
<RefPosition #5 @9 RefTypeUse <Ivl:12> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdi] minReg=1 last>
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1>
<RefPosition #11 @27 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #12 @28 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[rsi] minReg=1>
<RefPosition #13 @35 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[rsi] minReg=1 regOptional>
<RefPosition #14 @39 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #15 @45 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[rax] minReg=1 last>
<RefPosition #16 @46 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB02 regmask=[rsi] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1 last>
<RefPosition #18 @52 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #19 @59 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #20 @60 RefTypeDef <Ivl:13> ADD BB02 regmask=[rax] minReg=1>
<RefPosition #21 @61 RefTypeUse <Ivl:13> BB02 regmask=[rax] minReg=1 last>
<RefPosition #22 @62 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[rax] minReg=1>
<RefPosition #23 @71 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[rdi] minReg=1 last>
<RefPosition #24 @72 RefTypeDef <Ivl:14> HWIntrinsic BB02 regmask=[rdi] minReg=1>
<RefPosition #25 @73 RefTypeUse <Ivl:14> BB02 regmask=[rdi] minReg=1 last>
<RefPosition #26 @74 RefTypeDef <Ivl:15> CAST BB02 regmask=[rdi] minReg=1>
<RefPosition #27 @75 RefTypeUse <Ivl:4 V05> LCL_VAR BB02 regmask=[rsi] minReg=1>
<RefPosition #28 @75 RefTypeUse <Ivl:15> BB02 regmask=[rdi] minReg=1 last delay regOptional>
<RefPosition #29 @76 RefTypeDef <Ivl:16> SUB BB02 regmask=[rdx] minReg=1>
<RefPosition #30 @77 RefTypeUse <Ivl:16> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #31 @78 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[rdx] minReg=1>
<RefPosition #32 @85 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[rdx] minReg=1 regOptional>
<RefPosition #33 @89 RefTypeExpUse <Ivl:3 V04> BB02 regmask=[allInt] minReg=1>
<RefPosition #34 @89 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #35 @97 RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[rax] minReg=1 last>
<RefPosition #36 @98 RefTypeDef <Ivl:17> ADD BB03 regmask=[rax] minReg=1>
<RefPosition #37 @99 RefTypeUse <Ivl:17> BB03 regmask=[rax] minReg=1 last>
<RefPosition #38 @100 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB03 regmask=[rax] minReg=1>
<RefPosition #39 @109 RefTypeUse <Ivl:6 V07> LCL_VAR BB03 regmask=[rax] minReg=1>
<RefPosition #40 @110 RefTypeDef <Ivl:18> HWIntrinsic BB03 regmask=[rdx] minReg=1>
<RefPosition #41 @111 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[rsi] minReg=1>
<RefPosition #42 @111 RefTypeUse <Ivl:18> BB03 regmask=[rdx] minReg=1 last delay regOptional>
<RefPosition #43 @112 RefTypeDef <Ivl:19> SUB BB03 regmask=[rdi] minReg=1>
<RefPosition #44 @113 RefTypeUse <Ivl:19> BB03 regmask=[rdi] minReg=1 last>
<RefPosition #45 @114 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB03 regmask=[rdx] minReg=1>
<RefPosition #46 @121 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[rdx] minReg=1 regOptional>
<RefPosition #47 @125 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #48 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[rdx] minReg=1 last>
<RefPosition #49 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[rsi] minReg=1>
<RefPosition #50 @139 RefTypeUse <Ivl:6 V07> LCL_VAR BB04 regmask=[rax] minReg=1 last>
<RefPosition #51 @140 RefTypeDef <Ivl:20> ADD BB04 regmask=[rax] minReg=1>
<RefPosition #52 @141 RefTypeUse <Ivl:20> BB04 regmask=[rax] minReg=1 last>
<RefPosition #53 @142 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB04 regmask=[rax] minReg=1>
<RefPosition #54 @143 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #55 @149 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #56 @150 RefTypeDef <Ivl:21> IND BB05 regmask=[rdi] minReg=1>
<RefPosition #57 @151 RefTypeUse <Ivl:21> BB05 regmask=[rdi] minReg=1 last>
<RefPosition #58 @152 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB05 regmask=[rdi] minReg=1>
<RefPosition #59 @159 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[rax] minReg=1 last>
<RefPosition #60 @159 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[rcx] minReg=1 last delay regOptional>
<RefPosition #61 @160 RefTypeDef <Ivl:22> SUB BB05 regmask=[rax] minReg=1>
<RefPosition #62 @161 RefTypeUse <Ivl:22> BB05 regmask=[rax] minReg=1 last>
<RefPosition #63 @162 RefTypeDef <Ivl:10 V11> STORE_LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #64 @167 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #65 @168 RefTypeDef <Ivl:23> RSH BB05 regmask=[rcx] minReg=1>
<RefPosition #66 @171 RefTypeUse <Ivl:23> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #67 @172 RefTypeDef <Ivl:24> AND BB05 regmask=[rcx] minReg=1>
<RefPosition #68 @175 RefTypeUse <Ivl:24> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #69 @175 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[rax] minReg=1 last regOptional>
<RefPosition #70 @176 RefTypeDef <Ivl:25> ADD BB05 regmask=[rcx] minReg=1>
<RefPosition #71 @179 RefTypeUse <Ivl:25> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #72 @180 RefTypeDef <Ivl:26> RSH BB05 regmask=[rcx] minReg=1>
<RefPosition #73 @183 RefTypeUse <Ivl:26> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #74 @184 RefTypeDef <Ivl:27> LSH BB05 regmask=[rax] minReg=1>
<RefPosition #75 @185 RefTypeUse <Ivl:27> BB05 regmask=[rax] minReg=1 last>
<RefPosition #76 @186 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #77 @193 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[rsi] minReg=1 regOptional>
<RefPosition #78 @197 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #79 @203 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[rdi] minReg=1 regOptional>
<RefPosition #80 @204 RefTypeDef <Ivl:28> HWIntrinsic BB06 regmask=[rcx] minReg=1>
<RefPosition #81 @207 RefTypeUse <Ivl:28> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #82 @208 RefTypeDef <Ivl:29> ADD BB06 regmask=[rcx] minReg=1>
<RefPosition #83 @209 RefTypeUse <Ivl:29> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #84 @210 RefTypeDef <Ivl:9 V10> STORE_LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #85 @217 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #86 @218 RefTypeDef <Ivl:30> CAST BB06 regmask=[rdx] minReg=1>
<RefPosition #87 @219 RefTypeUse <Ivl:8 V09> LCL_VAR BB06 regmask=[rax] minReg=1 last regOptional>
<RefPosition #88 @219 RefTypeUse <Ivl:30> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #89 @220 RefTypeDef <Ivl:31> ADD BB06 regmask=[rax] minReg=1>
<RefPosition #90 @221 RefTypeUse <Ivl:31> BB06 regmask=[rax] minReg=1 last>
<RefPosition #91 @222 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB06 regmask=[rax] minReg=1>
<RefPosition #92 @229 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[rsi] minReg=1 last>
<RefPosition #93 @230 RefTypeDef <Ivl:32> ADD BB06 regmask=[rsi] minReg=1>
<RefPosition #94 @231 RefTypeUse <Ivl:32> BB06 regmask=[rsi] minReg=1 last>
<RefPosition #95 @232 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB06 regmask=[rsi] minReg=1>
<RefPosition #96 @239 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[rdi] minReg=1 last>
<RefPosition #97 @239 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #98 @239 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[rcx] minReg=1 last fixed delay>
<RefPosition #99 @240 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #100 @240 RefTypeDef <Ivl:33> RSZ BB06 regmask=[rdi] minReg=1>
<RefPosition #101 @241 RefTypeUse <Ivl:33> BB06 regmask=[rdi] minReg=1 last>
<RefPosition #102 @242 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB06 regmask=[rdi] minReg=1>
<RefPosition #103 @249 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[rsi] minReg=1 regOptional>
<RefPosition #104 @253 RefTypeExpUse <Ivl:4 V05> BB06 regmask=[allInt] minReg=1>
<RefPosition #105 @253 RefTypeExpUse <Ivl:7 V08> BB06 regmask=[allInt] minReg=1>
<RefPosition #106 @253 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #107 @259 RefTypeUse <Ivl:8 V09> LCL_VAR BB07 regmask=[rax] minReg=1 last>
<RefPosition #108 @260 RefTypeDef <Ivl:34> ADD BB07 regmask=[rax] minReg=1>
<RefPosition #109 @261 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #110 @261 RefTypeUse <Ivl:34> BB07 regmask=[rax] minReg=1 last fixed>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rdi] minReg=1 fixed>
<RefPosition #7 @15 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rdi] minReg=1 last>
--- V01
--- V02
<RefPosition #6 @10 RefTypeDef <Ivl:1 V02> STORE_LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #9 @21 RefTypeUse <Ivl:1 V02> LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #60 @159 RefTypeUse <Ivl:1 V02> LCL_VAR BB05 regmask=[rcx] minReg=1 last delay regOptional>
--- V03
<RefPosition #10 @22 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1>
<RefPosition #17 @51 RefTypeUse <Ivl:2 V03> LCL_VAR BB02 regmask=[rdi] minReg=1 last>
<RefPosition #22 @62 RefTypeDef <Ivl:2 V03> STORE_LCL_VAR BB02 regmask=[rax] minReg=1>
<RefPosition #35 @97 RefTypeUse <Ivl:2 V03> LCL_VAR BB03 regmask=[rax] minReg=1 last>
--- V04
<RefPosition #8 @16 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #11 @27 RefTypeUse <Ivl:3 V04> LCL_VAR BB01 regmask=[rax] minReg=1>
<RefPosition #15 @45 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[rax] minReg=1 last>
<RefPosition #31 @78 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB02 regmask=[rdx] minReg=1>
<RefPosition #32 @85 RefTypeUse <Ivl:3 V04> LCL_VAR BB02 regmask=[rdx] minReg=1 regOptional>
<RefPosition #33 @89 RefTypeExpUse <Ivl:3 V04> BB02 regmask=[allInt] minReg=1>
<RefPosition #45 @114 RefTypeDef <Ivl:3 V04> STORE_LCL_VAR BB03 regmask=[rdx] minReg=1>
<RefPosition #46 @121 RefTypeUse <Ivl:3 V04> LCL_VAR BB03 regmask=[rdx] minReg=1 regOptional>
<RefPosition #48 @131 RefTypeUse <Ivl:3 V04> LCL_VAR BB04 regmask=[rdx] minReg=1 last>
--- V05
<RefPosition #12 @28 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB01 regmask=[rsi] minReg=1>
<RefPosition #13 @35 RefTypeUse <Ivl:4 V05> LCL_VAR BB01 regmask=[rsi] minReg=1 regOptional>
<RefPosition #16 @46 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB02 regmask=[rsi] minReg=1>
<RefPosition #27 @75 RefTypeUse <Ivl:4 V05> LCL_VAR BB02 regmask=[rsi] minReg=1>
<RefPosition #41 @111 RefTypeUse <Ivl:4 V05> LCL_VAR BB03 regmask=[rsi] minReg=1>
<RefPosition #49 @132 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB04 regmask=[rsi] minReg=1>
<RefPosition #77 @193 RefTypeUse <Ivl:4 V05> LCL_VAR BB05 regmask=[rsi] minReg=1 regOptional>
<RefPosition #92 @229 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[rsi] minReg=1 last>
<RefPosition #95 @232 RefTypeDef <Ivl:4 V05> STORE_LCL_VAR BB06 regmask=[rsi] minReg=1>
<RefPosition #103 @249 RefTypeUse <Ivl:4 V05> LCL_VAR BB06 regmask=[rsi] minReg=1 regOptional>
<RefPosition #104 @253 RefTypeExpUse <Ivl:4 V05> BB06 regmask=[allInt] minReg=1>
--- V06
<RefPosition #18 @52 RefTypeDef <Ivl:5 V06> STORE_LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #19 @59 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[rdi] minReg=1>
<RefPosition #23 @71 RefTypeUse <Ivl:5 V06> LCL_VAR BB02 regmask=[rdi] minReg=1 last>
--- V07
<RefPosition #38 @100 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB03 regmask=[rax] minReg=1>
<RefPosition #39 @109 RefTypeUse <Ivl:6 V07> LCL_VAR BB03 regmask=[rax] minReg=1>
<RefPosition #50 @139 RefTypeUse <Ivl:6 V07> LCL_VAR BB04 regmask=[rax] minReg=1 last>
<RefPosition #53 @142 RefTypeDef <Ivl:6 V07> STORE_LCL_VAR BB04 regmask=[rax] minReg=1>
<RefPosition #55 @149 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #59 @159 RefTypeUse <Ivl:6 V07> LCL_VAR BB05 regmask=[rax] minReg=1 last>
--- V08
<RefPosition #58 @152 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB05 regmask=[rdi] minReg=1>
<RefPosition #79 @203 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[rdi] minReg=1 regOptional>
<RefPosition #96 @239 RefTypeUse <Ivl:7 V08> LCL_VAR BB06 regmask=[rdi] minReg=1 last>
<RefPosition #102 @242 RefTypeDef <Ivl:7 V08> STORE_LCL_VAR BB06 regmask=[rdi] minReg=1>
<RefPosition #105 @253 RefTypeExpUse <Ivl:7 V08> BB06 regmask=[allInt] minReg=1>
--- V09
<RefPosition #76 @186 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #87 @219 RefTypeUse <Ivl:8 V09> LCL_VAR BB06 regmask=[rax] minReg=1 last regOptional>
<RefPosition #91 @222 RefTypeDef <Ivl:8 V09> STORE_LCL_VAR BB06 regmask=[rax] minReg=1>
<RefPosition #107 @259 RefTypeUse <Ivl:8 V09> LCL_VAR BB07 regmask=[rax] minReg=1 last>
--- V10
<RefPosition #84 @210 RefTypeDef <Ivl:9 V10> STORE_LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #85 @217 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #98 @239 RefTypeUse <Ivl:9 V10> LCL_VAR BB06 regmask=[rcx] minReg=1 last fixed delay>
--- V11
<RefPosition #63 @162 RefTypeDef <Ivl:10 V11> STORE_LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #64 @167 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #69 @175 RefTypeUse <Ivl:10 V11> LCL_VAR BB05 regmask=[rax] minReg=1 last regOptional>
Active intervals at end of allocation:
Active Interval 9: (V10) RefPositions {#84@210 #85@217 #98@239} physReg:NA Preferences=[rcx]
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V02 V03 V04 V05 V07 V08 V09}
Has Critical Edges
Prior to Resolution
BB01 use def in out
{V00}
{V02 V03 V04 V05}
{V00}
{V02 V03 V04 V05}
Var=Reg beg of BB01: V00=rdi
Var=Reg end of BB01: V04=rax V05=rsi V03=rdi V02=rcx
BB02 use def in out
{V03 V04}
{V03 V04 V05 V06}
{V02 V03 V04}
{V02 V03 V04 V05}
Var=Reg beg of BB02: V04=rax V03=rdi V02=rcx
Var=Reg end of BB02: V04=rdx V05=rsi V03=rax V02=rcx
BB03 use def in out
{V03 V05}
{V04 V07}
{V02 V03 V05}
{V02 V04 V05 V07}
Var=Reg beg of BB03: V05=rsi V03=rax V02=rcx
Var=Reg end of BB03: V04=rdx V05=rsi V02=rcx V07=rax
BB04 use def in out
{V04 V07}
{V05 V07}
{V02 V04 V07}
{V02 V05 V07}
Var=Reg beg of BB04: V04=rdx V02=rcx V07=rax
Var=Reg end of BB04: V05=rsi V02=rcx V07=rax
BB05 use def in out
{V02 V05 V07}
{V08 V09 V11}
{V02 V05 V07}
{V05 V08 V09}
Var=Reg beg of BB05: V05=rsi V02=rcx V07=rax
Var=Reg end of BB05: V05=rsi V08=rdi V09=rax
BB06 use def in out
{V05 V08 V09}
{V05 V08 V09 V10}
{V05 V08 V09}
{V05 V08 V09}
Var=Reg beg of BB06: V05=rsi V08=rdi V09=rax
Var=Reg end of BB06: V05=rsi V08=rdi V09=rax
BB07 use def in out
{V09}
{}
{V09}
{}
Var=Reg beg of BB07: V09=rax
Var=Reg end of BB07: none
RESOLVING EDGES
fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB01, jumpBlk=BB00, runRarely=false)
fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB07
New Basic Block BB08 [0011] created.
Splitting edge from BB01 to BB03; adding BB08
BB08 bottom: move V03 from rdi to rax (Critical)
fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB02, jumpBlk=BB00, runRarely=false)
fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB07
New Basic Block BB09 [0012] created.
Splitting edge from BB02 to BB02; adding BB09
BB09 bottom: move V03 from rax to rdi (Critical)
BB09 bottom: move V04 from rdx to rax (Critical)
Set V00 argument initial register to rdi
Trees after linear scan register allocator (LSRA)
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB08 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB09 2 [000..001)-> BB09 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB08,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 1 BB03 0.25 [000..001) i LIR
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target LIR
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target LIR
BB09 [0012] 1 BB02 1 [???..???)-> BB02 (always) internal target bwd LIR
BB08 [0011] 1 BB01 0.50 [???..???)-> BB03 (always) internal target LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) -> BB08 (cond), preds={} succs={BB02,BB08}
N003 ( 5, 12) [000147] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N005 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] REG rcx $100
/--* t176 long
N007 ( 5, 12) [000001] x---G------- t1 = * IND long REG rcx <l:$140, c:$180>
/--* t1 long
N009 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2 rcx REG rcx
N011 ( 1, 3) [000150] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N013 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 rdi (last use) REG rdi $80
/--* t3 int
N015 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2 rax REG rax
N017 ( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N019 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 rcx REG rcx <l:$140, c:$180>
/--* t13 long
N021 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2 rdi REG rdi
N023 ( 1, 3) [000020] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N025 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V04 tmp3 u:2 rax REG rax $80
/--* t17 int
N027 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2 rsi REG rsi
N029 ( 5, 5) [000181] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N031 ( 1, 1) [000178] ------------ t178 = LCL_VAR int V05 tmp4 u:2 rsi REG rsi $80
N033 ( 1, 1) [000179] -c---------- t179 = CNS_INT int 0 REG NA $40
/--* t178 int
+--* t179 int
N035 ( 3, 3) [000177] J------N---- * LE void REG NA $200
N037 ( 5, 5) [000180] ------------ * JTRUE void REG NA
------------ BB02 [000..001) -> BB09 (cond), preds={BB01,BB09} succs={BB03,BB09}
N001 ( 0, 0) [000239] ------------ t239 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000227] ------------ t227 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t239 long
+--* t227 long
N005 ( 2, 2) [000224] ------------ t224 = * PHI long
/--* t224 long
N007 ( 2, 3) [000225] DA---------- * STORE_LCL_VAR long V03 tmp2 d:3
N001 ( 0, 0) [000241] ------------ t241 = PHI_ARG int V04 tmp3 u:4
N002 ( 0, 0) [000229] ------------ t229 = PHI_ARG int V04 tmp3 u:2 $80
/--* t241 int
+--* t229 int
N005 ( 2, 2) [000212] ------------ t212 = * PHI int
/--* t212 int
N007 ( 2, 3) [000213] DA---------- * STORE_LCL_VAR int V04 tmp3 d:3
N041 ( 1, 3) [000031] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N043 ( 1, 1) [000028] ------------ t28 = LCL_VAR int V04 tmp3 u:3 rax (last use) REG rax $280
/--* t28 int
N045 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3 rsi REG rsi
N047 ( 1, 3) [000041] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N049 ( 1, 1) [000033] ------------ t33 = LCL_VAR long V03 tmp2 u:3 rdi (last use) REG rdi $141
/--* t33 long
N051 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2 rdi REG rdi
N053 ( 3, 3) [000044] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N055 ( 1, 1) [000034] ------------ t34 = LCL_VAR long V06 tmp5 u:2 rdi REG rdi $141
N057 ( 1, 1) [000036] -c---------- t36 = CNS_INT long 8 REG NA $340
/--* t34 long
+--* t36 long
N059 ( 3, 3) [000037] ------------ t37 = * ADD long REG rax $241
/--* t37 long
N061 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4 rax REG rax
N063 ( 7, 7) [000052] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N065 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V05 tmp4 u:3 rsi REG rsi $280
N067 ( 1, 1) [000042] ------------ t42 = LCL_VAR long V06 tmp5 u:2 rdi (last use) REG rdi $141
/--* t42 long
N069 ( 3, 2) [000045] *c-XG------- t45 = * IND long REG NA <l:$142, c:$302>
/--* t45 long
N071 ( 4, 3) [000046] ---XG------- t46 = * HWIntrinsic long PopCount REG rdi $380
/--* t46 long
N073 ( 5, 5) [000047] ---XG------- t47 = * CAST int <- long REG rdi $201
/--* t32 int
+--* t47 int
N075 ( 7, 7) [000048] ---XG------- t48 = * SUB int REG rdx $202
/--* t48 int
N077 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4 rdx REG rdx
N079 ( 5, 5) [000026] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N081 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V04 tmp3 u:4 rdx REG rdx $202
N083 ( 1, 1) [000023] -c---------- t23 = CNS_INT int 0 REG NA $40
/--* t22 int
+--* t23 int
N085 ( 3, 3) [000024] J------N---- * GT void REG NA $203
N087 ( 5, 5) [000025] ------------ * JTRUE void REG NA
------------ BB03 [000..001) -> BB05 (cond), preds={BB08,BB02} succs={BB04,BB05}
N001 ( 0, 0) [000235] ------------ t235 = PHI_ARG long V03 tmp2 u:4
N002 ( 0, 0) [000231] ------------ t231 = PHI_ARG long V03 tmp2 u:2 <l:$140, c:$180>
/--* t235 long
+--* t231 long
N005 ( 2, 2) [000220] ------------ t220 = * PHI long
/--* t220 long
N007 ( 2, 3) [000221] DA---------- * STORE_LCL_VAR long V03 tmp2 d:5
N001 ( 0, 0) [000237] ------------ t237 = PHI_ARG int V05 tmp4 u:3 rsi
N002 ( 0, 0) [000233] ------------ t233 = PHI_ARG int V05 tmp4 u:2 rsi $80
/--* t237 int
+--* t233 int
N005 ( 2, 2) [000216] ------------ t216 = * PHI int
/--* t216 int
N007 ( 2, 3) [000217] DA---------- * STORE_LCL_VAR int V05 tmp4 d:4 rsi
N091 ( 3, 3) [000060] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N093 ( 1, 1) [000054] ------------ t54 = LCL_VAR long V03 tmp2 u:5 rax (last use) REG rax $143
N095 ( 1, 1) [000056] -c---------- t56 = CNS_INT long -8 REG NA $342
/--* t54 long
+--* t56 long
N097 ( 3, 3) [000057] ------------ t57 = * ADD long REG rax $242
/--* t57 long
N099 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2 rax REG rax
N101 ( 6, 5) [000069] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N103 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V05 tmp4 u:4 rsi REG rsi $281
N105 ( 1, 1) [000062] ------------ t62 = LCL_VAR long V07 tmp6 u:2 rax REG rax $242
/--* t62 long
N107 ( 3, 2) [000063] *c-XG------- t63 = * IND int REG NA <l:$282, c:$1c2>
/--* t63 int
N109 ( 4, 3) [000064] ---XG------- t64 = * HWIntrinsic int PopCount REG rdx $3c0
/--* t61 int
+--* t64 int
N111 ( 6, 5) [000065] ---XG------- t65 = * SUB int REG rdi $205
/--* t65 int
N113 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5 rdx REG rdx
N115 ( 5, 5) [000074] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N117 ( 1, 1) [000070] ------------ t70 = LCL_VAR int V04 tmp3 u:5 rdx REG rdx $205
N119 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 0 REG NA $40
/--* t70 int
+--* t71 int
N121 ( 3, 3) [000072] J------N---- * LE void REG NA $206
N123 ( 5, 5) [000073] ------------ * JTRUE void REG NA
------------ BB04 [000..001), preds={BB03} succs={BB05}
N127 ( 1, 3) [000137] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N129 ( 1, 1) [000134] ------------ t134 = LCL_VAR int V04 tmp3 u:5 rdx (last use) REG rdx $205
/--* t134 int
N131 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5 rsi REG rsi
N133 ( 3, 3) [000144] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N135 ( 1, 1) [000138] ------------ t138 = LCL_VAR long V07 tmp6 u:2 rax (last use) REG rax $242
N137 ( 1, 1) [000140] -c---------- t140 = CNS_INT long 4 REG NA $343
/--* t138 long
+--* t140 long
N139 ( 3, 3) [000141] ------------ t141 = * ADD long REG rax $243
/--* t141 long
N141 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3 rax REG rax
------------ BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
N001 ( 0, 0) [000247] ------------ t247 = PHI_ARG long V07 tmp6 u:3 rax
N002 ( 0, 0) [000243] ------------ t243 = PHI_ARG long V07 tmp6 u:2 rax $242
/--* t247 long
+--* t243 long
N005 ( 2, 2) [000208] ------------ t208 = * PHI long
/--* t208 long
N007 ( 6, 5) [000209] DA---------- * STORE_LCL_VAR long V07 tmp6 d:4 rax
N001 ( 0, 0) [000249] ------------ t249 = PHI_ARG int V05 tmp4 u:5 rsi
N002 ( 0, 0) [000245] ------------ t245 = PHI_ARG int V05 tmp4 u:4 rsi $281
/--* t249 int
+--* t245 int
N005 ( 2, 2) [000204] ------------ t204 = * PHI int
/--* t204 int
N007 ( 2, 3) [000205] DA---------- * STORE_LCL_VAR int V05 tmp4 d:6 rsi
N145 ( 3, 3) [000080] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N147 ( 1, 1) [000076] ------------ t76 = LCL_VAR long V07 tmp6 u:4 rax REG rax $144
/--* t76 long
N149 ( 3, 2) [000077] *--XG------- t77 = * IND int REG rdi <l:$284, c:$1c5>
/--* t77 int
N151 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2 rdi REG rdi
N153 ( 26, 9) [000092] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N155 ( 1, 1) [000081] ------------ t81 = LCL_VAR long V07 tmp6 u:4 rax (last use) REG rax $144
N157 ( 1, 1) [000082] ------------ t82 = LCL_VAR long V02 tmp1 u:2 rcx (last use) REG rcx <l:$140, c:$180>
/--* t81 long
+--* t82 long
N159 ( 3, 3) [000083] ------------ t83 = * SUB long REG rax <l:$244, c:$245>
/--* t83 long
N161 (???,???) [000268] DA---------- * STORE_LCL_VAR long V11 rat0 rax REG rax
N163 ( 1, 1) [000269] ------------ t269 = LCL_VAR long V11 rat0 rax REG rax
N165 ( 1, 1) [000270] -c---------- t270 = CNS_INT int 63 REG NA
/--* t269 long
+--* t270 int
N167 ( 3, 3) [000271] ------------ t271 = * RSH long REG rcx
N169 ( 1, 1) [000272] -c---------- t272 = CNS_INT long 3 REG NA
/--* t271 long
+--* t272 long
N171 ( 5, 5) [000273] ------------ t273 = * AND long REG rcx
N173 ( 1, 1) [000274] ------------ t274 = LCL_VAR long V11 rat0 rax (last use) REG rax
/--* t273 long
+--* t274 long
N175 ( 7, 7) [000275] ------------ t275 = * ADD long REG rcx
N177 ( 1, 1) [000085] -c---------- t85 = CNS_INT long 2 REG NA $343
/--* t275 long
+--* t85 long
N179 ( 9, 9) [000276] ------------ t276 = * RSH long REG rcx
N181 ( 1, 1) [000088] -c---------- t88 = CNS_INT long 5 REG NA $345
/--* t276 long
+--* t88 long
N183 ( 26, 9) [000089] ------------ t89 = * LSH long REG rax <l:$248, c:$249>
/--* t89 long
N185 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2 rax REG rax
N187 ( 5, 5) [000186] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N189 ( 1, 1) [000183] ------------ t183 = LCL_VAR int V05 tmp4 u:6 rsi REG rsi $283
N191 ( 1, 1) [000184] -c---------- t184 = CNS_INT int 0 REG NA $40
/--* t183 int
+--* t184 int
N193 ( 3, 3) [000182] J------N---- * LE void REG NA $208
N195 ( 5, 5) [000185] ------------ * JTRUE void REG NA
------------ BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
N001 ( 0, 0) [000261] ------------ t261 = PHI_ARG long V09 tmp8 u:4 rax
N002 ( 0, 0) [000251] ------------ t251 = PHI_ARG long V09 tmp8 u:2 rax <l:$248, c:$249>
/--* t261 long
+--* t251 long
N005 ( 2, 2) [000200] ------------ t200 = * PHI long
/--* t200 long
N007 ( 2, 3) [000201] DA---------- * STORE_LCL_VAR long V09 tmp8 d:3 rax
N001 ( 0, 0) [000263] ------------ t263 = PHI_ARG int V08 tmp7 u:4 rdi
N002 ( 0, 0) [000253] ------------ t253 = PHI_ARG int V08 tmp7 u:2 rdi <l:$284, c:$1c5>
/--* t263 int
+--* t253 int
N005 ( 2, 2) [000192] ------------ t192 = * PHI int
/--* t192 int
N007 ( 2, 3) [000193] DA---------- * STORE_LCL_VAR int V08 tmp7 d:3 rdi
N001 ( 0, 0) [000265] ------------ t265 = PHI_ARG int V05 tmp4 u:8 rsi
N002 ( 0, 0) [000255] ------------ t255 = PHI_ARG int V05 tmp4 u:6 rsi $283
/--* t265 int
+--* t255 int
N005 ( 2, 2) [000188] ------------ t188 = * PHI int
/--* t188 int
N007 ( 2, 3) [000189] DA---------- * STORE_LCL_VAR int V05 tmp4 d:7 rsi
N199 ( 4, 4) [000106] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N201 ( 1, 1) [000100] ------------ t100 = LCL_VAR int V08 tmp7 u:3 rdi REG rdi $285
/--* t100 int
N203 ( 2, 2) [000101] ------------ t101 = * HWIntrinsic int TrailingZeroCount REG rcx $400
N205 ( 1, 1) [000102] -c---------- t102 = CNS_INT int 1 REG NA $4b
/--* t101 int
+--* t102 int
N207 ( 4, 4) [000103] ------------ t103 = * ADD int REG rcx $20a
/--* t103 int
N209 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2 rcx REG rcx
N211 ( 4, 5) [000113] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N213 ( 1, 1) [000107] ------------ t107 = LCL_VAR long V09 tmp8 u:3 rax (last use) REG rax $145
N215 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V10 tmp9 u:2 rcx REG rcx $20a
/--* t108 int
N217 ( 2, 3) [000109] ---------U-- t109 = * CAST long <- ulong <- uint REG rdx $24a
/--* t107 long
+--* t109 long
N219 ( 4, 5) [000110] ------------ t110 = * ADD long REG rax $24b
/--* t110 long
N221 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4 rax REG rax
N223 ( 3, 3) [000119] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N225 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:7 rsi (last use) REG rsi $286
N227 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 REG NA $41
/--* t114 int
+--* t115 int
N229 ( 3, 3) [000116] ------------ t116 = * ADD int REG rsi $20b
/--* t116 int
N231 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8 rsi REG rsi
N233 ( 8, 5) [000127] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N235 ( 1, 1) [000120] ------------ t120 = LCL_VAR int V08 tmp7 u:3 rdi (last use) REG rdi $285
N237 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V10 tmp9 u:2 rcx (last use) REG rcx $20a
/--* t120 int
+--* t121 int
N239 ( 8, 5) [000124] ------------ t124 = * RSZ int REG rdi $20d
/--* t124 int
N241 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4 rdi REG rdi
N243 ( 5, 5) [000098] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N245 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V05 tmp4 u:8 rsi REG rsi $20b
N247 ( 1, 1) [000095] -c---------- t95 = CNS_INT int 0 REG NA $40
/--* t94 int
+--* t95 int
N249 ( 3, 3) [000096] J------N---- * GT void REG NA $20e
N251 ( 5, 5) [000097] ------------ * JTRUE void REG NA
------------ BB07 [000..001) (return), preds={BB05,BB06} succs={}
N001 ( 0, 0) [000259] ------------ t259 = PHI_ARG long V09 tmp8 u:4 rax
N002 ( 0, 0) [000257] ------------ t257 = PHI_ARG long V09 tmp8 u:2 rax <l:$248, c:$249>
/--* t259 long
+--* t257 long
N005 ( 2, 2) [000196] ------------ t196 = * PHI long
/--* t196 long
N007 ( 2, 3) [000197] DA---------- * STORE_LCL_VAR long V09 tmp8 d:5 rax
N255 ( 1, 1) [000129] C----------- t129 = LCL_VAR int V09 tmp8 u:5 rax (last use) REG rax $20f
N257 ( 1, 1) [000131] -c---------- t131 = CNS_INT int -1 REG NA $41
/--* t129 int
+--* t131 int
N259 ( 3, 3) [000132] ------------ t132 = * ADD int REG rax $210
/--* t132 int
N261 ( 4, 4) [000010] ------------ * RETURN int REG NA $1c7
------------ BB09 [???..???) -> BB02 (always), preds={BB02} succs={BB02}
N001 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V03 tmp2 rax REG rax
/--* t279 long
N002 ( 2, 2) [000280] ------------ t280 = * COPY long REG rdi
N001 ( 1, 1) [000281] ------------ t281 = LCL_VAR int V04 tmp3 rdx REG rdx
/--* t281 int
N002 ( 2, 2) [000282] ------------ t282 = * COPY int REG rax
------------ BB08 [???..???) -> BB03 (always), preds={BB01} succs={BB03}
N001 ( 1, 1) [000277] ------------ t277 = LCL_VAR long V03 tmp2 rdi REG rdi
/--* t277 long
N002 ( 2, 2) [000278] ------------ t278 = * COPY long REG rax
-------------------------------------------------------------------------------------------------------------------
Final allocation
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
0.#0 V0 Parm Alloc rdi | | | | | |V0 a| | |
1.#1 BB1 PredBB0 | | | | | |V0 a| | |
6.#2 C11 Def Alloc rcx | |C11a| | | |V0 a| | |
7.#3 C11 Use * Keep rcx | |C11i| | | |V0 a| | |
8.#4 I12 Def Alloc rcx | |I12a| | | |V0 a| | |
9.#5 I12 Use * Keep rcx | |I12i| | | |V0 a| | |
10.#6 V2 Def Alloc rcx | |V2 a| | | |V0 a| | |
15.#7 V0 Use * Keep rdi | |V2 a| | | |V0 i| | |
16.#8 V4 Def Alloc rax |V4 a|V2 a| | | | | | |
21.#9 V2 Use Keep rcx |V4 a|V2 a| | | | | | |
22.#10 V3 Def Alloc rdi |V4 a|V2 a| | | |V3 a| | |
27.#11 V4 Use Keep rax |V4 a|V2 a| | | |V3 a| | |
28.#12 V5 Def Alloc rsi |V4 a|V2 a| | |V5 a|V3 a| | |
35.#13 V5 Use Keep rsi |V4 a|V2 a| | |V5 a|V3 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
39.#14 BB2 PredBB1 |V4 a|V2 a| | | |V3 a| | |
45.#15 V4 Use * Keep rax |V4 i|V2 a| | | |V3 a| | |
46.#16 V5 Def Alloc rsi | |V2 a| | |V5 a|V3 a| | |
51.#17 V3 Use * Keep rdi | |V2 a| | |V5 a|V3 i| | |
52.#18 V6 Def Alloc rdi | |V2 a| | |V5 a|V6 a| | |
59.#19 V6 Use Keep rdi | |V2 a| | |V5 a|V6 a| | |
60.#20 I13 Def Alloc rax |I13a|V2 a| | |V5 a|V6 a| | |
61.#21 I13 Use * Keep rax |I13i|V2 a| | |V5 a|V6 a| | |
62.#22 V3 Def Alloc rax |V3 a|V2 a| | |V5 a|V6 a| | |
71.#23 V6 Use * Keep rdi |V3 a|V2 a| | |V5 a|V6 i| | |
72.#24 I14 Def Alloc rdi |V3 a|V2 a| | |V5 a|I14a| | |
73.#25 I14 Use * Keep rdi |V3 a|V2 a| | |V5 a|I14i| | |
74.#26 I15 Def Alloc rdi |V3 a|V2 a| | |V5 a|I15a| | |
75.#27 V5 Use Keep rsi |V3 a|V2 a| | |V5 a|I15a| | |
75.#28 I15 Use *D Keep rdi |V3 a|V2 a| | |V5 a|I15i| | |
76.#29 I16 Def Alloc rdx |V3 a|V2 a|I16a| |V5 a| | | |
77.#30 I16 Use * Keep rdx |V3 a|V2 a|I16i| |V5 a| | | |
78.#31 V4 Def Alloc rdx |V3 a|V2 a|V4 a| |V5 a| | | |
85.#32 V4 Use Keep rdx |V3 a|V2 a|V4 a| |V5 a| | | |
|V3 a|V2 a|V4 a| |V5 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
89.#34 BB3 PredBB2 |V3 a|V2 a| | |V5 a| | | |
97.#35 V3 Use * Keep rax |V3 i|V2 a| | |V5 a| | | |
98.#36 I17 Def Alloc rax |I17a|V2 a| | |V5 a| | | |
99.#37 I17 Use * Keep rax |I17i|V2 a| | |V5 a| | | |
100.#38 V7 Def Alloc rax |V7 a|V2 a| | |V5 a| | | |
109.#39 V7 Use Keep rax |V7 a|V2 a| | |V5 a| | | |
110.#40 I18 Def Alloc rdx |V7 a|V2 a|I18a| |V5 a| | | |
111.#41 V5 Use Keep rsi |V7 a|V2 a|I18a| |V5 a| | | |
111.#42 I18 Use *D Keep rdx |V7 a|V2 a|I18i| |V5 a| | | |
112.#43 I19 Def Alloc rdi |V7 a|V2 a| | |V5 a|I19a| | |
113.#44 I19 Use * Keep rdi |V7 a|V2 a| | |V5 a|I19i| | |
114.#45 V4 Def Alloc rdx |V7 a|V2 a|V4 a| |V5 a| | | |
121.#46 V4 Use Keep rdx |V7 a|V2 a|V4 a| |V5 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
125.#47 BB4 PredBB3 |V7 a|V2 a|V4 a| | | | | |
131.#48 V4 Use * Keep rdx |V7 a|V2 a|V4 i| | | | | |
132.#49 V5 Def Alloc rsi |V7 a|V2 a| | |V5 a| | | |
139.#50 V7 Use * Keep rax |V7 i|V2 a| | |V5 a| | | |
140.#51 I20 Def Alloc rax |I20a|V2 a| | |V5 a| | | |
141.#52 I20 Use * Keep rax |I20i|V2 a| | |V5 a| | | |
142.#53 V7 Def Alloc rax |V7 a|V2 a| | |V5 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
143.#54 BB5 PredBB3 |V7 a|V2 a| | |V5 a| | | |
149.#55 V7 Use Keep rax |V7 a|V2 a| | |V5 a| | | |
150.#56 I21 Def Alloc rdi |V7 a|V2 a| | |V5 a|I21a| | |
151.#57 I21 Use * Keep rdi |V7 a|V2 a| | |V5 a|I21i| | |
152.#58 V8 Def Alloc rdi |V7 a|V2 a| | |V5 a|V8 a| | |
159.#59 V7 Use * Keep rax |V7 i|V2 a| | |V5 a|V8 a| | |
159.#60 V2 Use *D Keep rcx | |V2 i| | |V5 a|V8 a| | |
160.#61 I22 Def Alloc rax |I22a| | | |V5 a|V8 a| | |
161.#62 I22 Use * Keep rax |I22i| | | |V5 a|V8 a| | |
162.#63 V11 Def Alloc rax |V11a| | | |V5 a|V8 a| | |
167.#64 V11 Use Keep rax |V11a| | | |V5 a|V8 a| | |
168.#65 I23 Def Alloc rcx |V11a|I23a| | |V5 a|V8 a| | |
171.#66 I23 Use * Keep rcx |V11a|I23i| | |V5 a|V8 a| | |
172.#67 I24 Def Alloc rcx |V11a|I24a| | |V5 a|V8 a| | |
175.#68 I24 Use * Keep rcx |V11a|I24i| | |V5 a|V8 a| | |
175.#69 V11 Use * Keep rax |V11i| | | |V5 a|V8 a| | |
176.#70 I25 Def Alloc rcx | |I25a| | |V5 a|V8 a| | |
179.#71 I25 Use * Keep rcx | |I25i| | |V5 a|V8 a| | |
180.#72 I26 Def Alloc rcx | |I26a| | |V5 a|V8 a| | |
183.#73 I26 Use * Keep rcx | |I26i| | |V5 a|V8 a| | |
184.#74 I27 Def Alloc rax |I27a| | | |V5 a|V8 a| | |
185.#75 I27 Use * Keep rax |I27i| | | |V5 a|V8 a| | |
186.#76 V9 Def Alloc rax |V9 a| | | |V5 a|V8 a| | |
193.#77 V5 Use Keep rsi |V9 a| | | |V5 a|V8 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
197.#78 BB6 PredBB5 |V9 a| | | |V5 a|V8 a| | |
203.#79 V8 Use Keep rdi |V9 a| | | |V5 a|V8 a| | |
204.#80 I28 Def Alloc rcx |V9 a|I28a| | |V5 a|V8 a| | |
207.#81 I28 Use * Keep rcx |V9 a|I28i| | |V5 a|V8 a| | |
208.#82 I29 Def Alloc rcx |V9 a|I29a| | |V5 a|V8 a| | |
209.#83 I29 Use * Keep rcx |V9 a|I29i| | |V5 a|V8 a| | |
210.#84 V10 Def Alloc rcx |V9 a|V10a| | |V5 a|V8 a| | |
217.#85 V10 Use Keep rcx |V9 a|V10a| | |V5 a|V8 a| | |
218.#86 I30 Def Alloc rdx |V9 a|V10a|I30a| |V5 a|V8 a| | |
219.#87 V9 Use * Keep rax |V9 i|V10a|I30a| |V5 a|V8 a| | |
219.#88 I30 Use * Keep rdx | |V10a|I30i| |V5 a|V8 a| | |
220.#89 I31 Def Alloc rax |I31a|V10a| | |V5 a|V8 a| | |
221.#90 I31 Use * Keep rax |I31i|V10a| | |V5 a|V8 a| | |
222.#91 V9 Def Alloc rax |V9 a|V10a| | |V5 a|V8 a| | |
229.#92 V5 Use * Keep rsi |V9 a|V10a| | |V5 i|V8 a| | |
230.#93 I32 Def Alloc rsi |V9 a|V10a| | |I32a|V8 a| | |
231.#94 I32 Use * Keep rsi |V9 a|V10a| | |I32i|V8 a| | |
232.#95 V5 Def Alloc rsi |V9 a|V10a| | |V5 a|V8 a| | |
239.#96 V8 Use * Keep rdi |V9 a|V10a| | |V5 a|V8 i| | |
239.#97 rcx Fixd Keep rcx |V9 a|V10a| | |V5 a| | | |
239.#98 V10 Use *D Keep rcx |V9 a|V10i| | |V5 a| | | |
240.#99 rcx Kill Keep rcx |V9 a| | | |V5 a| | | |
240.#100 I33 Def Alloc rdi |V9 a| | | |V5 a|I33a| | |
241.#101 I33 Use * Keep rdi |V9 a| | | |V5 a|I33i| | |
242.#102 V8 Def Alloc rdi |V9 a| | | |V5 a|V8 a| | |
249.#103 V5 Use Keep rsi |V9 a| | | |V5 a|V8 a| | |
|V9 a| | | |V5 a|V8 a| | |
|V9 a| | | |V5 a|V8 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
253.#106 BB7 PredBB6 |V9 a| | | | | | | |
259.#107 V9 Use * Keep rax |V9 i| | | | | | | |
260.#108 I34 Def Alloc rax |I34a| | | | | | | |
261.#109 rax Fixd Keep rax |I34a| | | | | | | |
261.#110 I34 Use * Keep rax |I34i| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
0.#0 BB9 PredBB2 | | | | | | | | |
261.#0 V3 Move rdi | |V2 a|V4 a| | |V3 a| | |
261.#0 V4 Move rax |V4 a|V2 a| | | |V3 a| | |
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+----+
0.#0 BB8 PredBB1 |V4 i|V2 i| | | |V3 i| | |
261.#0 V3 Move rax |V3 a|V2 a| | |V5 a| | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
BB01 [ 100]: SpillCount = 0, ResolutionMovs = 0, SplitEdges = 1, CopyReg = 0
BB02 [ 200]: SpillCount = 0, ResolutionMovs = 0, SplitEdges = 1, CopyReg = 0
Total Tracked Vars: 11
Total Reg Cand Vars: 11
Total number of Intervals: 34
Total number of RefPositions: 110
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 2
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(rdi)
BB01 [000..011) -> BB08 (cond), preds={} succs={BB02,BB08}
=====
N003. IL_OFFSET IL offset: 0x0 REG NA
N005. rcx* = CNS_INT(h) 0x7fe9bcfc4498 static Fseq[_bits] REG rcx
N007. rcx = IND ; rcx*
* N009. V02(rcx); rcx
N011. IL_OFFSET IL offset: 0x0 REG NA
N013. V00(rdi*)
* N015. V04(rax); rdi*
N017. IL_OFFSET IL offset: 0x0 REG NA
N019. V02(rcx)
* N021. V03(rdi); rcx
N023. IL_OFFSET IL offset: 0x0 REG NA
N025. V04(rax)
* N027. V05(rsi); rax
N029. IL_OFFSET IL offset: 0x0 REG NA
N031. V05(rsi)
N033. CNS_INT 0 REG NA
N035. LE ; rsi
N037. JTRUE
Var=Reg end of BB01: V04=rax V05=rsi V03=rdi V02=rcx
BB02 [000..001) -> BB09 (cond), preds={BB01,BB09} succs={BB03,BB09}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: V04=rax V03=rdi V02=rcx
N041. IL_OFFSET IL offset: 0x0 REG NA
N043. V04(rax*)
* N045. V05(rsi); rax*
N047. IL_OFFSET IL offset: 0x0 REG NA
N049. V03(rdi*)
* N051. V06(rdi); rdi*
N053. IL_OFFSET IL offset: 0x0 REG NA
N055. V06(rdi)
N057. CNS_INT 8 REG NA
N059. rax = ADD ; rdi
* N061. V03(rax); rax
N063. IL_OFFSET IL offset: 0x0 REG NA
N065. V05(rsi)
N067. V06(rdi*)
N069. STK = IND ; rdi*
N071. rdi = HWIntrinsic; STK
N073. rdi = CAST ; rdi
N075. rdx = SUB ; rsi,rdi
* N077. V04(rdx); rdx
N079. IL_OFFSET IL offset: 0x0 REG NA
N081. V04(rdx)
N083. CNS_INT 0 REG NA
N085. GT ; rdx
N087. JTRUE
Var=Reg end of BB02: V04=rdx V05=rsi V03=rax V02=rcx
BB03 [000..001) -> BB05 (cond), preds={BB08,BB02} succs={BB04,BB05}
=====
Predecessor for variable locations: BB02
Var=Reg beg of BB03: V05=rsi V03=rax V02=rcx
N091. IL_OFFSET IL offset: 0x0 REG NA
N093. V03(rax*)
N095. CNS_INT -8 REG NA
N097. rax = ADD ; rax*
* N099. V07(rax); rax
N101. IL_OFFSET IL offset: 0x0 REG NA
N103. V05(rsi)
N105. V07(rax)
N107. STK = IND ; rax
N109. rdx = HWIntrinsic; STK
N111. rdi = SUB ; rsi,rdx
* N113. V04(rdx); rdi
N115. IL_OFFSET IL offset: 0x0 REG NA
N117. V04(rdx)
N119. CNS_INT 0 REG NA
N121. LE ; rdx
N123. JTRUE
Var=Reg end of BB03: V04=rdx V05=rsi V02=rcx V07=rax
BB04 [000..001), preds={BB03} succs={BB05}
=====
Predecessor for variable locations: BB03
Var=Reg beg of BB04: V04=rdx V02=rcx V07=rax
N127. IL_OFFSET IL offset: 0x0 REG NA
N129. V04(rdx*)
* N131. V05(rsi); rdx*
N133. IL_OFFSET IL offset: 0x0 REG NA
N135. V07(rax*)
N137. CNS_INT 4 REG NA
N139. rax = ADD ; rax*
* N141. V07(rax); rax
Var=Reg end of BB04: V05=rsi V02=rcx V07=rax
BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07}
=====
Predecessor for variable locations: BB03
Var=Reg beg of BB05: V05=rsi V02=rcx V07=rax
N145. IL_OFFSET IL offset: 0x0 REG NA
N147. V07(rax)
N149. rdi = IND ; rax
* N151. V08(rdi); rdi
N153. IL_OFFSET IL offset: 0x0 REG NA
N155. V07(rax*)
N157. V02(rcx*)
N159. rax = SUB ; rax*,rcx*
* N161. V11(rax); rax
N163. V11(rax)
N165. CNS_INT 63 REG NA
N167. rcx = RSH ; rax
N169. CNS_INT 3 REG NA
N171. rcx = AND ; rcx
N173. V11(rax*)
N175. rcx = ADD ; rcx,rax*
N177. CNS_INT 2 REG NA
N179. rcx = RSH ; rcx
N181. CNS_INT 5 REG NA
N183. rax = LSH ; rcx
* N185. V09(rax); rax
N187. IL_OFFSET IL offset: 0x0 REG NA
N189. V05(rsi)
N191. CNS_INT 0 REG NA
N193. LE ; rsi
N195. JTRUE
Var=Reg end of BB05: V05=rsi V08=rdi V09=rax
BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06}
=====
Predecessor for variable locations: BB05
Var=Reg beg of BB06: V05=rsi V08=rdi V09=rax
N199. IL_OFFSET IL offset: 0x0 REG NA
N201. V08(rdi)
N203. rcx = HWIntrinsic; rdi
N205. CNS_INT 1 REG NA
N207. rcx = ADD ; rcx
* N209. V10(rcx); rcx
N211. IL_OFFSET IL offset: 0x0 REG NA
N213. V09(rax*)
N215. V10(rcx)
N217. rdx = CAST ; rcx
N219. rax = ADD ; rax*,rdx
* N221. V09(rax); rax
N223. IL_OFFSET IL offset: 0x0 REG NA
N225. V05(rsi*)
N227. CNS_INT -1 REG NA
N229. rsi = ADD ; rsi*
* N231. V05(rsi); rsi
N233. IL_OFFSET IL offset: 0x0 REG NA
N235. V08(rdi*)
N237. V10(rcx*)
N239. rdi = RSZ ; rdi*,rcx*
* N241. V08(rdi); rdi
N243. IL_OFFSET IL offset: 0x0 REG NA
N245. V05(rsi)
N247. CNS_INT 0 REG NA
N249. GT ; rsi
N251. JTRUE
Var=Reg end of BB06: V05=rsi V08=rdi V09=rax
BB07 [000..001) (return), preds={BB05,BB06} succs={}
=====
Predecessor for variable locations: BB06
Var=Reg beg of BB07: V09=rax
N255. V09(rax*)
N257. CNS_INT -1 REG NA
N259. rax = ADD ; rax*
N261. RETURN ; rax
Var=Reg end of BB07: none
*************** In genGenerateCode()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011)-> BB08 ( cond ) i label target LIR
BB02 [0002] 2 BB01,BB09 2 [000..001)-> BB09 ( cond ) i Loop Loop0 label target bwd LIR
BB03 [0004] 2 BB08,BB02 0.50 [000..001)-> BB05 ( cond ) i label target LIR
BB04 [0005] 1 BB03 0.25 [000..001) i LIR
BB05 [0006] 2 BB03,BB04 0.50 [000..001)-> BB07 ( cond ) i label target LIR
BB06 [0007] 2 BB05,BB06 2 [000..001)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR
BB07 [0009] 2 BB05,BB06 1 [000..001) (return) i label target LIR
BB09 [0012] 1 BB02 1 [???..???)-> BB02 (always) internal target bwd LIR
BB08 [0011] 1 BB01 0.50 [???..???)-> BB03 (always) internal target LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(rdi)
Modified regs: [rax rcx rdx rsi rdi]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
; Final local variable assignments
;
; V00 arg0 [V00,T07] ( 3, 3 ) int -> rdi
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
; V02 tmp1 [V02,T08] ( 3, 5 ) long -> rcx
; V03 tmp2 [V03,T05] ( 4, 5.50) long -> registers
; V04 tmp3 [V04,T00] ( 8, 18.50) int -> registers
; V05 tmp4 [V05,T01] ( 10, 13.25) int -> rsi
; V06 tmp5 [V06,T02] ( 3, 12 ) long -> rdi
; V07 tmp6 [V07,T10] ( 6, 2.50) long -> rax
; V08 tmp7 [V08,T03] ( 4, 6.50) int -> rdi
; V09 tmp8 [V09,T06] ( 4, 5.50) long -> rax
; V10 tmp9 [V10,T04] ( 3, 6 ) int -> rcx
; V11 rat0 [V11,T09] ( 3, 3 ) long -> rax
;
; Lcl frame size = 0
=============== Generating BB01 [000..011) -> BB08 (cond), preds={} succs={BB02,BB08} flags=0x00000000.40030020: i label target LIR
BB01 IN (1)={ V00 } + ByrefExposed + GcHeap
OUT(4)={V04 V05 V03 V02} + ByrefExposed + GcHeap
Recording Var Locations at start of BB01
V00(rdi)
Change life 0000000000000000 {} -> 0000000000000080 {V00}
V00 in reg rdi is becoming live [------]
Live regs: 00000000 {} => 00000080 {rdi}
Live regs: (unchanged) 00000080 {rdi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M7892_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Setting stack level from -572662307 to 0
Scope info: begin block BB01, IL range [000..011)
Scope info: open scopes =
0 (V00 arg0) [000..011)
Added IP mapping: 0x0000 STACK_EMPTY (G_M7892_IG02,ins#0,ofs#0) label
Generating: N003 ( 5, 12) [000147] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N005 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0x7fe9bcfc4498 static Fseq[_bits] REG rcx $100
IN0001: mov rcx, 0x7FE9BCFC4498
/--* t176 long
Generating: N007 ( 5, 12) [000001] x---G------- t1 = * IND long REG rcx <l:$140, c:$180>
IN0002: mov rcx, qword ptr [rcx]
/--* t1 long
Generating: N009 ( 5, 12) [000146] DA--G------- * STORE_LCL_VAR long V02 tmp1 d:2 rcx REG rcx
V02 in reg rcx is becoming live [000146]
Live regs: 00000080 {rdi} => 00000082 {rcx rdi}
Live vars: {V00} => {V00 V02}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N011 ( 1, 3) [000150] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N013 ( 1, 1) [000003] ------------ t3 = LCL_VAR int V00 arg0 u:2 rdi (last use) REG rdi $80
/--* t3 int
Generating: N015 ( 1, 3) [000149] DA---------- * STORE_LCL_VAR int V04 tmp3 d:2 rax REG rax
V00 in reg rdi is becoming dead [000003]
Live regs: 00000082 {rcx rdi} => 00000002 {rcx}
Live vars: {V00 V02} => {V02}
IN0003: mov eax, edi
V04 in reg rax is becoming live [000149]
Live regs: 00000002 {rcx} => 00000003 {rax rcx}
Live vars: {V02} => {V02 V04}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N017 ( 1, 3) [000016] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N019 ( 1, 1) [000013] ------------ t13 = LCL_VAR long V02 tmp1 u:2 rcx REG rcx <l:$140, c:$180>
/--* t13 long
Generating: N021 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR long V03 tmp2 d:2 rdi REG rdi
IN0004: mov rdi, rcx
V03 in reg rdi is becoming live [000015]
Live regs: 00000003 {rax rcx} => 00000083 {rax rcx rdi}
Live vars: {V02 V04} => {V02 V03 V04}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N023 ( 1, 3) [000020] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N025 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V04 tmp3 u:2 rax REG rax $80
/--* t17 int
Generating: N027 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V05 tmp4 d:2 rsi REG rsi
IN0005: mov esi, eax
V05 in reg rsi is becoming live [000019]
Live regs: 00000083 {rax rcx rdi} => 000000C3 {rax rcx rsi rdi}
Live vars: {V02 V03 V04} => {V02 V03 V04 V05}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N029 ( 5, 5) [000181] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N031 ( 1, 1) [000178] ------------ t178 = LCL_VAR int V05 tmp4 u:2 rsi REG rsi $80
Generating: N033 ( 1, 1) [000179] -c---------- t179 = CNS_INT int 0 REG NA $40
/--* t178 int
+--* t179 int
Generating: N035 ( 3, 3) [000177] J------N---- * LE void REG NA $200
IN0006: test esi, esi
Generating: N037 ( 5, 5) [000180] ------------ * JTRUE void REG NA
IN0007: jle L_M7892_BB08
Scope info: end block BB01, IL range [000..011)
Scope info: ending scope, LVnum=0 [000..011)
Scope info: open scopes =
<none>
=============== Generating BB02 [000..001) -> BB09 (cond), preds={BB01,BB09} succs={BB03,BB09} flags=0x00000000.42036020: i Loop Loop0 label target bwd LIR
BB02 IN (3)={V04 V03 V02} + ByrefExposed + GcHeap
OUT(4)={V04 V05 V03 V02} + ByrefExposed + GcHeap
Recording Var Locations at start of BB02
V04(rax) V03(rdi) V02(rcx)
Change life 0000000000000123 {V02 V03 V04 V05} -> 0000000000000121 {V02 V03 V04}
V05 in reg rsi is becoming dead [------]
Live regs: (unchanged) 00000000 {}
Live regs: 00000000 {} => 00000083 {rax rcx rdi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M7892_BB02:
G_M7892_IG02: ; offs=000000H, funclet=00
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB02, IL range [000..001)
Scope info: open scopes =
<none>
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N041 ( 1, 3) [000031] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N043 ( 1, 1) [000028] ------------ t28 = LCL_VAR int V04 tmp3 u:3 rax (last use) REG rax $280
/--* t28 int
Generating: N045 ( 1, 3) [000030] DA---------- * STORE_LCL_VAR int V05 tmp4 d:3 rsi REG rsi
V04 in reg rax is becoming dead [000028]
Live regs: 00000083 {rax rcx rdi} => 00000082 {rcx rdi}
Live vars: {V02 V03 V04} => {V02 V03}
IN0008: mov esi, eax
V05 in reg rsi is becoming live [000030]
Live regs: 00000082 {rcx rdi} => 000000C2 {rcx rsi rdi}
Live vars: {V02 V03} => {V02 V03 V05}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N047 ( 1, 3) [000041] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N049 ( 1, 1) [000033] ------------ t33 = LCL_VAR long V03 tmp2 u:3 rdi (last use) REG rdi $141
/--* t33 long
Generating: N051 ( 1, 3) [000040] DA---------- * STORE_LCL_VAR long V06 tmp5 d:2 rdi REG rdi
V03 in reg rdi is becoming dead [000033]
Live regs: 000000C2 {rcx rsi rdi} => 00000042 {rcx rsi}
Live vars: {V02 V03 V05} => {V02 V05}
V06 in reg rdi is becoming live [000040]
Live regs: 00000042 {rcx rsi} => 000000C2 {rcx rsi rdi}
Live vars: {V02 V05} => {V02 V05 V06}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N053 ( 3, 3) [000044] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N055 ( 1, 1) [000034] ------------ t34 = LCL_VAR long V06 tmp5 u:2 rdi REG rdi $141
Generating: N057 ( 1, 1) [000036] -c---------- t36 = CNS_INT long 8 REG NA $340
/--* t34 long
+--* t36 long
Generating: N059 ( 3, 3) [000037] ------------ t37 = * ADD long REG rax $241
IN0009: lea rax, [rdi+8]
/--* t37 long
Generating: N061 ( 3, 3) [000043] DA---------- * STORE_LCL_VAR long V03 tmp2 d:4 rax REG rax
V03 in reg rax is becoming live [000043]
Live regs: 000000C2 {rcx rsi rdi} => 000000C3 {rax rcx rsi rdi}
Live vars: {V02 V05 V06} => {V02 V03 V05 V06}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N063 ( 7, 7) [000052] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N065 ( 1, 1) [000032] ------------ t32 = LCL_VAR int V05 tmp4 u:3 rsi REG rsi $280
Generating: N067 ( 1, 1) [000042] ------------ t42 = LCL_VAR long V06 tmp5 u:2 rdi (last use) REG rdi $141
/--* t42 long
Generating: N069 ( 3, 2) [000045] *c-XG------- t45 = * IND long REG NA <l:$142, c:$302>
/--* t45 long
Generating: N071 ( 4, 3) [000046] ---XG------- t46 = * HWIntrinsic long PopCount REG rdi $380
V06 in reg rdi is becoming dead [000042]
Live regs: 000000C3 {rax rcx rsi rdi} => 00000043 {rax rcx rsi}
Live vars: {V02 V03 V05 V06} => {V02 V03 V05}
IN000a: popcnt rdi, qword ptr [rdi]
/--* t46 long
Generating: N073 ( 5, 5) [000047] ---XG------- t47 = * CAST int <- long REG rdi $201
/--* t32 int
+--* t47 int
Generating: N075 ( 7, 7) [000048] ---XG------- t48 = * SUB int REG rdx $202
IN000b: mov edx, esi
IN000c: sub edx, edi
/--* t48 int
Generating: N077 ( 7, 7) [000051] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:4 rdx REG rdx
V04 in reg rdx is becoming live [000051]
Live regs: 00000043 {rax rcx rsi} => 00000047 {rax rcx rdx rsi}
Live vars: {V02 V03 V05} => {V02 V03 V04 V05}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N079 ( 5, 5) [000026] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N081 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V04 tmp3 u:4 rdx REG rdx $202
Generating: N083 ( 1, 1) [000023] -c---------- t23 = CNS_INT int 0 REG NA $40
/--* t22 int
+--* t23 int
Generating: N085 ( 3, 3) [000024] J------N---- * GT void REG NA $203
IN000d: test edx, edx
Generating: N087 ( 5, 5) [000025] ------------ * JTRUE void REG NA
IN000e: jg L_M7892_BB09
Scope info: end block BB02, IL range [000..001)
Scope info: open scopes =
<none>
=============== Generating BB03 [000..001) -> BB05 (cond), preds={BB08,BB02} succs={BB04,BB05} flags=0x00000000.40030020: i label target LIR
BB03 IN (3)={ V05 V03 V02 } + ByrefExposed + GcHeap
OUT(4)={V04 V05 V02 V07} + ByrefExposed + GcHeap
Recording Var Locations at start of BB03
V05(rsi) V03(rax) V02(rcx)
Change life 0000000000000123 {V02 V03 V04 V05} -> 0000000000000122 {V02 V03 V05}
V04 in reg rdx is becoming dead [------]
Live regs: (unchanged) 00000000 {}
Live regs: 00000000 {} => 00000043 {rax rcx rsi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M7892_BB03:
G_M7892_IG03: ; offs=00001CH, funclet=00
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB03, IL range [000..001)
Scope info: open scopes =
<none>
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N091 ( 3, 3) [000060] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N093 ( 1, 1) [000054] ------------ t54 = LCL_VAR long V03 tmp2 u:5 rax (last use) REG rax $143
Generating: N095 ( 1, 1) [000056] -c---------- t56 = CNS_INT long -8 REG NA $342
/--* t54 long
+--* t56 long
Generating: N097 ( 3, 3) [000057] ------------ t57 = * ADD long REG rax $242
V03 in reg rax is becoming dead [000054]
Live regs: 00000043 {rax rcx rsi} => 00000042 {rcx rsi}
Live vars: {V02 V03 V05} => {V02 V05}
IN000f: add rax, -8
/--* t57 long
Generating: N099 ( 3, 3) [000059] DA---------- * STORE_LCL_VAR long V07 tmp6 d:2 rax REG rax
V07 in reg rax is becoming live [000059]
Live regs: 00000042 {rcx rsi} => 00000043 {rax rcx rsi}
Live vars: {V02 V05} => {V02 V05 V07}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N101 ( 6, 5) [000069] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N103 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V05 tmp4 u:4 rsi REG rsi $281
Generating: N105 ( 1, 1) [000062] ------------ t62 = LCL_VAR long V07 tmp6 u:2 rax REG rax $242
/--* t62 long
Generating: N107 ( 3, 2) [000063] *c-XG------- t63 = * IND int REG NA <l:$282, c:$1c2>
/--* t63 int
Generating: N109 ( 4, 3) [000064] ---XG------- t64 = * HWIntrinsic int PopCount REG rdx $3c0
IN0010: popcnt edx, dword ptr [rax]
/--* t61 int
+--* t64 int
Generating: N111 ( 6, 5) [000065] ---XG------- t65 = * SUB int REG rdi $205
IN0011: mov edi, esi
IN0012: sub edi, edx
/--* t65 int
Generating: N113 ( 6, 5) [000068] DA-XG------- * STORE_LCL_VAR int V04 tmp3 d:5 rdx REG rdx
IN0013: mov edx, edi
V04 in reg rdx is becoming live [000068]
Live regs: 00000043 {rax rcx rsi} => 00000047 {rax rcx rdx rsi}
Live vars: {V02 V05 V07} => {V02 V04 V05 V07}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N115 ( 5, 5) [000074] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N117 ( 1, 1) [000070] ------------ t70 = LCL_VAR int V04 tmp3 u:5 rdx REG rdx $205
Generating: N119 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 0 REG NA $40
/--* t70 int
+--* t71 int
Generating: N121 ( 3, 3) [000072] J------N---- * LE void REG NA $206
IN0014: test edx, edx
Generating: N123 ( 5, 5) [000073] ------------ * JTRUE void REG NA
IN0015: jle L_M7892_BB05
Scope info: end block BB03, IL range [000..001)
Scope info: open scopes =
<none>
=============== Generating BB04 [000..001), preds={BB03} succs={BB05} flags=0x00000000.40000020: i LIR
BB04 IN (3)={V04 V02 V07} + ByrefExposed + GcHeap
OUT(3)={ V05 V02 V07} + ByrefExposed + GcHeap
Recording Var Locations at start of BB04
V04(rdx) V02(rcx) V07(rax)
Change life 0000000000000503 {V02 V04 V05 V07} -> 0000000000000501 {V02 V04 V07}
V05 in reg rsi is becoming dead [------]
Live regs: (unchanged) 00000000 {}
Live regs: 00000000 {} => 00000007 {rax rcx rdx}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M7892_BB04:
Scope info: begin block BB04, IL range [000..001)
Scope info: open scopes =
<none>
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N127 ( 1, 3) [000137] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N129 ( 1, 1) [000134] ------------ t134 = LCL_VAR int V04 tmp3 u:5 rdx (last use) REG rdx $205
/--* t134 int
Generating: N131 ( 1, 3) [000136] DA---------- * STORE_LCL_VAR int V05 tmp4 d:5 rsi REG rsi
V04 in reg rdx is becoming dead [000134]
Live regs: 00000007 {rax rcx rdx} => 00000003 {rax rcx}
Live vars: {V02 V04 V07} => {V02 V07}
IN0016: mov esi, edx
V05 in reg rsi is becoming live [000136]
Live regs: 00000003 {rax rcx} => 00000043 {rax rcx rsi}
Live vars: {V02 V07} => {V02 V05 V07}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N133 ( 3, 3) [000144] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N135 ( 1, 1) [000138] ------------ t138 = LCL_VAR long V07 tmp6 u:2 rax (last use) REG rax $242
Generating: N137 ( 1, 1) [000140] -c---------- t140 = CNS_INT long 4 REG NA $343
/--* t138 long
+--* t140 long
Generating: N139 ( 3, 3) [000141] ------------ t141 = * ADD long REG rax $243
V07 in reg rax is becoming dead [000138]
Live regs: 00000043 {rax rcx rsi} => 00000042 {rcx rsi}
Live vars: {V02 V05 V07} => {V02 V05}
IN0017: add rax, 4
/--* t141 long
Generating: N141 ( 3, 3) [000143] DA---------- * STORE_LCL_VAR long V07 tmp6 d:3 rax REG rax
V07 in reg rax is becoming live [000143]
Live regs: 00000042 {rcx rsi} => 00000043 {rax rcx rsi}
Live vars: {V02 V05} => {V02 V05 V07}
Scope info: end block BB04, IL range [000..001)
Scope info: open scopes =
<none>
=============== Generating BB05 [000..001) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07} flags=0x00000000.40030020: i label target LIR
BB05 IN (3)={V05 V02 V07} + ByrefExposed + GcHeap
OUT(3)={V05 V08 V09 }
Recording Var Locations at start of BB05
V05(rsi) V02(rcx) V07(rax)
Liveness not changing: 0000000000000502 {V02 V05 V07}
Live regs: 00000000 {} => 00000043 {rax rcx rsi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M7892_BB05:
G_M7892_IG04: ; offs=000033H, funclet=00
Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB05, IL range [000..001)
Scope info: open scopes =
<none>
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N145 ( 3, 3) [000080] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N147 ( 1, 1) [000076] ------------ t76 = LCL_VAR long V07 tmp6 u:4 rax REG rax $144
/--* t76 long
Generating: N149 ( 3, 2) [000077] *--XG------- t77 = * IND int REG rdi <l:$284, c:$1c5>
IN0018: mov edi, dword ptr [rax]
/--* t77 int
Generating: N151 ( 3, 3) [000079] DA-XG------- * STORE_LCL_VAR int V08 tmp7 d:2 rdi REG rdi
V08 in reg rdi is becoming live [000079]
Live regs: 00000043 {rax rcx rsi} => 000000C3 {rax rcx rsi rdi}
Live vars: {V02 V05 V07} => {V02 V05 V07 V08}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N153 ( 26, 9) [000092] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N155 ( 1, 1) [000081] ------------ t81 = LCL_VAR long V07 tmp6 u:4 rax (last use) REG rax $144
Generating: N157 ( 1, 1) [000082] ------------ t82 = LCL_VAR long V02 tmp1 u:2 rcx (last use) REG rcx <l:$140, c:$180>
/--* t81 long
+--* t82 long
Generating: N159 ( 3, 3) [000083] ------------ t83 = * SUB long REG rax <l:$244, c:$245>
V07 in reg rax is becoming dead [000081]
Live regs: 000000C3 {rax rcx rsi rdi} => 000000C2 {rcx rsi rdi}
Live vars: {V02 V05 V07 V08} => {V02 V05 V08}
V02 in reg rcx is becoming dead [000082]
Live regs: 000000C2 {rcx rsi rdi} => 000000C0 {rsi rdi}
Live vars: {V02 V05 V08} => {V05 V08}
IN0019: sub rax, rcx
/--* t83 long
Generating: N161 (???,???) [000268] DA---------- * STORE_LCL_VAR long V11 rat0 rax REG rax
V11 in reg rax is becoming live [000268]
Live regs: 000000C0 {rsi rdi} => 000000C1 {rax rsi rdi}
Live vars: {V05 V08} => {V05 V08 V11}
Generating: N163 ( 1, 1) [000269] ------------ t269 = LCL_VAR long V11 rat0 rax REG rax
Generating: N165 ( 1, 1) [000270] -c---------- t270 = CNS_INT int 63 REG NA
/--* t269 long
+--* t270 int
Generating: N167 ( 3, 3) [000271] ------------ t271 = * RSH long REG rcx
IN001a: mov rcx, rax
IN001b: sar rcx, 63
Generating: N169 ( 1, 1) [000272] -c---------- t272 = CNS_INT long 3 REG NA
/--* t271 long
+--* t272 long
Generating: N171 ( 5, 5) [000273] ------------ t273 = * AND long REG rcx
IN001c: and rcx, 3
Generating: N173 ( 1, 1) [000274] ------------ t274 = LCL_VAR long V11 rat0 rax (last use) REG rax
/--* t273 long
+--* t274 long
Generating: N175 ( 7, 7) [000275] ------------ t275 = * ADD long REG rcx
V11 in reg rax is becoming dead [000274]
Live regs: 000000C1 {rax rsi rdi} => 000000C0 {rsi rdi}
Live vars: {V05 V08 V11} => {V05 V08}
IN001d: add rcx, rax
Generating: N177 ( 1, 1) [000085] -c---------- t85 = CNS_INT long 2 REG NA $343
/--* t275 long
+--* t85 long
Generating: N179 ( 9, 9) [000276] ------------ t276 = * RSH long REG rcx
IN001e: sar rcx, 2
Generating: N181 ( 1, 1) [000088] -c---------- t88 = CNS_INT long 5 REG NA $345
/--* t276 long
+--* t88 long
Generating: N183 ( 26, 9) [000089] ------------ t89 = * LSH long REG rax <l:$248, c:$249>
IN001f: mov rax, rcx
IN0020: shl rax, 5
/--* t89 long
Generating: N185 ( 26, 9) [000091] DA---------- * STORE_LCL_VAR long V09 tmp8 d:2 rax REG rax
V09 in reg rax is becoming live [000091]
Live regs: 000000C0 {rsi rdi} => 000000C1 {rax rsi rdi}
Live vars: {V05 V08} => {V05 V08 V09}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N187 ( 5, 5) [000186] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N189 ( 1, 1) [000183] ------------ t183 = LCL_VAR int V05 tmp4 u:6 rsi REG rsi $283
Generating: N191 ( 1, 1) [000184] -c---------- t184 = CNS_INT int 0 REG NA $40
/--* t183 int
+--* t184 int
Generating: N193 ( 3, 3) [000182] J------N---- * LE void REG NA $208
IN0021: test esi, esi
Generating: N195 ( 5, 5) [000185] ------------ * JTRUE void REG NA
IN0022: jle L_M7892_BB07
Scope info: end block BB05, IL range [000..001)
Scope info: open scopes =
<none>
=============== Generating BB06 [000..001) -> BB06 (cond), preds={BB05,BB06} succs={BB07,BB06} flags=0x00000000.42036020: i Loop Loop0 label target bwd LIR
BB06 IN (3)={V05 V08 V09}
OUT(3)={V05 V08 V09}
Recording Var Locations at start of BB06
V05(rsi) V08(rdi) V09(rax)
Liveness not changing: 000000000000004A {V05 V08 V09}
Live regs: 00000000 {} => 000000C1 {rax rsi rdi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M7892_BB06:
G_M7892_IG05: ; offs=00004FH, funclet=00
Label: IG06, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB06, IL range [000..001)
Scope info: open scopes =
<none>
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N199 ( 4, 4) [000106] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N201 ( 1, 1) [000100] ------------ t100 = LCL_VAR int V08 tmp7 u:3 rdi REG rdi $285
/--* t100 int
Generating: N203 ( 2, 2) [000101] ------------ t101 = * HWIntrinsic int TrailingZeroCount REG rcx $400
IN0023: tzcnt ecx, edi
Generating: N205 ( 1, 1) [000102] -c---------- t102 = CNS_INT int 1 REG NA $4b
/--* t101 int
+--* t102 int
Generating: N207 ( 4, 4) [000103] ------------ t103 = * ADD int REG rcx $20a
IN0024: inc ecx
/--* t103 int
Generating: N209 ( 4, 4) [000105] DA---------- * STORE_LCL_VAR int V10 tmp9 d:2 rcx REG rcx
V10 in reg rcx is becoming live [000105]
Live regs: 000000C1 {rax rsi rdi} => 000000C3 {rax rcx rsi rdi}
Live vars: {V05 V08 V09} => {V05 V08 V09 V10}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N211 ( 4, 5) [000113] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N213 ( 1, 1) [000107] ------------ t107 = LCL_VAR long V09 tmp8 u:3 rax (last use) REG rax $145
Generating: N215 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V10 tmp9 u:2 rcx REG rcx $20a
/--* t108 int
Generating: N217 ( 2, 3) [000109] ---------U-- t109 = * CAST long <- ulong <- uint REG rdx $24a
IN0025: mov edx, ecx
/--* t107 long
+--* t109 long
Generating: N219 ( 4, 5) [000110] ------------ t110 = * ADD long REG rax $24b
V09 in reg rax is becoming dead [000107]
Live regs: 000000C3 {rax rcx rsi rdi} => 000000C2 {rcx rsi rdi}
Live vars: {V05 V08 V09 V10} => {V05 V08 V10}
IN0026: add rax, rdx
/--* t110 long
Generating: N221 ( 4, 5) [000112] DA---------- * STORE_LCL_VAR long V09 tmp8 d:4 rax REG rax
V09 in reg rax is becoming live [000112]
Live regs: 000000C2 {rcx rsi rdi} => 000000C3 {rax rcx rsi rdi}
Live vars: {V05 V08 V10} => {V05 V08 V09 V10}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N223 ( 3, 3) [000119] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N225 ( 1, 1) [000114] ------------ t114 = LCL_VAR int V05 tmp4 u:7 rsi (last use) REG rsi $286
Generating: N227 ( 1, 1) [000115] -c---------- t115 = CNS_INT int -1 REG NA $41
/--* t114 int
+--* t115 int
Generating: N229 ( 3, 3) [000116] ------------ t116 = * ADD int REG rsi $20b
V05 in reg rsi is becoming dead [000114]
Live regs: 000000C3 {rax rcx rsi rdi} => 00000083 {rax rcx rdi}
Live vars: {V05 V08 V09 V10} => {V08 V09 V10}
IN0027: dec esi
/--* t116 int
Generating: N231 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR int V05 tmp4 d:8 rsi REG rsi
V05 in reg rsi is becoming live [000118]
Live regs: 00000083 {rax rcx rdi} => 000000C3 {rax rcx rsi rdi}
Live vars: {V08 V09 V10} => {V05 V08 V09 V10}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N233 ( 8, 5) [000127] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N235 ( 1, 1) [000120] ------------ t120 = LCL_VAR int V08 tmp7 u:3 rdi (last use) REG rdi $285
Generating: N237 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V10 tmp9 u:2 rcx (last use) REG rcx $20a
/--* t120 int
+--* t121 int
Generating: N239 ( 8, 5) [000124] ------------ t124 = * RSZ int REG rdi $20d
V08 in reg rdi is becoming dead [000120]
Live regs: 000000C3 {rax rcx rsi rdi} => 00000043 {rax rcx rsi}
Live vars: {V05 V08 V09 V10} => {V05 V09 V10}
V10 in reg rcx is becoming dead [000121]
Live regs: 00000043 {rax rcx rsi} => 00000041 {rax rsi}
Live vars: {V05 V09 V10} => {V05 V09}
IN0028: shr edi, cl
/--* t124 int
Generating: N241 ( 8, 5) [000126] DA---------- * STORE_LCL_VAR int V08 tmp7 d:4 rdi REG rdi
V08 in reg rdi is becoming live [000126]
Live regs: 00000041 {rax rsi} => 000000C1 {rax rsi rdi}
Live vars: {V05 V09} => {V05 V08 V09}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N243 ( 5, 5) [000098] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N245 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V05 tmp4 u:8 rsi REG rsi $20b
Generating: N247 ( 1, 1) [000095] -c---------- t95 = CNS_INT int 0 REG NA $40
/--* t94 int
+--* t95 int
Generating: N249 ( 3, 3) [000096] J------N---- * GT void REG NA $20e
IN0029: test esi, esi
Generating: N251 ( 5, 5) [000097] ------------ * JTRUE void REG NA
IN002a: jg SHORT L_M7892_BB06
Scope info: end block BB06, IL range [000..001)
Scope info: open scopes =
<none>
=============== Generating BB07 [000..001) (return), preds={BB05,BB06} succs={} flags=0x00000000.40030020: i label target LIR
BB07 IN (1)={V09}
OUT(0)={ }
Recording Var Locations at start of BB07
V09(rax)
Change life 000000000000004A {V05 V08 V09} -> 0000000000000040 {V09}
V05 in reg rsi is becoming dead [------]
Live regs: (unchanged) 00000000 {}
V08 in reg rdi is becoming dead [------]
Live regs: (unchanged) 00000000 {}
Live regs: 00000000 {} => 00000001 {rax}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M7892_BB07:
G_M7892_IG06: ; offs=000075H, funclet=00
Label: IG07, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB07, IL range [000..001)
Scope info: open scopes =
<none>
Generating: N255 ( 1, 1) [000129] C----------- t129 = LCL_VAR int V09 tmp8 u:5 rax (last use) REG rax $20f
Generating: N257 ( 1, 1) [000131] -c---------- t131 = CNS_INT int -1 REG NA $41
/--* t129 int
+--* t131 int
Generating: N259 ( 3, 3) [000132] ------------ t132 = * ADD int REG rax $210
V09 in reg rax is becoming dead [000129]
Live regs: 00000001 {rax} => 00000000 {}
Live vars: {V09} => {}
IN002b: dec eax
/--* t132 int
Generating: N261 ( 4, 4) [000010] ------------ * RETURN int REG NA $1c7
Scope info: end block BB07, IL range [000..001)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M7892_IG07,ins#1,ofs#2) label
Reserving epilog IG for block BB07
G_M7892_IG07: ; offs=000088H, funclet=00
*************** After placeholder IG creation
G_M7892_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M7892_IG02: ; offs=000000H, size=001CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG03: ; offs=00001CH, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG04: ; offs=000033H, size=001CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG05: ; offs=00004FH, size=0026H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG06: ; offs=000075H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG07: ; offs=000088H, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG08: ; epilog placeholder, next placeholder=<END>, BB07 [0009], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M7892_IG09: ; offs=00018AH, size=0000H, gcrefRegs=00000000 {} <-- Current IG
=============== Generating BB09 [???..???) -> BB02 (always), preds={BB02} succs={BB02} flags=0x00000000.42020040: internal target bwd LIR
BB09 IN (3)={V04 V03 V02}
OUT(3)={V04 V03 V02}
Recording Var Locations at start of BB09
V04(rdx) V03(rax) V02(rcx)
Change life 0000000000000000 {} -> 0000000000000121 {V02 V03 V04}
V04 in reg rdx is becoming live [------]
Live regs: 00000000 {} => 00000004 {rdx}
V03 in reg rax is becoming live [------]
Live regs: 00000004 {rdx} => 00000005 {rax rdx}
V02 in reg rcx is becoming live [------]
Live regs: 00000005 {rax rdx} => 00000007 {rax rcx rdx}
Live regs: (unchanged) 00000007 {rax rcx rdx}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M7892_BB09:
Label: IG09, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB09, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP STACK_EMPTY (G_M7892_IG09,ins#0,ofs#0) label
Generating: N001 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V03 tmp2 rax REG rax
/--* t279 long
Generating: N002 ( 2, 2) [000280] ------------ t280 = * COPY long REG rdi
IN002c: mov rdi, rax
V03 in reg rax is becoming dead [000279]
Live regs: 00000007 {rax rcx rdx} => 00000006 {rcx rdx}
V03 in reg rdi is becoming live [000280]
Live regs: 00000006 {rcx rdx} => 00000086 {rcx rdx rdi}
Generating: N001 ( 1, 1) [000281] ------------ t281 = LCL_VAR int V04 tmp3 rdx REG rdx
/--* t281 int
Generating: N002 ( 2, 2) [000282] ------------ t282 = * COPY int REG rax
IN002d: mov eax, edx
V04 in reg rdx is becoming dead [000281]
Live regs: 00000086 {rcx rdx rdi} => 00000082 {rcx rdi}
V04 in reg rax is becoming live [000282]
Live regs: 00000082 {rcx rdi} => 00000083 {rax rcx rdi}
Scope info: end block BB09, IL range [???..???)
Scope info: ignoring block end
IN002e: jmp L_M7892_BB02
=============== Generating BB08 [???..???) -> BB03 (always), preds={BB01} succs={BB03} flags=0x00000000.40020040: internal target LIR
BB08 IN (3)={V05 V03 V02}
OUT(3)={V05 V03 V02}
Recording Var Locations at start of BB08
V05(rsi) V03(rdi) V02(rcx)
Change life 0000000000000121 {V02 V03 V04} -> 0000000000000122 {V02 V03 V05}
V04 in reg rax is becoming dead [------]
Live regs: (unchanged) 00000000 {}
V05 in reg rsi is becoming live [------]
Live regs: 00000000 {} => 00000040 {rsi}
Live regs: 00000040 {rsi} => 000000C2 {rcx rsi rdi}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M7892_BB08:
G_M7892_IG09: ; offs=00018AH, funclet=00
Label: IG10, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB08, IL range [???..???)
Scope info: ignoring block beginning
genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
Generating: N001 ( 1, 1) [000277] ------------ t277 = LCL_VAR long V03 tmp2 rdi REG rdi
/--* t277 long
Generating: N002 ( 2, 2) [000278] ------------ t278 = * COPY long REG rax
IN002f: mov rax, rdi
V03 in reg rdi is becoming dead [000277]
Live regs: 000000C2 {rcx rsi rdi} => 00000042 {rcx rsi}
V03 in reg rax is becoming live [000278]
Live regs: 00000042 {rcx rsi} => 00000043 {rax rcx rsi}
Scope info: end block BB08, IL range [???..???)
Scope info: ignoring block end
IN0030: jmp L_M7892_BB03
Change life 0000000000000122 {V02 V03 V05} -> 0000000000000000 {}
V05 in reg rsi is becoming dead [------]
Live regs: 00000043 {rax rcx rsi} => 00000003 {rax rcx}
V03 in reg rax is becoming dead [------]
Live regs: 00000003 {rax rcx} => 00000002 {rcx}
V02 in reg rcx is becoming dead [------]
Live regs: 00000002 {rcx} => 00000000 {}
# compCycleEstimate = 134, compSizeEstimate = 141 Program:POPCNTButNoBMI2(int):int
; Final local variable assignments
;
; V00 arg0 [V00,T07] ( 3, 3 ) int -> rdi
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
; V02 tmp1 [V02,T08] ( 3, 5 ) long -> rcx
; V03 tmp2 [V03,T05] ( 4, 5.50) long -> registers
; V04 tmp3 [V04,T00] ( 8, 18.50) int -> registers
; V05 tmp4 [V05,T01] ( 10, 13.25) int -> rsi
; V06 tmp5 [V06,T02] ( 3, 12 ) long -> rdi
; V07 tmp6 [V07,T10] ( 6, 2.50) long -> rax
; V08 tmp7 [V08,T03] ( 4, 6.50) int -> rdi
; V09 tmp8 [V09,T06] ( 4, 5.50) long -> rax
; V10 tmp9 [V10,T04] ( 3, 6 ) int -> rcx
; V11 rat0 [V11,T09] ( 3, 3 ) long -> rax
;
; Lcl frame size = 0
*************** Before prolog / epilog generation
G_M7892_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M7892_IG02: ; offs=000000H, size=001CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG03: ; offs=00001CH, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG04: ; offs=000033H, size=001CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG05: ; offs=00004FH, size=0026H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG06: ; offs=000075H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG07: ; offs=000088H, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG08: ; epilog placeholder, next placeholder=<END>, BB07 [0009], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M7892_IG09: ; offs=00018AH, size=000AH, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M7892_IG10: ; offs=000194H, size=0000H, gcrefRegs=00000000 {} <-- Current IG
Recording Var Locations at start of BB01
V00(rdi)
G_M7892_IG10: ; offs=000194H, funclet=00
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M7892_IG01,ins#0,ofs#0) label
__prolog:
IN0031: push rbp
IN0032: mov rbp, rsp
*************** In genClearStackVec3ArgUpperBits()
*************** In genFnPrologCalleeRegArgs() for int regs
*************** In genEnregisterIncomingStackArgs()
IN0033: nop
G_M7892_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN0034: pop rbp
IN0035: ret
G_M7892_IG08: ; offs=00008AH, funclet=00
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M7892_IG01: ; func=00, offs=000000H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M7892_IG02: ; offs=000005H, size=001CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG03: ; offs=000021H, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG04: ; offs=000038H, size=001CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG05: ; offs=000054H, size=0026H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG06: ; offs=00007AH, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG07: ; offs=00008DH, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M7892_IG08: ; offs=00008FH, size=0002H, epilog, nogc, emitadd
G_M7892_IG09: ; offs=000091H, size=000AH, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M7892_IG10: ; offs=00009BH, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
*************** In emitJumpDistBind()
Binding: IN0007: 000000 jle L_M7892_BB08
Binding L_M7892_BB08 to G_M7892_IG10
Estimate of fwd jump [0232D554/007]: 001B -> 009B = 007E
Shrinking jump [0232D554/007]
Adjusted offset of block 03 from 0021 to 001D
Binding: IN000e: 000000 jg L_M7892_BB09
Binding L_M7892_BB09 to G_M7892_IG09
Estimate of fwd jump [0232D7D4/014]: 002E -> 008D = 005D
Shrinking jump [0232D7D4/014]
Adjusted offset of block 04 from 0038 to 0030
Binding: IN0015: 000000 jle L_M7892_BB05
Binding L_M7892_BB05 to G_M7892_IG05
Estimate of fwd jump [0232DAD4/021]: 0040 -> 004C = 000A
Shrinking jump [0232DAD4/021]
Adjusted offset of block 05 from 0054 to 0048
Binding: IN0022: 000000 jle L_M7892_BB07
Binding L_M7892_BB07 to G_M7892_IG07
Estimate of fwd jump [0232DE54/034]: 0068 -> 0081 = 0017
Shrinking jump [0232DE54/034]
Adjusted offset of block 06 from 007A to 006A
Binding: IN002a: 000000 jg SHORT L_M7892_BB06
Binding L_M7892_BB06 to G_M7892_IG06
Estimate of bwd jump [0232E104/042]: 007B -> 006A = 0013
Shrinking jump [0232E104/042]
Adjusted offset of block 07 from 008D to 007D
Adjusted offset of block 08 from 008F to 007F
Adjusted offset of block 09 from 0091 to 0081
Binding: IN002e: 000000 jmp L_M7892_BB02
Binding L_M7892_BB02 to G_M7892_IG03
Estimate of bwd jump [0232E434/046]: 0086 -> 001D = 006B
Shrinking jump [0232E434/046]
Adjusted offset of block 10 from 009B to 0088
Binding: IN0030: 000000 jmp L_M7892_BB03
Binding L_M7892_BB03 to G_M7892_IG04
Estimate of bwd jump [0232E5AC/048]: 008B -> 0030 = 005D
Shrinking jump [0232E5AC/048]
Total shrinkage = 22, min extra jump size = 4294967295
Hot code size = 0x8D bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x6)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M7892_IG01: ; func=00, offs=000000H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0031: 000000 55 push rbp
IN0032: 000001 488BEC mov rbp, rsp
IN0033: 000004 90 nop
G_M7892_IG02: ; func=00, offs=000005H, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0001: 000005 48B99844FCBCE97F0000 mov rcx, 0x7FE9BCFC4498
IN0002: 00000F 488B09 mov rcx, qword ptr [rcx]
IN0003: 000012 8BC7 mov eax, edi
IN0004: 000014 488BF9 mov rdi, rcx
IN0005: 000017 8BF0 mov esi, eax
IN0006: 000019 85F6 test esi, esi
IN0007: 00001B 7E6B jle SHORT G_M7892_IG10
G_M7892_IG03: ; func=00, offs=00001DH, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0008: 00001D 8BF0 mov esi, eax
IN0009: 00001F 488D4708 lea rax, [rdi+8]
IN000a: 000023 F3480FB83F popcnt rdi, qword ptr [rdi]
IN000b: 000028 8BD6 mov edx, esi
IN000c: 00002A 2BD7 sub edx, edi
IN000d: 00002C 85D2 test edx, edx
IN000e: 00002E 7F51 jg SHORT G_M7892_IG09
G_M7892_IG04: ; func=00, offs=000030H, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN000f: 000030 4883C0F8 add rax, -8
IN0010: 000034 F30FB810 popcnt edx, dword ptr [rax]
IN0011: 000038 8BFE mov edi, esi
IN0012: 00003A 2BFA sub edi, edx
IN0013: 00003C 8BD7 mov edx, edi
IN0014: 00003E 85D2 test edx, edx
IN0015: 000040 7E06 jle SHORT G_M7892_IG05
IN0016: 000042 8BF2 mov esi, edx
IN0017: 000044 4883C004 add rax, 4
G_M7892_IG05: ; func=00, offs=000048H, size=0022H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0018: 000048 8B38 mov edi, dword ptr [rax]
IN0019: 00004A 482BC1 sub rax, rcx
IN001a: 00004D 488BC8 mov rcx, rax
IN001b: 000050 48C1F93F sar rcx, 63
IN001c: 000054 4883E103 and rcx, 3
IN001d: 000058 4803C8 add rcx, rax
IN001e: 00005B 48C1F902 sar rcx, 2
IN001f: 00005F 488BC1 mov rax, rcx
IN0020: 000062 48C1E005 shl rax, 5
IN0021: 000066 85F6 test esi, esi
IN0022: 000068 7E13 jle SHORT G_M7892_IG07
G_M7892_IG06: ; func=00, offs=00006AH, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0023: 00006A F30FBCCF tzcnt ecx, edi
IN0024: 00006E FFC1 inc ecx
IN0025: 000070 8BD1 mov edx, ecx
IN0026: 000072 4803C2 add rax, rdx
IN0027: 000075 FFCE dec esi
IN0028: 000077 D3EF shr edi, cl
IN0029: 000079 85F6 test esi, esi
IN002a: 00007B 7FED jg SHORT G_M7892_IG06
G_M7892_IG07: ; func=00, offs=00007DH, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN002b: 00007D FFC8 dec eax
G_M7892_IG08: ; func=00, offs=00007FH, size=0002H, epilog, nogc, emitadd
IN0034: 00007F 5D pop rbp
IN0035: 000080 C3 ret
G_M7892_IG09: ; func=00, offs=000081H, size=0007H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, isz
IN002c: 000081 488BF8 mov rdi, rax
IN002d: 000084 8BC2 mov eax, edx
IN002e: 000086 EB95 jmp SHORT G_M7892_IG03
G_M7892_IG10: ; func=00, offs=000088H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN002f: 000088 488BC7 mov rax, rdi
IN0030: 00008B EBA3 jmp SHORT G_M7892_IG04
Allocated method code size = 141 , actual size = 141
*************** After end code gen, before unwindEmit()
G_M7892_IG01: ; func=00, offs=000000H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0031: 000000 push rbp
IN0032: 000001 mov rbp, rsp
IN0033: 000004 nop
G_M7892_IG02: ; offs=000005H, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0001: 000005 mov rcx, 0x7FE9BCFC4498
IN0002: 00000F mov rcx, qword ptr [rcx]
IN0003: 000012 mov eax, edi
IN0004: 000014 mov rdi, rcx
IN0005: 000017 mov esi, eax
IN0006: 000019 test esi, esi
IN0007: 00001B jle SHORT G_M7892_IG10
G_M7892_IG03: ; offs=00001DH, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0008: 00001D mov esi, eax
IN0009: 00001F lea rax, [rdi+8]
IN000a: 000023 popcnt rdi, qword ptr [rdi]
IN000b: 000028 mov edx, esi
IN000c: 00002A sub edx, edi
IN000d: 00002C test edx, edx
IN000e: 00002E jg SHORT G_M7892_IG09
G_M7892_IG04: ; offs=000030H, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN000f: 000030 add rax, -8
IN0010: 000034 popcnt edx, dword ptr [rax]
IN0011: 000038 mov edi, esi
IN0012: 00003A sub edi, edx
IN0013: 00003C mov edx, edi
IN0014: 00003E test edx, edx
IN0015: 000040 jle SHORT G_M7892_IG05
IN0016: 000042 mov esi, edx
IN0017: 000044 add rax, 4
G_M7892_IG05: ; offs=000048H, size=0022H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0018: 000048 mov edi, dword ptr [rax]
IN0019: 00004A sub rax, rcx
IN001a: 00004D mov rcx, rax
IN001b: 000050 sar rcx, 63
IN001c: 000054 and rcx, 3
IN001d: 000058 add rcx, rax
IN001e: 00005B sar rcx, 2
IN001f: 00005F mov rax, rcx
IN0020: 000062 shl rax, 5
IN0021: 000066 test esi, esi
IN0022: 000068 jle SHORT G_M7892_IG07
G_M7892_IG06: ; offs=00006AH, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0023: 00006A tzcnt ecx, edi
IN0024: 00006E inc ecx
IN0025: 000070 mov edx, ecx
IN0026: 000072 add rax, rdx
IN0027: 000075 dec esi
IN0028: 000077 shr edi, cl
IN0029: 000079 test esi, esi
IN002a: 00007B jg SHORT G_M7892_IG06
G_M7892_IG07: ; offs=00007DH, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN002b: 00007D dec eax
G_M7892_IG08: ; offs=00007FH, size=0002H, epilog, nogc, emitadd
IN0034: 00007F pop rbp
IN0035: 000080 ret
G_M7892_IG09: ; offs=000081H, size=0007H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, isz
IN002c: 000081 mov rdi, rax
IN002d: 000084 mov eax, edx
IN002e: 000086 jmp SHORT G_M7892_IG03
G_M7892_IG10: ; offs=000088H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN002f: 000088 mov rax, rdi
IN0030: 00008B jmp SHORT G_M7892_IG04
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x00008d (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x01
CountOfUnwindCodes: 1
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x00007FE9BE13F9D0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x8d, unwindSize=0x6, pUnwindBlock=0x000000000230C91A, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 4
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000005 ( STACK_EMPTY )
IL offs EPILOG : 0x0000007F ( STACK_EMPTY )
IL offs NO_MAP : 0x00000081 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 2
*************** Variable debug info
2 vars
0( UNKNOWN) : From 00000000h to 00000005h, in rdi
0( UNKNOWN) : From 00000005h to 00000012h, in rdi
*************** In gcInfoBlockHdrSave()
Set code length to 141.
Set ReturnKind to Scalar.
Set stack base register to rbp.
Set Outgoing stack arg area size to 0.
Defining interruptible range: [0x5, 0x7f).
Defining interruptible range: [0x81, 0x8d).
Method code size: 141
Allocations for Program:POPCNTButNoBMI2(int):int (MethodHash=622404b0)
count: 2091, size: 163426, max = 3072
allocateMemory: 196608, nraUsed: 169448
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 6460 | 3.95%
ASTNode | 38976 | 23.85%
InstDesc | 5844 | 3.58%
ImpStack | 384 | 0.23%
BasicBlock | 4296 | 2.63%
fgArgInfo | 0 | 0.00%
fgArgInfoPtrArr | 0 | 0.00%
FlowList | 672 | 0.41%
TreeStatementList | 0 | 0.00%
SiScope | 224 | 0.14%
FlatFPStateX87 | 0 | 0.00%
DominatorMemory | 288 | 0.18%
LSRA | 3852 | 2.36%
LSRA_Interval | 2800 | 1.71%
LSRA_RefPosition | 7104 | 4.35%
Reachability | 16 | 0.01%
SSA | 3148 | 1.93%
ValueNumber | 13448 | 8.23%
LvaTable | 4280 | 2.62%
UnwindInfo | 0 | 0.00%
hashBv | 440 | 0.27%
bitset | 472 | 0.29%
FixedBitVect | 0 | 0.00%
Generic | 3482 | 2.13%
IndirAssignMap | 0 | 0.00%
FieldSeqStore | 176 | 0.11%
ZeroOffsetFieldMap | 40 | 0.02%
ArrayInfoMap | 40 | 0.02%
MemoryPhiArg | 0 | 0.00%
CSE | 2624 | 1.61%
GC | 1336 | 0.82%
CorSig | 104 | 0.06%
Inlining | 808 | 0.49%
ArrayStack | 0 | 0.00%
DebugInfo | 208 | 0.13%
DebugOnly | 55142 | 33.74%
Codegen | 1144 | 0.70%
LoopOpt | 2560 | 1.57%
LoopHoist | 536 | 0.33%
Unknown | 434 | 0.27%
RangeCheck | 0 | 0.00%
CopyProp | 2088 | 1.28%
SideEffects | 0 | 0.00%
****** DONE compiling Program:POPCNTButNoBMI2(int):int
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